Mitsubishi M37560M2-XXXGP Single-chip 8-bit cmos microcomputer Datasheet

MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7560 group is the 8-bit microcomputer based on the 740 family core technology.
The 7560 group has the LCD drive control circuit, an 8-channel AD/D-A converter, UART and PWM as additional functions.
The various microcomputers in the 7560 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 7560 Group,
refer the section on group expansion.
•
FEATURES
• Basic machine-language instructions ....................................... 71
• The minimum instruction execution time ............................ 0.5 µs
(at 8 MHz oscillation frequency)
• Memory size
•
•
•
•
•
• Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2
• Serial I/O1 ..................... 8-bit ✕ 1 (UART or Clock-synchronous)
• Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronous)
• PWM output .................................................................... 8-bit ✕ 1
• A-D converter .................................................. 8-bit ✕ 8 channels
• D-A converter .................................................. 8-bit ✕ 2 channels
• LCD drive control circuit
ROM ................................................................ 32 K to 60 K bytes
RAM ............................................................... 1024 to 2560 bytes
Programmable input/output ports ............................................. 55
Software pull-up resistors .................................................... Built-in
Output ports ................................................................................. 8
Input ports .................................................................................... 1
Interrupts .................................................. 17 sources, 16 vectors
(includes key input interrupt)
•
•
•
•
Bias ................................................................................... 1/2, 1/3
Duty ............................................................................ 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ......................................................................... 40
2 Clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
Watchdog timer ............................................................. 14-bit ✕ 1
Power source voltage ................................................ 2.2 to 5.5 V
Power dissipation
In high-speed mode ........................................................... 40 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode .............................................................. 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... – 20 to 85°C
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
P30/SEG18
P31/SEG19
P32/SEG20
P33/SEG21
P34/SEG22
P35/SEG23
P36/SEG24
P37/SEG25
P00/SEG26
P01/SEG27
P02/SEG28
P03/SEG29
P04/SEG30
P05/SEG31
P06/SEG32
P07/SEG33
P10/SEG34
P11/SEG35
P12/SEG36
P13/SEG37
P14/SEG38
P15/SEG39
PIN CONFIGURATION (TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
VL2
C2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M37560MF-XXXFP
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
C1
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/SCLK22/AN3
P62/SCLK21/AN2
P61/SOUT2/AN1
P60/SIN2/AN0
P57/ADT/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/PWM1
P50/PWM0
P47/SRDY1
P46/SCLK1
P45/TXD
P44/RXD
P43/φ/TOUT
P42/INT2
P41/INT1
P40
P77
P76
P75
P74
1
Package type : 100P6S-A
Fig. 1 Pin configuration of M37560MF-XXXFP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
XCOUT
XCIN
RESET
P70/INT0
P71
P72
P73
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SEG13
SEG14
SEG15
SEG16
SEG17
P30/SEG18
P31/SEG19
P32/SEG20
P33/SEG21
P34/SEG22
P35/SEG23
P36/SEG24
P37/SEG25
P00/SEG26
P01/SEG27
P02/SEG28
P03/SEG29
P04/SEG30
P05/SEG31
P06/SEG32
P07/SEG33
P10/SEG34
P11/SEG35
P12/SEG36
P13/SEG37
PIN CONFIGURATION (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
VL2
C2
C1
VL1
50
49
48
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
47
46
45
44
43
42
41
40
39
M37560MF-XXXGP
32
31
30
29
28
27
26
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/SCLK22/AN3
P62/SCLK21/AN2
P61/SOUT2/AN1
P60/SIN2/AN0
P57/ADT/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/PWM1
P50/PWM0
P47/SRDY1
P46/SCLK1
P45/TXD
P44/RXD
P43/φ/TOUT
P42/INT2
P41/INT1
P40
P77
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package type : 100P6Q-A
Fig. 2 Pin configuration of M37560MF-XXXGP
2
38
37
36
35
34
33
P14/SEG38
P15/SEG39
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
XCOUT
XCIN
RESET
P70/INT0
P71
P72
P73
P74
P75
P76
39
38
27 28 29 30 31 32 33 34
P7(8)
Watchdog
timer
XCIN
Subclock
input
φ
XCOUT
Subclock
output
X COUT
INT0
X CIN
Sub-clock Sub-clock I/O port P7
input output
XCIN XCOUT
36 37
X COUT
X CIN
X OUT
X IN
Clock generating
circuit
Clock
output
3
4
6
7 8
P6(8)
VR E F
AVSS
92 93
A-D converter (8)
9 10
SI/O2(8)
I/O port P6
5
Reset
PC H
PS
P5(8)
CNTR0,CNTR1
D A2
D A1
I/O port P5
P4(8)
I/O port P4
φ
SI/O1 (8)
Output port P3
65 66 67 68 69 70 71 72
P3(8)
TOUT
Timer 3 (8)
Timer 2 (8)
Timer Y (16)
Timer X (16)
Timer 1 (8)
19 20 21 22 23 24 25 26
PWM(8)
35
ROM
40
91
PCL
S
Y
X
A
VS S
VC C
Data bus
(0V)
(5V)
RESET
Reset input
11 12 13 14 15 16 17 18
C P U
ADT
Clock
input
INT1,INT2
FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)
D-A2
I/O port P2
41 42 43 44 45 46 47 48
P2(8)
LCD display
RAM
(20 bytes)
RAM
P1(8)
I/O port P1
49 50 51 52 53 54 55 56
D-A1
P0(8)
I/O port P0
57 58 59 60 61 62 63 64
LCD
drive control
circuit
2
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
90
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
COM0
COM1
COM2
COM3
VL 1
C1
C2
VL 2
VL 3
97
98
99
100
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 3 Functional block diagram
3
Key input (Key-on wake up) interrupt
Real time port function
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
•Apply voltage of 2.2 V to 5.5 V to VCC, and 0 V to VSS.
VREF
Analog reference voltage
•Reference voltage input pin for A-D converter.
AVSS
Analog power
source
•GND input pin for A-D converter.
RESET
XIN
Reset input
•Reset input pin for active “L”.
Clock input
XOUT
Clock output
•Input and output pins for the main clock generating circuit.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•Connect to VSS.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A
feedback resistor is built-in.
VL1–VL3
LCD power
source
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
•Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.)
C1, C2
Charge-pump
capacitor pin
•External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
COM0–COM3
Common output
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
SEG0–SEG17
Segment output
•LCD segment output pins.
P00/SEG26–
P07/SEG33
I/O port P0
•8-bit I/O port.
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 8-bit pin to be programmed as either input or output.
P10/SEG34–
P15/SEG39
I/O port P1
•6-bit I/O port with same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 6-bit pin to be programmed as either input or output.
P16, P17
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually programmred as either input or output.
P20 – P27
I/O port P2
•Pull-up control is enabled.
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•Key input (key-on wake-up) interrupt
input pins
•CMOS 3-state output structure.
•Pull-up control is enabled.
P30/SEG18 –
P37/SEG25
4
Output port P3
•8-bit output port with same function as port P0.
•CMOS 3-state output structure.
•Port output control is enabled.
•LCD segment output pins
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
P40
Name
I/O port P4
Function
Function except a port function
•1-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•N-channel open-drain output structure.
P41/INT1,
P42/INT2
•7-bit I/O port with same function as P16 and P17.
P43/φ/TOUT
•CMOS 3-state output structure.
•Pull-up control is enabled.
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/PWM0,
P51/PWM1
•Interrupt input pins
•CMOS compatible input level.
•φ clock output pin
•Timer 2 output pin
•Serial I/O1 I/O pins
I/O port P5
•8-bit I/O port with same function as P16 and P17.
•PWM function pins
•CMOS compatible input level.
•CMOS 3-state output structure.
P52/RTP0,
P53/RTP1
•Real time port function pins
•Pull-up control is enabled.
P54/CNTR0,
P55/CNTR1
•Timer X, Y function pins
P56/DA1,
P57/ADT/DA2
•D-A conversion output pins
P60/AN0/SIN2,
P61/AN1/SOUT2,
P62/AN2/SCLK21,
P63/AN3/SCLK22
I/O port P6
•8-bit I/O port with same function as P16 and P17.
•A-D conversion input pins
•CMOS compatible input level.
•Serial I/O2 I/O pins
•CMOS 3-state output structure.
•Pull-up control is enabled.
P64/AN4–
P67/AN7
P70/INT0
P71–P77
•A-D conversion input pins
Input port P7
I/O port P7
•1-bit input port.
•Interrupt input pin
•7-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•N-channel open-drain output structure.
XCOUT
Sub-clock output
XCIN
Sub-clock input
•Sub-clock generating circuit I/O pins.
(Connect a resonator. External clock cannot be used.)
5
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M37560
M
F
–
XXX
FP
Package type
FP : 100P6S-A package
GP : 100P6Q-A package
ROM number
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
Fig. 4 Part numbering
6
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 7560 group as follows.
100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM version.
Memory Size
ROM size ........................................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2560 bytes
Memory Expansion Plan
Under development
ROM size (bytes)
60K
M37560MF
56K
52K
48K
44K
40K
Under development
36K
32K
M37560M8
28K
24K
20K
16K
12K
8K
4K
192
256
512
768
1024
1280
1536
1792
2048
2304
2560
RAM size (bytes)
Fig. 5 Memory expansion plan
Currently products are listed below.
As of Mar. 2001
Table 3. List of products
Product
ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
M37560M8-XXXFP
M37560M8-XXXGP
M37560MF-XXXFP
M37560MF-XXXGP
32768
(32638)
1024
61440
(61310)
2560
Package
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
7
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
The 7560 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
8
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
POP return
address from stack
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
9
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
• Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation.
It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
• Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal aritmetic.
• Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled between memory locations.
• Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7
of the memory location operated on by the BIT instruction is
stored in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
10
C flag
SEC
Z flag
–
I flag
SEI
D flag
SED
B flag
–
T flag
V flag
–
N flag
SET
CLC
–
CLI
CLD
–
CLT
CLV
–
–
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit
0 : Oscillation stop
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 8 Structure of CPU mode register
11
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Zero Page
The 256 bytes from addresses 000016 to 00FF 16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
192
00FF16
256
013F16
004016
384
01BF16
005416
512
023F16
640
02BF16
768
033F16
896
03BF16
1024
043F16
1536
063F16
2048
083F16
2560
0A3F16
000016
SFR area
010016
XXXX16
Reserved area
044016
Not used (Note)
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
F00016
F08016
YYYY16
Reserved ROM area
(128 bytes)
8192
E00016
E08016
12288
D00016
D08016
16384
C00016
C08016
20480
B00016
B08016
24576
A00016
A08016
28672
900016
908016
32768
800016
808016
36864
700016
708016
40960
600016
608016
45056
500016
508016
49152
400016
408016
53248
300016
308016
FFFE16
57344
200016
208016
FFFF16
61440
100016
108016
ZZZZ16
ROM
Note: When RAM area exceeds 1024 bytes, the areas shown the table are used.
12
Zero page
RAM
ROM area
Fig. 9 Memory map diagram
LCD display RAM area
FF0016
FFDC16
Interrupt vector area
Reserved ROM area
Special page
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716 Port P3 output control register (P3C)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
001016
001116
001216
001316
001416 Reserved area
001516 Key input control register (KIC)
001616 PULL register A (PULLA)
001716 PULL register B (PULLB)
001816 Transmit/Receive buffer register(TB/RB)
001916 Serial I/O1 status register (SIO1STS)
001A16 Serial I/O1 control register (SIO1CON)
001B16 UART control register (UARTCON)
001C16 Baud rate generator (BRG)
001D16 Serial I/O2 control register (SIO2CON)
001E16 Reserved area
001F16 Serial I/O2 register (SIO2)
002016 Timer X (low) (TXL)
002116 Timer X (high) (T XH)
002216 Timer Y (low) (TYL)
002316 Timer Y (high) (TYH)
002416 Timer 1 (T1)
002516 Timer 2 (T2)
002616 Timer 3 (T3)
002716 Timer X mode register (TXM)
002816 Timer Y mode register (TYM)
002916 Timer 123 mode register (T123M)
002A16 TOUT/φ output control register (CKOUT)
002B16 PWM control register (PWMCON)
002C16 PWM prescaler (PREPWM)
002D16 PWM register (PWM)
002E16 Reserved area
002F16 Reserved area
003016 Reserved area
003116 Reserved area
003216 D-A1 conversion register (DA1)
003316 D-A2 conversion register (DA2)
003416 A-D control register (ADCON)
003516 A-D conversion register (AD)
003616 D-A control register (DACON)
003716 Watchdog timer control register (WDTCON)
003816 Segment output enable register (SEG)
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003D16 Interrupt request register 2(IREQ2)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
Fig. 10 Memory map of special function register (SFR)
13
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direction registers which determine the input/output direction of each
individual pin. (Ports P00–P07 are shared with bit 0 of the port P0
direction register, and ports P10–P15 shared with bit 0 of the port
P1 direction register.) Each bit in a direction register corresponds
to one pin, and each pin can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 0007 16) enables control of the output of ports P30–P37.
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid) and pulled up.
Pull-up Control
By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P2, P4 to P6 can control pullup with a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
The PULL register A setting is invalid for pins set to segment output with the segment output enable register.
14
b7
b0
PULL register A
(PULLA : address 001616)
P00, P01 pull-up
P02, P03 pull-up
P04–P07 pull-up
P10–P13 pull-up
P14, P15 pull-up
P16, P17 pull-up
P20–P23 pull-up
P24–P27 pull-up
b7
b0
PULL register B
(PULLB : address 001716)
P41–P43 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Fig. 11 Structure of PULL register A and PULL register B
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 List of I/O port function (1)
Name
Port P0
Input/output,
byte unit
CMOS compatible
input level
CMOS 3-state output
LCD segment output
PULL register A
Segment output enable
register
P10/SEG34–
P15/SEG39
Port P1
Input/output,
6-bit unit
CMOS compatible
input level
CMOS 3-state output
LCD segment output
PULL register A
Segment output enable
register
(1)
(2)
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
PULL register A
(4)
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
Key input (key-on
wake-up) interrupt
input
LCD segment output
P16 , P17
P20–P27
Port P2
Input/Output
Non-Port Function
Pin
P00/SEG26–
P07/SEG33
I/O Format
P30/SEG18–
P37/SEG25
Port P3
Output
CMOS 3-state output
P40
Port P4
Input/output,
individual bits
CMOS compatible
input level
N-channel open-drain
output
CMOS compatible
input level
CMOS 3-state output
P41/INT1,
P42/INT2
P43/φ/TOUT
Diagram No.
(1)
(2)
PULL register A
Interrupt control register2
Key input control register
Segment output enable
register
P3 output enable register
(3)
(13)
External interrupt input
Timer output
φ output
Serial I/O1 function I/O
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
Related SFRs
Interrupt edge selection
register
PULL register B
Timer 123 mode register
TOUT/φ output control
register
PULL register B
Serial I/O1 control register
Serial I/O1 status register
UART control register
(4)
(12)
(5)
(6)
(7)
(8)
PWM output
PULL register B
PWM control register
(10)
Real time port
function output
PULL register B
Timer X mode register
(9)
P54/CNTR0
Timer X function I/O
(11)
P55/CNTR1
Timer Y function input
PULL register B
Timer X mode register
PULL register B
P56/DA1
DA1 output
P57/ADT/
DA2
DA2 output
A-D trigger input
P50/PWM0,
P51/PWM1
P52/RTP0,
P53/RTP1
Port P5
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
Timer Y mode register
PULL register B
D-A control register
PULL register B
D-A control register
A-D control register
(14)
(15)
(15)
15
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 List of I/O port function (2)
Pin
P60/SIN2/AN0
Name
Port P6
P61/SOUT2/
AN1
Input/Output
Input/
output,
individual
bits
I/O Format
CMOS compatible input
level
CMOS 3-state output
Non-Port Function
A-D conversion input
Serial I/O2 function I/O
Related SFRS
Diagram No.
PULL register B
A-D control register
Serial I/O2 control
register
(17)
(18)
P62/SCLK21/
AN2
(19)
P63/SCLK22 /
AN3
(20)
P64/AN4–
P67/AN7
P70/INT0
Port P7
P71–P77
Input
CMOS compatible input
level
Input/
output,
individual
bits
CMOS compatible input
level
N-channel open-drain
output
COM0–COM3
Common
Output
LCD common output
SEG0–SEG17
Segment
Output
LCD segment output
A-D conversion input
A-D control register
PULL register B
(16)
External interrupt input
Interrupt edge
selection register
(23)
(13)
LCD mode register
(21)
(22)
Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow VCC to VSS through the input-stage gate.
16
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P01–P07, P11–P15
Pull-up
Segment data
Data bus
Port latch
Port direction register
LCD drive timing
VL2/VL3/VCC
Segment/Port
Interface logic level
shift circuit
Segment
Port/Segment
VL1/VSS
Port
Port direction register
(2) Ports P00, P10
Pull-up
Direction register
Segment data
Data bus
VL2/VL3/VCC
Segment/Port
LCD drive timing
Interface logic level
shift circuit
Port latch
Segment
VL1/VSS
Port/Segment
Port
Port direction register
(3) Port P3
Pull-up
Segment data
Port latch
Data bus
LCD drive timing
VL2/VL3/VCC
Segment/Port
Interface logic level
shift circuit
Segment
VL1/VSS
Port
Port/Segment
Output control
(4) Ports P16,P17,P2,P41,P42
(5) Port P44
Pull-up control
Serial I/O1 enable bit
Reception enable bit
Direction
register
Data bus
Pull-up control
Direction
register
Port latch
Data bus
Key-on wake up interrupt input
INT1, INT2 interrupt input
Port latch
Serial I/O1 input
Except P16, P17
Fig. 12 Port block diagram (1)
17
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P45
(7) Port P46
Pull-up control
P45/TxD P-channel output disable bit
Serial I/O1 enable bit
Transmission enable bit
Direction
register
Data bus
Serial I/O1 synchronization
clock selection bit
Serial I/O1 enable bit
Pull-up control
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
Port latch
Data bus
Serial I/O1 output
Port latch
Serial I/O1 clock output
Serial I/O1 clock input
(8) Port P47
(9) Ports P52,P53
Pull-up control
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Real time control bit
Real time port data
Serial I/O1 ready output
(10) Ports P50,P51
Pull-up control
Pull-up control
(11) Port P54
Pull-up control
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Pulse output mode
Timer output
PWM function enable bit
PWM output
Fig. 13 Port block diagram (2)
18
CNTR0 interrupt input
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Ports P40,P71–P77
(12) Port P43
Pull-up control
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
TOUT/φ output control
Timer output
TOUT/φ selection bit
φ output
(15) Ports P56,P57
(14) Port P55
Direction
register
Direction
register
Data bus
Data bus
Port latch
(16) Ports P64–P67
Pull-up control
(17) Port P60
Pull-up control
Direction
register
Port latch
A-D conversion input
Analog input pin selection bit
Port latch
A-D trigger input
Except P56
D-A converter output
D-A1,D-A2 output enable bit
CNTR1 interrupt input
Data bus
Pull-up control
Pull-up control
Direction
register
Data bus
Port latch
Serial I/O2 input
A-D conversion input
Analog input pin selection bit
Fig. 14 Port block diagram (3)
19
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(19) Port P62
(18) Port P61
P61/SOUT2 P-channel output disable bit
Serial I/O2 transmit end signal
Synchronous clock selection bit
Serial I/O2 port selection bit
Direction
register
Data bus
Pull-up control
Synchronous clock selection bit
Pull-up control
Serial I/O2 port selection bit
Synchronous clock output pin
selection bit
Direction
register
Port latch
Data bus
Serial I/O2 output
A-D conversion input
Analog input pin selection bit
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
A-D conversion input
Analog input pin selection bit
(20) Port P63
Pull-up control
Synchronous clock selection bit
Serial I/O2 port selection bit
Synchronous clock output pin selection bit
Direction
register
Data bus
(21)COM0–COM3
VL 3
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
VL 2
Port latch
VL1
Serial I/O2 clock output
VSS
A-D conversion input
Analog input pin selection bit
(23) Port P70
(22)SEG0–SEG17
Direction
register
VL2/VL3
The voltage applied to the sources of Pchannel and N-channel transistors is the
controlled voltage by the bias value.
Data bus
Port latch
VL1/VSS
INT0 input
Fig. 15 Port block diagram (4)
20
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt Operation
Interrupts occur by seventeen sources: seven external, nine internal, and one software.
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 8 Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses (Note 1)
High
Low
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
Remarks
Reset (Note 2)
INT0
1
2
FFFD16
FFFB16
FFFC16
FFFA16
INT1
3
FFF916
FFF816
At detection of either rising or
falling edge of INT1 input
Serial I/O1
reception
4
FFF716
FFF616
At completion of serial I/O1 data
reception
Serial I/O1
transmission
5
FFF516
FFF416
Timer X
6
FFF316
FFF216
At completion of serial I/O1
transmit shift or when transmission buffer is empty
At timer X underflow
Timer Y
7
FFF116
FFF016
At timer Y underflow
Timer 2
Timer 3
FFEF16
FFED16
FFEB16
FFEE16
FFEC16
FFEA16
At timer 2 underflow
CNTR0
8
9
10
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
11
FFE916
FFE816
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
Timer 1
INT2
12
FFE716
FFE616
At timer 1 underflow
13
FFE516
FFE416
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
Serial I/O2
14
FFE316
FFE216
At completion of serial I/O2 data
transmission or reception
Valid when serial I/O2 is selected
Key input
(Key-on wake-up)
15
FFE116
FFE016
At falling of conjunction of input
level for port P2 (at input mode)
External interrupt
(valid at falling)
ADT
16
FFDF16
FFDE16
At falling edge of ADT input
At completion of A-D conversion
Valid when ADT interrupt is selected
External interrupt
(valid at falling)
Valid when A-D interrupt is selected
At BRK instruction execution
Non-maskable software interrupt
A-D conversion
BRK instruction
17
FFDD16
FFDC16
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
21
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When not requiring for the interrupt occurrence synchronous with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit (polarity switch bit) or the interrupt source select bit to “1”.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection bit of A-D control
regsiter (bit 6 of address 3416)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 16 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D16)
CNT R0 interrupt request bit
CNT R1 interrupt request bit
Timer 1 interrupt request bit
INT2 interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer 1 interrupt enable bit
INT2 interrupt enable bit
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 17 Structure of interrupt-related registers
22
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake Up)
A Key-on wake up interrupt request is generated by applying “L”
level voltage to any pin of port P2 that have been set to input
mode. In other words, it is generated when AND of input level
goes from “1” to “0”. An example of using a key input interrupt is
shown in Figure 18, where an interrupt request is generated by
pressing one of the keys consisted as an active-low key matrix
which inputs to ports P20–P23.
Port PXx
“L” level output
PULL register A
Bit 2 = “1”
✽
P27 output
✽
Port P27 Key input control register = “1”
direction register = “1”
✽✽
Port P27
latch
Key input interrupt request
Port P26 Key input control register = “1”
direction register = “1”
✽ ✽ Port P26
latch
P26 output
Key input control register = “1”
Port P25
direction register = “1”
✽
✽✽
P25 output
Port P25
latch
Key input control register = “1”
Port P24
direction register = “1”
✽
✽✽
P24 output
Port P24
latch
Key input control register = “1”
Port P23
direction register = “0”
✽
✽✽
P23 input
Port P2
Input reading circuit
Port P23
latch
Key input control register = “1”
Port P22
direction register = “0”
✽
✽✽
Port P22
latch
P22 input
Key input control register = “1”
Port P21
direction register = “0”
✽
✽✽
P21 input
Port P21
latch
Port P20
Key input control register = “1”
direction register = “0”
✽
P20 input
✽✽
Port P20
latch
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 18 Connection example when using key input control register, key input interrupt and port P2 block diagram
23
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
The 7560 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00 16”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
Data bus
Real time port
control bit “1”
P52 data for
real time port
Q D
P52/RTP0
Latch
“0 ”
Real time port
control bit “1”
P53 data for
real time port
Q D
P53/RTP1
Real time port
control bit “0”
Latch
“0 ”
Timer X mode register
write signal
“1 ”
P54/CNTR0
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
Timer X operatCNTR0 active
ing mode bits
edge switch bit “00”,“01”,“11”
“0”
Timer X stop
control bit
Timer X write
control bit
Timer X (low) latch (8)
Timer X (low) (8)
Timer X (high) latch (8)
Timer X (high) (8)
"10"
Pulse width “1”
measurement
mode
CNTR0 active
edge switch bit “0”
Pulse output mode
Q
“1”
P54 direction register
Timer X
interrupt
request
S
T
Q
Pulse width HL continuously
measurement mode
P54 latch
Rising edge detection
Pulse output mode
Period
measurement mode
Falling edge detection
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
Timer Y stop
control bit
CNTR1 active
edge switch bit
"00","01","11"
“0 ”
P55/CNTR1
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (low) (8)
Timer Y (high) (8)
"10" Timer Y
operating
mode bits
“1 ”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
Timer 1 count source
selection bit
“0”
Timer 1 latch (8)
Timer 1 (8)
XCIN
TOUT output
control bit
P43 direction register
Fig. 19 Timer block diagram
24
Timer 2 count source
selection bit
Timer 2 latch (8)
“0 ”
Timer 2 (8)
“1”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
“1 ”
P43/φ/TOUT
Timer Y
interrupt
request
Timer 2 write
control bit
Timer 1
interrupt
request
Timer 2
interrupt
request
TOUT output
TOUT output control bit
active edge
switch bit “0”
Q S
P43 latch
“1 ”
T
Q
f(XIN)/16
(f(XCIN)/16
when φ = XCIN/2)
“0 ”
Timer 3 latch (8)
Timer 3 (8)
“1”
Timer 3 count
source selection bit
Timer 3
interrupt
request
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR 0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode.
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P5 4 direction register to input
mode.
b7
b0
Timer X mode register
(TXM : address 002716)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P52 data for real time port
P53 data for real time port
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNT R0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width measurement
mode
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width measurement
mode
Rising edge active for CNT R0 interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
Fig. 20 Structure of timer X mode register
●Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P5 2 and P5 3 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1” after set of the real time port data, data are output
independent of the timer X operation.) If the data for the real time
port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
■Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
25
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period measurement mode
CNTR 1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR 1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
(3) Event counter mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
(4) Pulse width HL continuously measurement mode
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR 1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
26
b7
b0
Timer Y mode register
(TYM : address 002816)
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
Fig. 21 Structure of timer Y mode register
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
●Timer 2 Write Control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 Output Control
When the timer 2 (T OUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P56 shared with the port TOUT to the output mode.
■Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
b7
b0
Timer 123 mode register
(T123M :address 002916)
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT/φ output control bit
0 : TOUT/φ output disabled
1 : TOUT/φ output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN)
Not used (return “0” when read)
Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.
Fig. 22 Structure of timer 123 mode register
27
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O1
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Data bus
Serial I/O1 control register
Address 001816
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P44/RXD
Address 001A16
Receive buffer full flag (RBF)
Shift clock
Clock control circuit
P46/SCL K1
Serial I/O1 synchronization
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
XIN
Baud rate generator
P47/SRDY1
F/F
1/4
Address 001C16
1/4
Clock control circuit
Falling-edge detector
Shift clock
P45/TXD
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer empty flag (TBE)
Address 001916
Transmit buffer register (TB)
Address 001816
Data bus
Serial I/O1 status register
Fig. 23 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RXD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write signal to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 24 Operation of clock synchronous serial I/O1 function
28
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
P44/RXD
Serial I/O1 control register Address 001A16
OE
Receive buffer register
Character length selection bit
STdetector
7 bits
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
8 bits
UART control register
Address 001B16
SP detector
PE FE
Clock control circuit
Serial I/O1 synchronization clock selection bit
P46/SCL K1
BRG count source selection bit
Frequency division ratio 1/(n+1)
XIN
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
P45/TXD
Transmit shift register
Character length selection bit
Transmit buffer register
Address 001816
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 25 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TBE=1
Serial output TxD
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
✽ Generated
RBF=0
RBF=1
Serial input RxD
ST
D0
D1
D1
SP
ST
D0
D1
SP
at 2nd bit in 2-stop-bit mode
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : T he transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : T he receive interrupt (RI) is set when the RBF flag becomes “1”.
Fig. 26 Operation of UART serial I/O1 function
29
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer register is “0”.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the Serial I/O1 Control Register) also clears all the status
flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become
“1”.
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register contains eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O1 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronous with the transmission
enalbed, take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
30
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 status register
(SIO1STS : address 001916)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b0
Serial I/O1 control register
(SIO1CON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O1 synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
External clock input divided by 16 when UART is selected.
Overrun error flag (OE)
0: No error
1: Overrun error
SRDY1 output enable bit (SRDY)
0: P47 pin operates as ordinary I/O pin
1: P47 pin operates as SRDY1 output pin
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
b7
b7
b0 UART control regi ster
(UART CON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P44–P47 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P44–P47 operate as serial I/O pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (ST PS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 27 Structure of serial I/O1 control registers
31
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
When an internal clock is selected as the synchronous clock of the
serial I/O2, either P62 or P63 can be selected as an output pin of
the synchronous clock. In this case, the pin that is not selected as
an output pin of the synchronous clock functions as a port.
b7
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
Internal synchronous clock select bits
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 0 0:
1 0 1: Do not set
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK21/SCLK22 signal output
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains 8 bits which control various serial I/O2 functions.
P61/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output
(in output mode)
Transfer direction selection bit
0: LSB first
1: MSB first
Synchronous clock selection bit
0: External clock
1: Internal clock
Synchronous clock output pin selection bit
0: SCLK21
1: SCLK22
Fig. 28 Structure of serial I/O2 control register
1/8
Divider
1/16
XIN
Internal synchronous
clock select bits
1/32
Data bus
1/64
1/128
1/256
P63 latch
Synchronous clock
selection bit
(Note)
P63/SCLK22
“1”
SCLK2
Synchronous circuit
“0”
External clock
P62 latch
“0”
P62/SCLK21
(Note) “1”
Serial I/O counter 2 (3)
P61 latch
“0”
P61/SOUT2
“1”
Serial I/O2 port selection bit
P60/SIN2
Serial I/O shift register 2 (8)
Note: It is selected by the synchronous clock selection bit, the synchronous
clock output pin selection bit, and the serial I/O port selection bit.
Fig. 29 Block diagram of serial I/O2 function
32
Serial I/O2
interrupt request
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output S OUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input S IN2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion.
When the external clock is selected as the transfer clock, a content of the serial I/O shift register is continued to shift
during inputting a transfer clock. The S OUT2 pin does not go to high impedance after transfer completion.
Fig. 30 Timing of serial I/O2 function
33
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
PWM Operation
The 7560 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input XIN or that clock input divided by 2.
When at least either bit 1 (PWM 0 function enable bit) or bit 2
(PWM1 function enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”. When one PWM output is enabled and that the other PWM output is enabled, PWM output
which is enabled to output later starts pulse output from halfway.
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Data Setting
The PWM output pin also functions as ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255 ✕ (n+1)/f(XIN)
= 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” period = PWM period ✕ m/255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz)
31.875 ✕ m ✕ (n+1)
µs
255
PWM output
T = [31.875 ✕ (n+1)] µs
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(X IN ) = 8 MHz)
Fig. 31 Timing of PWM cycle
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
PWM1 function
enable bit
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Port P51
lacth
Port P51
Count source
selection bit
“0”
PWM prescaler
XIN
1/2
PWM circuit
Port P50
“1”
Port P50
lacth
PWM0 function
enable bit
Fig. 32 Block diagram of PWM function
34
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
b7
PWM control register
(PWMCON : address 002B16)
Count source selection bit
0 : f(XIN)
1 : f(XIN)/2
PWM0 function enable bit
0 : PWM0 disabled
1 : PWM0 enabled
PWM1 function enable bit
0 : PWM1 disabled
1 : PWM1 enabled
Not used (return “0” when read)
Fig. 33 Structure of PWM control register
A
PWM
(internal)
C
B
B = C
T2
T
stop
stop
T
T
T2
Port
PWM 0 output
PWM 1 output
Port
Port
Port
PWM register
write signal
(Changes from “A” to “B” during “H” period)
PWM prescaler
write signal
(Changes from “T” to “T2” during PWM period)
PWM 0 function
enable bit
PWM 1 function
enable bit
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 34 PWM output timing when PWM register or PWM prescaler is changed
35
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
Comparator and Control Circuit
The functional blocks of the A-D converter are described below.
The comparator and control circuit compare an analog input voltage with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the AD conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
b7
b0
A-D control register
(ADCON : address 003416)
Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : OFF
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P67/AN7–P60/
AN0.
Fig. 35 Structure of A-D control register
Data bus
b7
b0
A-D control register
P57/ADT/DA2
3
ADT/A-D interrupt request
A-D control circuit
P60/SIN2/AN0
P63/SCLK22/AN3
P64/AN4
P65/AN5
P66/AN6
Channel selector
P61/SOUT2/AN1
P62/SCLK21/AN2
Comparator
A-D conversion
register
8
Resistor ladder
P67/AN7
AVSS
Fig. 36 A-D converter block diagram
36
VREF
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A Converter
The 7560 group has an on-chip D-A converter with 8-bit resolution
and 2 channels (DAi (i=1, 2)). After the DA1 selection bit or DA2
selection bit is set to “0”, the D-A converter is performed by setting
the value in the D-A conversion register. The result of D-A converter is output from DAi pin. When using the D-A converter, the
corresponding port direction register bit (P5 6 /DA 1 , P5 7 /DA 2 )
should be set to “0” (input status) and the pull-up resistor should
be in the OFF state.
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
b7
b0
D-A control register
(DACON : address 0036 16)
DA1 output enable bit
0 : Disabled
1 : Enabled
DA2 output enable bit
0 : Disabled
1 : Enabled
Not used (return “0” when read)
(Do not write “1” to these bits.)
V=VREF ✕ n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are cleared to “0016”, the
DAi output enable bits are cleared to “0”, and DAi pin goes to
high impedance state. The DA output is not buffered, so connect
an external buffer when driving a low-impedance load.
■ Note on applied voltage to VREF pin
When the P56/DA1 pin and P57/DA2 pin are used as I/O ports, be
sure to apply Vcc level to VREF pin.
When these pins are used as D-A conversion output pins, the Vcc
level is recommended for the applied voltage to VREF pin.
When the voltage below Vcc level is applied, the D-A conversion
accuracy may be worse.
Fig. 37 Structure of D-A control register
Data bus
D-A1 conversion register
(DA1: address 003216)
D-A2 conversion register
(DA2: address 003316)
D-A i conversion register (8)
DA i output enable bit
R-2R resistor ladder
P56/DA1
P57/DA2
Fig. 38 Block diagram of D-A converter
37
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD DRIVE CONTROL CIRCUIT
The 7560 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output enable register
LCD mode register
Voltage multiplier
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Up to 160 pixels can be controlled for LCD display. When the LCD
•
•
•
•
•
•
•
•
•
b7
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel.
Table 9. Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
b0
Segment output enable register
(SEG : address 003816)
Segment output enable bit 0
0 : Output ports P30–P35
1 : Segment output SEG18–SEG23
Segment output enable bit 1
0 : Output ports P36, P37
1 : Segment output SEG24,SEG25
Segment output enable bit 2
0 : I/O ports P00–P05
1 : Segment output SEG26–SEG31
Segment output enable bit 3
0 : I/O ports P06,P07
1 : Segment output SEG32,SEG33
Segment output enable bit 4
0 : I/O port P10
1 : Segment output SEG34
Segment output enable bit 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD output enable bit
0 : Disabled
1 : Enabled
Not used (return “0” when read)
(Do not write “1” to this bit)
b7
b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM0, COM1)
1 0 : 3 duty (use COM0–COM2)
1 1 : 4 duty (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disable
1 : Voltage multiplier enable
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 39 Structure of segment output enable register and LCD mode register
38
Fig. 40 Block diagram of LCD controller/driver
Data bus
LCD enable bit
Address 004016
Address 005316
Address 004116
Duty ratio selection bits
LCD display RAM
LCD circuit
divider division
ratio selection bits
2
2
Voltage multiplier
control bit
LCD
divider
Bias control bit
“1”
Timing controller
Level
shift
Level
shift
f(XIN)/8192
(f(XCIN)/8192 in lowspeed mode)
Selector Selector
Selector Selector Selector Selector
Level
shift
LCDCK count source
selection bit
“0”
f(XCIN)/ 32
Level
shift
Level
shift
Level
shift
Level
Shift
Bias control
Level
Shift
Level
Shift
LCDCK
Level
Shift
VCC
SEG2
SEG3
P30/SEG18
P14/SEG38 P15/SEG39
driver
VSS VL1 VL2 VL3 C1 C2
driver
driver
driver
COM0 COM1 COM2 COM3
39
MITSUBISHI MICROCOMPUTERS
SEG1
LCD output
Common Common Common Common
enable bit
7560 Group
SEG0
Segment Segment
driver
driver
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Segment Segment Segment Segment
driver
driver
driver
driver
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Voltage Multiplier (3 Times)
Bias Control and Applied Voltage to LCD
Power Input Pins
The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin
VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and
apply voltage by external resistor division.)
Set each bit of the segment output enable register and the LCD
mode register in the following order for operating the voltage multiplier.
1. Set the segment output enable bits (bits 0 to 5) of the segment output enable register to “0” or “1.”
2. Set the duty ratio selection bits (bits 0 and 1), the bias control bit (bit 2), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register to “0” or “1.”
3. Set the LCD output enable bit (bit 6) of the segment output
enable register to “1.”
4. Set the voltage multiplier control bit (bit 4) of the LCD mode
register to “1.”
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
When using the voltage multiplier, apply 1.3 V ≤ Voltage ≤ 2.1 V to
the VL1 pin.
When not using the voltage multiplier,apply proper voltage to the
LCD power input pins (VL1–VL3). Then set the LCD output enable
bit to “1.”
When the LCD output enable bit is set to “0,” the V CC voltage is
applied to the VL3 pin inside of this microcomputer.
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
To the LCD power input pins (VL1–V L3), apply the voltage shown
in Table 10 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Table 10. Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Note : V LCD is the maximum value of supplied voltage for the
LCD panel.
Contrast control
VL3
VL3
Contrast control
VL3
R1
VL2
VL2
C2
C2
R4
VL2
Open
C2
Open
C1
Open
R2
C1
C1
VL1
VL1
Open
VL1
R3
R5
PXx
1/3 bias
when using the voltage multiplier
Fig. 41 Example of circuit at each bias
40
R1=R2=R3
1/3 bias
when not using the voltage multiplier
R4=R5
1/2 bias
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Common Pin and Duty Ratio Control
LCD Display RAM
The common pins (COM 0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When releasing from reset, the VCC (VL3) voltage is output from
the common pins.
Address 004016 to 005316 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation;
Table 11. Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bits
2
Bit 1
0
Bit 0
1
3
4
1
1
0
1
Common pins used
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
f(LCDCK)=
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
(frequency of count source for LCDCK)
(divider division ratio for LCD)
Frame frequency=
f(LCDCK)
duty ratio
Segment Signal Output Pin
Segment signal output pins are classified into the segment-only
pins (SEG 0 –SEG 17 ), the segment/output port pins (SEG 18 –
SEG25), and the segment/I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset release, a V CC
(=VL3) voltage is output to the segment-only pins and the segment/output port pins are the high impedance condition and
pulled up to VCC (=VL3) voltage.
Also, the segment/I/O port pins(SEG26–SEG39) are set to input
ports, and VCC (=VL3) is applied to them by pull-up resistor.
Bit
7
6
5
4
3
2
1
0
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG1
SEG0
SEG3
SEG2
SEG5
SEG4
SEG7
SEG6
SEG9
SEG8
SEG11
SEG10
SEG13
SEG12
SEG15
SEG14
SEG17
SEG16
SEG19
SEG18
SEG21
SEG20
SEG23
SEG22
SEG25
SEG24
SEG27
SEG26
SEG29
SEG28
SEG31
SEG30
SEG33
SEG32
SEG35
SEG34
SEG37
SEG36
SEG39
SEG38
Fig. 42 LCD display RAM map
41
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
VL2=VL1
VSS
COM0
COM1
COM2
COM3
VL3
VSS
SEG0
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2=VL1
VSS
COM0
COM1
COM2
VL3
VSS
SEG0
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2=VL1
VSS
COM0
COM1
VL3
VSS
SEG0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 43 LCD drive waveform (1/2 bias)
42
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
VL3
SEG0
VSS
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
VL3
SEG0
VSS
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 44 LCD drive waveform (1/3 bias)
43
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●value of high-order 6-bit counter
●value of STP instruction disable bit
●value of count source selection bit.
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software runaway).
The watchdog timer consists of an 8-bit watchdog timer L and a 6bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 0037 16), the watchdog timer is set to
“3FFF16.” When any data is not written to the watchdog timer control register (address 003716) after reset, the watchdog timer is in
stop state. The watchdog timer starts to count down from “3FFF16”
by writing an optional value into the watchdog timer control register (address 003716) and an internal reset occurs at an underflow.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0037 16) may be
started before an underflow. The watchdog timer does not function
when an optional value has not been written to the watchdog timer
control register (address 003716). When address 003716 is read,
the following values are read:
Data bus
“FF16” is set when
watchdog timer is
written to.
XCIN
“1”
Internal
system clock
selection bit
(Note)
“0”
Watchdog timer
L (8)
1/16
When bit 6 of the watchdog timer control register (address 003716)
is set to “0,” the STP instruction is valid. The STP instruction is
disabled by rewriting this bit to “1.” At this time, if the STP instruction is executed, it is processed as an undefined instruction, so
that a reset occurs inside.
This bit cannot be rewritten to “0” by programming. This bit is “0”
immediately after reset.
The count source of the watchdog timer becomes the system
clock φ divided by 8. The detection time in this case is set to 8.19 s
at f(XCIN) = 32 kHz and 32.768 ms at f(XIN) = 8 MHz.
However, count source of high-order 6-bit timer can be connected
to a signal divided system clock by 8 directly by writing the bit 7 of
the watchdog timer control register (address 003716) to “1.” The
detection time in this case is set to 32 ms at f(XCIN) = 32 kHz and
128 µs at f(XIN) = 8 MHz. There is no difference in the detection
time between the middle-speed mode and the high-speed mode.
Watchdog timer H count
source selection bit
“0”
“1”
Watchdog timer
H (6)
“3F16” is set when
watchdog timer is
written to.
XIN
Undefined instruction
Reset
STP instruction disable bit
STP instruction
RESET
Reset circuit
Internal reset
Reset release time wait
Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode.
Fig. 45 Block diagram of watchdog timer
b7
b0
Watchdog timer register (address 003716)
WDTCON
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF16” is set to the watchdog timer by writing values to this address.
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selecion bit
0 : Watchdog timer L underflow
1 : f(XIN)/16 or f(XCIN)/16
Fig. 46 Structure of watchdog timer control register
f(XIN)
Internal
reset signal
Watchdog timer detection
Fig. 47 Timing of reset output
44
≅ 1 ms (f(XIN) = 8 MHZ)
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TOUT/φ CLOCK OUTPUT FUNCTION
The internal system clock φ or timer 2 divided by 2 (TOUT output)
can be output from port P43 by setting the TOUT/φ output control
bit (bit 1) of the timer 123 mode register and the T OUT/φ output
control register. Set bit 3 of the port P4 direction register to “1”
when outputting the clock.
b7
b0
TOUT /φ output control register
(CKOUT : address 002A 16)
TOUT /φ output control bit
0 : φ clock output
1 : TOUT output
Not used (return “0” when read)
b7
b0
Timer 123 mode register
(T123M : address 0029 16)
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT /φ output control bit
0 : TOUT /φ output disabled
1 : TOUT /φ output enabled
Timer 2 write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN )/16
(or f(XCIN )/16 in low-speed mode ✽)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN )/16
(or f(XCIN )/16 in low-speed mode ✽)
Timer 1 count source selection bit
0 : f(XIN )/16
(or f(XCIN )/16 in low-speed mode ✽)
1 : f(XCIN )
Not used (return “0” when read)
✽ : Internal clock φ is f(XCIN)/2 in the low-speed mode.
φ output-related register
Fig. 48 Structure of TOUT/φ
45
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input
voltage is less than 0.2 VCC for VCC of VCC (min.).
RESET
VCC
Power
source
voltage
0V
Reset input
voltage
(Note)
0.2 VCC
0V
Note: Reset release voltage VCC = VCC (min.)
VCC
RESET
Power source voltage
detection circuit
Fig. 49 Example of reset circuit
XIN
φ
RESET
Internal reset
Reset address from
vector table
Address
?
?
?
?
FFFC
FFFD
ADL
Data
ADH, ADL
ADH
SYNC
XIN : about 8200
clock cycles
Fig. 50 Reset Sequence
46
Notes 1 : XIN and φ are in the relationship : f(XIN) = 8•f(φ)
2 : A question mark (?) indicates an undefined status that depends on the previous status.
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address
Register contents
(1) Port P0 direction register
000116
0016
(2) Port P1 direction register
000316
0016
(3) Port P2 direction register
000516
0016
(4) Port P3 output control register
000716
0016
(5) Port P4 direction register
000916
0016
(6) Port P5 direction register
000B16
0016
(7) Port P6 direction register
000D16
0016
(8) Port P7 direction register
000F16
0016
(9) Key input control register
001516
0016
(10) PULL register A
001616
3F16
(11) PULL register B
001716
0016
(12) Serial I/O1 status register
001916 1 0 0 0 0 0 0 0
(13) Serial I/O1 control register
001A16
(14) UART control register
001B16 1 1 1 0 0 0 0 0
(15) Serial I/O2 control register
001D16
0016
(16) Timer X (low)
002016
FF16
(17) Timer X (high)
002116
FF16
(18) Timer Y (low)
002216
FF16
(19) Timer Y (high)
002316
FF16
(20) Timer 1
002416
FF16
(21) Timer 2
002516
0116
(22) Timer 3
002616
FF16
(23) Timer X mode register
002716
0016
(24) Timer Y mode register
002816
0016
(25) Timer 123 mode register
002916
0016
(26) TOUT/φ output control register
002A16
0016
(27) PWM control register
002B16
0016
(28) D-A1 conversion register
003216
0016
(29) D-A2 conversion register
003316
0016
(30) A-D control register
003416 0 0 0 0 1 0 0 0
(31) D-A control register
003616
(32) Watchdog timer control register
003716 0 0 1 1 1 1 1 1
(33) Segment output enable register
003816
0016
(34) LCD mode register
003916
0016
(35) Interrupt edge selection register 003A16
0016
0016
0016
(36) CPU mode register
003B16 0 1 0 0 1 0 0 0
(37) Interrupt request register 1
003C16
0016
(38) Interrupt request register 2
003D16
0016
(39) Interrupt control register 1
003E16
0016
(40) Interrupt control register 2
003F16
0016
(41) Processor status register
(42) Program counter
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
(43) Watchdog timer (high-order)
3F16
(44) Watchdog timer (low-order)
FF16
Note: The contents of all other registers and RAM are undefined after
reset, so they must be initialized by software.
✕ : Undefined
Fig. 51 Internal state of microcomputer immediately after reset
47
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7560 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No external resistor is needed between X IN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the X OUT pin open. The sub-clock X CIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the X IN oscillation circuit starts
oscillating, and XCIN and XCOUT pins go to high-impedance state.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2)High-speed mode
The internal clock φ is half the frequency of XIN.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and X IN and X CIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either X IN or X CIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2.
The bits of the timer 123 mode register except bit 4 are cleared to
“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled
(“0”) before executing the STP instruction.
Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize when a ceramic resonator is used.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
(3) Low-speed mode
• The internal clock φ is half the frequency of XCIN.
• A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power-on and at returning from stop
mode. When switching the mode between middle/highspeed and low-speed, set the frequency in the condition
that f(XIN) > 3•f(XCIN).
XCIN XCOUT
Rf
XIN
Rd
CCOUT
CCIN
XOUT
CI N
COUT
Fig. 52 Ceramic resonator circuit
XCIN
Rf
XCOUT
XIN
XOUT
Open
Rd
External oscillation circuit
CCIN
CCOUT
VCC
VSS
Fig. 53 External clock input circuit
48
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
XIN
XOUT
Timer 1 count
source selection
bit
Internal system clock selection bit
(Note)
Low-speed mode
“0”
1/2
“1”
Middle-/High-speed mode
Timer 2 count
source selection
bit
“1”
1/4
1/2
Timer 1
“0”
“0”
Timer 2
“1”
Main clock division ratio selection bit
Middle-speed mode
“1”
Timing φ
(Internal clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
S
R
STP instruction
WIT
instruction
R
Q
Q
S
R
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note: When using the low-speed mode, set the XC switch bit to “1”.
Fig. 54 Clock generating circuit block diagram
49
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode
(φ = 1 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM6
High-speed mode
(φ = 4 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM7
”
“0
CM5
“1”
5
CM”
“1 M6
C
”
“1
Low-speed mode
(φ = 16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 1 (XIN stopped)
”
“0
CM6
“1”
“0”
Low-speed mode
(φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
C
“0 M5
CM ”
“1
6
”
“1
”
“0
”
“0”
“0”
“0”
“1”
CM5
“1”
CM6
Low-speed mode
(φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
“1”
“1”
CM7
“0”
“0”
“0”
“1”
Low-speed mode
(φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 1 (XIN stopped)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Xc switch bit
0: Oscillation stop
1: XCIN, XCOUT
CM5 : Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
CM6 : Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
CM7 : Internal system clock selection bit
0: XIN–XOUT selected
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes 1: Switch the mode by the arrows shown between the mode blocks. (Do not switch between the mode directly without an arrow.)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait
mode is ended.
3: Timer and LCD operate in the wait mode.
4: When the stop mode is ended, a delay time can be set by timer 1 and timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay time in low-speed mode can be set as well.
6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/highspeed mode.
7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 55 State transitions of system clock
50
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Interrupt
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a
BBC or BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to
“1”.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
In serial I/O2, the SOUT2 pin goes to high impedance state after
transmission is completed.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500kHz during an A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direction registers.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, refer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.mesc.co.jp/indexe.htm).
51
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 12 Absolute maximum ratings
Symbol
VCC
VI
Parameter
Conditions
VI
VI
VI
VI
VI
VI
VO
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
All voltages are based on VSS.
Output transistors are cut off.
VO
Output voltage P00–P07, P10–P15, P30–P37
At output port
At segment output
VO
VO
VO
VO
Pd
Topr
Tstg
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
Ta = 25°C
Ratings
–0.3 to 6.5
Unit
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VCC
–0.3 to VL3
V
V
V
V
V
V
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 6.5
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
V
V
V
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Table 13 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
VCC
Power source voltage
VSS
VREF
AVSS
VIA
Power source voltage
A-D, D-A conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
52
Min.
4.0
2.2
2.2
Limits
Typ.
5.0
5.0
5.0
0
2.0
Max.
5.5
5.5
5.5
VCC
0
AVSS
VCC
Unit
V
V
V
V
V
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Recommended operating conditions (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Parameter
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
Min.
Limits
Typ.
Max.
Unit
0.7 VCC
VCC
V
0.8 VCC
VCC
V
0.8 VCC
0.8 VCC
VCC
VCC
V
V
0
0.3 VCC
V
0
0.2 VCC
V
0
0
0.2 VCC
0.2 VCC
V
V
Table 15 Recommended operating conditions (3) (VCC = 2.2 to 2.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Parameter
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
Min.
Limits
Typ.
Max.
Unit
0.8 VCC
VCC
V
0.95 VCC
VCC
V
0.95 VCC
0.95 VCC
VCC
VCC
V
V
0
0.2 VCC
V
0
0.05 VCC
V
0
0
0.05 VCC
0.05 VCC
V
V
53
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Recommended operating conditions (4) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
IOH(peak)
“H” peak output current
IOL(peak)
“L” peak output current
IOL(peak)
“L” peak output current
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
“L” peak output current
“H” average output current
“H” average output current
“L” average output current
IOL(avg)
“L” average output current
IOL(avg)
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P40, P71–P77 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P40, P71–P77 (Note 3)
Min.
Limits
Typ.
Max.
–20
–20
20
20
80
–10
–10
10
10
40
–1.0
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
–5.0
mA
5.0
mA
10
mA
20
–0.5
–2.5
2.5
mA
mA
mA
mA
5.0
mA
10
mA
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
54
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17 Recommended operating conditions (5) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
f(CNTR0)
f(CNTR1)
Parameter
Input frequency for timers X and Y
(duty cycle 50%)
Test conditions
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
f(XIN)
Main clock input oscillation frequency
(Note 1)
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
Min.
Limits
Typ.
Max.
4.0
Unit
MHz
(10✕VCC
–4)/9 MHz
8.0
MHz
(20✕VCC
–8)/9 MHz
MHz
8.0
32.768
kHz
50
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
55
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage
P00–P07, P10–P15, P30–P37
VOH
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
VOL
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
ILOAD
ILEAK
56
“L” output voltage
P00–P07, P10–P15, P30–P37
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
“L” output voltage
P40, P71–P77
Test conditions
IOH = –1 mA
IOH = –0.25 mA
VCC = 2.2 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 2.2 V
IOL = 5 mA
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.2 V
IOL = 10 mA
IOL = 3.0 mA
IOL = 2.5 mA
VCC = 2.2 V
IOL = 10 mA
IOL = 5 mA
VCC = 2.2 V
Hysteresis
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
Hysteresis
SCLK, RXD, SIN2
Hysteresis
RESET
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
VI = VCC
P50–P57, P60–P67, P70–P77
“H” input current RESET
VI = VCC
“H” input current XIN
VI = VCC
VI = VSS
Pull-ups “off”
“L” input current
VCC = 5 V, VI = VSS
P00–P07,P10–P17, P20–P27,P41–P47,
Pull-ups “on”
P50–P57, P60–P67
VCC = 2.2 V, VI = VSS
Pull-ups “on”
“L” input current P40, P70–P77
“L” input current RESET
VI = VSS
“L” input current XIN
VI = VSS
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
Output load current
P30–P37
VCC = 2.2 V,VO = VCC, Pullup ON
Output transistors “off”
Output leak current
P30–P37
VO = VCC, Pullup OFF
Output transistors “off”
VO = VSS, Pullup OFF
Output transistors “off”
Limits
Min.
VCC–2.0
Typ.
Max.
Unit
V
VCC–0.8
V
VCC–2.0
VCC–0.5
V
V
VCC–0.8
V
2.0
0.5
V
V
0.8
V
2.0
0.5
V
V
0.8
V
0.5
V
0.3
V
0.5
V
0.5
0.5
V
V
5.0
µA
5.0
µA
µA
–5.0
µA
4.0
–60.0
–120.0
–240.0
µA
–5.0
–20.0
–40.0
µA
–5.0
–5.0
µA
µA
µA
–4.0
–60.0
–120.0
–240.0
µA
–5.0
–20.0
–40.0
µA
5.0
µA
–5.0
µA
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Electrical characteristics (2) (VCC =2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VRAM
Parameter
RAM retention voltage
Test conditions
Min.
Limits
Typ.
2.0
At clock stop mode
• High-speed mode, VCC = 5 V
Max.
5.5
Unit
V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
8.0
15
mA
2.5
4.0
mA
45
67
µA
23
46
µA
18
36
µA
8
16
µA
0.1
1.0
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
VL1
Power source voltage
IL1
Power source current
(VL1)
(Note)
When using voltage multiplier
VL1 = 1.8 V
Ta = 25 °C
µA
10
Ta = 85 °C
1.3
1.8
4.0
2.1
V
µA
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
57
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
Symbol
–
Parameter
Test conditions
Resolution
Absolute accuracy
(excluding quantization error)
VCC = VREF = 5 V
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
Reference power source input current
Analog port input current
VREF = 5 V
–
Min.
12
50
Limits
Typ.
35
150
Max.
8
±2
12.5
(Note)
100
200
5.0
Unit
Bits
LSB
µs
kΩ
µA
µA
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
Table 21 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted)
Symbol
–
–
tsu
RO
IVREF
Parameter
Test conditions
Min.
Limits
Typ.
Resolution
Absolute accuracy
Setting time
Output resistor
Reference power source input current
VCC = VREF = 5 V
VCC = VREF = 2.7 V
1
(Note)
3
2.5
Max.
8
1.0
2.0
4
3.2
Unit
Bits
%
%
µs
kΩ
mA
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
58
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
Parameter
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Table 23 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
Limits
Min.
2
125
45
40
900/(VCC+0.4)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
2000
950
950
400
300
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
59
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 24 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Limits
Min.
tC (SCLK1)/2–30
tC (SCLK1)/2–30
Typ.
Max.
140
–30
30
30
tC (SCLK2)/2–160
tC (SCLK2)/2–160
0.2 ✕ tC (SCLK2)
0
10
10
40
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 25 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Min.
tC (SCLK1)/2–50
tC (SCLK1)/2–50
Max.
350
–30
50
50
tC (SCLK2)/2–240
tC (SCLK2)/2–240
0.2 ✕ tC (SCLK2)
0
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
60
Limits
Typ.
20
20
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1 kΩ
Measurement output pin
Measurement output pin
100 pF
CMOS output
100 pF
N-channel open-drain output (Note)
Note: When P71–P77, P40 and bit 4 of the UART control
register (address 001B16 ) is “1” (N-channel opendrain output mode).
Fig. 56 Circuit for measuring output switching characteristics
61
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
C N TR 0 , C N TR 1
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0–INT2
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tf
SCLK1
SCLK2
0.2VCC
tC(SCLK1), tC(SCLK2)
tr
tWL(SCLK1), tWL(SCLK2)
0.8VCC
0.2VCC
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2)
RX D
SIN2
Fig. 57 Timing diagram
62
th(SCLK1-RXD),
th(SCLK2-SIN2)
0.8VCC
0.2VCC
td(SCLK1-TXD),td(SCLK2-SOUT2)
TX D
SOUT2
tWH(SCLK1), tWH(SCLK2)
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
Lead Material
Cu Alloy
MD
b2
HD
ME
Weight(g)
0.63
JEDEC Code
–
e
EIAJ Package Code
LQFP100-P-1414-0.50
D
76
100
l2
Recommended Mount Pad
75
1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
51
25
26
50
A
L1
F
A3
y
M
L
Detail F
100P6S-A
x
y
c
x
A1
b
A3
A2
e
b2
I2
MD
ME
Lp
MMP
EIAJ Package Code
QFP100-P-1420-0.65
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.1
0.2
0
1.4
–
–
0.13
0.18
0.28
0.105
0.125
0.175
13.9
14.0
14.1
13.9
14.0
14.1
0.5
–
–
15.8
16.0
16.2
15.8
16.0
16.2
0.3
0.5
0.7
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
0.1
–
–
0°
10°
–
0.225
–
–
0.9
–
–
14.4
–
–
14.4
–
–
Plastic 100pin 14✕20mm body QFP
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
81
1
b2
100
ME
HD
D
80
I2
Recommended Mount Pad
E
30
HE
Symbol
51
50
A
L1
c
A2
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
y
b
x
M
A1
F
e
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.65
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
–
–
0.1
–
0°
10°
–
–
0.35
–
–
1.3
14.6
–
–
–
–
20.6
63
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
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Specifications subject to change without notice.
REVISION HISTORY
Rev.
7560 GROUP DATA SHEET
Date
Description
Summary
Page
1.0
1.1
03/28/01
06/08/01
52
First Edition
Table 13 VREF Min. VCC+0.3 → VCC
(1/1)
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