HP HCPL-193K-300 Dual channel line receiver dual channel line receiver dual channel line receiver Datasheet

Dual Channel Line Receiver
Hermetically Sealed
Optocoupler
Technical Data
HCPL-1930
HCPL-1931
HCPL-193K
5962-89572
Features
Applications
Description
• Dual Marked with Device
Part Number and DSCC
Standard Microcircuit
Drawing
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and
Class K
• Hermetically Sealed 16-pin
Dual In-Line Package
• Performance Guaranteed
Over -55°C to +125°C
• High Speed – 10 Mb/s
• Accepts a Broad Range of
Drive Conditions
• Adaptive Line Termination
Included
• Internal Shield Provides
Excellent Common Mode
Rejection
• External Base Lead Allows
"LED Peaking" and LED
Current Adjustment
• 1500 Vdc Withstand Test
Voltage
• High Radiation Immunity
• HCPL-2602 Function
Compatibility
• Reliability Data Available
• Military and Space
• High Reliability Systems
• Isolated Line Receiver
• Simplex/Multiplex Data
Transmission
• Computer-Peripheral
Interface
• Microprocessor System
Interface
• Harsh Environmental
Environments
• Digital Isolation for A/D,
D/A Conversion
• Current Sensing
• Instrument Input/Output
Isolation
• Ground Loop Elimination
• Pulse Transformer
Replacement
The HCPL-193X devices are dual
channel, hermetically sealed,
high CMR, line receiver optocouplers. The products are capable of
operation and storage over the
full military temperature range
and can be purchased as either a
standard product or with full
MIL-PRF-38534 Class Level H or
K testing, or from the DSCC
Standard Microcircuit Drawing
(SMD) 5962-89572. This is a
sixteen pin DIP which may be
purchased with a variety of lead
bend and plating options. See
selection guide table for details.
Standard Microcircuit Drawing
(SMD) parts are available for each
lead style.
Truth Table
Functional Diagram
The connection of a 0.1 µF bypass capacitor between pins 15 and 10 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
All devices are manufactured and
tested on a MIL-PRF-38534
certified line and are included in
the DSCC Qualified Manufacturers List QML-38534 for Hybrid
Microcircuits.
Each unit contains two independent channels, consisting of a
GaAsP light emitting diode, an
input current regulator, and an
integrated high gain photon
detector. The input regulator
serves as a line termination for
line receiver applications. It
clamps the line voltage and
regulates the LED current so line
reflections do not interfere with
circuit performance. The regulator
allows a typical LED current of
12.5 mA before it starts to shunt
excess current. The output of the
detector IC is an open collector
Schottky clamped transistor. An
enable input gates the detector.
The internal detector shield
provides a guaranteed common
mode transient immunity specification of +1000 V/µsec.
Selection Guide–Package Styles and Lead
Configuration Options
Agilent Part # and Options
Commercial
MIL-PRF-38534 Class H
MIL-PRF-38534 Class K
Standard Lead Finish
Solder Dipped
Butt Joint/Gold Plate
Gull Wing/Soldered
Crew Cut/Gold Plate
Class H SMD Part #
Prescript for all below
Either Gold or Soldered
Gold Plate
Solder Dipped
Butt Joint/Gold Plate
Butt Joint/Soldered
Gull Wing/Soldered
Crew Cut/Gold Plate
Crew Cut/Soldered
Class K SMD Part #
Prescript for all below
Either Gold or Soldered
Gold Plate
Solder Dipped
Butt Joint/Gold Plate
Butt Joint/Soldered
Gull Wing/Soldered
HCPL-1930
HCPL-1931
HCPL-193K
Gold
Option #200
Option #100
Option #300
Option #600
59628957201EX
8957201EC
8957201EA
8957201YC
8957201YA
8957201XA
Available
Available
59628957202KEX
8957202KEC
8957202KEA
8957202KYC
8957202KYA
8957202KXA
DC specifications are compatible
with TTL logic and are guaranteed
from -55°C to +125°C allowing
trouble-free interfacing with
digital logic circuits. An input
current of 10 mA will sink a six
gate fan-out (TTL) at the output
with a typical propagation delay
from input to output of only
45 nsec.
3
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Device Marking
Agilent DESIGNATOR
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
* QUALIFIED PARTS ONLY
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Agilent CAGE CODE*
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
4
Hermetic Optocoupler Options
Option
100
Description
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option
is available on commercial and hi-rel product.
4.32 (0.170)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and
hi-rel product. DSCC Drawing part numbers contain provisions for lead finish.
300
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product. This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
2.29 (0.090)
2.79 (0.110)
600
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
5° MAX.
9.65 (0.380)
9.91 (0.390)
0.51 (0.020)
MAX.
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option
is available on commercial and hi-rel product. Contact factory for the availability of this option
on DSCC part types.
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
Note: Dimensions in millimeters (inches).
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.25 (0.049)
7.36 (0.290)
7.87 (0.310)
5
Absolute Maximum Ratings
Storage Temperature ................................................. -65°C to +150°C
Operating Temperature ............................................... -55°C to +125°C
Lead Solder Temperature ................................................ 260°C for 10 s
1.6 mm below seating plane
Forward Input Current – II (each channel) ................................. 60 mA2
Reverse Input Current ................................................................. 60 mA
Supply Voltage – VCC ....................................... 7 V (1 Minute Maximum)
Enable Input Voltage – VE (each channel) ...................................... 5.5 V
Not to exceed VCC by more than 500 mV
Output Collector Current – IO (each channel) ............................. 25 mA
Output Collector Power Dissipation (each channel) ................... 40 mW
Output Collector Voltage – VO (each channel) ................................... 7 V
Total Package Power Dissipation .............................................. 564 mW
Input Power Dissipation (each channel) ................................... 168 mW
Schematic
A 0.1 µF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN
PINS 10 AND 15 (SEE NOTE 1).
ESD Classification
(MIL-STD-883, Method 3015) .............................................. (∆), Class 1
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
IIL
0
250
µA
Input Current, High Level*
IIH
12.5
60
mA
Supply Voltage, Output
VCC
4.5
5.5
V
High Level Enable Voltage
VEH
2.0
VCC
V
Low Level Enable Voltage
VEL
0
0.8
V
5
TTL
Loads
125
°C
Fan Out (@ RL = 4 kΩ)
N
Operating Temperature
TA
-55
*12.5 mA condition permits at least 20% guardband for optical coupling variation. Initial
switching threshold is 10 mA or less.
6
Electrical Specifications TA = -55°C to 125°C unless otherwise stated. See note 15.
Parameter
Symbol
Test Conditions
High Level Output
Current
IOH
VCC = 5.5 V, VO = 5.5 V
II = 250 µA, VE = 2.0 V
Low Level
Output Voltage
VOL
VCC = 5.5 V; II = 10 mA
VE = 2.0 V,
IOL (Sinking) = 10 mA
Group A
Limits
Subgroups Min. Typ.* Max. Units Fig. Note
1, 2, 3
20
250
µA
3
3
1, 2, 3
0.3
0.6
V
1
3
2.2
2.6
V
2
3
2.35
2.75
II = 10 mA
Input Voltage
VI
1, 2, 3
II = 60 mA
Input Reverse
Voltage
VR
IR = 10 mA
1, 2, 3
0.8
1.10
V
3
Low Level Enable
Current
I EL
VCC = 5.5 V, VE = 0.5 V
1, 2, 3
-1.45
-2.0
mA
3
High Level Enable
Voltage
VEH
1, 2, 3
V
3, 12
Low Level Enable
Voltage
VEL
1, 2, 3
0.8
V
3
High Level
Supply Current
ICCH
VCC = 5.5 V; II = 0,
VE = 0.5 V both channels
1, 2, 3
21
28
mA
Low Level
Supply Current
ICCL
VCC = 5.5 V; II = 60 mA,
VE = 0.5 V both channels
1, 2, 3
27
36
mA
1
µA
Input-Output
Insulation
Leakage Current
II-O
Relative Humidity = 45%
t = 5 s,
VI-O = 1500 Vdc
Propagation Delay
Time to High
Output Level
t PLH
RL = 510 Ω; CL = 50 pF,
II = 13 mA,VCC = 5.0 V
Propagation Delay
Time to Low
Output Level
t PHL
Common Mode
Transient
Immunity at
High Output Level
Common Mode
Transient
Immunity at
Low Output Level
2.0
1
9
55
10, 11
|CMH|
|CML|
VCM = 50 V (peak),
VO (min.) = 2 V,
RL = 510 Ω; II = 0 mA,
VCC = 5.0 V
VCM = 50 V (peak),
VO (max.) = 0.8 V,
RL = 510 Ω; II = 10 mA,
VCC = 5.0 V
*All typical values are at VCC = 5 V, TA = 25°C.
100
ns
4, 5
3, 5
ns
4, 5
3, 6
140
9
RL = 510 Ω; CL = 50 pF,
II = 13 mA, VCC = 5.0 V
4
60
10, 11
100
120
9, 10, 11
1000
10,000
V/µs
8, 9
3, 9,
14
9, 10, 11
1000
10,000
V/µs
8, 9
3, 10,
14
7
Typical Specifications
TA = 25°C, VCC = 5 V
Parameter
Symbol
Typ.
Units
Test Conditions
Fig.
Note
Resistance (Input-Output)
R I-O
10
Ω
VI-O = 500 V dc
3, 13
Capacitance (Input-Output)
CI-O
1.7
pF
f = 1 MHz
3, 13
Input-Input Insulation
Leakage Current
II-I
0.5
nA
45% Relative Humidity,
VI-I = 500 Vdc, t = 5 s
11
Resistance (Input-Input)
R I-I
1012
Ω
VI-I = 500 Vdc
11
Capacitance (Input-Input)
CI-I
0.55
pF
f = 1 MHz
11
Propagation Delay Time of Enable
from VEH to VEL
tELH
35
ns
Propagation Delay Time of Enable
from VEL to VEH
tEHL
35
ns
Output Rise Time (10-90%)
tr
30
ns
Output Fall Time (90-10%)
tf
24
ns
Input Capacitance
CI
60
pF
12
RL = 510 Ω, CL = 15 pF,
II = 13 mA, V EH = 3 V, V EL = 0 V
RL = 510 Ω, CL = 15 pF, II = 13 mA
6, 7
3, 7
6, 7
3, 8
3
3
f = 1 MHz, VI = 0,
PINS 1 to 2 or 5 to 6
3
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each isolator. The power supply bus
for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to
suppress regenerative feedback via the power supply.
2. Derate linearly at 1.2 mA/°C above TA = 100°C.
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The tPLH propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing
edge of the output pulse.
6. The tPHL propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading
edge of the output pulse.
7. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point
on the trailing edge of the output pulse.
8. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point
on the leading edge of the output pulse.
9. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
VOUT > 2.0 V.
10. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
VOUT < 0.8 V.
11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted
together.
12. No external pull up is required for a high logic state on the enable input.
13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the
limits specified for all lots not specifically tested.
15. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
8
Figure 1. Input-Output
Characteristics.
Figure 2. Input Characteristics.
Figure 4. Propagation Delay vs.
Temperature.
Figure 5. Test Circuit for tPHL and tPLH.
Figure 6. Enable Propagation Delay vs.
Temperature.
Figure 7. Test Circuit for tEHL and t ELH.
Figure 3. High Level Output Current
vs. Temperature.
9
Figure 8. Typical Common Mode
Transient Immunity.
1
IIN
VIN
5V
16
A
2
B
3
14
4
13
5
12
VCC
15
6
11
7
GND 10
8
510 Ω
OUTPUT VO
MONITORING
0.01 µF NODE
BYPASS
9
VCM
+
–
PULSE GEN.
Figure 9. Test Circuit for Common
Mode Transient Immunity and Typical
Waveforms.
VCC
+5.5 V
VOUT
+2.6 V
100 Ω
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
200 Ω
100 Ω
200 Ω
–
VIN
+5.0 V
+
0.01 µF
CONDITIONS: II = 30 mA
IO = 10 mA
VCC = 5.5 V
Figure 10. Burn In Circuit.
TA = +125 °C
10
Application Circuits*
HCPL-193X
Figure A1. Polarity Non-Reversing.
HCPL-193X
Figure A2. Polarity Reversing, Split Phase.
11
Figure A3. Flop-Flop Configurations.
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent Technologies’ Hi-Rel
Optocouplers are in compliance
with MIL-PRF-38534 Class H and
K. Class H and Class K devices
are also in compliance with DSCC
drawing 5962-89572.
Testing consists of 100% screening and quality conformance
inspection to MIL-PRF-38534.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
Obsoletes 5967-5809E
5968-9401E (4/00)
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