AD AD5060ARJZ-1REEL7 Fully accurate 14-/16-bit vout nanodacâ ¢ spi interface 2.7 v to 5.5 v, in an sot-23 Datasheet

Fully Accurate 14-/16-Bit VOUT nanoDAC™
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5040/AD5060
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Single 14-/16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
SYNC interrupt facility
VREF
POWER-ON
RESET
VDD
AD5040/
AD5060
BUF
OUTPUT
BUFFER
DAC
REGISTER
REF(+)
VOUT
DAC
AGND
INPUT
CONTROL
LOGIC
RESISTOR
NETWORK
04767-001
POWER-DOWN
CONTROL LOGIC
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
SYNC
SCLK
DIN
DACGND
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD5040 and the AD5060, members of the ADI nanoDAC
family, are low power, single 14-/16-bit buffered voltage-out
DACs that operate from a single 2.7 V to 5.5 V supply. The
AD5040/AD5060 parts offer a relative accuracy specification
of ±1 LSB and operation are guaranteed monotonic with a
±1 LSB DNL specification. The parts use a versatile 3-wire serial
interface that operates at clock rates up to 30 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The reference for both the AD5040
and AD5060 is supplied from an external VREF pin. A reference
buffer is also provided on-chip. The AD5060 incorporates a
power-on reset circuit that ensures the DAC output powers up
to midscale or zero scale and remains there until a valid write
takes place to the device. The AD5040 and the AD5060 both
contain a power-down feature that reduces the current consumption of the device to typically 330 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The parts are put into power-down mode over the serial
interface. Total unadjusted error for the parts is <2 mV.
Both parts exhibit very low glitch on power-up.
1.
Available in a small, 8-lead SOT-23 package.
2.
14-/16-bit accurate, 1 LSB INL.
3.
Low glitch on power-up.
4.
High speed serial interface with clock speeds up to 30 MHz.
5.
Three power-down modes available to the user.
6.
Reset to known output voltage (midscale, zero scale).
Table 1. Related Devices
Part No.
AD5061
AD5062
AD5063
Description
2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23
2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23
2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved.
AD5040/AD5060
TABLE OF CONTENTS
Features .............................................................................................. 1
Reference Buffer ......................................................................... 15
Applications ....................................................................................... 1
Serial Interface ............................................................................ 15
General Description ......................................................................... 1
Power-On reset ........................................................................... 16
Functional Block Diagram .............................................................. 1
Software Reset ............................................................................. 16
Product Highlights ........................................................................... 1
Power-Down Modes .................................................................. 17
Revision History ............................................................................... 2
Microprocessor Interfacing ....................................................... 17
Specifications..................................................................................... 3
Applications..................................................................................... 19
Timing Characteristics..................................................................... 5
Choosing a Reference for the AD5040/ AD5060 ................... 19
Absolute Maximum Ratings............................................................ 6
Bipolar Operation Using the AD5040/ AD5060 .................... 19
ESD Caution .................................................................................. 6
Using the AD5040/AD5060 with a Galvanically Isolated
Interface Chip ............................................................................. 20
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Power Supply Bypassing and Grounding ................................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
DAC Architecture ....................................................................... 15
REVISION HISTORY
1/10—Rev. 0 to Rev. A
Changes to Table 2, Relative Accuracy (INL) and Endnote 1 .... 3
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5040/AD5060
SPECIFICATIONS
VDD = 5.5 V, VREF = 4.096 V @ RL = unloaded, CL = unloaded; TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
A, B, and Y Grades1
Min
Typ
Max
16
14
Relative Accuracy (INL)2
Total Unadjusted Error (TUE)2
Differential Nonlinearity (DNL)2
Gain Error
Gain Error Temperature Coefficient
Offset Error
Offset Error Temperature Coefficient
Full-Scale Error
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Voltage Settling Time
±0.5
±0.5
±0.5
±0.1
±0.1
±0.5
±2
±1
±1.5
±2.0
±2.0
±1
±0.5
±1
±0.01
±0.01
1
±0.02
±0.02
0.5
±0.05
±0.02
±0.03
±0.05
±2.0
±2.0
VREF
Test Conditions/Comments
Bits
Bits
LSB
LSB
AD5060
AD5040
−40°C to +85°C, AD5040/AD5060 A grade
−40°C to +85°C, AD5040/AD5060 B grade
−40°C to +125°C, AD5060 Y grade
−40°C to +85°C, AD5040/AD5060
−40°C to +125°C, AD5060 Y grade
Guaranteed monotonic,
−40°C to +85°C, AD5040/AD5060
Guaranteed monotonic,
−40°C to +125°C, Y grade
TA = −40°C to +85°C, AD5040/AD5060
TA = −40°C to +125°C AD5060 Y grade
mV
LSB
% of FSR
ppm of FSR/°C
mV
μV/°C
mV
TA = −40°C to + 85°C, AD5040/AD5060
TA = −40°C to + 125°C, AD5060 Y grade
All 1s loaded to DAC register,
AD5040 AD5060; TA = −40°C to +85°C
All 1s loaded to DAC register,
TA = −40°C to +125°C, AD5060 Y grade
4
V
μs
Output Noise Spectral Density
Output Voltage Noise
64
6
nV/√Hz
μV p-p
Digital-to-Analog Glitch Impulse
2
nV-s
Digital Feedthrough
DC Output Impedance (Normal)
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network)4
(Output Connected to 100 kΩ
Network)
Capacitive Load Stability
Slew Rate
0. 003
0. 015
nV-s
Ω
DAC code = midscale , 0.1 Hz to 10 Hz
bandwidth
1 LSB change around code 57386,
RL = 5 kΩ, CL = 200 pF
DAC code = full scale
Output impedance tolerance ±10%
1
100
kΩ
kΩ
Output impedance tolerance ±400 Ω
Output impedance tolerance ±20 kΩ
1. 2
nF
V/μs
60
ma
Loads used RL = 5 kΩ, RL = 100 kΩ, RL = ∞
¼ scale to ¾ scale code transition to
±1 LSB, RL = 5 kΩ, CL = 200 pF
DAC code = full scale, output shorted to
GND, TA = 25°C
DAC code = zero scale, output shorted to
VDD, TA = 25°C
Time to exit power-down mode to normal
mode of AD5060, 24th clock edge to 90%
of DAC final value, output unloaded
VDD ± 10%, DAC code = full scale
Short-Circuit Current
0
±1.5
±2.0
Unit
1
45
DAC Power-Up Time
4.5
μs
DC Power Supply Rejection Ratio
−92.11
db
Rev. A | Page 3 of 24
¼ scale to ¾ scale code transition to
±1 LSB, RL = 5 kΩ
DAC code = midscale, 1 kHz
AD5040/AD5060
Parameter
Wideband Spurious-Free Dynamic
Range (SFDR)
REFERENCE INPUT/OUTPUT
VREF Input Range5
Input Current (Power-Down)
Input Current (Normal)
DC Input Impedance
LOGIC INPUTS
Input Current6
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 2.7 V to 5.5 V
IDD (All Power-Down Modes)
VDD = 2.5 V to 5.5 V
A, B, and Y Grades1
Min
Typ
Max
−67
2
VDD − 50
±0.1
±0.5
1
±1
±2
0.8
0.8
2.0
1.8
Unit
db
mV
μA
μA
MΩ
μA
V
V
4
2.7
Test Conditions/Comments
Output frequency = 10 kHz
Zero scale loaded
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 3.6 V
pF
5.5
V
1.0
1.2
mA
0. 82
1. 0
0.33
1
0.065
μA
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIN = VDD and VIL = GND, VDD = 5.0 V,
VREF = 4.096 V, code = midscale
VIN = VDD and VIL = GND, VDD = 3.0 V,
VREF = 2.7 V, code = midscale
VIH = VDD and VIL = GND, VDD = 5.5 V,
VREF = 4.096 V, code = midscale
VIH = VDD and VIL = GND, VDD = 3.0 V,
VREF = 4.096 V, code = midscale
1
Temperature range for the A and B grades is −40°C to + 85° C, typical at 25°C; temperature range for the Y grade is −40°C to +125°C.
Linearity calculated using a reduced code range (160 to code 65535 for AD5060 ) and (40 to code 16383 for AD5040).
3
Guaranteed by design and characterization, not production tested.
4
1 kΩ power-down network not available with the AD5040.
5
The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 26.
6
Total current flowing into all pins.
2
Rev. A | Page 4 of 24
AD5040/AD5060
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit 1
33
5
3
10
3
2
0
12
9
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
2
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Maximum SCLK frequency is 30 MHz.
t4
t2
t1
t9
SCLK
t7
t3
t8
SYNC
t6
t5
DIN
D23
D22
D2
D1
Figure 2. AD5060 Timing Diagram
Rev. A | Page 5 of 24
D0
D23
D22
04767-002
1
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AD5040/AD5060
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREF to GND
Operating Temperature Range
Industrial (A, B Grade)
Extended Automotive Temperature
Range (Y Grade)
Storage Temperature Range
Maximum Junction Temperature
SOT-23 Package
Power Dissipation
θJA Thermal Impedance
θJc Thermal Impedance
Reflow Soldering (Pb-free)
Peak Temperature
Time-at-Peak Temperature
ESD (AD5040/AD5060)
Rating
−0.3 V to +7.0 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance integrated circuit with an
ESD rating of <2 kV. It is ESD sensitive. Proper precautions
should be taken for handling and assembly.
(TJ max − TA)/θJA
206°C/W
91°C/W
260°C
10 sec to 40 sec
1. 5 kV
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24
AD5040/AD5060
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
SCLK
VDD 2
AD5040/
AD5060
7
SYNC
VREF 3
TOP VIEW
(Not to Scale)
6
DACGND
5
AGND
VOUT 4
04767-003
DIN 1
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
DIN
2
3
4
5
6
7
VDD
VREF
VOUT
AGND
DACGND
SYNC
8
SCLK
Description
Serial Data Input. These parts have a 16-/24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND.
Reference Voltage Input.
Analog Output Voltage from DAC.
Ground Reference Point for Analog Circuitry.
Ground Input to the DAC Core.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 16th/24th clock cycle unless SYNC is taken high before this edge, in which case
the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Rev. A | Page 7 of 24
AD5040/AD5060
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
VDD = 5.5V
VREF = 4.096V
TA = 25°C
1.4
1.2
1.0
0.8
0.6
VDD = 5.5V
VREF = 4.096V
TA = 25°C
0.5
0.4
INL ERROR (LSB)
0.3
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0.2
0.1
0
–0.1
–0.2
–0.3
–1.6
160
10160
20160
30160
40160
DAC CODE
50160
–0.5
–0.6
160
60160
Figure 4. Typical AD5060 INL Plot
0.30
4360
6460
8560 10660
DAC CODE
12760
14860
VDD = 5.5V
VREF = 4.096V
TA = 25°C
DNL ERROR (LSB)
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
10160
20160
30160
40160
DAC CODE
50160
04767-060
–1.2
–1.4
–1.6
160
04767-039
DNL ERROR (LSB)
0.40
0.35
VDD = 5.5V
VREF = 4.096V
TA = 25°C
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.35
–0.40
160
60160
2260
4360
6460
8560 10660
DAC CODE
12760
14860
Figure 8. Typical AD5040 DNL Plot
Figure 5. Typical AD5060 DNL Plot
0.020
0.10
0.08
2260
Figure 7. Typical AD5040 INL Plot
1.6
1.4
1.2
1.0
0.8
0.6
0.4
04767-061
–0.4
04767-040
INL ERROR (LSB)
1.6
VDD = 5.5V
VREF = 4.096V
TA = 25°C
0.015
VDD = 5.5V
VREF = 4.096V
TA = 25°C
0.06
0.010
TUE ERROR (mV)
0.02
0
–0.02
0.005
0
–0.005
–0.04
–0.010
–0.06
10160
20160
30160
40160
DAC CODE
50160
–0.020
160
60160
04767-062
–0.08
–0.10
160
–0.015
04767-041
TUE ERROR (mV)
0.04
2260
4360
6460
8560 10660 12760 14860 16960
DAC CODE
Figure 9. Typical AD5040 TUE Plot
Figure 6. Typical AD5060 TUE Plot
Rev. A | Page 8 of 24
AD5040/AD5060
1.6
TA = 25°C
0.8
0.6
OFFSET ERROR (mV)
MAX INL ERROR @ VDD = 5.5V
0.4
0.2
0
–0.2
–0.4
–0.6
MIN INL ERROR @ VDD = 5.5V
–0.8
–1.4
–1.6
2.0
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
04767-067
04767-009
–1.0
–1.2
5.5
Figure 10. INL vs. Reference Input Voltage1
1.6
1.4
1.2
Figure 13. Typical Offset Error vs. Temperature1
0.5
TA = 25°C
0.3
0.8
0.6
0.4
GAIN ERROR (% FSR)
DNL ERROR (LSB)
1.0
MAX DNL ERROR @ VDD = 5.5V
0.2
0
–0.2
–0.4
–0.6
MIN DNL ERROR @ VDD = 5.5V
–0.8
–1.0
MAX GAIN ERROR @
VDD = 2.7V
MAX GAIN ERROR @
VDD = 5.5V
0.2
0.1
0
MIN GAIN ERROR @
VDD = 5.5V
–0.1
–0.2
MIN GAIN ERROR @
VDD = 2.7V
–0.3
04767-010
–1.2
–1.4
–1.6
2.0
VDD = 5.5V, VREF = 4.096V
VDD = 2.7V, VREF = 2.0V
0.4
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
–0.4
–0.5
–40
5.5
Figure 11. DNL vs. Reference Input Voltage1
20
40
60
80
TEMPERATURE (°C)
100
120
140
VDD = 5.5V, VREF = 4.096V
1.2 VDD = 2.7V, VREF = 2.0V
1.0
0.6
0.8
INL ERROR (LSB)
0.4
MAX TUE ERROR @ VDD = 5.5V
0.2
0
MIN TUE ERROR @ VDD = 5.5V
–0.2
–0.4
0.4
0.2
0
–0.4
–0.6
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
MIN INL ERROR @
VDD = 5.5V
MAX INL ERROR @
VDD = 5.5V
–0.2
–0.8
–1.0
MAX INL ERROR @
VDD = 2.7V
0.6
–0.6
04767-011
TUE ERROR (mV)
0
1.4
TA = 25°C
0.8
–1.2
2.0
–20
Figure 14. Typical Gain Error vs. Temperature1
1.2
1.0
04767-066
INL ERROR (LSB)
1.0
1.8
1.6 VDD = 5.5V, VREF = 4.096V
1.4 VDD = 2.7V, VREF = 2.0V
1.2
MAX OFFSET ERROR @
1.0
VDD = 2.7V
MAX OFFSET ERROR @
0.8
VDD = 5.5V
0.6
0.4
0.2
MIN OFFSET ERROR @
0
VDD = 5.5V
–0.2
–0.4
–0.6
MIN OFFSET ERROR @
–0.8
VDD = 2.7V
–1.0
–1.2
–1.4
–1.6
–1.8
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
MIN INL ERROR @
VDD = 2.7V
04767-069
1.4
1.2
–0.8
–1.0
–40
5.5
Figure 12. TUE vs. Reference Input Voltage1
–20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 15. Typical INL Error vs. Temperature1
1
AD5060 only.
Rev. A | Page 9 of 24
120
140
AD5040/AD5060
1.0
1.8
VDD = 5.5V, VREF = 4.096V
0.8 VDD = 2.7V, VREF = 2.0V
1.6
FULL-SCALE
THREE QUARTER SCALE
1.4
MAX DNL ERROR @
VDD = 2.7V
0.4
1.2
0.2
IDD (mA)
MAX DNL ERROR @
VDD = 5.5V
0
MIN DNL ERROR @
VDD = 5.5V
–0.2
1.0
MID-SCALE
QUARTER-SCALE
0.8
ZERO-SCALE
0.6
–0.4
MIN DNL ERROR @
VDD = 2.7V
0.4
–0.8
–1.0
–40
0.2
04767-071
–0.6
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
04767-044
DNL ERROR (LSB)
0.6
VDD = 5.5V
VREF = 4.096V
TA = 25°C
0
140
0
5M
10M
15M 20M 25M 30M
FREQUENCY (Hz)
35M
40M
45M
Figure 19. Typical Supply Current vs. Frequency @ 5.5 V1
Figure 16. Typical DNL Error vs. Temperature1
1.0
1.6
VDD = 5.5V, VREF = 4.096V
0.8 VDD = 2.7V, VREF = 2.0V
VDD = 3V
VREF = 2.5V
TA = 25°C
1.4
0.6
MAX TUE ERROR @
VDD = 5.5V
FULL-SCALE
1.0
MAX TUE ERROR @
VDD = 2.7V
0.2
0
MIN TUE ERROR @
VDD = 5.5V
–0.2
THREE QUARTER SCALE
1.2
IDD (mA)
TUE ERROR (mV)
0.4
0.8
MID-SCALE
0.6
ZERO-SCALE
–0.4
0.4
MIN TUE ERROR @
VDD = 2.7V
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
0
140
0
5M
10M
15M 20M 25M 30M
FREQUENCY (Hz)
35M
40M
45M
Figure 20. Typical Supply Current vs. Frequency @ 3 V1
Figure 17. Typical TUE Error vs. Temperature1
1.4
2.0
VDD = 5.5V, VREF = 4.096V
VDD = 2.7V, VREF = 2.0V
1.2
04767-045
–0.8
–1.0
–40
0.2
04767-068
–0.6
VREF = 2.5V
1.8 TA = 25°C
CODE = MIDSCALE
1.6
MAX IDD @
VDD = 5.5V
1.0
1.4
IDD (μA)
1.2
0.8
MAX IDD @
VDD = 2.7V
0.6
1.0
0.8
0.6
0.4
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
04767-015
0.4
0.2
04767-072
IDD (mA)
QUARTER-SCALE
0.2
0
2.5
140
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
Figure 21. Typical Supply Current vs. Supply Voltage1
Figure 18. Typical Supply Current vs. Temperature1
1
AD5060 only.
Rev. A | Page 10 of 24
6.0
AD5040/AD5060
3.00
TA = 25°C
2.75
VDD = 3V
DAC = FULL SCALE
VREF = 2.7V
TA = 25°C
2.50
2.25
IDD (mA)
2.00
1.75
1.50
VDD = 5.5V, VREF = 4.096V
1.25
1.00
0.75
VDD = 3.0V, VREF = 2.5V
0.25
0
0
10000
20000
30000
40000
DAC CODE
50000
60000
04767-020
04767-014
0.50
Y AXIS = 2μV/DIV
X AXIS = 4s/DIV
70000
Figure 22. Typical Supply Current vs. Digital Input Code1
Figure 25. 0.1 Hz to 10 Hz Noise Plot
0.50
24TH CLOCK FALLING
0.45
0.40
0.35
HEADROOM (V)
CH1 = SCLK
CH2 = VOUT
0.30
0.25
0.20
0.15
CH2 50mV/DIV
CH1 2V/DIV
0.05
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
REFERENCE VOLTAGE (V)
TIME BASE 400ns/DIV
Figure 23. AD5060 Digital-to-Analog Glitch Impulse
(See Figure 24)
VDD = 5V
VREF = 4.096V
R = 5kΩ
C = 220pF
CODE = 57386
0.113
0.112
5.00
DAC OUTPUT VOLTAGE (V)
0.115
0.114
0.111
0.110
0.109
0.108
0.107
0.106
0.105
4.95
4.90
4.85
4.80
4.75
4.70
4.65
0.104
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
04767-043
0.103
4.60
4.55
4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00
VREF (V)
SAMPLES
Figure 24. AD5060 Digital-to-Analog Glitch Energy
1
VDD = 5.0V
TA = 25°C
DAC = FULL-SCALE
04767-042
AMPLITUDE
Figure 26. VDD Headroom vs. Reference Voltage
5.05
0.117
0.116
0.102
0.101
04767-091
04767-017
0.10
Figure 27. Output Voltage vs. Reference Voltage
AD5060 only.
Rev. A | Page 11 of 24
AD5040/AD5060
5.005
C4 = 143mV p-p
VREF = 5V
TA = 25°C
ZERO-SCALE
DAC OUTPUT (V)
5.000
1kΩ TO GND
4.995
4.990
4.985
04767-065
4.975
04767-047
4.980
CH4 50.0mV
5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00
VDD (V)
M4.00μs
CH1
1.64V
Figure 31. Glitch upon Entering Software Power-Down to Zero Scale
Figure 28. Typical Output vs. Supply Voltage
CH3 = SCLK
1kΩ TO GND
ZERO-SCALE
C4 = 50mV p-p
CH2 = VOUT
CH1 2V/DIV CH2 2V/DIV
04767-048
04767-019
CH1 = TRIGGER
CH4 20.0mV
CH3 2V TIME BASE = 5.00μs
M1.00μs
CH1
1.64V
Figure 32. Glitch upon Exiting Software Power-Down to Zero Scale
Figure 29. Time to Exit Power-Down to Midscale
VDD = 5V
VREF = 4.096V
TA = 25°C
350
FULL-SCALE
C2
25mV p-p
300
250
200
C3
4.96V p-p
T
2
MID-SCALE
C3 FALL
935.0μs
150
T
50
ZERO-SCALE
1k
10k
FREQUENCY (Hz)
100k
Figure 30. Noise Spectral Density
3
04767-049
0
–50
100
C3 RISE
∞s
NO VALID
EDGE
QUARTER-SCALE
100
04767-046
NOISE SPECTRAL DENSITY (nV/ Hz)
400
CH3 2.00V
1M
CH2 50mV
M1.00ms
CH3
1.36V
Figure 33. Glitch upon Entering Hardware Power-Down to Three-State
Rev. A | Page 12 of 24
AD5040/AD5060
2.1
2.0
C2
30mV p-p
1.9
VDD = 5.5V
VREF = 4.096V
10% TO 90% RISE TIME = 0.688μs
SLEW RATE = 1.16V/μs
2.04V
1.8
C3
4.96V p-p
T
2
1.7
1.6
C3 FALL
∞s
NO VALID
EDGE
1.3
C3 RISE
946.2μs
1.2
1.04V
04767-050
3
CH3 2.00V
CH2 50mV
M1.00ms
CH3
1.1
1.0
–10μs –8μs –6μs –4μs –2μs
1.36V
Figure 34. Glitch upon Exiting Hardware Power-Down to Zero Scale
2μs
4μs
6μs
8μs 9.96μs
16
CODE = MID-SCALE
VDD = 5V, VREF = 4.096V
VDD = 3V, VREF = 2.5V
14
0.0006
12
0.0004
10
FREQUENCY
0.0002
0
8
6
–0.0002 VDD = 5.5V
4
–0.0004
VDD = 3V
–0.0008
–25
–20
–15
–10
2
04767-051
–0.0006
–5
0
5
10
CURRENT (mA)
15
20
25
0
30
04767-075
Δ VOLTAGE (V)
0
Figure 37. Typical Output Slew Rate
0.0010
0.0008
DAC
OUTPUT
1.4
04767-052
T
1.5
0.83
Figure 35. Typical Output Load Regulation
0.85
0.86
0.87 0.88
BIN
0.89
0.90
0.91 MORE
Figure 38. IDD Histogram VDD = 3.0 V
0.10
0.08
0.84
14
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
VDD = 3V, VREF = 2.5V
12
0.06
VDD = 3V, VREF = 2.5V
10
FREQUENCY
0.02
0
–0.02
–0.04
8
6
4
–0.06
–0.08
–0.10
–25
–20
–15
–10
–5
0
5
IOUT (mA)
10
15
20
25
30
Figure 36. Typical Current Limiting Plot
2
0
04767-076
VDD = 5V, VREF = 4.096V
04767-063
Δ VOUT (V)
0.04
1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11MORE
BIN
Figure 39. IDD Histogram VDD = 5.0 V
Rev. A | Page 13 of 24
AD5040/AD5060
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical AD5060 INL vs. code plot is shown in
Figure 4.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical AD5060 DNL vs. code plot is shown in Figure 5.
Offset Error
Offset error is a measure of the output error when zero code
(0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5040/AD5060 because the output of the DAC cannot go
below 0 V. This is due to a combination of the offset errors in
the DAC and output amplifier. Zero-code error is expressed
in mV.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF AD5060, 0x3FFF AD5040) is loaded to the DAC
register. Ideally, the output should be VDD − 1 LSB. Full-scale
error is expressed in percent of full-scale range.
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account. A typical AD5060 TUE vs.
code plot is shown in Figure 6.
Offset Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the worst case code 53786; see Figure 23 and Figure 24.
The expanded view in Figure 23 shows the glitch generated
following completion of the calibration routine; Figure 24
zooms in on this glitch.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus—that is, from all 0s to all 1s, and vice versa.
Gain Error
This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Rev. A | Page 14 of 24
AD5040/AD5060
THEORY OF OPERATION
SERIAL INTERFACE
The AD5040/AD5060 are single 14-/16-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V
to 5.5 V. Data is written to the AD5060 in a 24-bit word format,
and to the AD5040 in a 16-bit word format, via a 3-wire serial
interface.
The AD5060/AD5040 have a 3-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI, QSPI, and
MICROWIRE interface standards, as well as most DSPs.
Figure 2 shows a timing diagram of a typical AD5060 write
sequence.
Both the AD5040 and AD5060 incorporate a power-on reset
circuit that ensures the DAC output powers up to a known output state (midscale or zero-scale, see the Ordering Guide). The
devices also have a software power-down mode that reduces the
typical current consumption to less than 1 μa.
The write sequence begins by bringing the SYNC line low. For
the AD5060, data from the DIN line is clocked into the 24-bit
shift register on the falling edge of SCLK. The serial clock
frequency can be as high as 30 MHz, making these parts
compatible with high speed DSPs. On the 24th falling clock
edge, the last data bit is clocked in and the programmed
function is executed (that is, a change in the DAC output or a
change in the mode of operation).
DAC ARCHITECTURE
The DAC architecture of the AD5060 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 40. The 4 MSBs of the 16-bit data-word are decoded to
drive 15 switches, E1 to E15. Each of these switches connects
1 of 15 matched resistors to either DACGND or the VREF buffer
output. The remaining 12 bits of the data-word drive switches
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
At this stage, the SYNC line can be kept low or be brought
high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence so that a falling edge of
SYNC can initiate the next write sequence. Because the SYNC
buffer draws more current when VIH = 1.8 V than it does when
VIH = 0.8 V, SYNC should be idled low between write sequences
for an even lower power operation of the part. As previously
indicated, however, it must be brought high again just before
the next write sequence. The AD5040 requires 16 clock periods
to update the input shift register. On the 16th falling clock edge,
the last data bit is clocked in and the programmed function is
executed (that is, a change in the DAC output or a change in the
mode of operation).
VOUT
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
12-BIT R-2R LADDER
04767-027
VREF
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 40. AD5060 DAC Ladder Structure
REFERENCE BUFFER
Input Shift Register
The AD5040 andAD5060 operate with an external reference.
The reference input (VREF) has an input range of 2 V to
VDD − 50 mV. This input voltage is then used to provide a
buffered reference for the DAC core.
The AD5060 input shift register is 24 bits wide; see Figure 41.
PD1 and PD0 are control bits that control the operating mode
of the part—normal mode or any one of three power-down
modes (see the Power-Down Modes section for more detail).
The next 16 bits are the data bits. These are transferred to the
DAC register on the 24th falling edge of SCLK.
DB15 (MSB)
0
0
0
0
0
0
PD1
PD0
D15
D14
DB0 (LSB)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
NORMAL OPERATION
0
0
0
1
3-STATE
1
0
100kΩ TO GND
1
1
1kΩ TO GND
POWER-DOWN MODES
Figure 41. AD5060 Input Register Content
Rev. A | Page 15 of 24
04767-028
2R
AD5040/AD5060
The AD5040 input shift register is 16 bits wide; see Figure 42.
PD1 and PD0 are control bits that control the operating mode
of the part—normal mode or any one of two power-down
modes (see Power-Down Modes section for more detail). The
next 14 bits are the data bits. These are transferred to the DAC
register on the 16th falling edge of SCLK.
POWER-ON RESET
The AD5040 and AD5060 both contain a power-on reset
circuit that controls the output voltage during power-up. The
DAC register is filled with the zero-scale code or midscale code
and the output voltage is set to zero scale or midscale (see the
Ordering Guide for more details on the reset model). It remains
there until a valid write sequence is made to the DAC. This is
useful in applications where it is important to know the output
state of the DAC while it is in the process of powering up.
SYNC Interrupt
In a normal write sequence for the AD5060, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, the write sequence is
interrupted. The shift register is reset and the write sequence is
considered invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs; see Figure
43. In a normal write sequence for the AD5040, the SYNC line
is kept low for at least 16 falling edges of SCLK, and the DAC is
updated on the 16th falling edge. However, if SYNC is brought
high before the 16th falling edge, the write sequence is
interrupted. The shift register is reset and the write sequence is
considered invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs.
SOFTWARE RESET
The AD5060 device can be put into software reset by setting all
bits in the DAC register to 1; this includes writing 1s to Bit D23
and Bit D16, which is not the normal mode of operation. For
the AD5040 this includes writing 1s to Bit D15 and Bit D14,
which is also not the normal mode of operation. Note that the
SYNC interrupt command cannot be performed if a software
reset command is started in the AD5040 or AD5060.
DB13 (MSB)
PD1 PD0
D13
D12
DB0 (LSB)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
0
1
0
NORMAL OPERATION
3-STATE
POWER-DOWN MODES
100kΩ TO GND
04767-074
0
0
1
Figure 42. AD5040 Input Register Content
SCLK
DIN
DB23
DB0
DB23
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
Figure 43. AD5060 SYNC Interrupt Facility
Rev. A | Page 16 of 24
04767-031
SYNC
AD5040/AD5060
POWER-DOWN MODES
MICROPROCESSOR INTERFACING
The AD5060 features four operating modes, and the AD5040
features three operating modes. These modes are software programmable by setting two bits in the control register (Bit DB17
and Bit DB16 in the AD5060 and Bit DB15 and Bit DB14 in the
AD5040). Table 6 and Table 7 show how the state of the bits
corresponds to the operating mode of the two devices.
AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface
DB16
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes:
3-state
100 kΩ to GND
1 kΩ to GND
ADSP-2101/
ADSP-21031
AD5040/
AD50601
TFS
DT
SCLK
Table 7. Operating Modes for the AD5040
DB15
0
DB14
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes:
3-state
100 kΩ to GND
See Software Reset section
DIN
SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface
AD5040/AD5060 to 68HC11/68L11 Interface
In both the AD5060 and the AD5040, when the two most
significant bits are set to 0, the part has normal power
consumption. However, for the three power-down modes of the
AD5060 and the two power down modes of the AD5040, the
supply current falls to less than 1μA at 5 V (65 nA at 3 V). Not
only does the supply current fall, but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This is advantageous because the
output impedance of the part is known while the part is in
power-down mode. The output is connected internally to GND
through a 1 kΩ resistor (AD5060 only) or a 100 kΩ resistor, or
it is left open-circuited (three-stated). The output stage is
illustrated in Figure 44.
AD5040/
AD5060
SYNC
OUTPUT
BUFFER
Figure 46 shows a serial interface between the AD5040/
AD5060 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK pin of the AD5040/AD5060,
while the MOSI output drives the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface require that the
68HC11/68L11 be configured so that its CPOL bit is 0 and its
CPHA bit is 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured where its CPOL bit is 0 and its CPHA bit is 1, data
appearing on the MOSI output is valid on the falling edge of
SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit
bytes with only 8 falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. In order to load data to the
AD5040/AD5060, PC7 is left low after the first eight bits are
transferred, and a second serial write operation is performed to
the DAC. PC7 is taken high at the end of this procedure.
VOUT
DAC
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
04767-029
68HC11/
68L111
AD5040/
AD50601
PC7
SYNC
SCK
SCLK
MOSI
Figure 44. Output Stage During Power-Down
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY
The bias generator, the DAC core, and other associated linear
circuitry are all shut down when power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V;
see Figure 29.
Rev. A | Page 17 of 24
Figure 46. AD5040/AD5060 to 68HC11/68L11 Interface
04767-032
DB17
0
04767-030
Table 6. Operating Modes for the AD5060
Figure 45 shows a serial interface between the AD5040/AD5060
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP-2101/ADSP-2103 sport is programmed through the SPORT control register and should be
configured for internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
AD5040/AD5060
AD5040/AD5060 to Blackfin® ADSP-BF53x Interface
AD5040/AD5060 to MICROWIRE Interface
Figure 47 shows a serial interface between the AD5040/
AD5060 and the Blackfin ADSP-53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5040/AD5060, the setup for the interface is: DT0PRI
drives the SDIN pin of the AD5040/AD5060, while TSCLK0
drives the SCLK of the part; the SYNC is driven from TFS0.
Figure 49 shows an interface between the AD5040/AD5060 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5040/AD5060 on the rising edge of the SK.
AD5040/
AD50601
TSCLK0
SCLK
TFS0
SYNC
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. AD5040/AD5060 to Blackfin® ADSP-BF53x Interface
AD5040/AD5060 to 80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5060/
AD5040 and the 80C51/80L51 microcontroller. The setup
for the interface is: TxD of the 80C51/80L51 drives SCLK of
the AD5040/AD5060 while RxD drives the serial data line
of the part. The SYNC signal is again derived from a bitprogrammable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5040, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus only 8 falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a
format which has the LSB first. The AD5040/AD5060 require
data to be received with the MSB as the first bit. The
80C51/80L51 transmit routine should take this into account.
80C51/80L511
SYNC
TxD
SCLK
RxD
DIN
04767-034
AD5040/
AD50601
P3.3
CS
SYNC
SK
SCLK
SO
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY
DIN
04767-033
DT0PRI
AD5040/
AD50601
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5040/AD5060 to 80C51/80L51 Interface
Rev. A | Page 18 of 24
Figure 49. AD5040/AD5060 to MICROWIRE Interface
04767-035
ADSP-BF53x1
MICROWIRE1
AD5040/AD5060
APPLICATIONS
output noise in the 0.1 Hz to 10 Hz region. Table 8 shows
examples of recommended precision references for use as a
supply to the AD5040/AD5060.
CHOOSING A REFERENCE FOR THE AD5040/
AD5060
To achieve the optimum performance from the AD5040/
AD5060, carefully choose a precision voltage reference. The
AD5040/AD5060 have just one reference input, VREF. The
voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.
Table 8. Precision References for the AD5040/AD5060
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, ppm drift, long-term drift, and output voltage
noise. Initial accuracy on the output voltage of the DAC leads
to a full-scale error in the DAC. To minimize these errors, a
reference with high initial accuracy is preferred. Also, choosing
a reference with an output trim adjustment, such as an ADR43x
device, allows a system designer to trim out system errors by
setting a reference voltage to a voltage other than the nominal.
The trim adjustment can also be used at temperature to trim
out any errors.
Because the supply current required by the AD5040/AD5060 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended. This requires
less than 100 μA of quiescent current and can, therefore, drive
multiple DACs in one system, if required. It also provides very
good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range.
7V
SYNC
SCLK
DIN
0.1 Hz to 10 Hz
Noise (μV p-p typ)
8
3.4
10
10
8
BIPOLAR OPERATION USING THE AD5040/
AD5060
The AD5040/AD5060 have been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 51. The circuit shown yields an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD8675/AD820/AD8032 or an OP196/
OP295.
The output voltage for any input code can be calculated as
D ⎞ ⎛ R1 + R 2 ⎞
⎡
⎛ R 2 ⎞⎤
VO = ⎢V DD × ⎛⎜
⎟×⎜
⎟ − V DD × ⎜
⎟
⎝ 65536 ⎠ ⎝ R1 ⎠
⎝ R1 ⎠⎥⎦
⎣
where D represents the input code in decimal (0 to 65536,
AD5060).
With VREF = 5 V, R1 = R2 = 10 kΩ:
AD5040/
AD5060
10 × D ⎞
VO = ⎛⎜
⎟−5V
⎝ 65536 ⎠
VOUT = 0V TO 5V
Figure 50. ADR395 as Reference to AD5060/AD5040
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains relatively stable during
its entire lifetime. The temperature coefficient of a reference
output voltage affects INL, DNL, and TUE. A reference with a
tight temperature coefficient specification should be chosen to
reduce the temperature dependence of the DAC output voltage
on ambient conditions.
Using the AD5060, this is an output voltage range of ±5 V
with 0x0000 corresponding to a −5 V output and 0xFFFF
corresponding to a +5 V output .
R2 = 10kΩ
+5V
+5V
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the ADR435, produce low
Rev. A | Page 19 of 24
10μF
R1 = 10kΩ
0.1μF
VREF
AD5040/
AD5060
–
AD820/
OP295
+
VOUT
±5V
–5V
3-WIRE
SERIAL
INTERFACE
Figure 51. Bipolar Operation with the AD5040/AD5060
04767-037
3-WIRE
SERIAL
INTERFACE
Temp. Drift
(ppm/°C max)
3 (SO-8)
3 (SO-8)
3 (SO-8)
3 (SC70)
9 (TSOT-23)
5V
04767-036
ADR395
Part No.
ADR435
ADR425
ADR02
ADR02
ADR395
Initial
Accuracy
(mV max)
±2
±2
±3
±3
±5
AD5040/AD5060
USING THE AD5040/AD5060 WITH A
GALVANICALLY ISOLATED INTERFACE CHIP
POWER SUPPLY BYPASSING AND GROUNDING
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of
2.5 kV. Because the AD5040/AD5060 use a 3-wire serial logic
interface, the ADuM130x family provides an ideal digital
solution for the DAC interface.
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5040/
AD5060 should have separate analog and digital sections, each
having its own area of the board. If the AD5040/AD5060 are in
a system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5040/AD5060.
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.
Figure 52 shows a typical galvanically isolated configuration
using the AD5040/AD5060. The power supply to the part
also needs to be isolated; this is accomplished by using a
transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the
AD5040/AD5060.
5V
REGULATOR
10μF
POWER
0.1μF
VDD
V1A
V0A
SCLK
AD5040/
AD5060
ADuM1300
SDI
V1B
V0B
SYNC
DATA
V1C
V0C
DIN
VOUT
GND
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by a digital ground. Avoid crossover of digital and analog
signals, if possible. When traces cross on opposite sides of the
board, ensure that they run at right angles to each other to
reduce feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.
04767-038
SCLK
The power supply to the AD5040/AD5060 should be bypassed
with 10 μF and 0.1 μF capacitors. The capacitors should be
physically as close as possible to the device with the 0.1 μF
capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor has low effective series resistance (ESR) and
effective series inductance (ESI), as do common ceramic types
of capacitors. This 0.1 μF capacitor provides a low impedance
path to ground for high frequencies caused by transient
currents due to internal logic switching.
Figure 52. AD5040/AD5060 with a Galvanically Isolated Interface
Rev. A | Page 20 of 24
AD5040/AD5060
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
8
7
6
5
1
2
3
4
3.00
2.80
2.60
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.38 MAX
0.22 MIN
0.22 MAX
0.08 MIN
SEATING
PLANE
8°
4°
0°
0.60
BSC
0.60
0.45
0.30
121608-A
1.30
1.15
0.90
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5040BRJZ-500RL7
AD5040BRJZ-REEL7
AD5060ARJZ-1500RL7
AD5060ARJZ-1REEL7
AD5060ARJZ-2REEL7
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Maximum
INL
1 LSB
1 LSB
2 LSB
2 LSB
2 LSB
AD5060ARJZ-2500RL7
−40°C to +85°C
2 LSB
AD5060BRJZ-1500RL7
AD5060BRJZ-1REEL7
AD5060BRJZ-2REEL7
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1 LSB
1 LSB
1 LSB
AD5060BRJZ-2500RL7
−40°C to +85°C
1 LSB
AD5060YRJZ-1500RL7
AD5060YRJZ-1REEL7
EVAL-AD5060EBZ
−40°C to +125°C
−40°C to +125°C
±1.5 LSB
±1.5 LSB
1
Description
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to midscale
2.7 V to 5.5 V, reset to midscale
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to midscale
2.7 V to 5.5 V, reset to midscale
2.7 V to 5.5 V, reset to 0 V
2.7 V to 5.5 V, reset to 0 V
Z = RoHS Compliant Part.
Rev. A | Page 21 of 24
Package Description
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
Package
Option
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
Branding
D4C
D4C
D3Z
D3Z
D41
8 Lead SOT-23
RJ-8
D41
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
RJ-8
RJ-8
RJ-8
D3W
D3W
D3X
8 Lead SOT-23
RJ-8
D3X
8 Lead SOT-23
8 Lead SOT-23
Evaluation Board
RJ-8
RJ-8
D6F
D6F
AD5040/AD5060
NOTES
Rev. A | Page 22 of 24
AD5040/AD5060
NOTES
Rev. A | Page 23 of 24
AD5040/AD5060
NOTES
© 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04767-0-1/10(A)
Rev. A | Page 24 of 24
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