Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD17313Q2Q1 SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 CSD17313Q2Q1 30-V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • 1 Product Summary Qualified for Automotive Applications Optimized for 5-V Gate Drive Ultra-Low Qg and Qgd Low Thermal Resistance Pb-Free RoHS Compliant Halogen-Free SON 2-mm × 2-mm Plastic Package TA = 25°C 30 V Qg Gate Charge Total (4.5 V) 2.1 nC Qgd Gate Charge Gate-to-Drain Drain-to-Source On Resistance VGS(th) 0.4 31 mΩ VGS = 4.5 V 26 mΩ VGS = 8 V 24 mΩ Threshold Voltage PART NUMBER 3 Description This 30-V, 24-mΩ, 2-mm x 2-mm SON NexFET™ power MOSFET is designed to minimize losses in power conversion applications and is optimized for 5V gate drive applications. The 2-mm × 2-mm SON offers excellent thermal performance for the size of the package. 1.3 QTY MEDIA CSD17313Q2Q1 3000 13-Inch Reel CSD17313Q2Q1T 250 7-Inch Reel 1 6 PACKAGE SHIP SON 2-mm × 2-mm Plastic Package Tape and Reel Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage +10 / –8 V ID D D IDM Continuous Drain Current (package limited) 5 Continuous Drain Current (silicon limited), TC = 25°C 19 Continuous Drain Current(1) 7.3 Pulsed Drain Current, TA = 25°C(2) 57 (1) G 5 2 3 S 4 A A Power Dissipation 2.4 Power Dissipation, TC = 25°C 17 TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, Single Pulse, ID = 19A, L = 0.1mH, RG = 25Ω 18 mJ PD D S W (1) Typical RθJA = 53°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06-inch thick FR4 PCB. (2) Max RθJC = 7.4°C/W, pulse duration ≤100 μs, duty cycle ≤1%. P0108-01 Added text for spacing On State Resistance vs Gate to Source Voltage Gate Charge 80 8 TC = 25°C, I D = 4 A TC = 125°C, I D = 4 A 70 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) V (1) For all available packages, see the orderable addendum at the end of the data sheet. Top View D nC VGS = 3 V Ordering Information(1) DC-DC Converters Battery and Load Management Applications D UNIT Drain-to-Source Voltage RDS(on) 2 Applications • • TYPICAL VALUE VDS 60 50 40 30 20 10 ID = 4 A 7 VDS = 15 V 6 5 4 3 2 1 0 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 0 0.5 1 1.5 2 2.5 Qg - Gate Charge (nC) 3 3.5 4 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17313Q2Q1 SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q2 Package Dimensions .......................................... 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Pattern ................................. 9 Q2 Tape and Reel Information................................ 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D Page • Enhanced description ............................................................................................................................................................ 1 • Added 7-inch reel to Ordering Information table ................................................................................................................... 1 • Updated Continuous Drain Current ....................................................................................................................................... 1 • Updated pulsed current conditions ........................................................................................................................................ 1 • Updated Figure 1 to show RθJC curves .................................................................................................................................. 4 • Added VGS = 4.5 V line in Figure 8 ........................................................................................................................................ 6 • Updated the SOA in Figure 10 .............................................................................................................................................. 6 • Added Device and Documentation section. .......................................................................................................................... 9 Changes from Revision B (January 2013) to Revision C • Page Changed Figure 10, Maximum Safe Operating Area ............................................................................................................. 6 Changes from Revision A (November 2012) to Revision B Page • Changed the Recommended PCB Pattern............................................................................................................................. 9 • Added the Recommended Stencil Pattern ............................................................................................................................. 9 Changes from Original (October 2012) to Revision A • 2 Page Changed the device number From: CSD17313Q2-Q1 To: CSD17313Q2Q1 ........................................................................ 1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated CSD17313Q2Q1 www.ti.com SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage VGS = 0 V, VDS = 24 V IGSS Gate-to-source leakage VDS = 0 V, VGS = +10 / -8 V VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-source on resistance gfs Transconductance 30 0.9 V 1 μA 100 nA 1.3 1.8 V VGS = 3 V, ID = 4 A 31 42 mΩ VGS = 4.5 V, ID = 4 A 26 32 mΩ VGS = 8 V, ID = 4 A 24 30 mΩ VDS = 15 V, ID = 4 A 16 S DYNAMIC CHARACTERISTICS Ciss Input capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 260 340 pF Coss Output capacitance 140 180 pF Crss Reverse transfer capacitance 13 17 pF RG Series gate resistance 1.3 2.6 Ω Qg Gate charge total (4.5 V) 2.1 2.7 nC Qgd Gate charge – gate-to-drain 0.4 nC Qgs Gate charge – gate-to-source 0.7 nC Qg(th) Gate charge at Vth 0.3 nC Qoss Output charge 3.8 nC td(on) Turn on delay time 2.8 ns tr Rise time 3.9 ns td(off) Turn off delay time 4.2 ns tf Fall time 1.3 ns VDS = 15 V, ID = 4 A VDS = 13.5 V, VGS = 0 V VDS = 15 V, VGS = 4.5 V, ID = 4 A, RG = 2 Ω DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = 4 A, VGS = 0V 0.85 VDD= 13.5 V, IF = 4 A, di/dt = 300 A/μs 1 V 6.4 nC 12.9 ns 5.2 Thermal Information TA = 25°C (unless otherwise noted) TYP MAX UNIT RθJC Thermal resistance junction-to-case (1) THERMAL METRIC 7.4 °C/W RθJA Thermal resistance junction-to-ambient (1) (2) 67 °C/W (1) (2) MIN RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071=mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD17313Q2Q1 SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 www.ti.com Max RθJA = 67°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. G1 D1 S1 Max RθJA = 228°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. G1 S1 D1 M0179-01 M0180-01 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise noted) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated CSD17313Q2Q1 www.ti.com SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 Typical MOSFET Characteristics (continued) 10 10 9 9 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TA = 25°C (unless otherwise noted) 8 7 6 5 4 3 2 VGS = 3.0 V VGS = 4.5 V VGS = 8.0 V 1 TC = 125°C TC = 25°C TC = -55°C 8 7 6 5 4 3 2 1 0 0 0 0.1 0.2 0.3 0.4 VDS - Drain-to-Source Voltage (V) 0.5 1 1.2 Figure 2. Saturation Characteristics 2000 7 1000 6 5 4 3 2 2.8 3 D003 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 100 1 10 0 0 0.5 1 1.5 2 2.5 Qg - Gate Charge (nC) ID = 4 A 3 3.5 0 4 5 D004 Figure 4. Gate Charge 25 30 D005 Figure 5. Capacitance 80 RDS(on) - On-State Resistance (m:) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 -75 10 15 20 VDS - Drain-to-Source Voltage (V) VDS = 15 V 1.6 VGS(th) - Threshold Voltage (V) 1.6 1.8 2 2.2 2.4 2.6 VGS - Gate-to-Source Voltage (V) Figure 3. Transfer Characteristics 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 1.4 D002 TC = 25°C, I D = 4 A TC = 125°C, I D = 4 A 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Copyright © 2012–2015, Texas Instruments Incorporated 175 D006 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 ID = 4 A Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback 5 CSD17313Q2Q1 SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise noted) 10 1.6 VGS = 4.5 V VGS = 8 V 1.4 1.2 1 0.8 0.6 -75 TC = 25°C TC = 125°C ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.8 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 0 175 0.2 D008 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 ID = 4 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 DC 10 ms 1 ms 0.1 0.1 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25qC TC = 125qC 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single Pulse, Max RθJC = 7.4°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (°C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated CSD17313Q2Q1 www.ti.com SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 CSD17313Q2Q1 SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information 7.1 Q2 Package Dimensions D2 D K3 K1 K K2 5 4 6 E2 4 8 K4 E 7 E1 5 E3 6 Pin 1 Dot 3 2 3 L 1 Top View 2 1 Pin 1 ID e b D1 Pinout A A1 C Bottom View Source 4, 7 Gate 3 Drain 1, 2, 5, 6, 8 Front View M0175-02 MILLIMETERS DIM NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 0.300 0.002 0.012 C 0.203 TYP 0.008 TYP D 2.000 TYP 0.080 TYP D1 0.900 0.950 1.000 0.036 0.038 D2 0.300 TYP 0.012 TYP E 2.000 TYP 0.080 TYP E1 0.900 E2 1.000 1.100 0.036 0.040 0.280 TYP 0.0112 TYP E3 0.470 TYP 0.0188 TYP e 0.650 BSC 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP K4 0.470 TYP 0.0188 TYP L 8 INCHES MIN 0.200 Submit Documentation Feedback 0.25 0.300 0.008 0.010 0.014 0.040 0.044 0.012 Copyright © 2012–2015, Texas Instruments Incorporated CSD17313Q2Q1 www.ti.com SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note Reducing Ringing through PCB Layout Techniques, (SLPA005). 7.3 Recommended Stencil Pattern Note: All dimensions are in mm, unless otherwise specified. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 CSD17313Q2Q1 SLPS427D – OCTOBER 2012 – REVISED SEPTEMBER 2015 www.ti.com 7.4 Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 108 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD17313Q2Q1 ACTIVE WSON DQK 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 150 733Q CSD17313Q2Q1T ACTIVE WSON DQK 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 150 733Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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