LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 LM4935 Boomer™ Audio Power Amplifier Series Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC Check for Samples: LM4935, LM4935RLEVAL 1 Introduction 1.1 Features 1234 • • • • • • • • • • • • • • • • 18-Bit Stereo DAC 16-Bit Mono ADC 12-Bit 4 Input Multipurpose SAR ADC 8 kHz to 48 kHz Stereo Audio Playback 8 kHz to 48 kHz Mono Recording 1 Hz to 13.888 kHz Sample Rate on all 4 SAR Channels Bidirectional PCM/I2S Compatible Audio Interface Sigma-Delta PLL for Operation from any Clock at any Sample Rate Low Power Clock Network Operation if 12 MHz System Clock is Available Read/write I2C or SPI Compatible Control Interface 33mW Stereo Headphone Amplifier at 3.3V OCL or AC-coupled Headphone Operation Automatic Headphone & Microphone Detection Support for Internal and External Microphones Automatic Gain Control for Microphone Input High Efficiency BTL 8Ω Amplifier, 600 mW @ 3.3V 1.2 • 115 mW Earpiece Amplifier at 3.3V • Differential Audio I/O for External Cellphone Module • Mono Differential Auxiliary Output • Stereo Auxiliary Inputs • Differential Microphone Input for Internal Microphone • Flexible Audio Routing from Input to Output • 32 Step Volume Control for Mixers with 1.5 dB Steps • 16 Step Volume Control for Microphone in 2 dB Steps • Programmable Sidetone Attenuation in 3 dB Steps • DC Volume Control • Two Configurable GPIO Ports • Programmable Voltage Triggers on SAR Channels • Multi-function IRQ Output • Micro-power Shutdown Mode • Available in the 4 x 4 mm 49-Bump DSBGA Package Key Specifications 567 • PHP (AC-COUP) @ A_VDD = 3.3V, 32Ω, 1% THD: 33 mW • PHP (OCL) @ A_VDD = 3.3V, 32Ω, 1% THD: 31 mW • PLS @ LS_VDD = 5V, 8Ω, 1% THD: 1.3 W • PLS @ LS_VDD = 4.2V, 8Ω, 1% THD: 900 mW • Supply Voltage Range – BB_VDD = 1.8V to 4.5V, – D_VDD & PLL_VDD = 2.7V to 4.5V • • • • • • – LS_VDD & A_VDD = 2.7V to 5.5V PLS @ LS_VDD = 3.3V, 8Ω, 1% THD: 600 mW Shutdown Current: 1.1 µA PSRR @ 217 Hz, A_VDD = 3.3V, (Headphone): 60 dB SNR (Stereo DAC to AUXOUT): 88 dB (typ) SNR (Mono ADC from Cell Phone In): 90 dB (typ) SNR (Aux In to Headphones): 98 dB (typ) 1 2 3 4 5 6 7 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. I2C is a trademark of NXP. All other trademarks are the property of their respective owners. Boomer is a trademark of Texas Instruments. I2C is a trademark of NXP. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 1.3 • • • • • www.ti.com Applications Smartphones Mobile Phones and Multimedia Terminals PDAs, Internet Appliances and Portable Gaming Portable DVD/CD/AAC/MP3 Players Digital Cameras/Camcorders 1.4 Description The LM4935 is an integrated audio subsystem that supports both analog and digital audio functions. The LM4935 includes a high quality stereo DAC, a mono ADC, a multi-purpose SAR ADC, a stereo headphone amplifier, which supports output cap-less (OCL) or AC-coupled (SE)modes of operation, a mono earpiece amplifier and a mono high efficiency loudspeaker amplifier. It is designed for demanding applications in mobile phones and other portable devices. The LM4935 features a bi-directional I2S serial interface for full range audio and an I2C™ or SPI compatible interface for control. The stereo DAC path features an SNR of 88 dB with an 18-bit 48 kHz input. In SE mode the headphone amplifier delivers at least 33 mWRMS to a 32Ω single-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono earpiece amplifier delivers at least 115 mWRMS to a 32Ω bridged-tied load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono speaker amplifier delivers up to 600 mW into an 8Ω load with less than 1% distortion when LS_VDD = 3.3V and up to 1.3W when LS_VDD = 5.0V. The LM4935 also contains a general purpose SAR ADC for housekeeping duties such as battery and temperature monitoring. This can also be used for analog volume control of the output stages and can trigger interrupt events. The LM4935 employs advanced techniques to reduce power consumption, to reduce controller overhead to speed development time and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. It is therefore ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area and cost are primary requirements. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 Introduction Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com 1 2 3 SNAS296E – OCTOBER 2005 – REVISED MAY 2013 .............................................. ............................................. 1.2 Key Specifications ................................... 1.3 Applications .......................................... 1.4 Description ........................................... Device Information ...................................... 2.1 LM4935 Overview ................................... 2.2 Typical Application ................................... 2.3 Connection Diagrams ................................ 2.4 PIN TYPE DEFINITIONS ............................ Electrical Specifications ............................... 3.1 Absolute Maximum Ratings .......................... Introduction 1 1.1 1 Features ................................... 8 ............................ 9 Application Information .............................. 15 4.1 System Control ..................................... 15 4.2 Status & Control Registers ......................... 18 Typical Performance Characteristics ............. 46 Board Schematic Diagrams ......................... 82 3.2 Operating Ratings 3.3 Electrical Characteristics 5 6.1 LM4935 Demonstration Board Schematic Diagram 82 5 6.2 Demoboard PCB Layout 82 7 6.3 8 6.4 ........................... Product Status Definitions .......................... Revision History .................................... 1 4 2 2 4 4 5 6 84 85 8 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Contents 3 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 2 Device Information POWER MANAGEMENT and CONTROL CLOCKS and 6'_PLL MCLK AB AUX_OUT AB EP_OUT D LS_OUT CPI PLL_FLT RIGHT LM4935 Overview LEFT 2.1 BB_VDD D_VDD SCL/SCK SDA/SDI 2 I C/SPI SLAVE SDO GPIO1 GPIO2 6' ADC HP_VMIDFB HP_VMID AB HPL_OUT AB HPR_OUT 6' DAC SAR ADC IRQ VSAR2 BYPASS AMP BIAS and DET -46.5 dB to 12 dB A_VDD/2 D_VDD/2 BB_VDD SIDETONE SDI REGISTERS G7.11 WS DIGITAL AUDIO INTERFACE CLK LEVEL SHIFTERS TEST_MODE/CS SPI_MODE BG 0 dB to -30 dB VREF_FLT MIC BIAS and DET EXT_BIAS MIC_DET EXT_MIC 6 dB to MIC 36 dB VSAR1 INT_BIAS INT_MIC AUX_R AUX_L AB AUTO GAIN CONTROL DC VOLUME CONTROL -34.5 dB to 12 dB CP_OUT CP_IN Figure 2-1. Conceptual Schematic 4 Device Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com 2.2 SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Typical Application Synthesized FM Radio/ Analog Inputs LM4670 Can Be Used for Stereo Loudspeakers AUX_L AUX_R BYPASS VREF_FLT PLL_FILT AUX_OUT LM4670 GPIO1 0.5-30 MHz LS MCLK EP 2 INT_BIAS I S/PCM INT_MIC Baseband Controller BB_VDD 2 I C IRQ VSAR2 LM94022 Temperature Diode VSAR1 HP_VMIDFB MIC_DET EXT_BIAS EXT_MIC HP_VMID HP_R HP_L CP_OUT CP_IN LM4935 Analog General Purpose Interface (for volume control, battery monitor, joystick, contrast, etc...) Radio Module Figure 2-2. Example Application in Multimedia Mobile Phone 2.3 Connection Diagrams 7 6 5 4 3 2 1 A B C D E F G Figure 2-3. 49-Bump DSBGA (Top View) (Bump Side Down) See YPG0049 Package Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Device Information 5 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Table 2-1. PIN DESCRIPTIONS 6 Pin Pin Name Type Direction A1 EP_NEG Analog Output Description Earpiece negative output A2 A_VDD Supply Input Headphone and mixer VDD A3 INT_MIC_POS Analog Input Internal microphone positive input A4 EXT_MIC Analog Input External microphone input A5 VSAR2 Analog Input Input to SAR channel 2 A6 VSAR1 Analog Input Input to SAR channel 1 A7 PLL_VSS Supply Input PLL VSS B1 A_VSS Supply Input Headphone and mixer VSS B2 EP_POS Analog Output B3 INT_MIC_NEG Analog Input Internal microphone negative input B4 BYPASS Analog Inout A_VDD/2 filter point B5 TEST_MODE/CS Digital Input If SPI_MODE = 1, then this pin becomes CS. If SPI_MODE = 0, and TEST_MODE/CS = 1, then this places the LM4935 into test mode. B6 PLL_FILT Analog Inout Filter point for PLL VCO input PLL VDD Earpiece positive output B7 PLL_VDD Supply Input C1 HP_R Analog Output Headphone Right Output C2 EXT_BIAS Analog Output External microphone supply (2.0/2.5/2.8/3.3V) C3 INT_BIAS Analog Output 2.0V/2.5V ultra-clean supply for internal microphone C4 AUX_R Analog Input Right Analog Input C5 GPIO_2 Digital Inout General Purpose I/O 2 C6 SDA Digital Inout Control Data, I2C_SDA or SPI_SDI Control Clock, I2C_SCL or SPI_SCK C7 SCL Digital Input D1 HP_L Analog Output D2 VREF_FLT Analog Inout Filter point for the microphone power supply D3 AUX_L Analog Input Left Analog Input D4 SPI_MODE Digital Input Control mode select 1 = SPI, 0 = I2C (or test) D5 GPIO_1 Digital Inout General Purpose I/O 1 D6 BB_VDD Supply Input Baseband VDD for the digital I/Os D7 D_VDD Supply Input Digital VDD E1 HP_VMID Analog Inout Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input E2 HP_VMID_FB Analog Inout VMID Feedback in OCL mode, otherwise a 2nd headset detection input E3 MIC_DET Analog Input Headset insertion/removal and Microphone presence detection input E4 CPI_NEG Analog Input Cell Phone analog input negative E5 IRQ Digital Output Interrupt request signal (NOT open drain) E6 I2S_SDO Digital Output I2S Serial Data Out E7 I2S_SDI Digital Input I2S Serial Data Input F1 LS_VDD Supply Input Loudspeaker VDD F2 LS_VDD Supply Input Loudspeaker VDD F3 CPI_POS Analog Input Cell Phone analog input positive F4 CPO_NEG Analog Output Cell Phone analog output negative F5 AUX_OUT_NEG Analog Output Auxiliary analog output negative F6 I2S_WS Digital Inout I2S Word Select Signal (can be master or slave) I2S Clock Signal (can be master or slave) F7 I2S_CLK Digital Inout G1 LS_POS Analog Output G2 LS_VSS Supply Input G3 LS_NEG Analog Output Device Information Headphone Left Output Loudspeaker positive output Loudspeaker VSS Loudspeaker negative output Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Table 2-1. PIN DESCRIPTIONS (continued) 2.4 Pin Pin Name Type Direction G4 CPO_POS Analog Output Cell Phone analog output positive Description G5 AUX_OUT_POS Analog Output Auxiliary analog output positive G6 D_VSS Supply Input Digital VSS G7 MCLK Digital Input Input clock from 0.5 MHz to 30 MHz PIN TYPE DEFINITIONS Analog Input— A pin that is used by the analog and is never driven by the device. Supplies are part of this classification. Analog Output— A pin that is driven by the device and should not be driven by external sources. Analog Inout— A pin that is typically used for filtering a DC signal within the device, Passive components can be connected to these pins. Digital Input— A pin that is used by the digital but is never driven. Digital Output— A pin that is driven by the device and should not be driven by another device to avoid contention. Digital Inout— A pin that is either open drain (I2C_SDA) or a bidirectional CMOS in/out. In the later case the direction is selected by a control register within the LM4935. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Device Information 7 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 3 Electrical Specifications 3.1 Absolute Maximum Ratings (1) (2) (3) Analog Supply Voltage (A_VDD & LS_VDD) 6.0V Digital Supply Voltage (BB_VDD & D_VDD & PLL_VDD) 6.0V −65°C to +150°C Storage Temperature Power Dissipation (4) ESD Susceptibility Internally Limited Human Body Model (5) 2500V Machine Model (6) 200V Junction Temperature Thermal Resistance 150°C θJA – DSBGA (soldered down to PCB with 2in2 1oz. copper plane) 60°C/W Soldering Information (1) (2) (3) (4) (5) (6) 3.2 All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model: 100pF discharged through a 1.5kΩ resistor. Machine model: 220pF – 240pF discharged through all pins. Operating Ratings −40°C to +85°C Temperature Range Supply Voltage 8 Electrical Specifications D_VDD/PLL_VDD 2.7V to 4.5V BB_VDD 1.8V to 4.5V LS_VDD/A_VDD 2.7V to 5.5V Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Electrical Characteristics (1) (2) (3) 3.3 Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2-2 unless otherwise stated. Limits apply for 25°C. Symbol Parameter Conditions LM4935 Typical (4) Limit (5) Units DC CURRENT CONSUMPTION DISD Digital Shutdown Current (6) DIST Digital Standby Current DIDD Digital Active Current Chip Mode '00', fMCLK = 13MHz 0.7 Chip Mode '00', fMCLK = 19.2MHz 0.7 µA Chip Mode '01', fMCLK = 13MHz 1.5 Chip Mode '01', fMCLK = 19.2MHz 2.2 Chip Mode '10', fMCLK = 13MHz, DAC, ADC, SAR OFF 1.5 mA Chip Mode '10', fMCLK = 19.2MHz, DAC, ADC, SAR OFF 2.2 mA Chip Mode '10', fMCLK = 13MHz DAC, ADC, SAR ON 11.2 mA Chip Mode '10', fMCLK = 19.2MHz, DAC, ADC, SAR ON 16.2 20 mA (max) 5 µA (max) mA 3 mA (max) AISD Analog Shutdown Current Chip Mode '00' 0.2 3 µA (max) AIST Analog Standby Current Chip Mode '01', No headset inserted 0.2 3 µA (max) All Outputs OFF, SE MODE 6.1 mA All Outputs OFF, OCL MODE 5.7 mA All Outputs ON, SE MODE 18.3 mA AIDD Analog Active Current All Outputs ON, OCL MODE PLLIDD ADCIDD DACIDD PLL Active Current ADC Active Current DAC Active Current 18.7 28 mA (max) fMCLK = 13 MHz fPLLOUT = 12 MHz, PLL ON only 4.2 mA fMCLK = 19.2 MHz fPLLOUT = 12 MHz, PLL ON only 6.2 mA fMCLK = 13MHz, ADC ON only 2.5 mA fMCLK = 19.2MHz, ADC ON only 3.6 mA fMCLK = 13MHz, DAC ON only; PLL OFF, fS = 48kHz 7.4 mA fMCLK = 19.2MHz, DAC ON only PLL OFF; fS = 48kHz 10.7 mA fMCLK = 13MHz, SAR ON only 1.6 mA fMCLK = 19.2MHz, SAR ON only 2.3 mA LS ON only 8.8 mA HP ON only, SE MODE 3.5 mA HP ON only, OCL MODE 3.9 mA SARIDD SAR Active Current LSIDD Loudspeaker Quiescent Current HPIDD Headphone Quiescent Current EPIDD Earpiece Quiescent Current EP ON only 4.4 mA AUXIDD AUXOUT Quiescent Current AUXOUT ON only 4.8 mA CPOUTIDD CPOUT Quiescent Current CPOUT ON only 4.8 mA (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Best operation is achieved by maintaining 3.0V < A_VDD < 5.0 and 3.0V < D_VDD < 3.6V and A_VDD > D_VDD. Typical values are measured at 25°C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Electrical Specifications 9 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Electrical Characteristics(1)(2)(3) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2-2 unless otherwise stated. Limits apply for 25°C. Symbol Parameter LM4935 Conditions Typical (4) Limit (5) Units LOUDSPEAKER AMPLIFIER PLS Max Loudspeaker Power 8Ω load, LS_VDD = 5V 1.3 W 8Ω load, LS_VDD = 4.2V 0.9 W 8Ω load, LS_VDD = 3.3V 0.6 LSTHD+N Loudspeaker Harmonic Distortion 8Ω load, LS_VDD = 3.3V, PO = 400mW 0.44 W (min) 0.4 % LSEFF Efficiency 0 dB Input MCLK = 12.000 MHz 84 % PSRRLS Power Supply Rejection Ration (Loudspeaker) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz 54 dB SNRLS Signal to Noise Ratio From 0 dB Analog AUX input at 1 kHz, Aweighted 76 dB eN Output Noise A-weighted 350 µV VOS Offset Voltage 7 mV HEADPHONE AMPLIFIER PHP Headphone Power 32Ω load, 3.3V, SE 33 20 mW (min) 16Ω load, 3.3V, SE 52 mW 32Ω load, 3.3V, OCL, VCM = 1.5V 31 mW 32Ω load, 3.3V, OCL, VCM = 1.2V 20 mW 16Ω load, 3.3V, OCL, VCM = 1.5V 50 mW 16Ω load, 3.3V, OCL, VCM = 1.2V 32 mW SE Mode 60 dB OCL Mode VCM = 1.2V 68 dB OCL Mode VCM = 1.5V 65 dB SE Mode 98 dB OCL Mode VCM = 1.2V 97 dB OCL Mode VCM = 1.5V 96 dB AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz PSRRHP Power Supply Rejection Ratio (Headphones) From 0dB Analog AUX input A-weighted SNRHP Signal to Noise Ratio HPTHD+N Headphone Harmonic Distortion 32Ω load, 3.3V, PO = 7.5mW eN Output Noise A-weighted 0.05 % 12 µV ΔACH-CH Stereo Channel-to-Channel Gain Mismatch 0.3 dB XTALK Stereo Crosstalk SE Mode 61 dB OCL Mode 63 dB EARPIECE AMPLIFIER PEP Earpiece Power 32Ω load, 3.3V 115 16Ω load, 3.3V 10 Electrical Specifications 150 100 mW (min) mW Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Electrical Characteristics(1)(2)(3) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2-2 unless otherwise stated. Limits apply for 25°C. Symbol PSRREP Parameter Conditions Power Supply Rejection Ratio (Earpiece) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P FRIPPLE = 217 Hz SNREP Signal to Noise Ratio From 0dB Analog AUX input, A-weighted EPTHD+N Earpiece Harmonic Distortion 32Ω load, 3.3V, PO = 50mW eN Output Noise A-weighted VOS Offset Voltage LM4935 Typical (4) Limit (5) Units 65 dB 98 dB 0.04 % 24 µV 15 mV AUXOUT AMPLIFIER THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5kΩ load 0.02 % PSRR Power Supply Rejection Ratio AUX inputs terminated CBYPASS = 1.0μF VRIPPLE = 200mVPP fRIPPLE = 217Hz 70 dB 0.02 % 68 dB ±0.25 dB Lower (HPF Mode 1), fS = 8 kHz 300 Hz Upper 3470 Hz Above Passband 60 dB HPF Notch, 50 Hz/60 Hz (worst case) 58 dB From CPI, A-weighted 90 dB 1 VRMS CP_OUT AMPLIFIER THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5kΩ load PSRR Power SUpply Rejection Ratio CBYPASS = 1.0μF VRIPPLE = 200mVPP fRIPPLE = 217Hz MONO ADC RADC ADC Ripple PBADC ADC Passband SBAADC ADC Stopband Attenuation SNRADC ADC Signal to Noise Ratio ADCLEVEL ADC Full Scale Input Level STEREO DAC RDAC DAC Ripple 0.1 dB PBDAC DAC Passband 20 kHz SBADAC DAC Stopband Attenuation 70 dB SNRDAC DAC Signal to Noise Ratio 88 dB DRDAC DAC Dynamic Range 96 dB DACLEVEL DAC Full Scale Output Level 1 VRMS Min 0.5 MHz Max 30 MHz fS = 48kHz; 16 bit mode 1.536 MHz fS = 48kHz; 25 bit mode 2.4 MHz fS = 8kHz; 16 bit mode 0.256 MHz fS = 8kHz; 25 bit mode 0.4 MHz fS = 48kHz; 16 bit mode 0.768 MHz fS = 48kHz; 25 bit mode 1.2 MHz fS = 8kHz; 16 bit mode 0.128 MHz fS = 8kHz; 25 bit mode 0.2 MHz A-weighted, AUXOUT PLL (7) FIN Input Frequency Range I2S/PCM fI2SCLK fPCMCLK (7) I2S CLK Frequency PCM CLK Frequency Disabling or bypassing the PLL will usually result in an improvement in noise measurements. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Electrical Specifications 11 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Electrical Characteristics(1)(2)(3) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2-2 unless otherwise stated. Limits apply for 25°C. Symbol DCI2S_CLK DCI2S_WS Parameter LM4935 Conditions I2S_CLK Duty Cycle Typical (4) Limit (5) Units Min 40 % (min) Max 60 % (max) I2S_WS Duty Cycle 50 % I2C TI2CSET I2C Data Setup Time Refer to Section 4.1.5 for more details 100 ns (min) TI2CHOLD I2C Data Hold Time Refer to Section 4.1.5 for more details 300 ns (min) SPI TSPISETENB Enable Setup Time 100 ns (min) TSPIHOLD-ENB Enable Hold Time 100 ns (min) TSPISETD Data Setup Time 100 ns (min) TSPIHOLDD Data Hold Time 100 ns (min) TSPICL Clock Low Time 500 ns (min) TSPICH Clock High Time 500 ns (min) VOLUME CONTROL VCRAUX VCRDAC VCRCPIN VCRMIC AUX Volume Control Range Minimum Gain w/ AUX_BOOST OFF –46.5 dB Maximum Gain w/ AUX_BOOST OFF 0 dB –34.5 dB Maximum Gain w/ AUX_BOOST ON 12 dB Minimum Gain w/ DAC_BOOST OFF –46.5 dB Maximum Gain w/ DAC_BOOST OFF 0 dB Minimum Gain w/ DAC_BOOST ON –34.5 dB Maximum Gain w/ DAC_BOOST ON 12 dB Minimum Gain –34.5 dB Maximum Gain 12 dB Minimum Gain 6 dB Maximum Gain 36 dB Minimum Gain –30 dB Minimum Gain w/ AUX_BOOST ON DAC Volume Control Range CPIN Volume Control Range MIC Volume Control Range VCRSIDE SIDETONE Volume Control Range 0 dB SSAUX AUX VCR Stepsize 1.5 dB SSDAC DAC VCR Stepsize 1.5 dB SSCPIN CPIN VCR Stepsize 1.5 dB SSMIC MIC VCR Stepsize 2 dB SSSIDE SIDETONE VCR Stepsize 3 dB Maximum Gain AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer) Loudspeaker Audio Path Gain 12 Electrical Specifications Minimum Gain from AUX input, BOOST OFF –34.5 dB Maximum Gain from AUX input, BOOST OFF 12 dB Minimum Gain from CPI input –22.5 dB Maximum Gain from CPI input 24 dB Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Electrical Characteristics(1)(2)(3) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2-2 unless otherwise stated. Limits apply for 25°C. Symbol Parameter Conditions Headphone Audio Path Gain Earpiece Audio Path Gain AUXOUT Audio Path Gain Limit (5) Units Minimum Gain from AUX input, BOOST OFF –52.5 dB Maximum Gain from AUX input, BOOST OFF –6 dB Minimum Gain from CPI input –40.5 dB Maximum Gain from CPI input 6 dB Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB –30 dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB 0 dB Minimum Gain from AUX input, BOOST OFF –40.5 dB Maximum Gain from AUX input, BOOST OFF 6 dB Minimum Gain from CPI input –28.5 dB Maximum Gain from CPI input 18 dB Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB –18 dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB 12 dB Minimum Gain from AUX input, BOOST OFF –46.5 dB Maximum Gain from AUX input, BOOST OFF 0 dB –34.5 dB Maximum Gain from CPI input 12 dB Minimum Gain from AUX input, BOOST OFF –46.5 dB Maximum Gain from AUX input, BOOST OFF 0 dB Minimum Gain from MIC input 6 dB Maximum Gain from MIC input 36 dB fMCLK = 12MHz, PLL OFF 57 mW fMCLK = 13MHz, PLL ON fPLLOUT = 12MHz 63 mW fMCLK = 19.2MHz, PLL ON fPLLOUT = 12MHz 64 mW fMCLK = 12MHz, PLL OFF 24 mW fMCLK = 13MHz, PLL OFF 25 mW fMCLK = 19.2MHz, PLL OFF 27 mW fMCLK = 12MHz, PLL OFF 49 mW fMCLK = 13MHz, PLL OFF 50 mW fMCLK = 19.2MHz, PLL ON fPLLOUT = 12MHz 56 mW Minimum Gain from CPI input CPOUT Audio Path Gain LM4935 Typical (4) Total DC Power Dissipation DAC (fS = 48kHz) and HP ON MP3 Mode Power Dissipation AUX Inputs selected and HP ON FM Mode Power Dissipation PCM DAC (fS = 8kHz) + ADC (fS = 8kHz) and EP ON VOICE CODEC Mode Power Dissipation Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Electrical Specifications 13 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Electrical Characteristics(1)(2)(3) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2-2 unless otherwise stated. Limits apply for 25°C. Symbol Parameter LM4935 Conditions Typical (4) Limit (5) Units CP IN selected. EP and CPOUT ON VOICE Module Mode Power Dissipation 14 Electrical Specifications fMCLK = 12MHz, PLL OFF 30 mW fMCLK = 13MHz, PLL OFF 31 mW fMCLK = 19.2MHz, PLL OFF 33 mW Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4 Application Information 4.1 System Control Method 1. I2C Compatible Interface 4.1.1 I2C SIGNALS In I2C mode the LM4935 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM4935 is 00110102. 4.1.2 I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW. SCL SDA data change allowed data valid data change allowed data valid data change allowed Figure 4-1. I2C Signals: Data Validity 4.1.3 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. SDA SCL 4.1.4 S P START condition STOP condition TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM4935 address is 00110102. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 15 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com MSB LSB ADR6 Bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 2 I C SLAVE address (chip address) Figure 4-2. I2C Chip Address Register changes take an effect at the SCL rising edge during the last ACK from slave. ack from slave ack from slave start MSB Chip Address LSB w ack MSB Register 0x02h LSB ack start slave address = 00110102 w ack ack from slave MSB Data LSB ack stop ack stop SCL SDA register address = 0x02h ack register 0x02h data w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by slave) rs = repeated start Figure 4-3. Example I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. ack from slave repeated start ack from slave start MSB Chip Address LSB w ack MSB Register 0x00h LSB ack rs ack from slave data from slave ack from master MSB Chip Address LSB r ack MSB Data LSB ack stop SCL SDA start slave address = 00110102 w ack register address = 0x00h ack rs slave address = 00110102 r ack register 0x00h data ack stop Figure 4-4. Example I2C Read Cycle SDA 10 8 7 6 1 8 2 7 SCL 5 1 3 4 9 Figure 4-5. I2C Timing Diagram I2C TIMING PARAMETERS 4.1.5 Symbol Parameter Limit Min 16 1 Hold Time (repeated) START Condition 2 3 4 Units Max 0.6 µs Clock Low Time 1.3 µs Clock High Time 600 ns Setup Time for a Repeated START Condition 600 ns Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 5 Data Hold Time (Output direction, delay generated by LM4935) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 10 Bus Free Time between a STOP and a START Condition 1.3 Cb Capacitive Load for Each Bus Line 10 100 ns ns µs 200 pF Method 2. SPI/Microwire Control/3–wire Control The LM4935 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the chip_select as follows: TEST_MODE/CS CLK SDI 15 14 8 7 Register Address 1 0 Write Data Figure 4-6. SPI Write Transaction If the application requires read access to the register set; for example to determine the cause of an interrupt request or to read back a SAR data field, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-only locations above 0x80h: TEST_MODE/CS CLK SDI 15 14 8 Ignored 11 GPIO2 Address 1 4 SAR Data Figure 4-7. SPI Read Transaction TSPISETENB TSPIHOLDENB TEST_MODE/CS TSPICL TSPIT CLK TSPICH SDI TSPISETD TSPIHOLDD Figure 4-8. SPI Timing - Three Wire Mode Write Bus Timing Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 17 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2 www.ti.com Status & Control Registers Table 4-1. Register Map Address 18 Register 7 6 5 0x00h BASIC OCL STEREO 0x01h CLOCKS 0x02h PLL_M 0x03h PLL_N 4 CAP_SIZE 3 2 USE_OSC PLL_ENB 1 CHP_MODE R_DIV PLLINPUT 0 ADCLK PLL_M DACCLK RSVD PLL_N 0x04h PLL_P RSVD 0x05h PLL_MOD RSVD 0x06h ADC_1 Q_DIV HPF_MODE IF216 PLL_P DITHER_LEVEL SAMPLE_RATE 0x07h ADC_2 0x08h AGC_1 0x09h AGC_2 0x0Ah AGC_3 AGC_ATTACK 0x0Bh MIC_1 INT_EXT 0x0Ch MIC_2 0x0Dh SIDETONE 0x0Eh CP_INPUT 0x0Fh AUX_LEFT AUX_DAC 0x10h AUX_RIGH T 0x11h DAC 0x12h CP_OUTPU T 0x13h RIGHT LEFT CPI COMPND ADC_I2SM AGC_FRAME_TIME ADCMUTE NOISE_GATE_THRESHOLD NG_ON AGC_TARGET AGC_TIGH T RSVD PLL_N_MOD AGC_DECAY MIC U/ALAW AGC_ENB AGC_MAX_GAIN AGC_HOLD_TIME SE_DIFF MUTE BTN_DEBOUNCE_TIME PREAMP_GAIN BTNTYPE MIC_BIAS_VOLTAGE VCMVOLT SIDETONE_ATTEN MUTE CPI_LEVEL MUTE BOOST AUX_LEFT_LEVEL AUX_DAC MUTE BOOST AUX_RIGHT_LEVEL DACMUTE BOOST USAXLVL DAC_LEVEL MUTE LEFT RIGHT MIC AUX OUTPUT MUTE LEFT RIGHT CPI 0x14h LS_OUTPU T MUTE LEFT RIGHT CPI 0x15h HP_OUTPU T MUTE LEFT RIGHT CPI SIDE 0x16h EP_OUTPU T MUTE LEFT RIGHT CPI SIDE 0x17h DETECT TEMP_INT BTN_INT DET_INT STEREO HEADSET 0x18h STATUS 0x19h AUDIO_IF MICGATE HS_DBNC_TIME GPIN TEMP I2S_SDO_DATA SARTRG1 BTN MIC PCMSYMS I2SCLKMS I2SWSMS 0x1Ah GPIO GPIODATA 0x1Bh SAR_SLT0/ 1 SLT1ENB 0x1Ch SAR_SLT2/ 3 0x1Dh SAR_DATA _0 SLOT0_DATA 0x1Eh SAR_DATA _1 SLOT1_DATA 0x1Fh SAR_DATA _2 SLOT2_DATA 0x20h SAR_DATA _3 SLOT3_DATA 0x21h DC_VOL 0x22h TRIG_1 0x23h TRIG_1_M SB Application Information PCM_LNG SARTRG2 PCMCLMS I2S_MODE SAR_CH_SEL SLOT1_FS SLT2VBB SLT3ENB AUDIO_IF_MODE GPIO_SEL SLT0ENB SLOT0_FS SLT2ENB SLOT2_FS TRIG_1 [3:0] MAX_LVL EFFECT DCVLENB SOURCE DIR ENB TRIG_1 [11:4] Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Table 4-1. Register Map (continued) Address Register 0x24h TRIG_2 0x25h TRIG_2_M SB 0x26h DEBUG 7 6 5 4 3 TRIG_2 [3:0] 2 SOURCE 1 0 DIR ENB RSVD RSVD TRIG_2 [11:4] GPIO_TES T _MODE RSVD RSVD RSVD SOFT RESET RSVD For all registers, the default setting of data bits 7 through 0 are all set to zero. RESERVED bits should always be set to zero. 4.2.1 BASIC CONFIGURATION REGISTER This register is used to control the basic function of the chip. Table 4-2. BASIC (0x00h) Bits Field 1:0 CHIP_MODE Description The LM4935 can be placed in one of four modes which dictate its basic operation. When a new mode is selected the LM4935 will change operation silently and will re-configure the power management profile automatically. The modes are described as follows: CHIP MODE Audio System Detection System 002 Off Off Typical Application Power-down Mode 012 Off On Stand-by mode with headset event detection 102 On Off Active without headset event detection 112 On On Active with headset event detection 2 PLL_ENABLE 3 USE_OSC If set the power management and control circuits will assume that no external clock is available and will resort to using an on-chip oscillator for SAR, headset detection and analog power management functions such as click and pop. 5:4 CAP_SIZE Programs the extra delays required to stabilize once charge/discharge is complete, based on the size of the bypass capacitor. 6 STEREO 7 OCL If set the PLL can be used. CAP_SIZE Bypass Capacitor Size 002 0.1 µF Turn-off/on time 45 ms/75 ms 012 1 µF 45 ms/140 ms 102 2.2 µF 45 ms/260 ms 112 4.7 µF 45 ms/500 ms If set, the mixers assume that the signals on the left and right internal busses are highly correlated and when these signals are combined their levels are reduced by 6 dB to allow enough headroom for them to be summed at the Loudspeaker, Earpiece, CPOUT, and AUXOUT amplifiers. For the Headphone amplifier, if this bit is set, the left and right signal levels are routed to the corresponding left or right headphone output; if this bit is cleared, the left and the right signals are added and routed to both headphone outputs and their levels are reduced by 6dB to allow enough headroom. If set the part is placed in OCL (Output Capacitor Less) mode. For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by setting bit 0 of CHIP_MODE: The OCL-bit (Cap / Capless headphone interface; bit 7 of this register) The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h)) The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch)) The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch)) All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered while the audio sub-system is active. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 19 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com If the analog or digital levels are below −12 dB then it is not necessary to set the stereo bit allowing greater output levels to be obtained for such signals. 4.2.2 CLOCKS CONFIGURATION REGISTER This register is used to control the clocks throughout the chip. Table 4-3. CLOCKS (0x01h) Bits Field 0 DAC_CLK 1 ADC_CLK Description Selects the clock to be used by the audio DAC system. DAC_CLK DAC Input Source 0 PLL Input (MCLK or I2S_CLK) 1 PLL Output Selects the clock to be used by the audio ADC system. ADC_CLK 7:2 4.2.3 R_DIV Audio ADC Input Source 0 MCLK 1 PLL Output Programs the R divider (divides from an expected 12.000 MHz input). R_DIV Divide Value 0 Bypass 1 Bypass 2 1.5 3 2 4 2.5 5 3 6 3.5 7 4 8 4.5 9 5 10 5.5 11 6 12 6.5 13 to 61 7 to 31 62 31.5 63 32 LM4935 CLOCK NETWORK The audio ADC operates at 125*fs, so it requires a 1.000 MHz clock to sample at 8 kHz (at point C as marked on the following diagram). The stereo DAC operates at 250*fs, i.e. 12.000 MHz (at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system unless a 12.000 MHz master clock is supplied and the sample rate is always a multiple of 8 kHz, in which case the PLL can be bypassed to reduce power, clock division instead being performed by the Q and R dividers. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL output divided by 2*FSDAC/FSADC or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback. MCLK must be less than or equal to 30 MHz, the I2S clock should be an integer multiple of the DAC’s sampling frequency and should be below 6 MHz. When using the Class D amplifier with the DAC the Class D clock generator will assume 12 MHz at point A, if this is not the case then the DAC and power stage may become unsynchronized and SNR performance may be reduced. 20 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 The LM4935 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. This is used to drive the power management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly beyond this range. USE_ONCHIP_OSC From on chip 12 MHz oscillator %R PLL MCL K (to DET, PMC & SAR) A B %Q C I2S Interface Stereo DAC PCM Interface Mono ADC I2S_CL K PCM_CL K Figure 4-9. LM4935 Clock Network 4.2.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC The DAC has an over sampling rate of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point B for various clock sample rates in the different DAC modes: Table 4-4. Common DAC Clock Frequencies DAC Sample Rate (kHz) Clock Required at B (MHz) 8 2 11.025 2.75625 12 3 16 4 22.05 5.5125 24 6 32 8 44.1 11.025 48 12 The ADC has an over sampling ratio of 125 so the table below shows the required clock frequency at point C. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 21 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Table 4-5. Common ADC Clock Frequencies ADC Sample Rate (kHz) Clock Required at C (MHz) 8 1 11.025 1.378125 12 1.5 16 2 22.05 2.75625 24 3 Methods for producing these clock frequencies are described in the PLL Section. 4.2.5 PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input section of the PLL. Table 4-6. PLL_M (0x02h) Bits Field 0 RSVD 6:1 PLL_M 7 Description RESERVED PLL_INPUT PLL_M Input Divider Value 0 1 1 2 2 3 3 4 4...62 5...63 63 64 Programs the PLL input multiplexer to select between: PLL_INPUT PLL Input Source 0 MCLK 1 I2S_CLK The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. The division of the M divider is derived from PLL_M such that: M = PLL_M + 1 (1) NOTE See Section 4.2.9 for more detail. 22 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com 4.2.6 SNAS296E – OCTOBER 2005 – REVISED MAY 2013 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control the feedback divider of the PLL. Table 4-7. PLL_N (0x03h) Bits Field 7:0 PLL_N Description Programs the PLL feedback divider as follows: PLL_N Feedback Divider Value 0 to 10 10 11 11 12 12 13 13 14 14 … … 249 249 250 to 255 250 The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting VCO frequency, FVCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as Fcomp (comparison frequency) or Fref (reference frequency), in this document Fcomp is used. The integer division of the N divider is derived from PLL_N such that: For 9 < PLL_N < 251: N = PLL_N (2) NOTE See Section 4.2.9 for further details. 4.2.7 PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the output divider of the PLL. Table 4-8. PLL_P (0x04h) Bits Field 0 RSVD 3:1 PLL_P Description RESERVED PLL_P Output Divider Value 0002 1 0012 2 0102 3 0112 4 1002 5 1012 6 1102 7 1112 8 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 23 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Table 4-8. PLL_P (0x04h) (continued) Bits Field 6:4 Q_DIV 7 Description RSVD Programs the Q Divider (divides from an expected 12.000 MHz input). Q_DIV Divide Value 0002 2 0012 3 0102 4 0112 6 1002 8 1012 10 1102 12 1112 13 RESERVED The division of the P divider is derived from PLL_P such that: P = PLL_P + 1 (3) NOTE See Section 4.2.9 for more details. 4.2.8 PLL N MODULUS CONFIGURATION REGISTER This register is used to control the modulation applied to the feedback divider of the PLL. Table 4-9. PLL_N_MOD (0x05h) Bits Field 4:0 PLL_N_MOD 6:5 7 Description DITHER_LEVEL RSVD Programs the PLL N divider's fractional component: PLL_N_MOD Fractional Addition 0 0/32 1 1/32 2 to 30 2/32 to 30/32 31 31/32 Allows control over the dither used by the N divider: DITHER_LEVEL Value 002 Medium 012 Small 102 Large 112 Off RESERVED The complete N divider is a fractional divider as such: N = PLL_N + PLL_N_MOD/32 (4) If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin*N)/(M*P) (5) NOTE See Section 4.2.9 for more details. 24 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com 4.2.9 SNAS296E – OCTOBER 2005 – REVISED MAY 2013 FURTHER NOTES ON PLL PROGRAMMING The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 30 MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48 kHz and 44.1 kHz sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within 1 Hz of the correct sample rate although this is highly unlikely to be a problem. PLL_P M = 1..64 0.5-30 MHz Phase Comparator & Charge Pump %M 0 3 40 to 60 MHz External Loop Filter 250xFS VCO %P 0.5 < 5 MHz P = 1..8 6 %N N = 10..250 31/32 PLL_M 6'M 8 8 5 PLL_N PLL_N_MOD Figure 4-10. PLL Overview Table 4-10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MO D PLL_P Fout (MHz) 11 48 11 60 5 10 60 0 4 12 12.288 48 4 19.53125 5 3 19 17 4 12 13 48 13 60 5 12 60 0 4 12 14.4 48 9 37.5 5 8 37 16 4 12 16.2 48 27 100 5 26 100 0 4 12 16.8 48 14 50 5 13 50 0 4 12 19.2 48 13 40.625 5 12 40 20 4 12 19.44 48 27 100 6 26 100 0 5 12 19.68 48 21 64.03125 5 20 64 1 4 12 19.8 48 17 51.5 5 16 51 16 4 12 11 44.1 11 55.125 5 10 55 4 4 11.025 11.2896 44.1 8 39.0625 5 7 39 2 4 11.025 12 44.1 5 22.96875 5 4 22 31 4 11.025 13 44.1 13 55.125 5 12 55 4 4 11.025 14.4 44.1 12 45.9375 5 11 45 30 4 11.025 16.2 44.1 9 30.625 5 8 9 20 4 11.025 16.8 44.1 17 55.78125 5 16 30 25 4 11.025 19.2 44.1 16 45.9375 5 15 45 30 4 11.025 19.44 44.1 14 39.6875 5 13 39 22 4 11.025 19.68 44.1 21 47.0625 4 20 47 2 3 11.025 19.8 44.1 11 30.625 5 10 30 204 4 11.025 These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done by increasing the P divider value or using the R/Q dividers. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams). Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 25 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz. So for P = 3 to 5, sweep the M inputs from 1 to 3. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) (6) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) (7) This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison frequency of 1.5 MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact frequency match cannot be found. The I2S should be master on the LM4935 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than the PLL. The LM4935 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8, 13, 26, 52 kHz modes from a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR. The actual ADC and DAC sample rates are set up by the PLL and internal clock dividers. 4.2.10 ADC_1 CONFIGURATION REGISTER This register is used to control the LM4935's audio ADC. Table 4-11. ADC_1 (0x06h) Bits Field 0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal. Description 1 CPI_SELECT If set the cell phone input is added to the ADC input signal. 2 LEFT_SELECT 3 RIGHT_SELECT If set the left stereo bus is added to the ADC input signal. If set the right stereo bus is added to the ADC input signal. 5:4 ADC_SAMPLE_ RATE Programs the closest expected sample rate of the mono ADC, which is a variable required by the AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC. ADC_SAMPLE_RATE 7:6 HPF_MODE Sample Rate 002 8 kHz 012 12 kHz 102 16 kHz 112 24 kHz Sets the HPF of the ADC HPF-MODE HPF Response 002 No HPF 012 FS = 8 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz FS = 12 kHz, −0.5 dB @ 450 Hz, Notch @ 82 Hz FS = 16 kHz, −0.5 dB @ 600 Hz, Notch @ 110 Hz 102 FS = 8 kHz, −0.5 dB @ 150 Hz, Notch @ 27 Hz FS = 12 kHz, −0.5 dB @ 225 Hz, Notch @ 41 Hz FS = 16 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz 112 26 Application Information No HPF Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2.11 ADC_2 CONFIGURATION REGISTER This register is used to control the LM4935's audio ADC. Table 4-12. ADC_2 (0x07h) Bits Field 0 ULAW/ALAW Description If COMPAND is set then the data across the PCM interface to the DAC and from the ADC is companded as follows: ULAW/ALAW 1 2 5:3 Commanding Type 0 µ-law 1 A-law COMPAND If set the 16 bit PCM data from the ADC is companded before the PCM interface and the PCM data to the DAC is treated as companded data. ADC_MUTE If set the analog inputs to the ADC are muted. AGC_FRAME_TIME This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC's peak detector determines the peak value of the incoming microphone audio signal and compares this value to the target value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in order to adjust the microphone preamplifiers gain accordingly. AGC_FRAME_TIME basically sets the sample rate of the AGC to adjust for a wide variety of speech patterns. (Note 15) AGC_FRAME_TIME 6 ADC_I2S_M 7 AUDIO_IF_2_16BIT Time (ms) 0002 96 0012 128 0102 192 0112 256 1002 384 1012 512 1102 768 1112 1000 If set the DAC clock system is enabled to drive the I2S in master mode. The Point B frequency should be double that at Point C. This bit should be set when using the I2S interface in master mode to read SAR information whenever both the audio ADC and DAC are inactive. If set the PCM and I2S interfaces are 16 bits per word in master mode. The 2 last clock cycles per word are 25% shorter to allow generation. 4.2.12 AGC_1 CONFIGURATION REGISTER This register is used to control the LM4935's Automatic Gain Control. (Note 16) Table 4-13. AGC_1 (0x08h) Bits Field 0 AGC_ENABLE If set the AGC controls the analog microphone preamplifier gain into the system. The microphone input must be passed to the ADC. Description 3:1 AGC_TARGET Programs the target level of the AGC. This will depend on the expected transients and desired headroom. Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail. AGC_TARGET Target Level 0002 −6 dB 0012 −8 dB 0102 −10 dB 0112 −12 dB 1002 −14 dB 1012 −16 dB 1102 −18 dB 1112 −20 dB Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 27 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Table 4-13. AGC_1 (0x08h) (continued) Bits 4 7:5 Field Description NOISE_GATE_ON If set, signals below the noise gate threshold are muted.The noise gate is only activated after a set period of signal absence. NOISE_ GATE_ THRES This field sets the expected background noise level relative to the peak signal level. The sole presence of signals below this level will not result in an AGC gain change of the input and will be gated from the ADC output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is required by the AGC algorithm. NOISE_GATE_THRES Level 0002 −72 dB 0012 −66 dB 0102 −60 dB 0112 −54 dB 1002 −48 dB 1012 −42 dB 1102 −36 dB 1112 −30 dB 4.2.13 AGC_2 CONFIGURATION REGISTER This register is used to control the LM4935's Automatic Gain Control. Table 4-14. AGC_2 (0x09h) Bits Field 3:0 AGC_MAX_GAIN 6:4 28 AGC_DECAY Description This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier. AGC_MAX_GAIN Max Preamplifier Gain 00002 6 dB 00012 8 dB 00102 10 dB 00112 12 dB 01002 to 11002 14 dB to 30 dB 11012 32 dB 11102 34 dB 11112 36 dB Programs the speed at which the AGC will increase gains if it detects the input level is a quiet signal. Application Information AGC_DECAY Step Time (ms) 0002 32 0012 64 0102 128 0112 256 1002 512 1012 1024 1102 2048 1112 4096 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Table 4-14. AGC_2 (0x09h) (continued) Bits Field 7 AGC_TIGHT AGC_TIGHT = 0 AGC_TIGHT = 1 Description If set the AGC algorithm controls the microphone preamplifier more exactly. (Note 17) AGC_TARGET Min Level Max Level 0002 −6 dB −3 dB 0012 −8 dB −4 dB 0102 −10 dB −5 dB 0112 −12 dB −6 dB 1002 −14 dB −7 dB 1012 −16 dB −8 dB 1102 −18 dB −9 dB 1112 −20 dB −10 dB 0002 −6 dB −3 dB 0012 −8 dB −5 dB 0102 −10 dB −7 dB 0112 −12 dB −9 dB 1002 −14 dB −11 dB 1012 −16 dB −13 dB 1102 −18 dB −15 dB 1112 −20 dB −17 dB 4.2.14 AGC_3 CONFIGURATION REGISTER This register is used to control the LM4935's Automatic Gain Control. (Note 18) Table 4-15. AGC_3 (0x0Ah) Bits Field 4:0 AGC_HOLDTIME 7:5 AGC_ATTACK Description Programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone preamplifier. AGC_HOLDTIME No. of speech segments 000002 0 000012 1 000102 2 000112 3 001002 to 111002 4 to 28 111012 29 111102 30 111112 31 Programs the speed at which the AGC will reduce gains if it detects the input level is too large. AGC_ATTACK Step Time (ms) 0002 32 0012 64 0102 128 0112 256 1002 512 1012 1024 1102 2048 1112 4096 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 29 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 4.2.15 AGC OVERVIEW The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level of the source is unknown. A target level for the output is set so that any transients on the input won’t clip during normal operation. The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone preamplifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range of the ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone level. In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients closely to the target level. To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone preamplifier gain, the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is consistently below target, the gain will be increased at a programmable rate (AGC_DECAY). If the signal ever exceeds the target level (AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demonstrated below: (1) Decay hold time, (2) Slow Decay, (3) Quick Attack (2) (3) (1) target level peak detection and ADC output attack decay microphone gain 12 dB 12 dB 14 dB signal below target 10 dB signal above target Figure 4-11. AGC Operation Example The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the gain ((1) → (2)). After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases the gain at a faster rate ((2) → (3)) to allow the elimination of typical popping noises. Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm. The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC, the ADC's HPF should always be enabled. 4.2.16 MIC_1 CONFIGURATION REGISTER This register is used to control the microphone configuration. 30 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Table 4-16. MIC_1 (0x0Bh) Bits Field 3:0 PREAMP_GAIN Description Programs the gain applied to the microphone preamplifier if the AGC is not in use. PREAMP_GAIN Gain 00002 6 dB 00012 8 dB 00102 10 dB 00112 12 dB 01002 to 11002 14 dB to 30 dB 11012 32 dB 11102 34 dB 11112 36 dB 4 MIC_MUTE If set the microphone preamplifier is muted. 5 INT_SE_DIFF If set the internal microphone is assumed to be single ended and the negative connection is connected to the ADC common mode point internally. This allows a single-ended internal microphone to be used. 6 INT_EXT If set the single ended external microphone is used and the negative microphone input is grounded internally, otherwise internal microphone operation is assumed. (Note 19) 4.2.17 MIC_2 CONFIGURATION REGISTER This register is used to control the microphone configuration. Table 4-17. MIC_2 (0x0Ch) Bits Field 0 OCL_ VCM_ VOLTAGE 2:1 MIC_ BIAS_ VOLTAGE 3 BUTTON_TYPE 5:4 BUTTON_ DEBOUNCE_ TIME Description Selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the available supply and the power output requirements of the headphone amplifiers. OCL_VCM_VOLTAGE Voltage 0 1.2V 1 1.5V Selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE should be set to '11' only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = '00' (EXT_BIAS = 2.0V) should not be used to generate the EXT_BIAS supply for a cellular headset external microphone. Please refer to Table 4-18 for more detail. MIC_BIAS_VOLTAGE EXT_BIAS INT_BIAS 002 2.0V 2.0V 012 2.5V 2.5V 102 2.8V 2.8V 112 3.3V 3.3V If set the LM4935 assumes that the button (if used) in the headset is in series (series push button) with the microphone, opening the circuit when pressed. The default is for the button to be in parallel (parallel push button), shorting out the microphone when pressed. Sets the time used for debouncing the pushing of the button on a headset with a parallel push button. BUTTON_DEBOUNCE_TIME Time (ms) 002 0 012 8 102 16 112 32 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 31 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS OCL_VCM_ VOLTAGE) and the maximum output power possible from the headphones. A lower OCL_VCM_VOLTAGE gives a higher microphone supply voltage but a lower maximum output power from the headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_VSS. Table 4-18. External MIC Supply Voltages in OCL Mode Available A_VDD Recommended EXT_MIC_BIAS > 3.4V Supply to Microphone OCL_VCM_VOLT = 1.5V OCL_VCM_VOLT = 1.2V 3.3V 1.8V 2.1V 2.9V to 3.4V 2.8V 1.3V 1.6V 2.8V to 2.9V 2.5V 1.0V 1.3V 2.7V to 2.8V 2.5V - 1.3V 4.2.18 SIDETONE ATTENUATION REGISTER This register is used to control the analog sidetone attenuation. (Note 20) Table 4-19. SIDETONE (0x0Dh) Bits Field 3:0 SIDETONE_ ATTEN Description Programs the attenuation applied to the microphone preamp output to produce a sidetone signal. SIDETONE_ATTEN Attenuation 00002 -Inf 00012 −30 dB 00102 −27 dB 00112 −24 dB 01002 −21 dB 01012 to 10102 −18 dB to −3 dB 10112 to 11112 0 dB 4.2.19 CP_INPUT CONFIGURATION REGISTER This register is used to control the differential cell phone input. Table 4-20. CP_INPUT (0x0Eh) Bits Field 4:0 CPI_LEVEL 5 32 CPI_MUTE Description Programs the gain/attenuation applied to the cell phone input. CPI_LEVEL Level 000002 −34.5 dB 000012 −33 dB 000102 −31.5 dB 000112 −30 dB 00100 to 111002 −28.5 dB to +7.5 dB 111012 +9 dB 111102 +10.5 dB 111112 +12 dB If set the CPI input is muted at source. Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2.20 AUX_LEFT CONFIGURATION REGISTER This register is used to control the left aux analog input. Table 4-21. AUX_LEFT (0x0Fh) Bits Field 4:0 AUX_ LEFT_ LEVEL 5 AUX_ LEFT_ BOOST 6 AUX_L_MUTE 7 AUX_OR_DAC_L Description Programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (Note 21) AUX_LEFT_LEVEL Level (With Boost) Level (Without Boost) 000002 −34.5 dB −46.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.5 dB 111012 +9 dB −3 dB 111102 +10.5 dB −1.5 dB 111112 +12 dB 0 dB If set the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above). If set the AUX LEFT input is muted. If set the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be passed to the mixer. 4.2.21 AUX_RIGHT CONFIGURATION REGISTER This register is used to control the right aux analog input. Table 4-22. AUX_RIGHT (0x10h) Bits Field 4:0 AUX_ RIGHT_ LEVEL Description Programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (Note 22) AUX_RIGHT_LEVEL Level (With Boost) Level (Without Boost) 000002 −34.5 dB −46.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.5 dB 111012 +9 dB −3 dB 111102 +10.5 dB −1.5 dB 111112 +12 dB 0 dB 5 AUX_ RIGHT_BOOST If set the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above). 6 AUX_R_MUTE If set the AUX RIGHT input is muted. 7 AUX_OR_DAC_R If set the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be passed to the mixer. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 33 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 4.2.22 DAC CONFIGURATION REGISTER This register is used to control the DAC levels to the mixer. Table 4-23. DAC (0x11h) Bits Field 4:0 DAC_LEVEL 5 USE_AUX_ LEVELS 6 BOOST 7 DAC_MUTE Description Programs the gain/attenuation applied to the DAC input to the mixer. (Note 23) DAC_LEVEL Level (With Boost) Level (Without Boost) 000002 −34.5 dB −46.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.5 dB 111012 +9 dB −3 dB 111102 +10.5 dB −1.5 dB 111112 +12 dB 0 dB If set the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing a stereo balance to be applied. If set the gain of the DAC inputs to the mixer is increased by 12 dB (see above). If set the stereo DAC input is muted on the next zero crossing. 4.2.23 CP_OUTPUT CONFIGURATION REGISTER This register is used to control the differential cell phone output. (Note 24) Table 4-24. CP_OUTPUT (0x12h) Bits Field 0 MIC_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 CPO_MUTE 4 MIC_NOISE_GAT E Description If set the microphone channel of the mixer is added to the cellphone output signal. If set the right channel of the mixer is added to the cellphone output signal. If set the left channel of the mixer is added to the cellphone output signal. If set the CPOUT output is muted. If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be gated if the signal is determined to be noise by the AGC (that is, if the signal is below the set noise threshold). 4.2.24 AUX_OUTPUT CONFIGURATION REGISTER This register is used to control the differential auxiliary output. (Note 25) Table 4-25. AUX_OUTPUT (0x13h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 AUX_MUTE 34 Description If set the cell phone input channel of the mixer is added to the aux output signal. If set the right channel of the mixer is added to the aux output signal. If set the left channel of the mixer is added to the aux output signal. If set the aux output is muted. Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2.25 LS_OUTPUT CONFIGURATION REGISTER This register is used to control the loudspeaker output. (Note 26) Table 4-26. LS_OUTPUT (0x14h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 LS_MUTE Description If set the cell phone input channel of the mixer is added to the loudspeaker output signal. If set the right channel of the mixer is added to the loudspeaker output signal. If set the left channel of the mixer is added to the loudspeaker output signal. If set the loudspeaker output is muted. 4.2.26 HP_OUTPUT CONFIGURATION REGISTER This register is used to control the stereo headphone output. (Note 27) Table 4-27. HP_OUTPUT (0x15h) Bits Field 0 SIDETONE_SELECT 1 CPI_SELECT 2 RIGHT_SELECT 3 LEFT_SELECT 4 HP_MUTE Description If set the sidetone channel of the mixer is added to both of the headphone output signals. If set the cell phone input channel of the mixer is added to both of the headphone output signals. If set the right channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the right channel is added to the right headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. If set the left channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the left channel is added to the left headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. If set the headphone output is muted. 4.2.27 EP_OUTPUT CONFIGURATION REGISTER This register is used to control the mono earpiece output. (Note 28) Table 4-28. EP_OUTPUT (0x16h) Bits Field 0 SIDETONE_SELECT Description 1 CPI_SELECT 2 RIGHT_SELECT 3 LEFT_SELECT 4 EP_MUTE If set the sidetone channel of the mixer is added to the earpiece output signal. If set the cell phone input channel of the mixer is added to the earpiece output signal. If set the right channel of the mixer is added to the earpiece output signal. If set the left channel of the mixer is added to the earpiece output signal. If set the earpiece output is muted. 4.2.28 DETECT CONFIGURATION REGISTER This register is used to control the headset detection system. Table 4-29. DETECT (0x17h) Bits Field Description 0 DET_INT If set an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ that has been triggered by the headset detect. 1 BTN_INT If set an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that has been triggered by a button event. 2 TEMP_INT If set an IRQ is raised during a temperature event. If cleared, the LM4935 will still automatically cycle the power amplifiers off if the internal temperature is too high. This bit should not be set whenever the loudspeaker amplifier is turned on. Clearing this bit will clear an IRQ that has been triggered by a temperature event. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 35 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Table 4-29. DETECT (0x17h) (continued) Bits Field 6:3 HS_ DBNC_TIME Description Sets the time used for debouncing the analog signals from the detection inputs used to sense the insertion/removal of a headset. HS_DBNC_TIME Time (ms) 00002 0 00012 8 00102 16 00112 32 01002 48 01012 64 01102 96 01112 128 10002 192 10012 256 10102 384 10112 512 11002 768 11012 1024 11102 1536 11112 2048 4.2.29 HEADSET DETECT OVERVIEW The LM4935 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM4935 updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no analog supply current when the headset is absent. The LM4935 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will be disconnected from the MIC_BIAS amplifier, irrespective of control register settings. The LM4935 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series button-type (in series with the headset microphone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected in stand-by mode; this consumes 10 µA of analog supply current for a series type push button and 100 µA for a parallel type push button. Upon button press, the LM4935 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected (INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN (bit 3 of STATUS (0x18h)) can be read. The LM4935 can also be programmed to raise an interrupt on the IRQ pin when button press is sensed by setting bit 1 of DETECT. The LM4935 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button. Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch). 36 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the debounce time for series button press in defined by HS_DBNC_TIME. Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push button detection all following bits should be defined before enabling the headset detection system: 1) the OCL-bit (AC-Coupled / Capless headphone interface (bit 7 of BASIC (0x00h)) 2) the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h)) 3) the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch)) 4) the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch)) Figure 4-12 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from the MIC_DET pin to ground when a headset is not inserted. s s s g g g 47: s 47: s m m Stereo + Cellular g m s s Cellular g m s s s g g Stereo g s s s m m Stereo + Cellular g m s s Cellular g m s Figure 4-12. Headset Configurations Supported by the LM4935 The wiring of the headset jack to the LM4935 will depend on the intended mode of the headphone amplifier: Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 37 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com EXT_MIC_BIAS 3.3/2.8/2.5V MIC_DET 2.2 k: EXT_MIC s s 1 PF LM4935 g Stereo HP_L Cellular g m Stereo + Cellular g m s HP_R s s HP_VMID_FB m = mic s = speaker g = virtual ground HP_VMID 1.2/1.5V Connection for OCL Mode (DC-Coupled) Headset Detection EXT_MIC_BIAS 2.0/2.5V MIC_DET 2.2 k: s s 1 PF s 47 PF s 47 PF LM4935 EXT_MIC g Stereo HP_L Cellular g m Stereo + Cellular g m HP_R s HP_VMID_FB m = mic s = speaker 1 k: g = ground (A_VSS) HP_VMID A_VDD/2 1 k: Connection for Non-OCL Mode (AC-Coupled) Headset Detection Figure 4-13. Connection of Headset Jack to LM4935 Depends on the Mode of the Headphone Amplifier. 4.2.30 STATUS REGISTER This register is used to report the status of the device. Table 4-30. STATUS (0x18h) Bits Field Description 0 HEADSET This field is high when headset presence is detected (only valid if the detection system is enabled). (Note 29) 1 STEREO_ HEADSET This field is high when a headset with stereo speakers is detected (only valid if the detection system is enabled). (Note 29) 2 MIC This field is high when a headset with a microphone is detected (only valid if the detection system is enabled). (Note 29) 3 BTN This field is high when the button on the headset is pressed (only valid if the detection system is enabled). IRQ is cleared when the button has been released and this register has been written to. 4 SAR TRIG 1 If this field is high then an event has happened on SAR trigger 1 (write to this register to clear IRQ). 5 SAR TRIG 2 If this field is high then an event has happened on SAR trigger 2 (write to this register to clear IRQ). 6 TEMP If this field is high then a temperature event has occurred (write to this register to clear IRQ). This field will stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid whenever the loudspeaker amplifier is turned off. 7 GPIN When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back here. 38 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2.31 AUDIO INTERFACE CONFIGURATION REGISTER This register is used to control the configuration of the audio data interfaces. Table 4-31. AUDIO_IF (0x19h) Bits Field 1:0 AUDIO_IF_MODE Description Selects the function of the 6 audio interface IOs. AUDIO_IF_MODE I2S_ CLK pin I2S_ WS pin I2S_ SDI pin I2S_ SDO pin GPIO_1 pin GPIO_2 pin 002 I2S CLK I2S WS I2S SDI I2S SDO GPIO 1 GPIO 2 012 PCM CLK PCM SYNC - PCM SDO GPIO 1 GPIO 2 102 PCM CLK PCM SYNC PCM SDI PCM SDO GPIO 1 GPIO 2 112 I2S CLK I2S WS I2S SDI PCM SDO PCM CLK PCM SYNC 2 I2S_WS_MS If set the I2S_WS is produced by the LM4935 and the I2S_WS pin will be an output. 3 I2S_CLK_MS If set the I2S_CLK is produced by the LM4935 and the I2S_CLK pin will be an output. 4 PCM_SYNC_MS 5 PCM_CLK_MS 7:6 I2S_SDO_DATA If set the PCM_SYNC is produced by the LM4935 and the relevant pin will be an output. If set the PCM_CLK is produced by the LM4935 and the relevant pin will be an output. The two ADCs on the LM4935 can both be read via the isochronous I2S interface. The most recent valid sample is output from the following source: (Please refer to Table 4-32 for more information on SAR_CH_SEL) I2S_SDO_DATA LEFT RIGHT 002 AUDIO ADC SAR_CH_SEL 012 SAR VSAR 1 SAR_CH_SEL 102 SAR VSAR 2 SAR_CH_SEL 112 A_VDD/2 SAR_CH_SEL 4.2.32 DIGITAL AUDIO DATA FORMATS I2S master mode can only be used when the DAC is enabled unless the ADC_I2S_M bit is set. PCM Master mode can only be used when the ADC is enabled. If the PCM receiver interface is operated in slave mode the clock and sync should be enabled at the same time as the PCM receiver uses the first PCM frame to calculate the PCM interface format. This format can not be changed unless a soft reset is issued. It is strongly recommended that the LM4935 is operated in master mode as this eliminates the risk of sample rate mismatch between the data converters and the audio interfaces. In master mode the I2S_CLK has a 60/40 duty cycle and a frequency of 50*fs. In slave mode the PCM and I2S receivers only record the 1st 16 and 18 bits of the serial words respectively. The I2S format is as follows: I2S_CLK I2S_WS I2S_SDO/ I2S_SDI 0 24 23 22 21 3 Left Word 2 1 0 24 23 22 21 3 2 1 0 24 Right Word 2 Figure 4-14. I S Serial Data Format (Default Mode) Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 39 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com PCM_CLK PCM_SYNC PCM_SDO/ PCM_SDI 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 Short frame sync mode (PCM_LONG = 0) Long frame sync mode (PCM_LONG = 1) Figure 4-15. PCM Serial Data Format (16 bit Slave Example) When SAR SDO data is passed to the I2S, it is left aligned (MSB aligned) to allow lower I2S resolutions to be used. If the DAC is driven from the PCM interface then the left channel of the DAC is used and the right channel is inactive. 4.2.33 GPIO CONFIGURATION REGISTER This register is used to control the GPIO system. Table 4-32. GPIO (0x1Ah) Bits Field 2:0 GPIO_SEL Description This sets the function of the GPIOs when the Audio Interface is not using them. GPIO_SEL GPIO 1 GPIO 2 0002 0 0 0012 READABLE SPI_SDO 0102 LS_AMP_ENABLE SPI_SDO 0112 GPIO_DATA SPI_SDO 1002 0 SPI_SDO 1012 READABLE SAR_SDO 1102 LS_AMP_ENABLE SAR_SDO 1112 GPIO_DATA SAR_SDO Setting GPIO_SEL = “010” with the GPIO_TEST_MODE bit (register 0X26h) set configures the GPIOs for digital mic operation. With this setting, GPI01 will output VADC_CLK_OUT to provide a clock for the digital mic. GPIO2 will accept digital mic data. GPIO1's LS_AMP_ENABLE setting will be logic high whenever the loudspeaker amplifier is enabled. This is useful for enabling an external amplifier for stereo loudspeaker applications. 4:3 40 SAR_CH_SEL This field selects the SAR output channel for the 2nd (Right) I2S channel or for SAR_SDO via GPIO2. SAR_CH_SEL Selected Channel 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 5 I2S_MODE If set the I2S operates in left justified mode (sometimes referred to as DSP mode). See example below. (Note 30) 6 PCM_LONG If set the PCM interface uses LONG frame sync which is essentially an inverted short frame sync. 7 GPIO_DATA If GPIO_SEL is set to GPIO_DATA then the content of this field is passed to GPIO1 as an output. Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2.34 SAR CHANNELS 0 & 1 CONFIGURATION REGISTER This register is used to control channel 0 and 1 of the SAR system. (Note 31) Table 4-33. SAR_SLOT01 (0x1Bh) Bits Field 2:0 SLOT_0_FS 3 SLOT_0_ENB 6:4 SLOT_1_FS 7 SLOT_1_ENB Description Programs the sampling frequency of SAR channel 0: SLOT_0_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz If set then VSAR 1 is sampled into SAR slot 0 which also activates the SAR ADC. Programs the sampling frequency of SAR channel 1: SLOT_1_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz If set then VSAR 2 is sampled into SAR slot 1 which also activates the SAR ADC. 4.2.35 SAR CHANNELS 2 & 3 CONFIGURATION REGISTER This register is used to control channel 2 and 3 of the SAR system. (Note 31) Table 4-34. SAR_SLOT23 (0x1Ch) Bits Field 2:0 SLOT_2_FS Description Programs the sampling frequency of SAR channels 2 and 3: SLOT_2_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz 3 SLOT_2_ENB If set then D_VDD / 2 or BB_VDD (depending on SLOT2_VBB) is sampled into SAR slot 2 which also activates the SAR ADC. 4 SLOT_3_ENB If set then A_VDD / 2 is sampled into SAR slot 3 which also activates the SAR ADC. 5 SLOT_2_VBB If set then BB_VDD input is used as input to SAR slot 2 rather than the D_VDD. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 41 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 4.2.36 SAR DATA 0 TO 3 REGISTERS These registers are used to read the 8 MSBs from the 4 SAR channels. Table 4-35. SAR_DATA_0 Register (0x1Dh) Bits Field 7:0 SLOT_0_DATA Description Latest slot 0 sample bits 11:4. Table 4-36. SAR_DATA_1 Register (0x1Eh) Bits Field 7:0 SLOT_1_DATA Description Latest slot 1 sample bits 11:4. Table 4-37. SAR_DATA_2 Register (0x1Fh) Bits Field 7:0 SLOT_2_DATA Description Latest slot 2 sample bits 11:4. Table 4-38. SAR_DATA_3 Register (0x20h) Bits Field 7:0 SLOT_3_DATA Description Latest slot 3 sample bits 11:4. 4.2.37 SAR OVERVIEW The SAR controller works via a scheduler that allocates time slots for each of the four channels. All four channels can operate up to the same maximum frequency. When the sampling frequency of a channel is to be reduced the time slot allocated to that channel is simply enabled less often. For example if one slot is to work at a quarter of the frequency of the others then only one in four of its allocated slot triggers the SAR to activate: FREQ0 FREQ1 FREQ2/3 counter slot 0 enable counter slot 1 enable counter slot 2 enable counter slot 3 enable Rotates at SAR clock / 72 Figure 4-16. Internal SAR Control Signals to SAR Module Each time slot is used to sample a single fixed input, slot 0 is used for VSAR 1, slot 1 for VSAR 2, slot 2 for either D_VDD or BB_VDD* and slot 3 for the A_VDD. When a particular time slot is activated the correct mux, clock and enable controls to the ADC module are produced and the output sampled when ready. If the D_VDD or the A_VDD are being sampled then a voltage divider is used to half the input to below the full scale reference of 2.5V. As this results in a current path to ground it is only inserted while the ADC is settling to reduce power consumption. Using this method, samples can be taken using as little power as possible while allowing sample rates as low as 1 Hz. The data can either be read directly or used to trigger interrupts when set voltages are passed. This reduces the baseband controllers software overhead and IO bandwidth, further reducing system power. 42 Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 The full scale digital output from the SAR is equal to 2.5V. The A_VDD and D_VDD inputs are divided by two during sampling. The SAR ADC can be activated at any time, even while the chip is in shutdown mode (chip mode '00'). This allows the LM4935 to perform housekeeping duties such as voltage monitoring with minimal power consumption. *Depending on SLOT_2_VBB in SAR_SLOT23 (0x1Ch). Only the 8 MSBS [11:4] from the 12 bits of SAR output data can be read back using the I2C interface. The SPI interface can be used to access all 12 bits of the SAR output data. In this case, GPIO2 should be set to SAR_SDO by setting GPIO_SEL in register (0x1Ah). The SAR channel selected by SAR_CH_SEL in the GPIO register is then output onto GPIO2 as follows: TEST_MODE/CS CLK SDI 15 14 13 12 GPIO2 11 1 0 11 1 0 SAR Data Figure 4-17. SPI SAR Read Transaction (GPIO2 set to SAR_SDO) In applications where the 8 MSBS [11:4] from the SAR output data is enough resolution, GPIO2 should be set to SPI_SDO by setting GPIO_SEL in register (0x1Ah). The SAR data is then output on GPIO2 as follows: TEST_MODE/CS CLK SDI 15 14 8 Ignored 11 GPIO2 Address 1 4 SAR Data Figure 4-18. SPI SAR Read Transaction (GPIO2 set to SPI_SDO) If the user performs a write to the GPIO register the changes will not take effect until the next SPI operation so SAR data can be read while the next channel is being selected. The SAR data is sampled at the start of the SPI transaction to ensure that the data is stable during the read operation. All 12 bits of the SAR output data for up to 2 SAR channels can be read back simultaneously through the bi-directional I2S interface. This is accomplished by setting I2S_SDO_DATA (bit [7:6] of (0x19h)) to the desired SAR channel(s). As mentioned previously in the Section 4.2.32 section, when SAR SDO is passed to the I2S bus, the SAR SDO's MSB is aligned with the MSB of I2S_SDO. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 43 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 4.2.38 DC VOLUME CONFIGURATION REGISTER This register is used to control the DC volume control system. Table 4-39. DC_VOLUME (0x21h) Bits Field 0 DC_VOL_ENB 1 DC_VOL_EFFECT 3:2 MAX_LEVEL Description Enables the DC volume control system to use the voltage applied on the VSAR 1 pin to set the gain of the DC volume control. (Note 32) Selects which volume is altered: DC_VOL_EFFECT Source 0 AUX/DAC 1 CPI Programs the maximum level that can be applied by the system MAX_LEVEL LEVEL 002 0 dB 012 −3 dB 102 −6 dB 112 −12 dB 4.2.39 SAR TRIGGER 1 CONFIGURATION REGISTER This register is used to setup a voltage trigger on one of the SAR outputs. Table 4-40. TRIG_1 (0x22h) Bits Field 0 TRIG_1_ENB Enables the 1st SAR trigger interrupt, if cleared will clear the IRQ. 1 TRIG_1_DIR Selects the direction the voltage should be moving: 3:2 TRIG_1_SOURCE 7:4 TRIG_1_LSB Description TRIG_1_DIR Trigger if signal passes: 0 Above Threshold 1 Below Threshold Programs the channel used by the trigger. TRIG_1_SOURCE Source 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 Sets bits 3:0 of the threshold used by the trigger. 4.2.40 SAR TRIGGER 1 MSBs CONFIGURATION REGISTER This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. Table 4-41. TRIG_1_MSB (0x23h) Bits Field 7:0 TRIG_1_MSB 44 Description Sets bits 11:4 of the threshold used by the trigger. Application Information Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 4.2.41 SAR TRIGGER 2 CONFIGURATION REGISTER This register is used to setup a voltage trigger on one of the SAR outputs. Table 4-42. TRIG_2 (0x24h) Bits Field 0 TRIG_2_ENB Enables the 2nd SAR trigger interrupt, if cleared will clear the IRQ. 1 TRIG_2_DIR Selects the direction the voltage should be moving: 3:2 Description TRIG_2_SOURCE 7:4 TRIG_2_DIR Trigger if signal passes: 0 Above Threshold 1 Below Threshold Programs the channel used by the trigger TRIG_2_LSB TRIG_2_SOURCE Source 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 Sets bits 3:0 of the threshold used by the trigger. 4.2.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. Table 4-43. TRIG_2_MSB (0x25h) Bits Field 7:0 TRIG_2_MSB Description Sets bits 11:4 of the threshold used by the trigger. 4.2.43 DEBUG REGISTER This register is used to set test modes within the device. Table 4-44. DEBUG (0x26h) Bits Field 0 RSVD Reserved Description 1 RSVD Reserved 2 RSVD Reserved 3 SOFT_RESET 4 RSVD Reserved 5 RSVD Reserved 6 RSVD Reserved 7 GPIO_TEST_MODE This field can be used to reset the chip without a power cycle. If set and GPIO_SEL = '010', then the GPIOs are configured to interface with the LMV1026 digital microphone as long as AUDIO_IF_MODE (0x19h) is not set to '11'. GPIO_SEL GPIO 1 GPIO 2 0002 RSVD RSVD 0012 RSVD RSVD 0102 VADC_CLOCK_OUT DIG_MIC_IN 0112 RSVD RSVD 1002 RSVD RSVD 1012 RSVD RSVD 1102 RSVD RSVD 1112 RSVD RSVD Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Application Information 45 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 5 Typical Performance Characteristics (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Stereo DAC Frequency Response fS = 8kHz +3 Stereo DAC Frequency Response Zoom fS = 8kHz +0.5 +0.4 +2 MAGNITUDE (dB) MAGNITUDE (dB) +0.3 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -2 -0.3 -3 20 -0.5 20 -0.4 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-1. Figure 5-2. Stereo DAC Frequency Response fS = 16kHz Stereo DAC Frequency Response Zoom fS = 16kHz +3 +0.5 +0.4 +2 MAGNITUDE (dB) MAGNITUDE (dB) +0.3 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -2 -0.3 -3 20 -0.5 20 -0.4 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-3. Figure 5-4. Stereo DAC Frequency Response fS = 24kHz Stereo DAC Frequency Response Zoom fS = 24kHz +3 +0.5 +0.4 +2 MAGNITUDE (dB) MAGNITUDE (dB) +0.3 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -2 -0.3 -3 20 -0.5 20 -0.4 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Typical Performance Characteristics 5k 10k 20k FREQUENCY (Hz) Figure 5-5. 46 50 100 200 500 1k 2k Figure 5-6. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Stereo DAC Frequency Response fS = 32kHz +3 Stereo DAC Frequency Response Zoom fS = 32kHz +0.5 +0.4 +2 MAGNITUDE (dB) MAGNITUDE (dB) +0.3 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -2 -0.3 -3 20 -0.5 20 -0.4 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 10k 20k FREQUENCY (Hz) Figure 5-7. Figure 5-8. Stereo DAC Frequency Response fS = 48kHz Stereo DAC Frequency Response Zoom fS = 48kHz +3 +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.4 -3 20 -0.5 20 50 100 200 500 1k 2k 5k 10k 20k 30k 50 100 200 500 1k 2k FREQUENCY (Hz) 10 Figure 5-9. Figure 5-10. THD+N vs Stereo DAC Input Voltage (0dB DAC, AUXOUT) Stereo DAC Crosstalk (0dB DAC, HP SE) +0 -10 5 -20 CROSSTALK (dB) 2 THD+N (%) 1 0.5 0.2 0.1 0.05 -30 -40 -50 -60 -70 -80 -90 0.02 0.01 1m 2m 5k 10k 20k FREQUENCY (Hz) 5m 10m 20m 50m 100m200m 500m 1 -100 20 2 I S INPUT VOLTAGE (FFS) Figure 5-11. 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-12. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 47 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) MONO ADC Frequency Response Zoom fS = 8kHz, 6dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) MONO ADC Frequency Response fS = 8kHz, 6dB MIC -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.3 -80 -0.4 -90 -100 20 +0.2 50 100 200 500 1k 2k -0.5 20 5k 10k 20k Figure 5-14. MONO ADC Frequency Response fS = 8kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 36dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 -30 -40 -50 -60 -70 -100 20 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -0.4 -90 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-15. Figure 5-16. MONO ADC Frequency Response fS = 16kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 16kHz, 6dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) 5k 10k 20k Figure 5-13. -80 -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.4 -90 -100 20 +0.2 -0.3 -80 50 100 200 500 1k 2k 5k 10k 20k -0.5 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-17. 48 50 100 200 500 1k 2k FREQUENCY (Hz) MAGNITUDE (dB) MAGNITUDE (dB) FREQUENCY (Hz) Figure 5-18. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) MONO ADC Frequency Response Zoom fS = 16kHz, 36dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) MONO ADC Frequency Response fS = 16kHz, 36dB MIC -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.3 -80 -0.4 -90 -100 20 +0.2 50 100 200 500 1k 2k -0.5 20 5k 10k 20k 5k 10k 20k Figure 5-19. Figure 5-20. MONO ADC Frequency Response fS = 24kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 6dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.4 -90 -100 20 +0.2 -0.3 -80 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-21. Figure 5-22. MONO ADC Frequency Response fS = 24kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 36dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) 50 100 200 500 1k 2k FREQUENCY (Hz) MAGNITUDE (dB) MAGNITUDE (dB) FREQUENCY (Hz) -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.3 -80 -0.4 -90 -100 20 +0.2 50 100 200 500 1k 2k 5k 10k 20k -0.5 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-23. Figure 5-24. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 49 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) MONO ADC Frequency Response Zoom fS = 32kHz, 6dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) MONO ADC Frequency Response fS = 32kHz, 6dB MIC -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.3 -80 -0.4 -90 -100 20 +0.2 50 100 200 500 1k 2k -0.5 20 5k 10k 20k 50 100 200 500 1k 2k Figure 5-25. Figure 5-26. MONO ADC Frequency Response fS = 32kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 36dB MIC +10 +0.5 +0 +0.4 -10 +0.3 -20 -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -0.4 -90 -100 20 +0.2 -0.3 -80 50 100 200 500 1k 2k -0.5 20 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 10k 20k FREQUENCY (Hz) Figure 5-27. Figure 5-28. MONO ADC HPF Frequency Response fS = 8kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') MONO ADC HPF Frequency Response fS = 16kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') +10 +0 +0 -10 -10 -20 -20 MAGNITUDE (dB) MAGNITUDE (dB) +10 -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 5-29. 50 5k 10k 20k FREQUENCY (Hz) MAGNITUDE (dB) MAGNITUDE (dB) FREQUENCY (Hz) Figure 5-30. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) MONO ADC HPF Frequency Response fS = 24kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') MONO ADC HPF Frequency Response fS = 32kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') +10 +0 +0 -10 -10 -20 -20 MAGNITUDE (dB) MAGNITUDE (dB) +10 -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) 10 5 200 500 Figure 5-31. Figure 5-32. MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 6dB MIC) MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 36dB MIC) 10 5 1k 2k 2 1 0.5 0.5 THD+N (%) THD+N (%) 100 FREQUENCY (Hz) 2 1 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 100P 200P 500P 1m 2m 5m 10m 20m 40m MIC INPUT VOLTAGE (Vrms) MIC INPUT VOLTAGE (Vrms) 0 Figure 5-33. Figure 5-34. MONO ADC PSRR vs Frequency AVDD = 3.3V, 6dB MIC MONO ADC PSRR vs Frequency AVDD = 5V, 6dB MIC 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 50 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-35. Figure 5-36. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 51 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) MONO ADC PSRR vs Frequency AVDD = 3.3V, 36dB MIC 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 0 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k MONO ADC PSRR vs Frequency AVDD = 5V, 36dB MIC 5k 10k 20k 20 50 100 200 FREQUENCY (Hz) Figure 5-38. AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 5-40. AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-41. 52 5k 10k 20k 50k 100k Figure 5-39. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 20 5k 10k 20k Figure 5-37. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 500 1k 2k Figure 5-42. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Figure 5-44. CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) CPOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-45. Figure 5-46. CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) CPOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 5k 10k 20k 50k 100k Figure 5-43. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 500 1k 2k -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-47. Figure 5-48. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 53 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC (EXTMIC inputs terminated, AGC on) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC (EXTMIC inputs terminated, AGC on) 0 -10 -20 PSRR (dB) PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-50. CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-49. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-52. CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-51. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-53. 54 50 100 200 500 1k 2k Figure 5-54. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC off) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-56. CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-55. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-58. CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-57. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-59. Figure 5-60. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 55 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC off) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-62. CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 3.3V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 3.3V (INTMIC DIFF inputs terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-61. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-64. CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC (INTMIC SE input terminated, AGC on) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC (INTMIC SE input terminated, AGC on) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-63. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-65. 56 50 100 200 500 1k 2k Figure 5-66. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Earpiece PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Figure 5-68. Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Earpiece PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-69. Figure 5-70. Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Earpiece PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 5k 10k 20k 50k 100k Figure 5-67. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 500 1k 2k -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-71. Figure 5-72. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 57 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.2V (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.2V (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Figure 5-74. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.2V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.2V (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-75. Figure 5-76. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB ADC, OCL 1.2V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB ADC, OCL 1.2V (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-77. 58 5k 10k 20k 50k 100k Figure 5-73. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 500 1k 2k Figure 5-78. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.5V (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.5V (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Figure 5-80. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.5V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.5V (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-81. Figure 5-82. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, OCL 1.5V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, OCL 1.5V (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 5k 10k 20k 50k 100k Figure 5-79. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 500 1k 2k -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-83. Figure 5-84. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 59 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, SE (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, SE (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Figure 5-86. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, SE (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, SE (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-87. Figure 5-88. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, SE (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, SE (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-89. 60 5k 10k 20k 50k 100k Figure 5-85. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 500 1k 2k Figure 5-90. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 20 5k 10k 20k FREQUENCY (Hz) Figure 5-92. Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-93. Figure 5-94. Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 500 1k 2k Figure 5-91. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-95. Figure 5-96. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 61 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.0V 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.0V -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-98. INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.5V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.5V 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 5-97. -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-99. Figure 5-100. INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.8V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.8V 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 5-101. 62 50 100 200 500 1k 2k Figure 5-102. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 3.3V AUXOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ 10 5 0 -20 2 1 -30 0.5 THD+N (%) PSRR (dB) -10 -40 -50 -60 0.2 0.1 0.05 0.02 0.01 0.005 -70 -80 -90 0.002 0.001 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-104. AUXOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ CPOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ 10 5 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) FREQUENCY (Hz) Figure 5-103. 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) 5k 10k 20k FREQUENCY (Hz) Figure 5-105. Figure 5-106. CPOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ Earpiece THD+N vs Frequency AVDD = 3.3V, 0dB, POUT = 500mW, 32Ω 10 10 5 5 2 1 2 0.5 1 THD+N (%) THD+N (%) 50 100 200 500 1k 2k 0.2 0.1 0.05 0.2 0.1 0.02 0.01 0.005 0.002 0.001 20 0.5 0.05 0.02 50 100 200 500 1k 2k 5k 10k 20k 0.01 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 5-107. Figure 5-108. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 63 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.5V, 0dB POUT = 7.5mW, 32Ω 10 10 5 5 2 2 1 1 THD+N (%) THD+N (%) Earpiece THD+N vs Frequency AVDD = 5V, 0dB, POUT = 50mW, 32Ω 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 0.01 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) 10 Figure 5-109. Figure 5-110. Headphone THD+N vs Frequency AVDD = 5V, OCL 1.5V, 0dB POUT = 10mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.2V, 0dB POUT = 7.5mW, 32Ω 10 5 2 2 THD + N (%) THD+N (%) 1 0.5 0.2 0.1 1 0.5 0.2 0.1 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 0.01 20 5k 10k 20k FREQUENCY (Hz) 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-112. Headphone THD+N vs Frequency AVDD = 5V, OCL 1.2V, 0dB POUT = 10mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, SE, 0dB POUT = 7.5mW, 32Ω 10 5 2 2 1 1 THD+N (%) THD+N (%) 50 100 200 Figure 5-111. 5 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 0.01 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Typical Performance Characteristics 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-113. 64 5k 10k 20k FREQUENCY (Hz) 5 10 50 100 200 500 1k 2k Figure 5-114. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Frequency AVDD = 5V, SE, 0dB POUT = 10mW, 32Ω 10 Loudspeaker THD+N vs Frequency AVDD = 3.3V, POUT = 400mW 15μH+8Ω+15μH 10 5 5 2 2 THD + N (%) THD+N (%) 1 0.5 0.2 0.1 1 0.5 0.2 0.1 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 0.01 20 5k 10k 20k 50 100 200 FREQUENCY (Hz) Figure 5-116. Loudspeaker THD+N vs Frequency AVDD = 5V, POUT = 400mW 15μH+8Ω+15μH Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 5 2 1 2 0.5 THD+N (%) 1 0.5 0.2 0.1 0.2 0.1 0.05 0.02 0.01 0.005 0.05 0.02 0.01 20 5k 10k 20k FREQUENCY (Hz) Figure 5-115. 10 THD + N (%) 500 1k 2k 50 100 200 500 1k 2k 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 5k 10k 20k OUTPUT POWER (W) FREQUENCY (Hz) 10 5 Figure 5-117. Figure 5-118. Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 32Ω 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 OUTPUT POWER (W) Figure 5-119. OUTPUT POWER (W) Figure 5-120. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 65 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) 10 5 Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 32Ω 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 16Ω 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 OUTPUT POWER (W) 10 5 OUTPUT POWER (W) Figure 5-121. Figure 5-122. Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 32Ω 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m 2m OUTPUT POWER (W) 10 5 Figure 5-123. Figure 5-124. Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m OUTPUT POWER (W) Typical Performance Characteristics 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-125. 66 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) Figure 5-126. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 50m 100m Figure 5-128. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 10m 20m Figure 5-127. 10 5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 0.2 0.1 0.05 0.02 0.01 0.005 2m 5m 10m 20m 0.002 0.001 1m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-129. Figure 5-130. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω 10 5 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 5m OUTPUT POWER (W) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-131. Figure 5-132. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 67 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω 10 5 2 1 0.5 THD+N (%) THD+N (%) 50m 100m Figure 5-134. 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 0.2 0.1 0.05 0.02 0.01 0.005 2m 5m 10m 20m 0.002 0.001 1m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-135. Figure 5-136. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 10m 20m Figure 5-133. 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Typical Performance Characteristics 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-137. 68 5m OUTPUT POWER (W) Figure 5-138. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 10m 20m 50m 100m Figure 5-139. Figure 5-140. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 2m 5m 10m 20m 50m 100m 10 5 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) OUTPUT POWER (W) Figure 5-141. Figure 5-142. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 32Ω 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) 5m OUTPUT POWER (W) THD+N (%) THD+N (%) OUTPUT POWER (W) 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 2m 0.2 0.1 0.05 0.02 0.01 0.005 5m 10m 20m 50m 100m 200m 0.002 0.001 1m OUTPUT POWER (W) 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-143. Figure 5-144. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 69 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N F vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 32Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 16Ω 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 2m 5m 10m 20m 50m 100m Figure 5-145. Figure 5-146. Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 32Ω 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 2m 0.002 0.001 1m 5m 10m 20m 50m 100m 200m 2m OUTPUT POWER (W) 10 5 10m 20m 50m 100m Figure 5-147. Figure 5-148. Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 2 1 0.5 THD+N (%) THD+N (%) 5m OUTPUT POWER (W) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Typical Performance Characteristics 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-149. 70 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) OUTPUT POWER (W) Figure 5-150. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 50m 100m Figure 5-152. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 10m 20m Figure 5-151. 10 5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 0.2 0.1 0.05 0.02 0.01 0.005 2m 5m 10m 20m 0.002 0.001 1m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-153. Figure 5-154. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω 10 5 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 5m OUTPUT POWER (W) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-155. Figure 5-156. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 71 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω 10 5 2 1 0.5 THD+N (%) THD+N (%) 50m 100m Figure 5-158. 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 0.2 0.1 0.05 0.02 0.01 0.005 2m 5m 10m 20m 0.002 0.001 1m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-159. Figure 5-160. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 10m 20m Figure 5-157. 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Typical Performance Characteristics 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-161. 72 5m OUTPUT POWER (W) Figure 5-162. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 50m 100m Figure 5-164. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 10m 20m Figure 5-163. 10 5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 0.2 0.1 0.05 0.02 0.01 0.005 2m 5m 10m 20m 0.002 0.001 1m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-165. Figure 5-166. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω 10 5 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 5m OUTPUT POWER (W) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-167. Figure 5-168. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 73 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 10m 20m 50m 100m Figure 5-169. Figure 5-170. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω 10 5 10 5 THD + N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-171. Figure 5-172. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 16Ω 2 1 0.5 10 5 THD + N (%) THD + N (%) 10 5 0.2 0.1 0.05 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Typical Performance Characteristics 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-173. 74 5m OUTPUT POWER (W) Figure 5-174. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.5 THD+N (%) THD + N (%) 2 1 0.5 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 32Ω 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 10 5 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 16Ω 10 5 2 1 0.5 THD+N (%) THD+N (%) 50m 100m Figure 5-176. 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 5-177. Figure 5-178. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 32Ω 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) 10m 20m Figure 5-175. 2 1 0.5 10 5 5m OUTPUT POWER (W) 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 2m 0.2 0.1 0.05 0.02 0.01 0.005 5m 10m 20m 50m 100m 200m 0.002 0.001 1m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) Figure 5-179. Figure 5-180. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 75 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) 10 5 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 32Ω Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH 10 5 2 1 2 THD + N (%) THD+N (%) 0.5 0.2 0.1 0.05 1 0.5 0.2 0.1 0.02 0.01 0.005 0.05 0.02 0.002 0.001 1m 2m 0.01 10m 20m 5m 10m 20m 50m 100m 200m Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH 10 10 5 5 2 2 1 0.5 0.2 2 1 2 0.2 0.1 0.05 0.02 0.02 50m 100m 200m 500m 1 0.01 10m 20m 2 OUTPUT POWER (W) 50m 100m 200m 500m OUTPUT POWER (W) Figure 5-183. Figure 5-184. Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH 10 10 5 5 2 2 1 THD + N (%) THD + N (%) 1 1 0.05 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 50m 100m 200m 500m 1 2 0.01 10m 20m OUTPUT POWER (W) 50m 100m 200m 500m OUTPUT POWER (W) Figure 5-185. Typical Performance Characteristics 2 0.5 0.1 0.01 10m 20m 1 OUTPUT POWER (W) Figure 5-182. 0.01 10m 20m 76 50m 100m 200m 500m Figure 5-181. THD + N (%) THD + N (%) OUTPUT POWER (W) Figure 5-186. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH 10 10 5 5 2 2 1 THD + N (%) THD + N (%) Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 10m 20m 50m 100m 200m 500m 1 0.01 10m 20m 2 OUTPUT POWER (W) 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Figure 5-188. Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH 10 10 5 5 2 2 1 THD + N (%) THD + N (%) Figure 5-187. 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 10m 20m 50m 100m 200m 500m 1 0.01 10m 20m 2 OUTPUT POWER (W) 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Figure 5-190. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 10 10 5 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) Figure 5-189. 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 2 3 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-191. Figure 5-192. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL 2 3 Typical Performance Characteristics 77 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB CPI fOUT = 1kHz, 5kΩ 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) 10 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 2 100m 500m 2 3 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-193. Figure 5-194. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ 10 5 THD + N (%) THD + N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.002 0.001 500m 1 6m 10m 20m 50m 100m 200m 2 3 500m 1 6m10m 20m 50m100m 200m 2 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-195. Figure 5-196. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ 10 5 THD + N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20m 4 10 5 2 1 0.5 THD + N (%) 4 10 5 2 1 0.5 78 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 50m 100m 200m 500m 1 2 3 0.002 0.001 20m 50m 100m 200m 500m 1 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-197. Figure 5-198. Typical Performance Characteristics 2 4 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 10 5 10 5 2 1 2 1 0.5 0.5 THD + N (%) THD + N (%) CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ 0.2 0.1 0.05 0.02 0.01 0.05 0.02 0.01 0.005 0.005 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 2 3 2 3 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-199. Figure 5-200. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ 10 5 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD + N (%) 0.2 0.1 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20m 0.002 0.001 50m 100m 200m 500m 1 6m 10m 20m 2 3 50m 100m 200m 500m 1 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-201. Figure 5-202. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 6dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 6dB MIC fOUT = 1kHz, 5kΩ 10 5 2 2 1 0.5 1 0.5 THD+N (%) THD+N (%) 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.02 0.01 0.005 0.01 0.005 0.002 0.002 0.001 1m 0.001 1m 5m 2m 10m 20m 100m 500m 50m 200m 1 2 4 5m 2m 10m 20m 100m 500m 50m 200m 1 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-203. Figure 5-204. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL 2 4 Typical Performance Characteristics 79 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) CPOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20m 0.002 0.001 20m 10 5 50m 100m 200m 500m 1 2 3 Figure 5-205. Figure 5-206. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 36dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 36dB MIC fOUT = 1kHz, 5kΩ 10 5 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 10m 20m 50m100m 200m 500m 1 0.002 0.001 10m 20m 50m100m 200m 500m 1 2 4 2 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 5-207. Figure 5-208. Headphone Crosstalk vs Frequency OCL 1.2V, 0dB AUX, 32Ω Headphone Crosstalk vs Frequency OCL 1.5V, 0dB AUX, 32Ω CROSSTALK (dB) +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 4 2 1 THD+N (%) THD+N (%) 2 OUTPUT VOLTAGE (VRMS) 0.5 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-209. Typical Performance Characteristics 4 +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 FREQUENCY (Hz) 80 50m 100m 200m 500m 1 OUTPUT VOLTAGE (VRMS) 2 1 CROSSTALK (dB) CPOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ Figure 5-210. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. (continued) CROSSTALK (dB) Headphone Crosstalk vs Frequency SE, 0dB AUX, 32Ω +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 5-211. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Typical Performance Characteristics 81 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com 6 Board Schematic Diagrams LM4935 Demonstration Board Schematic Diagram AGND C33 0.1 PF DVDD S11 SW SPST R18 47k 5 15 18 16 14 20 8 0.1 PF 0.1 PF SW SPDT G7 F6 F7 E7 E6 C5 D5 S3 24 SW SPDT 28 27 26 S4 SW SPDT AUDIO RXSEL1 RXSEL0 TXSEL0 10 11 13 U2 JP12 D3 C4 A6 A5 F3 E4 25 1 2 3 MCLK I2S_WS I2S_CLK I2S_SDI I2S_SDO GPIO_2 GPIO_1 AUX_L AUX_R VSAR1 VSAR2 CPI_POS CPI_NEG A2 F1 HP_VMID R3 5k USB_SPIDO USB_SCL USB_SDA C23 USB_CS AUX_R SCL SDA CS / TEST_MODE INT_BIAS SPI_MODE IRQ CPO_POS CPO_NEG A_VSS B1 G2 LS_VSS PLL_VSS INT_MIC_NEG D_VSS D4 E5 G4 F4 A7 1 PF X2 USB_SCL USB_CS 1 3 5 7 9 11 13 15 2 1 S19 2 4 6 8 10 12 14 16 SW SPST USB_5V 1 2 VSAR1 JP26 JP15 USB_SPIDO 2 1 2 1 JP16 CPO (RCA) VSAR2 USB_3.3V CPI SW SPST 1 PF R6 JP8 2.2k 1 2 E2 S6 E1 SW SPDT LEFT HP R7 SW SPST D1 JP23 MIC LEFT 47 PF SW SPST C1 CPO (Header) JP11 SLEEVE 47 PF 4 Conductor Headset Jack (2.5mm) R8 C3 JP9 2.2k C20 1 PF PLL_FILT U1 JP10 USB_SDA EXT MIC C15 C7 C6 B5 JP14 MOUNTING SUPPORT 1 2 S20 RIGHT B4 1 PF USB_SPI_M C25 JP7 AUX_OUT (RCA) C13 S8 R4 5k INT_MIC_POS C24 AUX_OUT (Header) 2 1 S7 1 PF SW SPST 1 2 JP25 G1 G3 A1 B2 G5 F5 A4 E3 C2 C14 1 PF 100k 1 2 EP (Header) JP6 LM4935RL G6 2 4 6 8 10 12 14 16 JP5 L2 1 mH L1 1 mH 1k HP_L R2 5k C22 JP13 R16 FILTERED LS OUTPUT F2 LS_POS LS_NEG EP_NEG EP_POS AUX_OUT_POS AUX_OUT_NEG EXT_MIC MIC_DET EXT_BIAS HP_VMID_FB BBVDD AUX_L AVDD R5 300 UNFILTERED LS OUT LS_VDD SW SPDT D7 S2 S17 USB_SPI_M 0.1 PF HP_R C32 22 nF X1 1 3 5 7 9 11 13 15 0.1 PF LS_VDD 6 21 VL VA OMCK RXP3 RXP2 RXP1 U 96 kHz NV/RERR TX FILT 0.1 PF 1 2 EP (Banana) 2 1 R17 47k CS8416 RXN C10 S1 RXP0 R15 3k C31 1 nF 23 12 4 0.01 PF C30 DGND C29 0.01 PF R22 47k R21 47k R20 47k R19 47k 75 22 S12 R12 C9 1 2 FILTERED LS OUT (BANANA) JP3 0.1 PF RMCK OLRCLK OSCLK SDOUT AGND SW SPDT C RCBL RST VD 17 9 PB SPST JP20 S/PDIF IN SW SPDT R14 47k B S13 A TXSEL1 0.1 PF 2 19 C26 7 GND C8 D_VDD 1 10 PF C28 OUTPUT 1 PF C7 A_VDD C34 TOSLINK RECEIVER 1 PF JP1 3 R13 47k 1 PF C6 D6 S18 VCC 1 PF B7 JP21 L3 Ferrite Bead JP27 JP4 2 1 1 PF 7 6 5 4 3 2 1 C12 22 nF C5 C4 C3 BB_VDD SW SPST DVDD C2 PLL_VDD 2 1 14 13 12 11 10 9 8 C1 SW SPST DIGITAL INTERFACE C27 0.1 PF C11 22 nF JP24 S21 AVDD USB_3.3V S15 AVDD DVDD DGND USB_5V SW SPST BYPASS BB_VDD DVDD S16 2 1 SW SPST JP18 BBVDD AVDD JP19 S14 2 1 VREF BBVDD JP17 D2 6.1 A3 C16 1 2 1 PF B3 C17 R11 1k 1 PF S9 RIGHT HP R10 2.2k B6 SW SPDT R9 422 S10 SW SPDT C19 10 nF C21 C18 1 PF 150 nF JP28 MIC LEFT S22 JP2 SW SPST 1 2 IRQ 2 1 INT_MIC RIGHT SLEEVE 4 Conductor Headset Jack (3.5mm) JP22 USB INTERFACE LEFT RIGHT SLEEVE Microphone Jack (3.5mm) 6.2 Demoboard PCB Layout Figure 6-1. Top Silkscreen 82 Board Schematic Diagrams Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Figure 6-2. Top Layer Figure 6-3. Mid Layer 1 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Board Schematic Diagrams 83 LM4935, LM4935RLEVAL SNAS296E – OCTOBER 2005 – REVISED MAY 2013 www.ti.com Figure 6-4. Mid Layer 2 Figure 6-5. Bottom Layer 6.3 Product Status Definitions Datasheet Status Product Status Definition Advance Information Formative or in Design This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This data sheet contains preliminary data. Supplementary data will be published at a later date. No Identification Noted Full Production This data sheet contains final specifications. Obsolete Not in Production This data sheet contains specifications on a product that has been discontinued. The datasheet is printed for reference information only. 84 Board Schematic Diagrams Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL LM4935, LM4935RLEVAL www.ti.com 6.4 SNAS296E – OCTOBER 2005 – REVISED MAY 2013 Revision History Rev Date Description 1.0 5/11/05 Filled in the actual limits (for TBDs) under Limit and edited few Typical values, all under the EC table. Edits from Alvin F. 1.1 7/29/05 Input more edits. Replaced the correct boards. Replaced the Schematic Diagram (pg 60). 1.2 9/8/05 Added the 1st set of Typ Perf curves. 1.3 9/21/05 Added a couple of tables. 1.4 9/30/05 Input text edits. 1.5 10/5/05 Input more edits. 1.6 10/11/05 More edits. 1.7 10/12/05 First D/S WEB release. 1.8 10/14/5 Input more text edits after the 1st released. 1.9 10/17/05 Input some text edits, then re-released D/S to the WEB. 2.0 10/18/05 More text edits. Also used graphic 20134107 back. 2.1 12/19/05 Added the RL package 2.2 12/20/05 Deleted the WL pkg and replaced with the RL pkg. 2.3 1/19/06 Fixed 20134132(top silkscreen) and 35 (schem layout) plus few text edits. 2.4 1/25/06 Fixed the value on X3 (mktg outline). Rereleased D/S to the WEB. E 5/03/13 Changed layout of National Data Sheet to TI format. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL Board Schematic Diagrams 85 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM4935RL/NOPB ACTIVE DSBGA YPG 49 250 Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GG7 LM4935RLX/NOPB ACTIVE DSBGA YPG 49 1000 Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GG7 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM4935RL/NOPB DSBGA YPG 49 250 178.0 12.4 LM4935RLX/NOPB DSBGA YPG 49 1000 178.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.19 4.19 0.76 8.0 12.0 Q1 4.19 4.19 0.76 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4935RL/NOPB DSBGA YPG LM4935RLX/NOPB DSBGA YPG 49 250 210.0 185.0 35.0 49 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPG0049xxx D 0.650±0.075 E RLA49XXX (Rev B) D: Max = 3.94 mm, Min = 3.88 mm E: Max = 3.94 mm, Min = 3.88 mm 4214898/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated