iP2005CPbF PD-60360 Synchronous Buck Optimized LGA Power Block Features • • • • • • • • • 40A Multiphase building block No derating up to TPCB = 95ºC Optimized for low power loss Bias supply range of 4.5V to 7.0V Operation up to 1.5MHz Bi-directional current flow Under Voltage Lockout LGA interface 7.65mm x 7.65mm outline Applications • • • • Multi-phase Architectures Low Duty-Ratio, High Current Microprocessor Power Supplies High Frequency Low Profile DC-DC Converters Description The iP2005C is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 7.65mm x 7.65mm x 1.66mm power block. The only additional components required for a complete multiphase converter are a PWM controller, the output inductors, and the input and output capacitors. Package Description iP2005CPbF iP2005CTRPbF Interface Connection LGA LGA Standard Quantity 10 2000 Typical Application www.irf.com 04/09/2009 1 iP2005CPbF PD-60360 Absolute Maximum Ratings VIN to PGND ……………………..……...-0.5V to 16.5V VDD to PGND …………………….….…..-0.5V to 7.5V PWM to PGND ………………….………-0.5V to VDD + 0.5V (Note 1) ENABLE to PGND …………………….. -0.5V to VDD + 0.5V (Note 1) Storage Temperature …………………. -60ºC to 150ºC Block Temperature….. …………………. -40ºC to 135ºC (Note 2) ESD Rating……………………………... JEDEC, JESD22-A114 (HBM[4KV], Class 3A) ……………………………... JEDEC, JESD22-A115 (MM[400V], Class C) MSL Rating……………………………… 3 Reflow Temperature …..………………..260ºC Peak CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Recommended Operation Conditions PARAMETER Min Typ Max Units Supply Voltage (VDD) 4.5 - 7.0 V Input Voltage (VIN) 2.5 - 13.2 V Output Voltage (VOUT) - - 5.5 V Output Current (IOUT) - - 40 A 250 - 1500 kHz - - 85 % Minimum On Time 50 - - ns Block Temperature -40 - 125 ºC Switching Frequency (FSW) On Time Duty Cycle Conditions Electrical Specifications These specifications apply for TBLK = 0ºC to 125ºC and VDD = 5.0V, unless otherwise specified. PARAMETER Min Typ Max Units Conditions - 7.8 9.4 W VIN = 12V, VDD = 5.0V, VOUT = 1.3V, IOUT = 40A, FSW = 1MHz, LOUT = 0.3uH, TBLK = 25ºC - - 0.5 mA VIN = 12V, ENABLE = 0V -30 - - µA Iout=0, current pulled from VSW until VSW=0 PLOSS Power Block Losses VIN Leakage Current VSW Leakage Current VDD www.irf.com 04/09/2009 2 iP2005CPbF PD-60360 PARAMETER Min Typ Max Units Conditions Supply Current (Stand By) - 3 4 mA Supply Current (Operating) - 60 75 mA VDD = 5.0V, ENABLE = 0V VIN = 12V, ENABLE = VDD = 5.0V, FSW = 1MHz, Vo = 1.3V VDD Rising 3.8 4.15 4.5 V VDD Falling 3.6 3.95 4.3 V Hysteresis - 200 - mV Logic Level Low Threshold (VIL) - - 0.8 V Logic Level High Threshold (VIH) 2.0 - - V Threshold Hysteresis - 100 - mV Weak Pull-down impedance - 100 - kΩ Rising Propagation Delay (TPDH) - 40 - ns Falling Propagation Delay (TPDL) - 75 - ns PWM INPUT Logic Level Low Threshold (VIL) Logic Level High Threshold (VIH) Threshold Hysteresis 2.0 - 100 0.8 - V V mV Weak Pull-down Impedance - 100 - kΩ Rising Propagation Delay (TPDH) - 60 - ns Falling Propagation Delay (TPDL) - 30 - ns Power-On Reset (POR) VDD Rising & Falling ENABLE INPUT VDD = POR to 7.0V VDD = POR to 7.0V Notes: 1. Must not exceed 7.5V. 2. Block temperature (TBLK) is defined as the highest Junction temperature within the package www.irf.com 04/09/2009 3 iP2005CPbF PD-60360 Power Loss Curve 15 14 VI = 12V VD = 5.0V VO = 1.3V FSW = 1MHz LO = 300nH T BLK = 125ºC Power Loss(W) 13 12 11 10 9 8 Maximum Typical 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Output Current(A) Figure 1 Power Loss Curve SOA Curve Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 44 40 36 Output Current (A) 32 Safe Operating Area 28 24 20 16 Tx 12 VI = 12V VD = 5.0V VO = 1.3V Fsw = 1MHz LO = 300nH 8 4 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) Figure 2 Safe Operating Area Curve www.irf.com 04/09/2009 4 iP2005CPbF PD-60360 Typical Performance Curves 1.15 1.10 1.30 5.5 1.25 4.4 3.3 2.2 1.05 1.1 1.00 0.0 0.95 -1.1 0.90 -2.2 2.5 4 5.5 7 8.5 10 Input Voltage (V) 12 13 Power Loss (Normalized) 1.20 6.6 0.99 -0.2 0.98 -0.4 0.3 0.4 0.5 0.6 Output Inductance (µH) 0.7 0.8 6.50 Power Loss (Normalized) 2.0 1.6 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 7.00 Figure 7 Normalized Power Loss vs. Drive Voltage www.irf.com -1.0 -2.0 1.3 1.8 2.3 Output Voltage (V) 2.8 3.3 1.1 1.0 3.9 VI = 12.0V VDD = 5.0V VO = 1.3V IOUT = 40A LO = 300nH T BLK = 125ºC 2.0 0.0 0.9 -2.0 0.8 -3.9 500 750 1000 1250 -5.9 1500 Figure 6 Normalized Power Loss vs. Switching Frequency SOA Temp Adjustment (ºC) 5.00 5.50 6.00 Drive Voltage (V) 0.95 Switching Frequency (kHz) VI = 12.0V VO = 1.3V IO = 40A FSW = 1MHz LO = 300nH T BLK = 125ºC 4.75 0.0 0.7 250 Figure 5 Normalized Power Loss vs. Inductance 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0.86 4.50 1.00 1.2 Power Loss (Normalized) 0.0 0.2 1.0 04/09/2009 120 VI = 12.0V 110 VDD = 5.0V 100 VO = 1.3V 90 IOUT = 40A 80 LO = 300nH 70 T BLK = 125ºC 60 50 40 30 20 10 0 250 500 Average IDD (mA) Power Loss (Normalized) 0.2 1.00 0.1 2.0 1.05 SOA Temp Adjustment (oC) 0.4 2.9 Figure 4 Normalized Power Loss vs. Output Voltage SOA Temp Adjustm ent (o C) 1.01 0.7 3.9 1.10 0.8 0.9 VI = 12.0V VDD = 5.0V VO = 1.3V IOUT = 40A FSW = 1MHz T BLK = 125ºC 1.02 1.15 4.9 0.90 Figure 3 Normalized Power Loss vs. Input Voltage 1.03 1.20 14 1.04 5.9 VI = 12.0V VDD = 5.0V IOUT = 40A FSW = 1MHz LO = 300nH T BLK = 125ºC SOA Temp Adjustment (oC) VD = 5.0V VO = 1.3V IO = 40A FSW = 1MHz LO = 300nH T BLK = 125ºC 1.25 SOA Temp Adjustment (oC) Power Loss (Normalized) 1.30 750 1000 1250 1500 Switching Frequency (kHz) Figure 8 Max. Drive Current vs. Switching Frequency 5 iP2005CPbF PD-60360 P IN = V IN Average x I IN Average P DD = V DD Average x I DD Average P O UT = V O UT Average x I O UT Average P LO SS = (P IN + P DD ) - P O UT Average VDD Current A Average VDD Voltage V DC DC Average Input Current Average Input Voltage A N /C V IN Average Output Current V SW A V DD ENABLE V PW M P G ND N/C iP2005C Averaging Circuit Average Output Voltage V Figure 9 Power Loss Test Circuit 90% PW M 10% 90% V SW 10% t PDH t PD L Figure 10 Timing Diagram www.irf.com 04/09/2009 6 iP2005CPbF PD-60360 Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case. Please refer to International Rectifier Application Note AN1047 for further details on using this SOA curve in your thermal environment. Procedure 1. Calculate (based on estimated Power Loss) or measure the Case temperature on the device and the board temperature near the device (1mm from the edge). 2. Draw a line from Case Temperature axis to the PCB Temperature axis. 3. Draw a vertical line from the TX axis intercept to the SOA curve. 4. Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. Figure 11 SOA Example, Continuous current ≈ 31A for TPCB = 100ºC & TCASE = 110ºC www.irf.com 04/09/2009 7 iP2005CPbF PD-60360 Calculating Power Loss and SOA for Different Operating Conditions To calculate Power Loss for a given set of operation conditions, the following procedure should be followed: Power Loss Procedure 1. Determine the maximum current and obtain the maximum power loss from figure 1 2. Use the normalized curves to obtain power loss values that match the operating conditions in the application 3. The maximum power loss under the application conditions is then the product of the power loss from figure 1and the normalized values. To calculate the Safe Operating Area (SOA) for a given set of operating conditions, the following procedure should be followed: SOA Procedure 1. Determine the maximum PCB and CASE temperature at the maximum operating current for each iP2005C 2. Use the normalized curves to obtain SOA temperature adjustments that match the operating conditions in the application 3. Then, add the sum of the SOA temperature adjustments to the TX axis intercept in figure 2 Design Example Operating Conditions: Output Current = 30A Input Voltage = 10V Output Voltage = 1.3V Switching Freq = 750 kHz Inductor = 0.2µH Drive Voltage (VDD) = 5V Calculating Maximum Power Loss: (Figure 1) Maximum power loss = 7.0W (Figure 3) Normalized power loss for input voltage ≈ 0.975 (Figure 5) Normalized power loss for output inductor ≈ 1.012 (Figure 6) Normalized power loss for switch frequency ≈ 0.88 Calculated Maximum Power Loss ≈ 7.0W x 0.975 x 1.0 x 1.012 x 0.88 ≈ 6.09W www.irf.com 04/09/2009 8 iP2005CPbF PD-60360 Calculating SOA Temperature: (Figure 3) SOA temperature adjustment for input voltage ≈ -0.6ºC (Figure 5) SOA temperature adjustment for output inductor ≈ 0.25 ºC (Figure 6) SOA temperature adjustment for switch frequency ≈ -2.5 ºC TX axis intercept adjustment ≈ -0.6 ºC + 0.25 ºC – 2.5 ºC ≈ -2.9 ºC Assuming TPCB = 100ºC & TCASE = 110ºC, the following example shows how the SOA current is adjusted for TX decrease of 2.8 ºC Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 44 5 40 Output Current (A) 36 3 32 28 2 Safe Operating Area 24 20 16 4 Tx 12 VI = 12V VD = 5.0V VO = 1.3V Fsw = 1MHz LO = 300nH 8 4 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) 1. Draw a line from Case Temperature axis to the PCB Temperature axis. 2. Draw a vertical line from the TX axis intercept to the SOA curve. 3. Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. 4. Draw a new vertical line from the TX axis by adding or subtracting the SOA adjustment temperature from the original TX intercept point. 5. Draw a horizontal line from the intersection of the new vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the new SOA continuous current. The SOA adjustment indicates the part is still allowed to run at a continuous current of 39A. www.irf.com 04/09/2009 9 iP2005CPbF PD-60360 Internal Block Diagram Figure 12 Internal Block Diagram Pin Description Pin Number Pin Name Description 1 VIN Input voltage pin. Connect input capacitors close to this pin. 2 VSW Voltage Switching Node – pin connection to the output inductor. 3 PGND Power Ground 4 VDD Supply voltage to internal circuitry. 5 PWM 6 ENABLE 7,8 N/C TTL level input to MOSFET drivers. When PWM is HIGH, the Control FET is on and the Sync FET is off. When PWM is LOW, the Sync FET is on and the Control FET is off. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the Control and Synchronous FETs are turned off. No Connection, can be left floating. (Note A) Notes: A. It is recommended to connect PIN 7 and 8 to PIN 1 on PCB to reduce thermal resistance. www.irf.com 04/09/2009 10 iP2005CPbF PD-60360 Recommended PCB Layout N/C 8 VIN 1 N/C 7 VSW 2 ENABLE 6 PWM 5 PGND 3 VDD 4 Copper Solder Mask Over Copper Solde Mask Over FR-4 A A Section A-A Figure 13 Top copper and Solder-mask layer of PCB layout www.irf.com 04/09/2009 11 iP2005CPbF PD-60360 U1 L1 C1x C6x C3 C2 C1 PGND PGND PGND PGND PGND VIN VIN VIN VIN VIN VIN 1 N/C 8 VIN VIN VIN PGND PGND PGND N/C 7 VSW 2 ENABLE 6 VSW PWM 5 PGND 3 C4 C5 C6 VDD 4 Bottom Component Layer Top Component Layer Figure 14 Top & Bottom Component and Via Placement (Topside, Transparent view down) PCB Layout Guidelines The following guidelines are recommended to reduce the parasitic values and optimize overall performance. • All pads on the iP2005C footprint design need to be Solder-mask defined (see Figure 13). Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint design guidance. • Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal performance. • A minimum of six 10µF, X5R, 16V ceramic capacitors per iP2005C are needed for greater than 30A operation at 1MHz switching frequency. This will result in the lowest loss due to input capacitor ESR. • Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where there is a heatsink on the case of iP2005C, place all six ceramic capacitors right underneath the iP2005C footprint (see Figure Bottom Component Layer). In cases where there is no heatsink, C1 and C6 on the bottom layer may be moved to the C1x and C6x locations (respectively) on the top component layer (see Figure Top Component Layer). In both cases, C2 – C5 need to be placed right underneath the iP2005C PCB footprint. • Dedicate at least two layers to PGND. • Duplicate the Power Nodes on multiple layers (refer to AN1029). www.irf.com 04/09/2009 12 iP2005CPbF PD-60360 Mechanical Outline Drawing CORNER ID 0.15 [.006] C 7.65 [.301] B A 8 NC 1 VIN 7 NC CORNER ID 2 VSW 6 EN 5 PWM 7.65 [.301] 3 PGND 4 VDD ELECTRICAL I/O 0.15[.006] C 0.07 [.0027] C TOP VIEW 4 C 3.48 [.137] 1.66 [.065] CORNER ID 0.31 [.012] 1.65 [.065] NOTES: 0.31 [.012] 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES] 3. CONTROLLING DIMENSION: MILLIMETER 0.79 [.031] 1.90 [.075] 4X 0.66 [.026] 4 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SOLDER RESIST OPENING 0.79 [.031] 1.90 [.075] 5X 0.89 [.035] 1.78 [.070] 3X 3.86 [.152] SIDE VIEW BOTTOM VIEW Figure 15 Mechanical Outline Drawing www.irf.com 04/09/2009 13 iP2005CPbF PD-60360 Figure 16 Tape and Reel Information www.irf.com 04/09/2009 14 iP2005CPbF PD-60360 Recommended Solder Paste Stencil Design CORNER ID Figure 17 Solder Paste Stencil Design The recommended reflow peak temperature is 260°C. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. Figure 18 Part Marking www.irf.com 04/09/2009 15