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FAN73912 High-Current, Half-Bridge, GateDriver IC The FAN73912 is a monolithic half bridge gate-drive IC designed for high-voltage and high-speed driving for MOSFETs and IGBTs that operate up to +1200 V. www.onsemi.com The advanced input filter of HIN provides protection against short-pulsed input signals caused by noise. PACKAGE PICTURE An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8 V (typical) for VBS=15 V. The UVLO circuit prevents malfunction when VCC and VBS are lower than the specified threshold voltage. Output drivers typically source and sink 2 A and 3 A, respectively. Wide 16-SOIC Features Floating Channel for Bootstrap Operation to +1200 V Typically 2 A/ 3 A Sourcing/Sinking Current Driving Capability for Both Channels Gate Driver Supply (VCC) Range from 12 V to 20 V Separate Logic Supply (VDD) Range from 3 V to 20 V Extended Allowable Negative VS Swing to -9.8 V for Signal Propagation at VCC=VBS=15 V Built-in Cycle-by-Cycle Edge-Triggered Shutdown Logic Built-in Shoot-Through Protection Logic Common-Mode dv/dt Noise Canceling Circuit UVLO Functions for Both Channels Built-in Advanced Input Filter Matched Propagation Delay Below 50 ns Outputs in-Phase with Input Signal Logic and Power Ground +/- 10 V Offset LOT No. FAN73912 MX ORDERING INFORMATION Device (1) FAN73912MX 1. Typical Applications MARKING DIAGRAM Package Packing Method Wide16SOIC Tape & Reel This device passed wave-soldering test by JESD22A-111 Industrial Motor Driver UPS Solar Inverter Ballast General-Purpose Half-Bridge Topology. © Semiconductor Components Industries, LLC, 2016 December 2016- Rev. 1 1 Publication Order Number: FAN73912/D FAN73912 Up to 1200V Q1 Typically 3.3~15V R1 9 NC HO 8 10 NC VB 7 11 VDD VS 6 HIN 12 HIN NC 5 Controller SD 13 SD NC 4 LIN 14 LIN VCC 3 15 VSS COM 2 CBOOT Load DBOOT RBOOT 15V C1 Q2 R2 16 NC LO 1 Figure 1. Application Schematic – Adjustable Option 7 VB 8 HO 6 VS 3 VCC 1 LO 2 COM UVLO HIN 12 LIN 14 13 VSS 15 SCHMITT TRIGGER INPUT VSS/COM LEVEL SHIFT NOISE CANCELLER R R S Q SHOOTTHROUGH PREVENTION UVLO CYCLE-ByCYCLE EDGE TRIGGERED SHUTDOWN DELAY DRIVER SD HS(ON/OFF) DRIVER 11 PULSE GENERATOR VDD LS(ON/OFF) Pin 4,5,9,10 and 16 are no connection Figure 2. Simplified Block Diagram www.onsemi.com 2 FAN73912 PIN CONNECTIONS 1 16 NC COM 2 15 VSS VCC 3 14 LIN NC 4 13 SD NC 5 12 HIN VS 6 11 VDD VB 7 10 NC HO 8 9 NC FAN73912 LO Figure 3 Pin Connections – Wide 16-SOIC (Top View) PIN FUNCTION DESCRIPTION Pin No. Pin Name 1 LO Low-Side Driver Output Description 2 COM Low-Side Driver return 3 VCC Low-Side Supply Voltage 4 NC No Connection 5 NC No Connection 6 Vs High-Voltage Floating Supply Return 7 VB High-Side Floating Supply 8 HO High-Side Driver Output 9 NC No Connection 10 NC No Connection 11 VDD Logic Supply Voltage 12 HIN Logic Input for High-Side Gate Driver Output 13 SD Logic Input for Shutdown 14 LIN Logic Input for Low-Side Gate Driver Output 15 VSS Logic Ground 16 NC No Connection www.onsemi.com 3 FAN73912 MAXIMUM RATINGS (Note 2) TA=25°C, unless otherwise specified. All voltage parameters are referenced to COM unless otherwise stated in the table. Symbol 5. Max. Unit High-Side Floating Supply Voltage -0.3 1225.0 V VS High-Side Floating Offset Voltage VB- 25 VB+0.3 V VHO High-Side Floating Output Voltage VS-0.3 VB+0.3 V VCC Low-Side Supply Voltage -0.3 25 V VLO Low-Side Floating Output Voltage VDD Logic Supply Voltage VSS Logic GND VIN Logic Input Voltage (HIN, LIN and SD) -0.3 VCC+0.3 V VSS-0.3 VSS+25 V VDD -25 VDD+0.3 V VSS + VDD -25.3 VDD+0.3 V Allowable Offset Voltage Slew Rate ±50 V/ns Power Dissipation 1.3 W θJA Thermal Resistance 95 °C/W TJ Junction Temperature 150 °C PD (Note 3, 4, 5) 3. 4. Min. VB dVS/dt 2. Parameter TSTG Storage Temperature -55 150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). Refer to the following standards: JESD51-2: Integral circuit’s thermal test method environmental conditions, natural convection; JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. Do not exceed maximum power dissipation (PD) under any circumstances. RECOMMENDED OPERATING CONDITIONS All voltage parameters are referenced to COM. Symbol 6. Parameter Min. Max. Unit VB High-Side Floating Supply Voltage VS+12 VS+20 V VS High-Side Floating Supply Offset Voltage 8-VCC 1200 V VHO High-Side (HO) Output Voltage VS VB V VCC Low-Side Supply Voltage 12 20 V VLO Low-Side (LO) Output Voltage 0 VCC V VDD Logic Supply Voltage VSS+3 VSS+20 V VSS Logic Ground (Note 6) -10 10 V VIN Logic Input Voltage (HIN, LIN, SD) TA Ambient Temperature When VDD<10 V, the minimum VSS offset is limited to -VDD. www.onsemi.com 4 VSS + VDD -20 VDD V -40 +125 °C FAN73912 STATIC ELECTRICAL CHARACTERISTICS VBIAS(VCC, VBS, VDD) = 15.0 V, TA = 25 °C, unless otherwise specified. The VIH, VIL and IIN parameters are referenced to VSS and are applicable to respective input leads: HIN, LIN and SD. The VO and IO parameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO. The VDDUV parameters are referenced to COM. The VBSUV parameters are referenced to VS1,2,3. Symbol Parameter Condition Min. Typ. Max. Unit 170 300 A 10 A 950 A LOW-SIDE POWER SUPPLY SECTION IQCC Quiescent VCC Supply Current VIN=0 V or VDD IQDD Quiescent VDD Supply Current VIN=0 V or VDD IPCC Operating VCC Supply Current fIN=20 kHz, rms VIN=15VPP 650 IPDD Operating VDD Supply Current fIN=20 kHz, rms VIN=15VPP 2 ISD Shutdown Supply Current SD=VDD 30 50 A VCCUV+ VCC Supply Under-Voltage Positive-Going Threshold Voltage VCC=Sweep 9.7 11.0 12 V VCCUV- VCC Supply Under-Voltage Negative-Going Threshold Voltage VCC=Sweep 9.2 10.5 11.4 V VCCUVH VCC Supply Under-Voltage Lockout Hysteresis Voltage VCC=Sweep 0.5 A V BOOTSTRAPPED SUPPLY SECTION IQBS Quiescent VBS Supply Current VIN=0 V or VDD 50 100 A IPBS Operating VBS Supply Current fIN=20 kHz, rms value 550 850 A VBSUV+ VBS Supply Under-Voltage Positive-Going Threshold Voltage VBS=Sweep 9.7 11.0 12.0 V VBSUV- VBS Supply Under-Voltage Negative-Going Threshold Voltage VBS=Sweep 9.2 10.5 11.4 V VBSUVH VBS Supply Under-Voltage Lockout Hysteresis Voltage VBS=Sweep Offset Supply Leakage Current VB=VS=1200 V ILK 0.5 V 50 A INPUT Logic SECTION(HIN.LIN and SD) VIH VIL VDD=3 V 2.4 V VDD=15 V 9.5 V Logic "1" Input Voltage Logic "0" Input Voltage VDD=3 V 0.8 V VDD=15 V 6.0 V 50 A 1 A IIN+ Logic "1" Input bias Current VIN=15 V IIN- Logic "0" Input bias Current VIN=0 V RIN Logic Input Pull-down Resistance 30 500 kΩ GATE DRIVER OUTPUT SECTION VOH High-Level Output Voltage, VBIAS-VO IO=0 A 1.2 V VOL Low-Level Output Voltage, VO IO=0 A 0.1 V IO+ Output HIGH Short-Circuit Pulse Current VO=0 V, VIN=5 V with PW≤10 μs 2.0 A IO- Output LOW Short-Circuit Pulsed Current VO=15 V, VIN=0 V with PW≤10 μs 3.0 A VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO www.onsemi.com 5 -9.8 -7.0 V FAN73912 DYNAMIC ELECTRICAL CHARACTERISTICS VBIAS(VCC, VBS, VDD) = 15.0 V, VS = VSS = COM, CL = 1000 pF and TA = 25°C, unless otherwise specified. Symbol Conditions Min. Typ. Max. Unit tON Turn-On Propagation Delay VS=0 V 500 ns tOFF Turn-Off Propagation Delay VS=0V 550 ns tFLTIN Input Filtering Time (HIN, LIN) (Note7) tFLTSD Input Filtering Time (SD) 80 150 220 30 260 ns Shutdown Propagation Delay Time tR Turn-On Rise Time 25 ns tF Turn-Off Fall Time 15 ns 200 ns ns Dead-Time Matching (Note 8) 50 ns MT Delay Matching , HO & LO Turn-On/OFF(Note 9) 50 ns PM Output Pulse-Width Matching (Note 10) 100 ns PWIN > 1 µs 330 400 450 MDT Dead Time 330 ns tSD DT 7. 8. 9. 10. Parameter 50 The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded. MDT is defined as | DTHO-LO-DTLO-HO | referenced to Figure 40. MT is defined as an absolute value of matching delay time between High-side and Low-side PM is defined as an absolute value of matching pulse-width between Input and Output. www.onsemi.com 6 FAN73912 580 620 560 600 540 580 tOFF [ns] tON [ns] TYPICAL CHARACTERISTICS 520 500 560 540 480 520 460 500 440 -40 -20 0 20 40 60 80 100 480 -40 120 -20 0 Temperature [°C] Figure 4 Turn-On Propagation Delay vs. Temperature 30 tF [ns] tR [ns] 80 100 120 25 25 20 15 20 10 15 5 -20 0 20 40 60 80 100 0 -40 120 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 6 Turn-On Rise Time vs. Temperature Figure 7 Turn-Off Fall Time vs. Temperature 50 50 40 40 MTOFF [ns] MTON [ns] 60 30 35 30 20 30 20 10 10 0 -40 40 Figure 5 Turn-Off Propagation Delay vs. Temperature 40 10 -40 20 Temperature [°C] -20 0 20 40 60 80 100 120 0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 8 Turn-On Delay Matching vs. Temperature Figure 9 Turn-Off Delay Matching vs. Temperature www.onsemi.com 7 FAN73912 TYPICAL CHARACTERISTICS 400 40 380 IIN+ [A] tSD [ns] 30 360 340 20 320 10 300 280 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 40 60 80 100 Figure 10 Shutdown Propagation Delay vs. Figure 11 Logic Input High Bias Current Temperature vs. Temperature 220 210 200 190 180 170 160 150 140 130 120 110 100 -40 120 2.0 VHIN=VLIN=0V VHIN=VLIN=0V 1.8 VHIN=VDD, VLIN=0V (or VHIN=0V, VLIN=VDD) IQDD [A] IQCC [A] 20 Temperature [°C] Temperature [°C] 1.6 VHIN=VDD, VLIN=0V 1.4 (or VHIN=0V, VLIN=VDD) 1.2 1.0 0.8 0.6 0.4 0.2 -20 0 20 40 60 80 100 0.0 -40 120 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 12 Quiescent VCC Supply Current Figure 13 Quiescent VDD Supply Current vs. Temperature vs. Temperature 80 800 70 700 600 50 IPCC [A] IQBS [A] 60 40 30 500 400 20 300 10 0 -40 -20 0 20 40 60 80 100 120 200 -40 -20 0 20 40 60 80 100 Temperature [°C] Temperature [°C] Figure 14 Quiescent VBS Supply Current Figure 15 Operating VCC Supply Current vs. Temperature vs. Temperature www.onsemi.com 8 120 FAN73912 TYPICAL CHARACTERISTICS 5.0 1000 4.5 4.0 800 3.0 IPBS [A] IPDD [A] 3.5 2.5 2.0 600 400 1.5 1.0 200 0.5 0.0 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 20 Temperature [°C] 60 80 100 Figure 16 Operating VDD Supply Current Figure 17 Operating VBS Supply Current vs. Temperature vs. Temperature 120 11.0 11.4 10.8 11.2 10.6 11.0 VCCUV- [V] VCCUV+ [V] 40 Temperature [°C] 10.8 10.6 10.4 10.2 10.0 10.4 9.8 10.2 9.6 10.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature [°C] 60 80 100 120 Figure 19 VCC UVLO- vs. Temperature 11.4 11.0 11.2 10.8 11.0 10.6 VBSUV- [V] VBSUV+ [V] Figure 18 VCC UVLO+ vs. Temperature 10.8 10.6 10.4 10.2 10.0 10.4 9.8 10.2 10.0 -40 40 Temperature [°C] 9.6 -20 0 20 40 60 80 100 120 Temperature [°C] -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 20 VBS UVLO+ vs. Temperature Figure 21 VBS UVLO- vs. Temperature www.onsemi.com 9 120 FAN73912 TYPICAL CHARACTERISTICS 0.010 1.4 0.008 1.2 0.006 0.004 VOL [V] VOH [V] 1.0 0.8 0.6 0.002 0.000 -0.002 -0.004 0.4 -0.006 0.2 -0.008 0.0 -40 -20 0 20 40 60 80 100 120 -0.010 -40 -20 0 20 Temperature [°C] 80 100 Figure 23 Low-Level Output Voltage vs. Temperature vs. Temperature 10 10 9 9 VDD =3V 6 5 7 VDD=15V 6 VDD=3V 5 4 4 3 3 2 2 1 -40 -20 0 20 40 60 80 100 1 -40 120 -20 0 20 Temperature [°C] 40 60 80 100 120 Temperature [°C] Figure 24 Logic High Input Voltage Figure 25 Logic Low Input Voltage vs. Temperature vs. Temperature 12 Logic Threshold Voltage [V] -7 -8 -9 -10 -11 -12 -40 120 8 VDD=15V 7 VIL [V] VIH [V] 60 Figure 22 High-Level Output Voltage 8 VS [V] 40 Temperature [°C] -20 0 20 40 60 80 100 10 8 6 4 VIH 2 0 0 120 VIL 2 4 6 8 10 12 14 16 18 20 VDD Logic Supply Voltage [V] Temperature [°C] Figure 26 Allowable Negative VS Figure 27 Input Logic(HIN&LIN) Threshold Voltage vs. Temperature vs. VDD Supply Voltage www.onsemi.com 10 FAN73912 TYPICAL CHARACTERISTICS 600 -4 -6 540 TA=25C -8 HighSide LowSide 560 VCOM=0V tON [ns] VS [V] 580 VCC=VBS -10 520 500 480 -12 460 -14 440 420 -16 10 11 12 13 14 15 16 17 18 19 20 400 3 4 5 6 7 VCC Supply Voltage [V] Figure 28 Allowable Negative Vs Voltage for HIN 9 10 11 12 13 14 15 16 17 18 19 20 Figure 29 Turn-On Propagation Delay Signal Propagation to High Side vs. VCC Supply Voltage vs. VDD Supply Voltage 600 350 580 HighSide LowSide 560 Positive Negative 300 250 tFLTIN [ns] 540 tOFF [ns] 8 VDD Supply Voltage [V] 520 500 200 480 150 460 100 440 50 420 400 3 4 5 6 7 8 0 3 9 10 11 12 13 14 15 16 17 18 19 20 4 5 6 7 VDD Supply Voltage [V] 9 10 11 12 13 14 15 16 17 18 19 20 Figure 30 Turn-Off Propagation Delay Figure 31 Logic Input Filtering Time vs. VDD Supply Voltage vs. VDD Supply Voltage 160 440 Positive Negative 140 120 400 100 380 80 360 340 60 320 40 300 20 280 0 3 HighSide LowSide 420 tSD [ns] tFLTSD [ns] 8 VDD Supply Voltage [V] 260 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD Supply Voltage [V] 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD Supply Voltage [V] Figure 32 Shutdown Input Filtering Time Figure 33 Shutdown Propagation Delay vs. VDD Supply Voltage vs. VDD Supply Voltage www.onsemi.com 11 FAN73912 TYPICAL CHARACTERISTICS 400 26 380 DTHO-LO 360 DTLO-HO 24 MDT [ns] DT [ns] 340 320 300 22 20 280 18 260 240 16 220 200 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD Supply Voltage [V] PM [ns] 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 35 Dead-Time Matching vs. VDD Supply Voltage vs. VDD Supply Voltage HighSide LowSide 60 40 20 5 5 Figure 34 Dead Time 80 4 4 VDD Supply Voltage [V] 100 0 3 14 3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD Supply Voltage [V] Figure 36 Output Pulse-Width Matching vs. VDD Supply Voltage www.onsemi.com 12 FAN73912 Switching Time Definitions 9 NC HO 8 10 NC VB 7 11 VDD VS 6 HIN 12 HIN NC 5 SD 13 SD NC 4 LIN 14 LIN VCC 3 15 VSS COM 2 16 NC LO 1 15V HO 1nF 100nF 15V (0 to 1200V) 15V 100nF LO 1nF Figure 37. Switching Time Test Circuit A B C D HIN LIN SD Shutdown Shutdown SKIP SKIP Shoot-Through Protection HO Shoot-Through Protection LO Figure 38. Input/Output Timing Diagram HIN 50% 50% More than dead-time LIN 50% More than dead-time 50% 50% tOFF tOFF 90% 90% tON HO tF 10% 10% tOFF tR 90% 90% tON LO 10% Figure 39. Switching Time Definition www.onsemi.com 13 FAN73912 Switching Time Definitions (continued) HIN 50% LIN 50% tOFF DTLO-HO 90% HO 10% tR DTHO-LO 90% 90% LO tOFF 10% tF MDT= DTHO-LO - DTLO-HO Figure 40. Internal Dead Time Definition HIN (LIN) 50% ton 50% tr toff 90% HO (LO) tf 90% 10% 10% Figure 41. Switching Time Waveform Definitions 50% SD tSD 90% HO (LO) Figure 42. Switching Time Definitions www.onsemi.com 14 10% FAN73912 APPLICATIONS INFORMATION Dead Time Shutdown Input Dead time is automatically inserted whenever the dead time of the external two input signals (between HIN and LIN signals) is shorter than internal fixed dead times (DT1 and DT2). Otherwise, external dead times larger than internal dead times are not modified by the gate driver and internal dead-time waveform definition is shown in Figure 43. When the SD pin is in LOW state, the gate driver operates normally. When a condition occurs that should shut down the gate driver, the SD pin should be HIGH. The Shutdown circuitry has an input filter; the minimum input duration is specified by tFLTIN (typically 250 ns). 50% HIN SD 50% 50% tSD LIN 90% 50% HO (LO) 50% LO DT1 HO DT2 50% Figure 45. Output Shutdown Timing Waveform 50% Noise Filter Figure 43. Internal Dead-Time Definitions Input Noise Filter Protection Function Shoot-Through Protection The shoot-through protection circuitry prevents both high- and low-side switches from conducting at the same time, as shown in Figure 44. HIN LIN Shoot-Through Protection HO After DT After DT Example A Example A LO Figure 46 shows the input noise filter method, which has symmetry duration between the input signal (t INPUT) and the output signal (tOUTPUT) and helps to reject noise spikes and short pulses. This input filter is applied to the HIN, LIN, and EN inputs. The upper pair of waveforms (Example A) shows an input signal duration (tINPUT) much longer than input filter time (tFLTIN); it is approximately the same duration between the input signal time (tINPUT) and the output signal time (tOUTPUT). The lower pair of waveforms (Example B) shows an input signal time (tINPUT) slightly longer than input filter time (tFLTIN); it is approximately the same duration between input signal time (tINPUT) and the output signal time (tOUTPUT). HIN IN tFLTIN tINPUT tOUTPUT OUT LIN HO After DT Example B Shoot-Through Protection IN tFLTIN tINPUT tOUTPUT Output duration is same as input duration OUT LO Example B Figure 46. Input Noise Filter Definition Figure 44. Shoot-Through Protection www.onsemi.com 15 FAN73912 Short-Pulsed Input Noise Rejection Method The input filter circuitry provides protection against short-pulsed input signals (HIN, LIN, and SD) on the input signal lines by applied noise signal. If the input signal duration is less than input filter time (tFLTIN), the output does not change states. Example A and B of the Figure 47 show the input and output waveforms with short-pulsed noise spikes with a duration less than input filter time; the output does not change states. the source VS pin of the gate driver, shown in Figure 49. This undershoot voltage is called “negative V S transient”. Q1 GND VS Example A IN GND tFLTIN tFLTIN tFLTIN Freewheeling OUT (LOW) Figure 49. VS Waveforms during Q1 Turn-Off Example B IN tFLTIN tFLTIN tFLTIN OUT (HIGH) Figure 47. Noise Rejecting Input Filter Definition Negative VS Transient The bootstrap circuit has the advantage of being simple and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at the emitter of the high-side switching device when high-side switch is turned-off in half-bridge application. If the high-side switch, Q1, turns-off while the load current is flowing to an inductive load, a current commutation occurs from high-side switch, Q1, to the diode, D2, in parallel with the low-side switch of the same inverter leg. Then the negative voltage present at the emitter of the high-side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to suddenly flow to the low-side freewheeling diode, D2, as shown in Figure 48. DC+ Bus Figure 50 and Figure 51 show the commutation of the load current between high-side switch, Q1, and low-side freewheeling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die wire bonding to the PCB tracks are jumped together in LC and LE for each IGBT. When the high-side switch, Q1, and low-side switch, Q4, are turned on, the V S1 node is below DC+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as shown in Figure 50. When the high-side switch, Q1, is turned off and Q4, remained turned on, the load current to flows the low-side freewheeling diode, D3, due to the inductive load connected to VS1 as shown in Figure 51. Q1 Turn-Off and D3 Conducting. The current flows from ground (which is connected to the COM pin of the gate driver) to the load and the negative voltage present at the emitter of the high-side switching device. In this case, the COM pin of the gate driver is at a higher potential than the VS pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, LC3 and LE3. DC+ Bus Q1 D1 LC1 iLOAD LC2 VLC1 Q2 Q1 ifreewheeling D1 D2 iLOAD ifreewheeling Load VS LE1 Load VS1 LC3 Q2 D2 LE2 VLE1 VS2 VLC4 Q4 Q3 D3 LE3 Figure 48. Half-Bridge Application Circuits This negative voltage can be trouble for the gate driver’s output stage, there is the possibility to develop an overvoltage condition of the bootstrap capacitor, input signal missing and latch-up problems because it directly affects www.onsemi.com 16 LC4 Figure 50. Q1 and Q4 Turn-On D4 VLE4 LE4 FAN73912 Consider co-locating both power switches to reduce DC+ Bus LC1 LC2 Q1 Q2 D1 D2 ifreewheeling LE2 LE1 LC3 Load VS2 VLC3 LC4 VLC4 Q4 Q3 D3 LE3 D4 VLE3 LE4 VLE4 Figure 51. Q1 Turn-Off and D3 Conducting The FAN73912 has a typical negative VS transient characteristics, as shown in Figure 52. VS [V] To minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. iLOAD VS1 track length. To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible. Placement of Components The recommended placement and selection of component as follows: Place a bypass capacitor between the VCC and VSS pins. A ceramic 1 µF capacitor is suitable for most applications. This component should be placed as close as possible to the pins to reduce parasitic elements. 0 The bypass capacitor from VCC to VSS supports both -5 -10 the low-side driver and bootstrap capacitor recharge. A value at least ten times higher than the bootstrap capacitor is recommended. -15 The bootstrap resistor, RBOOT, must be considered in -20 -25 -30 -35 50 100 150 200 250 300 Pulse Width [ns] Figure 52. Negative VS Transient Characteristic Even though the FAN73912 has been shown able to handle these negative VS transient conditions, it is strongly recommended that the circuit designer limit the negative VS transient as much as possible by careful PCB layout to minimize the value of parasitic elements and component use. The amplitude of negative V S voltage is proportional to the parasitic inductances and the turn-off speed, di/dt, of the switching device. sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM (ground). Recommended use is typically 5 ~ 10 that increase the VBS time constant. If the voltage drop of bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. The bootstrap capacitor, CBOOT, uses a low-ESR capacitor, such as ceramic capacitor. It is strongly recommended that the placement of components is as follows: Place components tied to the floating voltage pins (VB and VS) near the respective high-voltage portions of the device and the FAN73912. Not Connected (NC) pins in this package maximize the distance between the high-voltage and low-voltage pins (see Figure 3) Place and route for bypass capacitors and gate resistors General Guidelines as close as possible to gate drive IC. Locate the bootstrap diode, DBOOT, as close as possible Printed Circuit Board Layout The layout recommended for minimized parasitic elements is as follows: Direct tracks between switches with no loops or deviation. to bootstrap capacitor, CBOOT. The bootstrap diode must use a lower forward voltage Avoid interconnect links. These can add significant drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode. inductance. Reduce the effect of lead-inductance by lowering package height above the PCB. www.onsemi.com 17 FAN73912 PACKAGE DIMENSIONS Figure 53. 16-Lead, Small Outline Package(SOP) www.onsemi.com 18 FAN73912 ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] © Semiconductor Components Industries, LLC N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 1 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative www.onsemi.com