CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 D D D D D D D D D 4.5-V to 5.5-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times Direct LSTTL Input Logic Compatibility – VIL = 0.8 V Maximum; VIH = 2 V Minimum CMOS Input Compatibility – II ≤ 1 µA at VOL, VOH Packaged in Ceramic (F) DIP Packages and Also Available in Chip Form (H) F PACKAGE (TOP VIEW) 5 1 0 2 6 7 3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC MR CP CE TC 9 4 8 description The CD54HCT4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low. The CD54HCT4017 is characterized for operation over the full military temperature range of –55°C to 125°C. FUNCTION TABLE INPUTS CP CE MR OUTPUT STATE† L X L No change X H L No change X X H 0=H 1–9 = L ↑ L L Increments counter ↓ X L No change X ↑ L No change H ↓ L Increments counter † If n < 5, TC = H; otherwise, TC = L. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 logic diagram (positive logic) 3 0 4 7 10 1 2 3 4 1 5 5 6 6 7 9 8 11 9 12 D C MR R Q D Q C R Q D Q C R Q D Q C R Q D Q C 15 13 CE 14 CP 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q R Q TC Decoded Decimal Out 2 CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 V or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, each output pin, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA VCC or ground current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see Note 1) MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO Output voltage tt Input transition (rise and fall) time High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 UNIT V V 0.8 V VCC VCC V 0 VCC = 2 V VCC = 4.5 V 0 1000 0 500 VCC = 6 V 0 400 V ns TA Operating free-air temperature –55 125 °C NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL CMOS loads TTL loads CMOS loads TTL loads TEST CONDITIONS VCC MIN TA = 25°C TYP MAX MIN MAX UNIT VI = VIH or VIL, VI = VIH or VIL, IO = –0.02 mA IO = –4 mA 4.5 V 4.4 4.4 4.5 V 3.98 3.7 VI = VIH or VIL, VI = VIH or VIL, IO = 0.02 mA IO = 4 mA 4.5 V 0.1 0.1 4.5 V 0.26 0.4 5.5 V ±100 ±1000 nA 5.5 V 8 160 µA 360 490 µA 10 10 pF II ICC VI = VCC to 0 VI = VCC or 0 ∆ICC† Ci VI = VCC to 2.1 V, IO = 0 4.5 to 5.5 V 100 V V † For dual-supply systems, theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. INPUT LOADING INPUT UNIT LOAD CP 0.15 CE 0.25 MR 0.3 Unit load is ∆ICC limit, e.g., 360 µA MAX at TA = 25°C. timing requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER fclock 4 Maximum clock frequency VCC TA = 25°C MIN MAX MIN MAX UNIT MHz 4.5 V 25 17 CP 4.5 V 16 24 MR 4.5 V 16 24 tw Pulse duration tsu th Setup time, CE to CP 4.5 V 15 22 ns Hold time, CE to CP 4.5 V 0 0 ns trem Removal time, MR 4.5 V 5 5 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 timing requirements CP MR CE 0 1 2 3 4 5 6 0 1 1 2 2 3 4 5 6 7 7 8 8 9 9 TC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 switching characteristics, CL = 50 pF, TA = 25°C (see Figures 1 and 2) PARAMETER FROM (INPUT) fmax tPLH tPHL tPLH tPHL tPLH tPHL tTHL TO (OUTPUT) VCC 4.5 V Any output CP TC Any output CE TC Any output MR TC Any output tTLH TC 45V 4.5 45V 4.5 45V 4.5 45V 4.5 TA = 25°C TA = –55°C TO 125°C MIN MIN MAX 25 UNIT MAX 17 MHz 46 69 46 69 50 75 50 75 46 69 46 69 15 22 15 22 ns ns ns ns operating characteristics PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 39 UNIT pF CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER From Output Under Test CL (see Note A) Test Point S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open S1 1 kΩ ten S2 tdis tpd or tt LOAD CIRCUIT High-Level Pulse 50% VCC VCC Reference Input VCC 50% VCC 50% VCC 0V 0V Data Input tw Low-Level Pulse VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATIONS 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-ofPhase Output 90% tf 50% 10% 90% VCC 50% 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES Output Control VCC 50% VCC 50% VCC 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ ≈ VCC 50% tPZH tPLH 50% 10% 90% tr 0V In-Phase Output 50% 10% 50% VCC VCC Input th tsu 90% VOH VOL Output Waveform 2 (See Note B) ≈ VCC 10% VOL tPHZ 50% 90% VOH ≈0V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 PARAMETER MEASUREMENT INFORMATION tf tr CP VCC VS 0.5 VCC Input Level VS f max tPLH tPHL Input Level VS CE GND 1 GND tPHL tPLH VS TC VS 0–9 MR INPUT LEVEL Input Level VS Input Level VS CP GND tw GND tPLH tw tPHL tPHL VS TC VS 1–9 Input Level tPLH CE 0, TC VS VS GND tPLH CP Input Level VS 0–9 tPLH VS GND trem MR Input Level VS CE VS tsu CP GND Figure 2. Voltage Waveforms 8 POST OFFICE BOX 655303 GND tw tsu CE VS GND Input Level Input Level • DALLAS, TEXAS 75265 th VS Input Level GND IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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