TI1 MSP430FG6625IZQWR Mixed-signal microcontroller Datasheet

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MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
MSP430FG662x, MSP430FG642x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active:
250 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
– Standby Mode (LPM3):
Watchdog With Crystal, and Supply Supervisor
Operational, Full RAM Retention, Fast Wakeup:
3.2 µA at 2.2 V, 3.4 µA at 3.0 V (Typical)
– Shutdown RTC Mode (LPM3.5):
Shutdown Mode, Active Real-Time Clock With
Crystal:
0.9 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.2 µA at 3.0 V (Typical)
• Wake up From Standby Mode in 3 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
20-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals up to 32 MHz (XT2)
• Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers
1.2
•
•
•
• Two Universal Serial Communication Interfaces
– USCI_A0 and USCI_A1 Each Support
• Enhanced UART With Automatic Baud-Rate
Detection
• IrDA Encoder and Decoder
• Synchronous SPI
– USCI_B0 and USCI_B1 Each Support
• I2C
• Synchronous SPI
• Full-Speed Universal Serial Bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB Power System
– Integrated USB-PLL
– Eight Input and Eight Output Endpoints
• Continuous-Time Sigma-Delta 16-Bit Analog-toDigital Converter (ADC) With Internal Reference
With 10 External Analog Inputs, 6 Single-Ended
and 4 Selectable as Differential or Single-Ended
• Dual Low-Power Operational Amplifiers
• Quad Low-Impedance Ground Switches
• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
• Voltage Comparator
• Integrated LCD Driver With Contrast Control for up
to 160 Segments
• Hardware Multiplier Supports 32-Bit Operations
• Serial Onboard Programming, No External
Programming Voltage Needed
• Six-Channel Internal DMA
• Real-Time Clock (RTC) Module With Supply
Voltage Backup Switch
• Table 3-1 Summarizes Family Members
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
Applications
Analog Sensor Systems
Digital Sensor Systems
Hand-Held Meters
•
•
•
Medical Diagnostic Meters
Hand-Held Industrial Testers
Measurement Equipment
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
1.3
www.ti.com
Description
The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in 3 µs (typical).
The MSP430FG6626 and MSP430FG6625 are microcontrollers with a high-performance 16-bit analog-todigital converter (ADC), dual 12-bit digital-to-analog converters (DACs), dual operational amplifiers, a
comparator, two universal serial communication interfaces (USCIs), USB 2.0, a hardware multiplier, DMA,
four 16-bit timers, a real-time clock (RTC) module with alarm capabilities, an LCD driver, and up to 73 I/O
pins.
The MSP430FG6426 and MSP430FG6425 are microcontrollers with a high-performance 16-bit ADC, dual
12-bit DACs, dual low-power operational amplifiers, a comparator, two USCIs, a 3.3-V LDO, a hardware
multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, an LCD driver, and up to 73 I/O
pins.
Typical applications for these devices include analog and digital sensor systems, hand-held meters, such
as medical diagnostic meters, measurement equipment, and hand-held industrial testers.
Device Information (1)
PART NUMBER
MSP430FG6626IPZ
MSP430FG6626IZQW
(1)
(2)
2
PACKAGE
BODY SIZE (2)
PZ (100)
14 mm × 14 mm
ZQW (113)
7 mm × 7 mm
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2015, Texas Instruments Incorporated
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MSP430FG6426, MSP430FG6425
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1.4
SLAS874 – MAY 2015
Functional Block Diagrams
Figure 1-1 shows the functional block diagram for the MSP430FG6626 and MSP430FG6625 devices.
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
VCORE
NR
P1.x
XT2IN
XT2OUT
Unified
Clock
System
8KB
RAM
ACLK
128KB
64KB
SMCLK
Flash
MCLK
SYS
Power
Management
Watchdog
+2KB RAM
USB Buffer
+8B Backup
RAM
LDO
SVM, SVS
Brownout
P2 Port
Mapping
Controller
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
P7.x
PD
P8.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
1×7 I/Os
1×8 I/Os
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×15 I/Os
PD
1×14 I/Os
P9.x
DP, DM, PUR
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
USCI0,1
USB
Ax: UART,
IrDA, SPI
Full-Speed
Bx: SPI, I2C
CPUXV2
and
Working
Registers
DMA
6 Channel
EEM
(L: 8+2)
TA0
JTAG,
SBW
Interface
MPY32
Port PJ
Timer_A
5 CC
Registers
PJ.x
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CTSD16
Sigma-Delta
ADC
RTC_B
CRC16
Comp_B
Battery
Backup
System
14 inputs
(6 SE ext,
4 SE/diff ext,
4 int)
DAC12_A
12 bit
2 channels
voltage out
Reference
1.5 V,
2.0 V,
2.5 V
LCD_B
160
Segments
Operational
Amplifiers
OA0, OA1
Quad
Ground
Switches
1.16 V
VREFBG
Figure 1-1. Functional Block Diagram – MSP430FG6626, MSP430FG6625
Figure 1-2 shows the functional block diagram for the MSP430FG6426 and MSP430FG6425 devices.
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
VCORE
NR
P1.x
XT2IN
XT2OUT
Unified
Clock
System
MCLK
ACLK
SMCLK
Power
Management
128KB
64KB
10KB
RAM
Flash
+8B Backup
RAM
SYS
Watchdog
LDO
SVM, SVS
Brownout
P2 Port
Mapping
Controller
PA
P2.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
P3.x
PB
P4.x
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
P5.x
PC
P6.x
P7.x
I/O Ports
P5, P6
1×7 I/Os
1×8 I/Os
PC
1×15 I/Os
PD
P8.x
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
PD
1×14 I/Os
PU.0,
PU.1 LDOO LDOI
P9.x
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
USCI0,1
PU Port
Ax: UART,
IrDA, SPI
LDO
2
Bx: SPI, I C
CPUXV2
and
Working
Registers
DMA
6 Channel
EEM
(L: 8+2)
JTAG,
SBW
Interface
Port PJ
PJ.x
TA0
MPY32
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
CTSD16
Sigma-Delta
ADC
RTC_B
TB0
Timer_B
7 CC
Registers
CRC16
Battery
Backup
System
Comp_B
14 inputs
(6 SE ext,
4 SE/dif ext,
4 int)
Reference
DAC12_A
12 bit
2 channels
voltage out
1.5 V,
2.0 V,
2.5 V
LCD_B
160
Segments
Operational
Amplifiers
OA0, OA1
Quad
Ground
Switches
1.16 V
VREFBG
Figure 1-2. Functional Block Diagram – MSP430FG6426, MSP430FG6425
Device Overview
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Copyright © 2015, Texas Instruments Incorporated
3
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
www.ti.com
Table of Contents
1
2
3
4
Device Overview ......................................... 1
6.6
USB BSL ............................................ 74
1.1
Features .............................................. 1
6.7
UART BSL
1.2
Applications ........................................... 1
6.8
JTAG Operation ..................................... 75
1.3
Description ............................................ 2
6.9
Flash Memory ....................................... 75
1.4
Functional Block Diagrams ........................... 3
6.10
RAM ................................................. 76
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
6.11
Backup RAM ........................................ 76
6.12
Peripherals
6.13
Device Descriptors ................................. 131
4.1
Pin Diagrams ......................................... 6
6.14
Memory
4.2
Pin Attributes ......................................... 9
6.15
Identification........................................ 146
4.3
Signal Descriptions .................................. 16
.....................................
4.5
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings ........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
5.4
Thermal Characteristics ............................
5.5
Timing and Switching Characteristics ...............
Detailed Description ...................................
6.1
Overview ............................................
6.2
CPU .................................................
6.3
Instruction Set .......................................
6.4
Operating Modes ....................................
6.5
Interrupt Vector Addresses..........................
4.4
5
6
Pin Multiplexing
7
23
25
25
8
..........................................
............................................
74
76
132
Applications, Implementation, and Layout ...... 147
7.1
7.2
24
..........................................
Device Connection and Layout Fundamentals .... 147
Peripheral- and Interface-Specific Design
Information ......................................... 151
Device and Documentation Support .............. 160
25
8.1
Device Support..................................... 160
25
8.2
Documentation Support ............................ 163
30
8.3
Related Links
30
8.4
Community Resources............................. 163
70
8.5
Trademarks ........................................ 163
70
8.6
Electrostatic Discharge Caution
70
8.7
Glossary............................................ 164
71
72
73
9
......................................
...................
163
164
Mechanical, Packaging, and Orderable
Information ............................................. 164
9.1
Packaging Information ............................. 164
2 Revision History
4
DATE
REVISION
NOTES
May 2015
*
Initial Release
Revision History
Copyright © 2015, Texas Instruments Incorporated
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MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
www.ti.com
SLAS874 – MAY 2015
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
USCI
DEVICE
FLASH
(KB)
SRAM
(KB) (3)
MSP430FG6626
128
8+2
5, 3, 3
7
2
MSP430FG6625
64
8+2
5, 3, 3
7
MSP430FG6426
128
10
5, 3, 3
MSP430FG6425
64
10
5, 3, 3
(1)
(2)
(3)
(4)
(5)
(6)
Timer_A
(4)
CTSD16
(Ch) (6)
DAC12_A
(Ch)
OA
Comp_B
(Ch)
USB
I/O
PACKAGE
2
10 ext,
5 int
2
2
12
1
73
100 PZ
113 ZQW
2
2
10 ext,
5 int
2
2
12
1
73
100 PZ
113 ZQW
7
2
2
10 ext,
5 int
2
2
12
0
73
100 PZ
113 ZQW
7
2
2
10 ext,
5 int
2
2
12
0
73
100 PZ
113 ZQW
Timer_B
(5)
CHANNEL A:
CHANNEL B:
UART, IrDA,
SPI, I2C
SPI
For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
ADC inputs consist of a mix of single ended and differential. Refer to the pinning for available input pairs and types.
Device Comparison
Copyright © 2015, Texas Instruments Incorporated
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5
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MSP430FG6626
MSP430FG6625
PZ PACKAGE
(TOP VIEW)
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
DVCC1
DVSS1
VCORE
LCDCAP/R33
COM0
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/CB4/AD0+/OA0O
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
P7.4/CB8/AD2+/OA1O
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
P5.0/VREFBG/VeREF+
P5.1/A4/DAC0
P5.6/A5/DAC1
NR
AVSS1
XOUT
XIN
AVCC
CPCAP
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/CB3/A3/OA1IP0
P6.2/CB2/A2/OA0IP0
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/DMAE0/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
Figure 4-1 shows the pin assignments for the MSP430FG6626 and MSP430FG6625 devices in the 100pin PZ package.
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 4-1. 100-Pin PZ Package (Top View), MSP430FG6626IPZ, MSP430FG6625IPZ
6
Terminal Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
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MSP430FG6426, MSP430FG6425
www.ti.com
SLAS874 – MAY 2015
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430FG6426
MSP430FG6425
PZ PACKAGE
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
DVCC1
DVSS1
VCORE
LCDCAP/R33
COM0
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/CB4/AD0+/OA0O
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
P7.4/CB8/AD2+/OA1O
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
P5.0/VREFBG/VeREF+
P5.1/A4/DAC0
P5.6/A5/DAC1
NR
AVSS1
XOUT
XIN
AVCC
CPCAP
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/CB3/A3/OA1IP0
P6.2/CB2/A2/OA0IP0
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/DMAE0/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS2
NC
LDOO
LDOI
PU.1
NC
PU.0
VSSU
Figure 4-2 shows the pin assignments for the MSP430FG6426 and MSP430FG6425 devices in the 100pin PZ package.
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 4-2. 100-Pin PZ Package (Top View), MSP430FG6426IPZ, MSP430FG6425IPZ
Terminal Configuration and Functions
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SLAS874 – MAY 2015
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Figure 4-3 shows the pin assignments for the 113-pin ZQW package.
ZQW PACKAGE
(TOP VIEW)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C11
C12
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
E1
E2
E4
E5
E6
E7
E8
E9
E11
E12
F1
F2
F4
F5
F8
F9
F11
F12
G1
G2
G4
G5
G8
G9
G11
G12
H1
H2
H4
H5
H6
H7
H8
H9
H11
H12
J1
J2
J4
J5
J6
J7
J8
J9
J11
J12
K1
K2
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
NOTE: For terminal assignments, see Table 4-2.
Figure 4-3. 113-Pin ZQW Package (Top View), MSP430FG6626IZQW, MSP430FG6625IZQW,
MSP430FG6426IZQW, MSP430FG6425IZQW
8
Terminal Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
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4.2
SLAS874 – MAY 2015
Pin Attributes
Table 4-1 describes the attributes of the pins.
Table 4-1. Pin Attributes
PIN NO.
PZ
1
2
ZQW
A1
B2
SIGNAL NAME
4
5
6
7
B1
C3
C2
C1
D4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
D2
(3)
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
I/O
LVCMOS
DVCC
OFF
CB4
I
Analog
DVCC
N/A
AD0+
I
Analog
DVCC
N/A
OA0O
O
Analog
DVCC
N/A
P6.5
I/O
LVCMOS
DVCC
OFF
CB5
I
Analog
DVCC
N/A
AD0-
I
Analog
DVCC
N/A
I
Analog
DVCC
N/A
P6.6
I/O
LVCMOS
DVCC
OFF
CB6
I
Analog
DVCC
N/A
AD1+
I
Analog
DVCC
N/A
G0SW0
I
Analog
DVCC
N/A
P6.7
I/O
LVCMOS
DVCC
OFF
CB7
I
Analog
DVCC
N/A
AD1-
I
Analog
DVCC
N/A
G0SW1
I
Analog
DVCC
N/A
P7.4
I/O
LVCMOS
DVCC
OFF
CB8
I
Analog
DVCC
N/A
AD2+
I
Analog
DVCC
N/A
OA1O
O
Analog
DVCC
N/A
P7.5
I/O
LVCMOS
DVCC
OFF
CB9
I
Analog
DVCC
N/A
AD2-
I
Analog
DVCC
N/A
OA1IN0
I
Analog
DVCC
N/A
P7.6
I/O
LVCMOS
DVCC
OFF
CB10
I
Analog
DVCC
N/A
AD3+
I
Analog
DVCC
N/A
G1SW0
8
SIGNAL TYPE
P6.4
OA0IN0
3
(1) (2)
I
Analog
DVCC
N/A
P7.7
I/O
LVCMOS
DVCC
OFF
CB11
I
Analog
DVCC
N/A
AD3-
I
Analog
DVCC
N/A
G1SW1
I
Analog
DVCC
N/A
For each multiplexed pin, the signal that is listed first in this table is the reset default.
To determine the pin mux encodings for each pin, refer to Section 6.12.23, Input/Ouput Schematics.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
Buffer Types: LVCMOS, HVCMOS, Analog, or Power (see Table 4-3 for details).
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
HiZ = High-impedance (neither input nor output)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
For Debug pins: Emu = with emulator attached at reset, No Emu = without emulator attached at reset
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
ZQW
9
D1
SIGNAL NAME
11
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
I/O
LVCMOS
DVCC
OFF
O
Analog
DVCC
N/A
I
Analog
N/A
N/A
I/O
LVCMOS
DVCC
OFF
A4
I
Analog
DVCC
N/A
DAC0
O
Analog
DVCC
N/A
P5.6
I/O
LVCMOS
DVCC
OFF
A5
I
Analog
DVCC
N/A
DAC1
O
Analog
DVCC
N/A
12
E1
NR
I
Analog
N/A
N/A
13
F2
AVSS1
P
Power
N/A
N/A
14
F1
XOUT
O
Analog
N/A
N/A
15
G1
XIN
I
Analog
N/A
N/A
16
H1, G2
DVCC
P
Power
N/A
N/A
17
G4
CPCAP
I/O
Analog
DVCC
N/A
P2.0
I/O
LVCMOS
DVCC
OFF
P2MAP0
I/O
LVCMOS
DVCC
N/A
DAC0
O
Analog
DVCC
N/A
P2.1
I/O
LVCMOS
DVCC
OFF
P2MAP1
I/O
LVCMOS
DVCC
N/A
DAC1
O
Analog
DVCC
N/A
P2.2
I/O
LVCMOS
DVCC
OFF
P2MAP2
I/O
LVCMOS
DVCC
N/A
P2.3
I/O
LVCMOS
DVCC
OFF
P2MAP3
I/O
LVCMOS
DVCC
N/A
P2.4
I/O
LVCMOS
DVCC
OFF
P2MAP4
I/O
LVCMOS
DVCC
N/A
R03
I/O
Analog
DVCC
N/A
P2.5
I/O
LVCMOS
DVCC
OFF
P2MAP5
I/O
LVCMOS
DVCC
N/A
P2.6
I/O
LVCMOS
DVCC
OFF
P2MAP6
I/O
LVCMOS
DVCC
N/A
N/A
18
19
20
21
22
23
24
H2
J1
H4
J2
K1
K2
L2
LCDREF
I
Analog
N/A
R13
I/O
Analog
DVCC
N/A
P2.7
I/O
LVCMOS
DVCC
OFF
P2MAP7
I/O
LVCMOS
DVCC
N/A
R23
25
L3
I/O
Analog
DVCC
N/A
26
L1
DVCC1
P
Power
N/A
N/A
27
M1
DVSS1
P
Power
N/A
N/A
28
M2
VCORE
P
Power
DVCC
N/A
LCDCAP
I/O
Analog
DVCC
N/A
R33
I/O
Analog
DVCC
N/A
29
M3
30
J4
31
10
E2
(3)
VREFBG
P5.1
E4
SIGNAL TYPE
P5.0
VeREF+
10
(1) (2)
L4
COM0
O
Analog
DVCC
N/A
P5.3
I/O
LVCMOS
DVCC
OFF
COM1
O
Analog
DVCC
N/A
S42
O
Analog
DVCC
N/A
Terminal Configuration and Functions
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SLAS874 – MAY 2015
Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
ZQW
32
M4
33
34
35
36
37
38
39
40
41
42
43
44
45
J5
L5
M5
J6
H6
M6
L6
J7
M7
L7
H7
M8
L8
SIGNAL NAME
(1) (2)
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
P5.4
I/O
LVCMOS
DVCC
OFF
COM2
O
LVCMOS
DVCC
N/A
S41
O
Analog
DVCC
N/A
P5.5
I/O
LVCMOS
DVCC
OFF
COM3
I/O
LVCMOS
DVCC
N/A
S40
O
Analog
DVCC
N/A
P1.0
I/O
LVCMOS
DVCC
OFF
TA0CLK
I
LVCMOS
DVCC
N/A
ACLK
O
LVCMOS
DVCC
N/A
S39
O
Analog
DVCC
N/A
P1.1
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
N/A
BSLTX
O
LVCMOS
DVCC
N/A
S38
O
Analog
DVCC
N/A
P1.2
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
N/A
BSLRX
I
LVCMOS
DVCC
N/A
S37
O
Analog
DVCC
N/A
P1.3
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
N/A
S36
O
Analog
DVCC
N/A
P1.4
I/O
LVCMOS
DVCC
OFF
TA0.3
I/O
LVCMOS
DVCC
N/A
S35
O
Analog
DVCC
N/A
P1.5
I/O
LVCMOS
DVCC
OFF
TA0.4
I/O
LVCMOS
DVCC
N/A
S34
O
Analog
DVCC
N/A
P1.6
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
N/A
S33
O
Analog
DVCC
N/A
P1.7
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
N/A
S32
O
Analog
DVCC
N/A
P3.0
I/O
LVCMOS
DVCC
OFF
TA1CLK
I
LVCMOS
DVCC
N/A
CBOUT
O
LVCMOS
DVCC
N/A
S31
O
Analog
DVCC
N/A
P3.1
I/O
LVCMOS
DVCC
OFF
TA1.0
I/O
LVCMOS
DVCC
N/A
S30
O
Analog
DVCC
N/A
P3.2
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
N/A
S29
O
Analog
DVCC
N/A
P3.3
I/O
LVCMOS
DVCC
OFF
TA1.2
I/O
LVCMOS
DVCC
N/A
S28
O
Analog
DVCC
N/A
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
ZQW
SIGNAL NAME
P3.4
46
47
48
49
50
51
52
53
54
55
56
57
58
59
12
J8
M9
L9
M10
J9
M11
L10
M12
L12
L11
K11
K12
J11
J12
(1) (2)
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
I/O
LVCMOS
DVCC
OFF
TA2CLK
I
LVCMOS
DVCC
N/A
SMCLK
O
LVCMOS
DVCC
N/A
S27
O
Analog
DVCC
N/A
P3.5
I/O
LVCMOS
DVCC
OFF
TA2.0
I/O
LVCMOS
DVCC
N/A
S26
O
Analog
DVCC
N/A
P3.6
I/O
LVCMOS
DVCC
OFF
TA2.1
I/O
LVCMOS
DVCC
N/A
S25
O
Analog
DVCC
N/A
P3.7
I/O
LVCMOS
DVCC
OFF
TA2.2
I/O
LVCMOS
DVCC
N/A
S24
O
Analog
DVCC
N/A
P4.0
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
N/A
S23
O
Analog
DVCC
N/A
P4.1
I/O
LVCMOS
DVCC
OFF
TB0.1
I/O
LVCMOS
DVCC
N/A
S22
O
Analog
DVCC
N/A
P4.2
I/O
LVCMOS
DVCC
OFF
TB0.2
I/O
LVCMOS
DVCC
N/A
S21
O
Analog
DVCC
N/A
P4.3
I/O
LVCMOS
DVCC
OFF
TB0.3
I/O
LVCMOS
DVCC
N/A
S20
O
Analog
DVCC
N/A
P4.4
I/O
LVCMOS
DVCC
OFF
TB0.4
I/O
LVCMOS
DVCC
N/A
S19
O
Analog
DVCC
N/A
P4.5
I/O
LVCMOS
DVCC
OFF
TB0.5
I/O
LVCMOS
DVCC
N/A
S18
O
Analog
DVCC
N/A
P4.6
I/O
LVCMOS
DVCC
OFF
TB0.6
I/O
LVCMOS
DVCC
N/A
S17
O
Analog
DVCC
N/A
P4.7
I/O
LVCMOS
DVCC
OFF
TB0OUTH
I
LVCMOS
DVCC
N/A
SVMOUT
O
LVCMOS
DVCC
N/A
S16
O
Analog
DVCC
N/A
P8.0
I/O
LVCMOS
DVCC
OFF
TB0CLK
I
LVCMOS
DVCC
N/A
S15
O
Analog
DVCC
N/A
P8.1
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
N/A
UCA1CLK
I/O
LVCMOS
DVCC
N/A
S14
O
Analog
DVCC
N/A
Terminal Configuration and Functions
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SLAS874 – MAY 2015
Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
60
61
62
SIGNAL NAME
ZQW
H11
H12
G11
(1) (2)
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
P8.2
I/O
LVCMOS
DVCC
OFF
UCA1TXD
O
LVCMOS
DVCC
N/A
UCA1SIMO
I/O
LVCMOS
DVCC
N/A
S13
O
Analog
DVCC
N/A
P8.3
I/O
LVCMOS
DVCC
OFF
UCA1RXD
I
LVCMOS
DVCC
N/A
UCA1SOMI
I/O
LVCMOS
DVCC
N/A
S12
O
Analog
DVCC
N/A
P8.4
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
N/A
UCA1STE
I/O
LVCMOS
DVCC
N/A
S11
O
Analog
DVCC
N/A
N/A
63
G12
DVSS2
P
Power
N/A
64
F12
DVCC2
P
Power
N/A
N/A
P8.5
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
N/A
UCB1SDA
I/O
LVCMOS
DVCC
N/A
S10
O
Analog
DVCC
N/A
P8.6
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
N/A
UCB1SCL
I/O
LVCMOS
DVCC
N/A
S9
O
Analog
DVCC
N/A
P8.7
I/O
LVCMOS
DVCC
OFF
S8
O
Analog
DVCC
N/A
P9.0
I/O
LVCMOS
DVCC
OFF
S7
O
Analog
DVCC
N/A
P9.1
I/O
LVCMOS
DVCC
OFF
S6
O
Analog
DVCC
N/A
P9.2
I/O
LVCMOS
DVCC
OFF
65
66
67
F11
G9
E12
68
E11
69
F9
70
D12
71
D11
72
E9
73
C12
74
C11
75
D9
76
B11, B12
77
78
A12
B10
S5
O
Analog
DVCC
N/A
P9.3
I/O
LVCMOS
DVCC
OFF
S4
O
Analog
DVCC
N/A
P9.4
I/O
LVCMOS
DVCC
OFF
S3
O
Analog
DVCC
N/A
P9.5
I/O
LVCMOS
DVCC
OFF
S2
O
Analog
DVCC
N/A
P9.6
I/O
LVCMOS
DVCC
OFF
S1
O
Analog
DVCC
N/A
P9.7
I/O
LVCMOS
DVCC
OFF
S0
O
Analog
DVCC
N/A
VSSU
P
Power
N/A
N/A
PU.0
I/O
HVCMOS
VBUS
HiZ
DP
I/O
HVCMOS
VBUS
N/A
PUR (FG662x only)
I/O
HVCMOS/opendrain
VBUS
HiZ
NC (FG642x only)
I/O
N/A
N/A
N/A
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
ZQW
79
A11
80
A10
81
A9
82
B9
83
A8
84
B8
SIGNAL NAME
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
PU.1
I/O
HVCMOS
VBUS
HiZ
DM
I/O
HVCMOS
VBUS
N/A
VBUS
I
Power
N/A
N/A
LDOI
I
Analog
External
N/A
VUSB
O
Power
N/A
N/A
LDOO
O
Analog
VBUS
N/A
V18 (FG662x only)
O
Power
N/A
N/A
NC (FG642x only)
–
N/A
N/A
N/A
AVSS2
P
Power
N/A
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
P7.2
XT2IN
P7.3
85
B7
XT2OUT
O
Analog
DVCC
N/A
86
A7
VBAK
I/O
Analog
N/A
N/A
87
D8
VBAT
P
Power
N/A
N/A
P5.7
I/O
LVCMOS
DVCC
OFF
DMAE0
I
LVCMOS
DVCC
N/A
RTCCLK
O
LVCMOS
DVCC
N/A
N/A
88
D7
89
A6
DVCC3
P
Power
N/A
90
A5
DVSS3
P
Power
N/A
N/A
91
B6
TEST
I
LVCMOS
DVCC
No Emu: PD
Emu: PD
SBWTCK
I
LVCMOS
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
No Emu: OFF
Emu: DRIVE0
PJ.0
92
93
B5
A4
94
E7
95
D6
96
A3
97
98
14
(1) (2)
B4
B3
TDO
O
LVCMOS
DVCC
PJ.1
I/O
LVCMOS
DVCC
OFF
TDI
I
LVCMOS
DVCC
No Emu: OFF
Emu: PU
TCLK
I
LVCMOS
DVCC
No Emu: OFF
Emu: OFF
PJ.2
I/O
LVCMOS
DVCC
OFF
No Emu: OFF
Emu: PU
TMS
I
LVCMOS
DVCC
PJ.3
I/O
LVCMOS
DVCC
OFF
No Emu: OFF
Emu: PU
TCK
I
LVCMOS
DVCC
RST
I/O
LVCMOS
DVCC
PU
NMI
I
LVCMOS
DVCC
N/A
SBWTDIO
I/O
LVCMOS
DVCC
PU
P6.0
I/O
LVCMOS
DVCC
OFF
CB0
I
Analog
DVCC
N/A
A0
I
Analog
DVCC
N/A
P6.1
I/O
LVCMOS
DVCC
OFF
CB1
I
Analog
DVCC
N/A
A1
I
Analog
DVCC
N/A
Terminal Configuration and Functions
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SLAS874 – MAY 2015
Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
99
100
N/A
SIGNAL NAME
ZQW
A2
D5
E5, E6, E8,
F4, F5, F8,
G5, G8, H5,
H8, H9
(1) (2)
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
(7)
P6.2
I/O
LVCMOS
DVCC
OFF
CB2
I
Analog
DVCC
N/A
A2
I
Analog
DVCC
N/A
OA0IP0
I
Analog
DVCC
N/A
P6.3
I/O
LVCMOS
DVCC
OFF
CB3
I
Analog
DVCC
N/A
A3
I
Analog
DVCC
N/A
OA1IP0
I
Analog
DVCC
N/A
Reserved
-
–
–
–
Terminal Configuration and Functions
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Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
SIGNAL
NAME
ADC
BSL
PIN NO.
PZ
ZQW
PIN
TYPE (1)
A0
97
B4
I
ADC analog single ended input A0
A1
98
B3
I
ADC analog single ended input A1
A2
99
A2
I
ADC analog single ended input A2
A3
100
D5
I
ADC analog single ended input A3
A4
10
E4
I
ADC analog single ended input A4
A5
11
E2
I
ADC analog single ended input A5
AD0+
1
A1
I
ADC positive analog differential input AD0+
AD0-
2
B2
I
ADC negative analog differential input AD0-
AD1+
3
B1
I
ADC positive analog differential input AD1+
AD1-
4
C3
I
ADC negative analog differential input AD1-
AD2+
5
C2
I
ADC positive analog differential input AD2+
AD2-
6
C1
I
ADC negative analog differential input AD2-
AD3+
7
D4
I
ADC positive analog differential input AD3+
AD3-
8
D2
I
ADC negative analog differential input AD3-
VeREF+
9
D1
I
Input for an external reference voltage to the ADC and DAC
BSLRX
36
J6
I
BSL receive input
BSLTX
35
M5
O
BSL transmit output
VBAK
86
A7
I/O
Capacitor for backup subsystem. Do not load this pin externally. For
capacitor values, see CBAK in Recommended Operating Conditions.
VBAT
87
D8
P
CPCAP
17
G4
I/O
Capacitor for op amp and CTSD16 rail-to-rail charge pump
ACLK
34
L5
O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
RTCCLK
88
D7
O
RTCCLK output
SMCLK
46
J8
O
SMCLK output
XIN
15
G1
I
Input terminal for crystal oscillator XT1
XOUT
14
F1
O
Output terminal of crystal oscillator XT1
XT2IN
84
B8
I
Input terminal for crystal oscillator XT2
XT2OUT
85
B7
O
Output terminal of crystal oscillator XT2
CB0
97
B4
I
Comparator_B input CB0
CB1
98
B3
I
Comparator_B input CB1
CB2
99
A2
I
Comparator_B input CB2
CB3
100
D5
I
Comparator_B input CB3
CB4
1
A1
I
Comparator_B input CB4
CB5
2
B2
I
Comparator_B input CB5
CB6
3
B1
I
Comparator_B input CB6
CB7
4
C3
I
Comparator_B input CB7
CB8
5
C2
I
Comparator_B input CB8
CB9
6
C1
I
Comparator_B input CB9
CB10
7
D4
I
Comparator_B input CB10
CB11
8
D2
I
Comparator_B input CB11
CBOUT
42
L7
O
Comparator_B output
FUNCTION
Backup
Charge Pump
Clock
Comparator
(1)
16
DESCRIPTION
Backup or secondary supply voltage. If backup voltage is not supplied,
connect to DVCC externally.
I = input, O = output, I/O = input or output, P = power
Terminal Configuration and Functions
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SLAS874 – MAY 2015
Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL
NAME
Debug
PIN
TYPE (1)
DESCRIPTION
ZQW
DAC0
10
18
E4
H2
O
DAC output channel 0
DAC1
11
19
E2
J1
O
DAC output channel 1
DMAE0
88
D7
I
DMA external trigger input
SBWTCK
91
B6
I
Spy-Bi-Wire input clock
TCK
95
D6
I
Test clock
TCLK
93
A4
I
Test clock input
TDI
93
A4
I
Test data input
TDO
92
B5
O
Test data output
TEST
91
B6
I
Test mode pin; selects digital I/O on JTAG pins
TMS
94
E7
I
Test mode select
SBWTDIO
96
A3
I/O
Spy-Bi-Wire data input/output
P1.0
34
L5
I/O
General-purpose digital I/O with port interrupt
P1.1
35
M5
I/O
General-purpose digital I/O with port interrupt
P1.2
36
J6
I/O
General-purpose digital I/O with port interrupt
P1.3
37
H6
I/O
General-purpose digital I/O with port interrupt
P1.4
38
M6
I/O
General-purpose digital I/O with port interrupt
P1.5
39
L6
I/O
General-purpose digital I/O with port interrupt
P1.6
40
J7
I/O
General-purpose digital I/O with port interrupt
P1.7
41
M7
I/O
General-purpose digital I/O with port interrupt
P2.0
18
H2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.1
19
J1
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.2
20
H4
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.3
21
J2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.4
22
K1
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.5
23
K2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.6
24
L2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.7
25
L3
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P3.0
42
L7
I/O
General-purpose digital I/O with port interrupt
P3.1
43
H7
I/O
General-purpose digital I/O with port interrupt
P3.2
44
M8
I/O
General-purpose digital I/O with port interrupt
P3.3
45
L8
I/O
General-purpose digital I/O with port interrupt
P3.4
46
J8
I/O
General-purpose digital I/O with port interrupt
P3.5
47
M9
I/O
General-purpose digital I/O with port interrupt
P3.6
48
L9
I/O
General-purpose digital I/O with port interrupt
P3.7
49
M10
I/O
General-purpose digital I/O with port interrupt
DAC
DMA
PIN NO.
PZ
GPIO
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
GPIO
18
SIGNAL
NAME
PIN NO.
PZ
ZQW
PIN
TYPE (1)
DESCRIPTION
P4.0
50
J9
I/O
General-purpose digital I/O with port interrupt
P4.1
51
M11
I/O
General-purpose digital I/O with port interrupt
P4.2
52
L10
I/O
General-purpose digital I/O with port interrupt
P4.3
53
M12
I/O
General-purpose digital I/O with port interrupt
P4.4
54
L12
I/O
General-purpose digital I/O with port interrupt
P4.5
55
L11
I/O
General-purpose digital I/O with port interrupt
P4.6
56
K11
I/O
General-purpose digital I/O with port interrupt
P4.7
57
K12
I/O
General-purpose digital I/O with port interrupt
P5.0
9
D1
I/O
General-purpose digital I/O
P5.1
10
E4
I/O
General-purpose digital I/O
P5.3
31
L4
I/O
General-purpose digital I/O
P5.4
32
M4
I/O
General-purpose digital I/O
P5.5
33
J5
I/O
General-purpose digital I/O
P5.6
11
E2
I/O
General-purpose digital I/O
P5.7
88
D7
I/O
General-purpose digital I/O
P6.0
97
B4
I/O
General-purpose digital I/O
P6.1
98
B3
I/O
General-purpose digital I/O
P6.2
99
A2
I/O
General-purpose digital I/O
P6.3
100
D5
I/O
General-purpose digital I/O
P6.4
1
A1
I/O
General-purpose digital I/O
P6.5
2
B2
I/O
General-purpose digital I/O
P6.6
3
B1
I/O
General-purpose digital I/O
P6.7
4
C3
I/O
General-purpose digital I/O
P7.2
84
B8
I/O
General-purpose digital I/O
P7.3
85
B7
I/O
General-purpose digital I/O
P7.4
5
C2
I/O
General-purpose digital I/O
P7.5
6
C1
I/O
General-purpose digital I/O
P7.6
7
D4
I/O
General-purpose digital I/O
P7.7
8
D2
I/O
General-purpose digital I/O
P8.0
58
J11
I/O
General-purpose digital I/O
P8.1
59
J12
I/O
General-purpose digital I/O
P8.2
60
H11
I/O
General-purpose digital I/O
P8.3
61
H12
I/O
General-purpose digital I/O
P8.4
62
G11
I/O
General-purpose digital I/O
P8.5
65
F11
I/O
General-purpose digital I/O
P8.6
66
G9
I/O
General-purpose digital I/O
P8.7
67
E12
I/O
General-purpose digital I/O
P9.0
68
E11
I/O
General-purpose digital I/O
P9.1
69
F9
I/O
General-purpose digital I/O
P9.2
70
D12
I/O
General-purpose digital I/O
P9.3
71
D11
I/O
General-purpose digital I/O
P9.4
72
E9
I/O
General-purpose digital I/O
P9.5
73
C12
I/O
General-purpose digital I/O
P9.6
74
C11
I/O
General-purpose digital I/O
P9.7
75
D9
I/O
General-purpose digital I/O
Terminal Configuration and Functions
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SLAS874 – MAY 2015
Table 4-2. Signal Descriptions (continued)
SIGNAL
NAME
GPIO
PIN NO.
PZ
ZQW
PIN
TYPE (1)
PJ.0
92
B5
I/O
General-purpose digital I/O
PJ.1
93
A4
I/O
General-purpose digital I/O
PJ.2
94
E7
I/O
General-purpose digital I/O
PJ.3
95
D6
I/O
General-purpose digital I/O
PU.0
77
A12
I/O
General-purpose digital I/O - controlled by USB control register (FG662x
devices) or PU control register
PU.1
79
A11
I/O
General-purpose digital I/O - controlled by USB control register (FG662x
devices) or PU control register
G0SW0
3
B1
I
Analog switch to AVSS. Internally connected to ADC positive analog
differential input AD1+.
G0SW1
4
C3
I
Analog switch to AVSS. Internally connected to ADC negative analog
differential input AD1-.
G1SW0
7
D4
I
Analog switch to AVSS. Internally connected to ADC positive analog
differential input AD3+.
G1SW1
8
D2
I
Analog switch to AVSS. Internally connected to ADC negative analog
differential input AD3-.
UCB1SCL
66
G9
I/O
USCI_B1 I2C clock
UCB1SDA
65
F11
I/O
USCI_B1 I2C data
COM0
30
J4
O
LCD common output COM0 for LCD backplane
COM1
31
L4
O
LCD common output COM1 for LCD backplane
COM2
32
M4
O
LCD common output COM2 for LCD backplane
COM3
33
J5
I/O
LCD common output COM3 for LCD backplane
LCDCAP
29
M3
I/O
LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF
24
L2
I
R03
22
K1
I/O
Input/output port of lowest analog LCD voltage (V5)
R13
24
L2
I/O
Input/output port of third most positive analog LCD voltage (V3 or V4)
R23
25
L3
I/O
Input/output port of second most positive analog LCD voltage (V2)
R33
29
M3
I/O
Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
S0
75
D9
O
LCD segment output S0
S1
74
C11
O
LCD segment output S1
S2
73
C12
O
LCD segment output S2
S3
72
E9
O
LCD segment output S3
S4
71
D11
O
LCD segment output S4
S5
70
D12
O
LCD segment output S5
S6
69
F9
O
LCD segment output S6
S7
68
E11
O
LCD segment output S7
S8
67
E12
O
LCD segment output S8
S9
66
G9
O
LCD segment output S9
S10
65
F11
O
LCD segment output S10
S11
62
G11
O
LCD segment output S11
S12
61
H12
O
LCD segment output S12
S13
60
H11
O
LCD segment output S13
S14
59
J12
O
LCD segment output S14
S15
58
J11
O
LCD segment output S15
S16
57
K12
O
LCD segment output S16
S17
56
K11
O
LCD segment output S17
S18
55
L11
O
LCD segment output S18
FUNCTION
Ground Switch
I2C
LCD
DESCRIPTION
External reference voltage input for regulated LCD voltage
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
LCD
SIGNAL
NAME
PIN NO.
PZ
ZQW
PIN
TYPE (1)
S19
54
L12
O
LCD segment output S19
S20
53
M12
O
LCD segment output S20
S21
52
L10
O
LCD segment output S21
S22
51
M11
O
LCD segment output S22
S23
50
J9
O
LCD segment output S23
S24
49
M10
O
LCD segment output S24
S25
48
L9
O
LCD segment output S25
S26
47
M9
O
LCD segment output S26
S27
46
J8
O
LCD segment output S27
S28
45
L8
O
LCD segment output S28
S29
44
M8
O
LCD segment output S29
S30
43
H7
O
LCD segment output S30
S31
42
L7
O
LCD segment output S31
S32
41
M7
O
LCD segment output S32
S33
40
J7
O
LCD segment output S33
S34
39
L6
O
LCD segment output S34
S35
38
M6
O
LCD segment output S35
S36
37
H6
O
LCD segment output S36
S37
36
J6
O
LCD segment output S37
S38
35
M5
O
LCD segment output S38
S39
34
L5
O
LCD segment output S39
S40
33
J5
O
LCD segment output S40
S41
32
M4
O
LCD segment output S41
S42
31
L4
O
LCD segment output S42
P2MAP0
18
H2
I/O
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock
input/output
Mapping Options: See Table 6-8
P2MAP1
19
J1
I/O
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
Mapping Options: See Table 6-8
P2MAP2
20
H4
I/O
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
Mapping Options: See Table 6-8
P2MAP3
21
J2
I/O
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave
transmit enable
Mapping Options: See Table 6-8
P2MAP4
22
K1
I/O
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave
in/master out
Mapping Options: See Table 6-8
P2MAP5
23
K2
I/O
Default mapping: USCI_A0 UART receive data; USCI_A0 slave
out/master in
Mapping Options: See Table 6-8
P2MAP6
24
L2
I/O
Default mapping: no secondary function
Mapping Options: See Table 6-8
P2MAP7
25
L3
I/O
Default mapping: no secondary function
Mapping Options: See Table 6-8
NR
12
E1
I
Mappable
Noise
Reduction
20
DESCRIPTION
Terminal Configuration and Functions
Noise reduction. Connect pin to analog ground.
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SLAS874 – MAY 2015
Table 4-2. Signal Descriptions (continued)
FUNCTION
Op Amp
SIGNAL
NAME
ZQW
PIN
TYPE (1)
OA1IN0
6
C1
I
OA1 negative input internally connected to ADC negative analog
differential input AD2-
OA0IN0
2
B2
I
OA0 negative input internally connected to ADC negative analog
differential input AD0-
OA0IP0
99
A2
I
OA0 positive input internally connected to ADC analog input A2
OA0O
1
A1
O
OA0 output internally connected to ADC positive analog differential input
AD0+
100
D5
I
OA1 positive input internally connected to ADC analog input A3
OA1O
5
C2
O
OA1 output internally connected to ADC positive analog differential input
AD2+
AVSS1
13
F2
P
Analog ground supply
AVSS2
83
A8
P
Analog ground supply
DVCC
16
H1, G2
P
Digital power supply
DVCC1
26
L1
P
Digital power supply
DVCC2
64
F12
P
Digital power supply
DVCC3
89
A6
P
Digital power supply
DVSS1
27
M1
P
Digital ground supply
DVSS2
63
G12
P
Digital ground supply
DVSS3
90
A5
P
Digital ground supply
LDOI
80
A10
I
LDO input (not available on FG662x devices)
81
A9
O
LDO output (not available on FG662x devices)
28
M2
O
Regulated core power supply (internal use only, no external current
loading)
VREFBG
9
D1
O
Output of reference voltage to the ADC and DAC
NC
78
82
B10
B9
I/O
Not connected (not available on FG662x devices)
Reserved
–
E5, E6,
E8, F4,
F5, F8,
G5, G8,
H5, H8,
H9
-
UCA1CLK
59
J12
I/O
USCI_A1 clock input/output
UCA1SIMO
60
H11
I/O
USCI_A1 SPI slave in/master out
UCA1SOMI
61
H12
I/O
USCI_A1 SPI slave out/master in
UCA1STE
62
G11
I/O
USCI_A1 SPI slave transmit enable
UCB1CLK
62
G11
I/O
USCI_B1 clock input/output
UCB1SIMO
65
F11
I/O
USCI_B1 SPI slave in/master out
UCB1SOMI
66
G9
I/O
USCI_B1 SPI slave out/master in
UCB1STE
59
J12
I/O
USCI_B1 SPI slave transmit enable
NMI
96
A3
I
RST
96
A3
I/O
Reset input (active low) (3)
SVMOUT
57
K12
O
SVM output
OA1IP0
Power
LDOO
VCORE
REF
PIN NO.
PZ
(2)
Reserved
SPI
System
(2)
(3)
DESCRIPTION
Reserved. Internally connected to DVSS. TI recommends external
connection to ground (DVSS).
Nonmaskable interrupt input
VCORE is for internal use only. No external current loading is possible. VCORE must be connected to the recommended capacitor
value, CVCORE.
When this pin is configured as reset, the internal pullup resistor is enabled by default.
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
SIGNAL
NAME
ZQW
PIN
TYPE (1)
35
M5
I/O
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
36
J6
I/O
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
40
J7
I/O
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
37
H6
I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
41
M7
I/O
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
TA0.3
38
M6
I/O
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
TA0.4
39
L6
I/O
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
TA0CLK
34
L5
I
TA1.0
43
H7
I/O
Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
TA1.1
44
M8
I/O
Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
TA1.2
45
L8
I/O
Timer TA1 capture CCR2: CCI2A input, compare: Out2 output
TA1CLK
42
L7
I
TA2.0
47
M9
I/O
Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
TA2.1
48
L9
I/O
Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
TA2.2
49
M10
I/O
Timer TA2 capture CCR2: CCI2A input, compare: Out2 output
TA2CLK
46
J8
I
TB0.0
50
J9
I/O
Timer TB0 capture CCR0: CCI0A input, compare: Out0 output
TB0.1
51
M11
I/O
Timer TB0 capture CCR1: CCI1A input, compare: Out1 output
TB0.2
52
L10
I/O
Timer TB0 capture CCR2: CCI2A input, compare: Out2 output
TB0.3
53
M12
I/O
Timer TB0 capture CCR3: CCI3A input, compare: Out3 output
TB0.4
54
L12
I/O
Timer TB0 capture CCR4: CCI4A input, compare: Out4 output
TB0.5
55
L11
I/O
Timer TB0 capture CCR5: CCI5A input, compare: Out5 output
TB0.6
56
K11
I/O
Timer TB0 capture CCR6: CCI6A input, compare: Out6 output
TB0CLK
58
J11
I
Timer TB0 clock input
TB0OUTH
57
K12
I
Timer TB0: Switch all PWM outputs high impedance
UCA1CLK
59
J12
I/O
UCA1RXD
61
H12
I
USCI_A1 UART receive data
UCA1TXD
60
H11
O
USCI_A1 UART transmit data
DM
79
A11
I/O
USB data terminal DM (not available on FG6426 and FG6425 devices)
DP
77
A12
I/O
USB data terminal DP (not available on FG6426 and FG6425 devices)
TA0.0
TA0.1
TA0.2
Timer_A
Timer_B
UART
PIN NO.
PZ
FUNCTION
DESCRIPTION
Timer TA0 clock signal TACLK input
Timer TA1 clock input
Timer TA2 clock input
USCI_A1 clock input/output
USB pullup resistor pin (open drain). The voltage level at the PUR pin is
used to invoke the default USB BSL.
PUR
78
B10
I/O
USB
(FG662x only)
22
Recommended 1-MΩ resistor to ground. See Section 6.6 for more
information.
Not available on FG6426 and FG6425 devices.
V18
82
B9
O
USB regulated power (internal use only, no external current loading) (not
available on FG6426 and FG6425 devices)
VBUS
80
A10
I
USB LDO input (connect to USB power source) (not available on
FG6426 and FG6425 devices)
VSSU
76
B11
B12
P
USB PHY ground supply
VUSB
81
A9
O
USB LDO output (not available on FG6426 and FG6425 devices)
Terminal Configuration and Functions
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4.4
SLAS874 – MAY 2015
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.12.23.
Table 4-3. Buffer Type
BUFFER TYPE
(STANDARD)
Analog (1)
HVCMOS
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
OTHER
CHARACTERISTICS
3.0 V
N
N/A
N/A
N/A
See analog modules in
Section 5, Specifications for
details
N/A
N/A
See
Section 5.5.5.1,
Typical
Characteristics
– Outputs
See
Section 5.5.5.1,
Typical
Characteristics
– Outputs
5.0 V
Y
LVCMOS
3.0 V
Y (2)
Programmable
See
Section 5.5.5,
GeneralPurpose I/Os
Power
(DVCC) (3)
3.0 V
N
N/A
N/A
N/A
Power
(AVCC) (3)
3.0 V
N
N/A
N/A
N/A
0V
N
N/A
N/A
N/A
Power (DVSS
and AVSS) (3)
(1)
(2)
(3)
SVS enables hysteresis on
DVCC
This is a switch, not a buffer.
Only for input pins
This is supply input, not a buffer.
Terminal Configuration and Functions
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Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins (1)
PIN
POTENTIAL
COMMENT
AVCC
DVCC
AVSS
DVSS
CPCAP
Open
LCDCAP
DVSS
LDOI
DVSS
For devices with LDO-PWR module when not being used in the application.
LDOO
Open
For devices with LDO-PWR module when not being used in the application.
NC
Open
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these must
be switched to port function, output direction (PJDIR.n = 1). When used as JTAG pins, these pins
must remain open.
PU.0/DP
PU.1/DM
Open
For USB devices only when USB module is not being used in the application
PUR (2)
DVSS
For USB devices only when USB module is not being used in the application
Px.y
Open
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y of port x
(for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown (3)
Reserved
DVSS
TEST
Open
This pin always has an internal pulldown enabled.
V18
Open
For USB devices only when USB module is not being used in the application
VBAK
Open
For devices where no separate battery backup supply is used in the system. Set bit BAKDIS = 1.
VBAT
DVCC
For devices where no separate battery backup supply is used in the system. Set bit BAKDIS = 1.
VBUS, VSSU
DVSS
For USB devices only when USB module is not being used in the application
VUSB
Open
For USB devices only when USB module is not being used in the application
XIN
DVSS
For dedicated XIN pins only. XIN pins with shared GPIO functions must be programmed to GPIO
and follow Px.y recommendations.
XOUT
Open
For dedicated XOUT pins only. XOUT pins with shared GPIO functions must be programmed to
GPIO and follow Px.y recommendations.
XT2IN
DVSS
For dedicated XT2IN pins only. XT2IN pins with shared GPIO functions must be programmed to
GPIO and follow Px.y recommendations.
XT2OUT
Open
For dedicated XT2OUT pins only. XT2OUT pins with shared GPIO functions must be programmed
to GPIO and follow Px.y recommendations.
(1)
(2)
(3)
24
For devices where the charge pump is not used (no rail-to-rail OA and no rail-to-rail CTSD16).
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.y unused pin connection
guidelines.
The default USB BSL evaluates the state of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked.
Therefore, unless invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends a 1-MΩ resistor to ground.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools such as FET interfaces or GANG programmers.
Terminal Configuration and Functions
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SLAS874 – MAY 2015
5 Specifications
5.1
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
Voltage applied to any pin (excluding VCORE, VBUS, V18, LDOI)
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device pin
Storage temperature, Tstg
(3)
–55
(2)
(3)
150
°C
95
°C
ESD Ratings
VALUE
V(ESD)
(2)
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
(1)
V
±2
Maximum junction temperature, TJ
(1)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
Supply voltage during program execution and flash
programming (AVCC = DVCC1 = DVCC2 = DVCC3 =
DVCC = VCC) (1) (2) (3)
VCC
VCC,USB
(2)
Supply voltage during USB operation, USB PLL disabled
(USB_EN = 1, UPLLEN = 0)
Supply voltage during USB operation, USB PLL enabled
(4)
(USB_EN = 1, UPLLEN = 1)
VSS
NOM
MAX
PMMCOREV = 0
1.8
3.6
PMMCOREV = 0, 1
2.0
3.6
PMMCOREV = 0, 1, 2
2.2
3.6
PMMCOREV = 0, 1, 2, 3
2.4
3.6
PMMCOREV = 0
1.8
3.6
PMMCOREV = 0, 1
2.0
3.6
PMMCOREV = 0, 1, 2
2.2
3.6
PMMCOREV = 0, 1, 2, 3
2.4
3.6
PMMCOREV = 2
2.2
3.6
PMMCOREV = 2, 3
2.4
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS)
UNIT
V
V
3.6
0
V
TA = 0°C to 85°C
1.55
3.6
TA = –40°C to 85°C
1.70
3.6
VBAT,RTC
Backup-supply voltage with RTC operational
VBAT,MEM
Backup-supply voltage with backup memory retained.
TA = –40°C to 85°C
1.20
3.6
V
TA
Operating free-air temperature
I version
–40
85
°C
TJ
Operating junction temperature
I version
–40
85
°C
CBAK
Capacitance at pin VBAK
10
nF
CVCORE
Capacitor at VCORE (5)
(1)
(2)
(3)
(4)
(5)
1
4.7
470
V
nF
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
Some modules may have reduced recommended ranges of operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Table 5-19 for
the exact values and further details.
USB operation with USB PLL enabled requires PMMCOREV ≥ 2 for proper operation.
A capacitor tolerance of ±20% is required.
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Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
fSYSTEM_USB
Minimum processor frequency for USB operation
USB_wait
Wait state cycles during USB operation
(6)
(7)
MAX
UNIT
10
Processor frequency (maximum MCLK frequency)
(see Figure 5-1)
fSYSTEM
NOM
(6) (7)
PMMCOREV = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREV = 1,
2 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREV = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
16.0
PMMCOREV = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
20.0
1.5
MHz
MHz
16
cycles
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
System Frequency - MHz
20
3
16
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Frequency vs Supply Voltage
26
Specifications
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SLAS874 – MAY 2015
Table 5-1. Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
PMMCOREV
1 MHz
TYP
IAM,
IAM,
(1)
(2)
(3)
Flash
RAM
Flash
RAM
3V
3V
8 MHz
MAX
0.36
TYP
2.0
12 MHz
MAX
TYP
0
0.31
1
0.35
2.3
3.4
2
0.37
2.5
3.8
3
0.4
0
0.2
1
0.22
1.3
1.9
2
0.24
1.5
2.2
3
0.26
1.6
2.4
1.1
MAX
TYP
UNIT
MAX
2.4
2.7
0.23
20 MHz
4.0
4.0
mA
6.6
1.2
2.1
mA
3.9
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing. FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0).
FG6426 and FG6425 LDO disabled (LDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
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Specifications
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Table 5-2. Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0,1MHz
Low-power mode 0 (3)
(4)
ILPM2
Low-power mode 2 (5)
(4)
VLO,WDT
Low-power mode 4 (8)
ILPM4
0
72
77
87
81
87
98
3V
3
86
92
105
97
104
117
2.2 V
0
6.9
7.5
9.9
8.5
12
17
3V
3
7.9
8.5
11
9.7
14
20
0
2.8
3.2
3.7
4.2
7.6
13.5
1
3.1
3.6
4.6
8.2
2
3.5
4.0
5.1
8.8
0
3.0
3.4
4.4
7.9
1
3.3
3.8
4.9
8.5
2
3.7
4.2
5.3
9.0
3
3.7
4.2
4.8
5.3
9.1
16
0
1.2
1.5
2.1
2.4
5.8
12.5
1
1.4
1.6
2.6
6.1
2
1.6
1.8
2.8
6.5
3
1.6
1.8
2.6
2.9
6.5
14
0
0.6
0.9
1.8
1.9
5.4
11.5
1
0.7
1.0
2.0
5.6
2
0.8
1.1
2.2
5.9
3
0.8
1.1
2.2
6.0
13
ILPM3.5,
RTC,VCC
ILPM3.5,
RTC,VBAT
ILPM3.5,
RTC,TOT
3V
(4)
85°C
2.2 V
Low-power mode 3,
crystal mode (6) (4)
Low-power mode 3,
VLO mode, Watchdog
enabled (7) (4)
60°C
PMMCOREV
3V
ILPM3,
25°C
VCC
2.2 V
ILPM3,XT1LF
-40°C
(2)
3V
TYP
MAX
TYP
MAX
4.0
2.1
TYP
MAX
TYP
MAX
14
UNIT
µA
µA
µA
µA
µA
Low-power mode 3.5
(LPM3.5) current with
active RTC into primary
supply pin DVCC (9)
3V
0.2
0.7
1.7
µA
Low-power mode 3.5
(LPM3.5) current with
active RTC into backup
supply pin VBAT (10)
3V
0.7
0.9
1.2
µA
Total low-power mode
3.5 (LPM3.5) current
with active RTC (11)
3V
1.6
2.9
µA
0.8
0.9
1.0
(1)
(2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(4) Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO
setting = 1 MHz operation, DCO bias generator enabled.
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(7) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(9) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(11) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
28
Specifications
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SLAS874 – MAY 2015
Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
Low-power mode 4.5
(LPM4.5) (12)
ILPM4.5
VCC
PMMCOREV
3V
-40°C
TYP
MAX
0.12
25°C
TYP
60°C
MAX
0.2
0.6
TYP
MAX
85°C
TYP
0.32
MAX
0.8
1.9
UNIT
µA
(12) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Table 5-3. Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(2)
Temperature (TA)
PARAMETER
VCC
PMMCOREV
-40°C
TYP
ILPM3,
LCD,
ext. bias
ILPM3,
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, external
biasing (3) (4)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (5)
3V
3V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
(6)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled (3) (6)
3V
MAX
25°C
TYP
0
3.7
4.3
1
4.1
2
60°C
MAX
TYP
MAX
TYP
UNIT
MAX
5.5
9.0
4.7
5.9
9.6
4.5
5.1
6.3
10.2
3
4.5
5.2
5.8
6.5
10.4
18.0
0
4.2
4.8
5.4
6.0
9.6
17.0
1
4.7
5.4
6.6
10.4
2
5.1
5.8
7.1
11.0
3
5.0
5.7
7.0
11.0
0
6.4
1
6.77
2
7.13
0
6.53
1
7.0
2
7.43
3
7.6
4.9
85°C
6.4
15.0
µA
µA
19.0
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and
high-side monitor (SVMH) disabled. RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
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5.4
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Thermal Characteristics
PARAMETER
θJA
Junction-to-ambient thermal resistance, still air
θJC(TOP)
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance
(1)
(2)
(3)
VALUE
(1)
(2)
(3)
QFP (PZ)
122
BGA (ZQW)
108
QFP (PZ)
83
BGA (ZQW)
72
QFP (PZ)
98
BGA (ZQW)
76
UNIT
°C/W
°C/W
°C/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
5.5
5.5.1
Timing and Switching Characteristics
Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power
down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Section 5.1, Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and flash.
Table 5-4. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
5.5.2
MIN
TYP
0.80
1.30
60
MAX
UNIT
1.47
V
1.55
V
250
mV
TYP
UNIT
Reset Timing
Table 5-5. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tRESET
30
Pulse duration required at RST/NMI pin to accept a reset
Specifications
2
µs
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5.5.3
SLAS874 – MAY 2015
Clock Specifications
Table 5-6. Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1
ΔIDVCC,LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1 (2)
Oscillation allowance for
LF crystals (4)
0.170
32768
XTS = 0, XT1BYPASS = 0
OALF
3V
0.290
XT1 oscillator crystal frequency,
LF mode
(3)
10
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
fFault,LF
tSTART,LF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Integrated effective load
capacitance, LF mode (5)
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Duty cycle, LF mode
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
Start-up time, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
CL,eff = 12 pF
Hz
50
kHz
1
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
µA
kΩ
XTS = 0, XCAPx = 0 (6)
CL,eff
UNIT
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3
fXT1,LF0
MAX
pF
30%
70%
10
10000
Hz
1000
3V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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SLAS874 – MAY 2015
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Table 5-7. Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
IDVCC,XT2
TEST CONDITIONS
XT2 oscillator crystal current
consumption
VCC
MIN
(2)
TYP
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
MAX
UNIT
3V
µA
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
450
fXT2,HF0
XT2 oscillator crystal frequency,
mode 0
XT2DRIVEx = 0, XT2BYPASS = 0 (3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal frequency,
mode 1
XT2DRIVEx = 1, XT2BYPASS = 0 (3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal frequency,
mode 2
XT2DRIVEx = 2, XT2BYPASS = 0 (3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal frequency,
mode 3
XT2DRIVEx = 3, XT2BYPASS = 0 (3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level squarewave input frequency
XT2BYPASS = 1 (4)
0.7
32
MHz
Oscillation allowance for
HF crystals (5)
OAHF
tSTART,HF
CL,eff
fFault,HF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
32
Start-up time
Integrated effective load
capacitance, HF mode (6)
(3)
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C,
CL,eff = 15 pF
0.5
fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C,
CL,eff = 15 pF
Ω
3V
ms
0.3
1
(1)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
Oscillator fault frequency (7)
XT2BYPASS = 1 (8)
40%
30
50%
pF
60%
300
kHz
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT2BYPASS is set, the XT2 circuit is automatically powered down.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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SLAS874 – MAY 2015
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
TEST CONDITIONS
Measured at ACLK
VCC
MIN
TYP
MAX
6
9.4
14
1.8 V to 3.6 V
(1)
1.8 V to 3.6 V
0.5
Measured at ACLK (2)
1.8 V to 3.6 V
4
Measured at ACLK
1.8 V to 3.6 V
Measured at ACLK
40%
50%
UNIT
kHz
%/°C
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-9. Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
REFO oscillator current
consumption
TA = 25°C
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
REFO absolute tolerance
calibrated
Full temperature range
1.8 V to 3.6 V
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage
drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
IREFO
fREFO
tSTART
(1)
(2)
TA = 25°C
±3.5%
3V
±1.5%
40%
50%
60%
25
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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Table 5-10. DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fDCO(0,0)
TEST CONDITIONS
DCO frequency (0, 0) (1)
(1)
MAX
UNIT
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
MIN
TYP
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0) (1)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
(1)
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31) (1)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
(1)
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0) (1)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
(1)
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0) (1)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
(1)
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz,
0.1
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
(1)
40
50
60
%
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-2. Typical DCO Frequency
34
Specifications
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5.5.4
SLAS874 – MAY 2015
Wake-Up Characteristics
Table 5-11. Wake-Up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
fMCLK ≥ 4 MHz
3
6.5
1 MHz < fMCLK <
4 MHz
4
8.0
150
165
µs
Wake-up time from LPM3.5 or
LPM4.5 to active mode (3)
2
3
ms
Wake-up time from RST or
BOR event to active mode (3)
2
3
ms
tWAKE-UP-FAST
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode (2)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-LPM5
tWAKE-UP-RESET
(1)
(2)
(3)
MIN
UNIT
µs
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSL and SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSL and SVML are in normal mode (low
current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2,
LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx
Family User's Guide (SLAU208).
This value represents the time from the wake-up event to the reset vector execution.
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General-Purpose I/Os
Table 5-12. Schmitt-Trigger Inputs – General-Purpose I/O (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
1.8 V
0.80
TYP
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
35
MAX
UNIT
V
V
V
50
kΩ
5
pF
Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Table 5-13. Inputs – Ports P1, P2, P3, and P4 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Port P1, P2, P3, P4: P1.x to P4.x,
External trigger pulse duration to set interrupt flag
External interrupt timing (2)
t(int)
(1)
(2)
TEST CONDITIONS
MIN
2.2 V, 3 V
MAX
UNIT
20
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Table 5-14. Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
±50
nA
(1) (2)
Ilkg(Px.x)
(1)
(2)
1.8 V,
3V
High-impedance leakage current
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Table 5-15. Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (2)
I(OHmax) = –5 mA
I(OLmax) = 3 mA (1)
Low-level output voltage
I(OLmax) = 10 mA (2)
I(OLmax) = 5 mA
(2)
36
3V
1.8 V
(1)
I(OLmax) = 15 mA (2)
(1)
1.8 V
(1)
I(OHmax) = –15 mA (2)
VOL
VCC
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Specifications
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SLAS874 – MAY 2015
Table 5-16. Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
I(OHmax) = –1 mA (2)
VOH
1.8 V
I(OHmax) = –3 mA (3)
High-level output voltage
I(OHmax) = –2 mA (2)
3V
I(OHmax) = –6 mA (3)
I(OLmax) = 1 mA (2)
VOL
I(OLmax) = 2 mA (2)
(3)
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
3V
I(OLmax) = 6 mA (3)
(1)
(2)
MAX
1.8 V
I(OLmax) = 3 mA (3)
Low-level output voltage
MIN
VCC – 0.25
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Table 5-17. Output Frequency – Ports P1, P2 and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
fPort_CLK
(1)
(2)
(3)
TEST CONDITIONS
Port output frequency
(with load)
P3.4/TA2CLK/SMCLK/S27
CL = 20 pF, RL = 1 kΩ (1) or 3.2 kΩ (2)
Clock output frequency
P1.0/TA0CLK/ACLK/S39
P3.4/TA2CLK/SMCLK/S27
P2.0/P2MAP0 (P2MAP0 = PM_MCLK )
CL = 20 pF (3)
(3)
MIN
MAX
VCC = 1.8 V
PMMCOREVx = 0
8
VCC = 3 V
PMMCOREVx = 3
20
VCC = 1.8 V
PMMCOREVx = 0
8
VCC = 3 V
PMMCOREVx = 3
20
UNIT
MHz
MHz
Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Figure 5-3. Typical Low-Level Output Current vs Low-Level
Output Voltage
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
−10.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
VCC = 3.0 V
P3.2
Figure 5-5. Typical High-Level Output Current Vs High-Level
Output Voltage
38
3.0
2.0
1.0
0.5
1.0
1.5
2.0
0.0
−5.0
−25.0
0.0
4.0
Figure 5-4. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
−20.0
TA = 85°C
5.0
VOL – Low-Level Output Voltage – V
VCC = 1.8 V
P3.2
VOL – Low-Level Output Voltage – V
VCC = 3.0 V
P3.2
−15.0
6.0
0.0
0.0
3.5
TA = 25°C
7.0
Specifications
−1.0
−2.0
−3.0
−4.0
−5.0
TA = 85°C
−6.0
TA = 25°C
−7.0
−8.0
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
VCC = 1.8 V
P3.2
2.0
Figure 5-6. Typical High-Level Output Current Vs High-Level
Output Voltage
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SLAS874 – MAY 2015
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
TA = 25°C
55.0
50.0
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
TA = 85°C
12
8
4
0.5
1.0
1.5
2.0
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
IOH – Typical High-Level Output Current – mA
0.0
IOH – Typical High-Level Output Current – mA
16
VOL – Low-Level Output Voltage – V
VCC = 1.8 V
P3.2
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
−5.0
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
TA = 85°C
−55.0
−60.0
0.0
TA = 25°C
20
0
0.0
3.5
VOL – Low-Level Output Voltage – V
VCC = 3.0 V
P3.2
−50.0
24
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
VCC = 3.0 V
P3.2
Figure 5-9. Typical High-Level Output Current vs High-level
Output Voltage
−4
−8
−12
TA = 85°C
−16
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VCC = 1.8 V
P3.2
Figure 5-10. Typical High-Level Output Current vs High-level
Output Voltage
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PMM
Table 5-18. PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.90
V
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.80
V
VCORE1(AM)
Core voltage, active mode,
PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
1.60
V
VCORE0(AM)
Core voltage, active mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
1.40
V
VCORE3(LPM)
Core voltage, low-current
mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.94
V
VCORE2(LPM)
Core voltage, low-current
mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.84
V
VCORE1(LPM)
Core voltage, low-current
mode, PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.64
V
VCORE0(LPM)
Core voltage, low-current
mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.44
V
Table 5-19. PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
SVSH on voltage level (1)
SVSH off voltage level (1)
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
(1)
40
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
2.0
µA
SVSHE = 1, SVSHRVL = 0
1.59
1.64
1.69
SVSHE = 1, SVSHRVL = 1
1.79
1.84
1.91
SVSHE = 1, SVSHRVL = 2
1.98
2.04
2.11
SVSHE = 1, SVSHRVL = 3
2.10
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.81
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.01
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.20
2.26
2.33
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVSHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVSHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVSHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0→1, SVSHFP = 1
12.5
SVSHE = 0→1, SVSHFP = 0
100
0
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
µs
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREV) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.
Specifications
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Table 5-20. PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMH on or off voltage level (1)
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
(1)
UNIT
nA
200
2.0
µA
SVMHE = 1, SVSMHRRL = 0
1.65
1.74
1.86
SVMHE = 1, SVSMHRRL = 1
1.85
1.94
2.02
SVMHE = 1, SVSMHRRL = 2
2.02
2.14
2.22
SVMHE = 1, SVSMHRRL = 3
2.18
2.26
2.35
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVMHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVMHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVMHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
MAX
0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0→1, SVSMFP = 1
12.5
SVMHE = 0→1, SVMHFP = 0
100
µs
µs
The SVMH settings available depend on the VCORE (PMMCOREV) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.
Table 5-21. PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
TYP
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
2.0
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0→1, SVSLFP = 1
12.5
SVSLE = 0→1, SVSLFP = 0
100
UNIT
nA
µA
µs
µs
Table 5-22. PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on or off delay time
TYP
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
2.0
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0→1, SVMLFP = 1
12.5
SVMLE = 0→1, SVMLFP = 0
100
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MAX
0
Specifications
UNIT
nA
µA
µs
µs
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Timers
Table 5-23. Timer_A, Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs,
Minimum pulse duration required for
capture
1.8 V, 3 V
MIN
MAX
UNIT
20
MHz
20
ns
Table 5-24. Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs,
Minimum pulse duration required for
capture
5.5.8
VCC
1.8 V, 3 V
1.8 V, 3 V
MIN
MAX
UNIT
20
MHz
20
ns
Battery Backup
Table 5-25. Battery Backup
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBAT = 1.7 V,
DVCC not connected,
RTC running
Current into VBAT terminal in VBAT = 2.2 V,
case no primary battery is
DVCC not connected,
connected.
RTC running
IVBAT
VBAT = 3 V,
DVCC not connected,
RTC running
VCC
MIN
TYP
TA = –40°C
0.43
TA = 25°C
0.52
TA = 60°C
0.58
TA = 85°C
0.66
TA = –40°C
0.50
TA = 25°C
0.59
TA = 60°C
0.64
TA = 85°C
0.72
TA = –40°C
0.68
TA = 25°C
0.75
TA = 60°C
0.79
TA = 85°C
Switch-over level (VCC to
VBAT)
RON_VBAT
On-resistance of switch
between VBAT and VBAK
VBAT3
VBAT to ADC:
VBAT divided,
VBAT3 = VBAT /3
VCHVx
42
Charger end voltage
Specifications
CVCC = 4.7 µF
VBAT = 1.8 V
CHVx = 2
UNIT
µA
0.86
General
VSWITCH
MAX
VSVSH_IT-
SVSHRL = 0
1.59
1.69
SVSHRL = 1
1.79
1.91
SVSHRL = 2
1.98
2.11
SVSHRL = 3
2.10
2.23
0.35
1
1.8 V
0.6
±5%
3V
1.0
±5%
3.6 V
1.2
±5%
2.7
2.9
0V
2.65
V
kΩ
V
V
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SLAS874 – MAY 2015
Battery Backup (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RCHARGE
5.5.9
Charge limiting resistor
TEST CONDITIONS
VCC
MIN
TYP
MAX
CHCx = 1
5.2
CHCx = 2
10.2
CHCx = 3
20
UNIT
kΩ
USCI
Table 5-26. USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time (1)
(1)
TEST CONDITIONS
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-27. USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(see Figure 5-11 and Figure 5-12)
PARAMETER
fUSCI
USCI input clock frequency
TEST CONDITIONS
SOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,MI
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
SIMO output data valid time (2)
(2)
(3)
55
3V
38
2.4 V
30
3V
25
1.8 V
0
3V
0
2.4 V
0
3V
0
UNIT
fSYSTEM
MHz
ns
ns
1.8 V
20
3V
18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
16
SIMO output data hold time (3)
CL = 20 pF, PMMCOREV = 3
(1)
1.8 V
MAX
UCLK edge to SIMO valid,
CL = 20 pF,
PMMCOREV = 0
CL = 20 pF, PMMCOREV = 0
tHD,MO
MIN
SMCLK, ACLK,
Duty cycle = 50% ±10%
PMMCOREV = 0
tSU,MI
VCC
3V
ns
15
1.8 V
–10
3V
–8
2.4 V
–10
3V
–8
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-12. SPI Master Mode, CKPH = 1
44
Specifications
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Table 5-28. USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(see Figure 5-13 and Figure 5-14)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, Last clock to STE high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
tHD,SO
(1)
(2)
(3)
SOMI output data valid time (2)
SOMI output data hold time (3)
VCC
MIN
1.8 V
11
3V
8
2.4 V
7
3V
6
1.8 V
3
3V
3
2.4 V
3
3V
3
MAX
ns
ns
1.8 V
66
3V
50
2.4 V
36
3V
30
1.8 V
30
3V
30
2.4 V
30
3V
UNIT
ns
ns
30
1.8 V
5
3V
5
2.4 V
2
3V
2
1.8 V
5
3V
5
2.4 V
5
3V
5
ns
ns
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 0
1.8 V
76
3V
60
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 3
2.4 V
44
3V
40
CL = 20 pF,
PMMCOREV = 0
1.8 V
12
3V
12
CL = 20 pF,
PMMCOREV = 3
2.4 V
12
3V
12
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 5-14. SPI Slave Mode, CKPH = 1
46
Specifications
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Table 5-29. USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
TEST CONDITIONS
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
2.2 V, 3 V
fSCL ≤ 100 kHz
0
MAX
UNIT
fSYSTEM
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
2.2 V, 3 V
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
tSU,STO
Setup time for STOP
tSP
Pulse duration of spikes suppressed by input
filter
tSU,STA
µs
0.6
4.0
2.2 V, 3 V
fSCL > 100 kHz
tHD,STA
4.7
2.2 V, 3 V
fSCL > 100 kHz
µs
0.6
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-15. I2C Mode Timing
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5.5.10 LCD Controller
Table 5-30. LCD_B, Recommended Operating Conditions
CONDITIONS
MIN
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
PARAMETER
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
Supply voltage range, external
LCD voltage, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage at
LCDCAP/R33, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
10
µF
fFrame
LCD frame frequency range
fLCD = 2 × mux × fFRAME
(mux = 1 (static), 2, 3, 4)
100
Hz
fACLK,in
ACLK input frequency range
40
kHz
CPanel
Panel capacitance
100-Hz frame frequency
10000
pF
VCC +
0.2
V
VCC,LCD_B,
CP en,3.6
VCC,LCD_B,
CP en,3.3
VCC,LCD_B,
int. bias
VCC,LCD_B,
ext. bias
VCC,LCD_B,
VLCDEXT
NOM
4.7
0
30
32
UNIT
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
VR23,1/3bias
Analog input voltage at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3 ×
(VR33 – VR03)
VR33
V
VR13,1/3bias
Analog input voltage at R13 with
1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3 ×
(VR33 – VR03)
VR23
V
VR13,1/2bias
Analog input voltage at R13 with
1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VR03 + 1/2 ×
(VR33 – VR03)
VR33
V
VR03
Analog input voltage at R03
R0EXT = 1
VLCD-VR03
Voltage difference between VLCD
and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD reference voltage
applied at LCDREF/R13
VLCDREFx = 01
0.8
48
Specifications
2.4
MAX
VSS
V
1.2
VCC
+ 0.2
V
1.5
V
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Table 5-31. LCD_B, Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
TYP
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.60
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.66
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.72
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.79
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.85
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.92
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.98
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
3.05
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.10
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.17
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.24
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.30
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.36
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.42
MAX
UNIT
V
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.48
ICC,Peak,CP
Peak supply currents due to
charge pump activities
3.6
LCDCPEN = 1, VLCDx = 1111
2.2 V
400
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF,
LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
µA
500
50
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5.5.11 CTSD16
NOTE
The delta-sigma analog-to-digital converter uses the CTSD16. The CTSD16 is proceeded by a unitygain buffer stage following the channel muxing as shown in Figure 6-1. Refer to Table 5-46 for the
electrical characteristics of the PGA buffer stages.
Table 5-32. CTSD16, Power Supply and Recommended Operating Conditions
PARAMETER
VCC
ICTSD16
ICTSD16CLK
(1)
TEST CONDITIONS
Supply voltage range
VCC
MIN
AVSS = DVSS = 0 V
TYP
2.2
Analog plus digital supply
current per converter
(reference current not
included)
CTSD16OSRx = 256,
CTSD16RRI = 0
GAIN: 1, 2, 4, 8, 16
3V
GAIN: 1, 16
3V
CTSD16 clock current
consumption
This is requested when CTSD16 is converting, or
CTSD16RRIBURST = 0, or when OA is in rail-to-rail
input mode (OARRI = 1), or when OA charge pump
is on. The current should only be counted once
even if both OA and CTSD16 are requesting the
clock.
MAX
UNIT
3.6
190
V
(1)
µA
300 (1)
3V
205
240
µA
Refer to table Table 5-33 to calculate total current from CTSD16 for different use cases.
Table 5-33 explains how to compute the total current, ITOTAL, when the CTSD, along with associated modules,
are used. Refer to Table 5-47 for a similar table for the OA. A "yes" means it must be included in computing
ITOTAL. Here is an example current calculation for CTS16D in rail-to-rail input mode (CTSD16RRI = 1) using the
internal reference (CTSD16REFS = 1) and OA0 and OA1 enabled in rail-to-rail input modes, OARRI = 1.
As an example, assume that the application uses the CTS16D in rail-to-rail input mode (CTSD16RRI = 1) with
the internal reference (CTSD16REFS = 1) and OA0 and OA1 are enabled in rail-to-rail input modes, OARRI = 1.
The total current, ITOTAL, would be computed as follows:
ITOTAL = ICTSD16 + ICTSD16CLK+ ICP + IREFBG + 2 × IOA
Table 5-33. CTSD16, Current Calculation
USE CASE
DETAILS
USE CASE NAME
CTSD16
CTSD16 rail-to-rail inputs
(1)
(2)
(3)
(4)
50
CTSD16RRI = 1
ICTSD16
(1)
ICP
(2)
IREFBG
(3)
IREF
(4)
yes
yes
no
yes if CTSD16REFS = 1
no if CTSD16REFS = 0
yes
yes
yes
yes
yes if CTSD16REFS = 1
no if CTSD16REFS = 0
yes
Count this only once no matter how many modules use it.
Count this only once no matter how many modules use it.
Count this only once no matter how many modules use it.
REFOUT=1. This current is listed in the Table 5-39 table.
Count this only once no matter how many modules use it.
IREF current.
Specifications
ICTSD16CLK
OA can also use this when rail-to-rail input is selected.
OA also uses this. This current is listed in the Table 5-46 table.
DAC can use this as well as internal reference when it is available externally,
This current is listed in the Table 5-46 table. If IREFBG is used that includes
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Table 5-34. CTSD16, External Voltage Reference
VCC
MIN
TYP
MAX
VVeREF+
Input voltage range
PARAMETER
CTSD16REFS = 0
TEST CONDITIONS
3V
1.0
1.2
1.5
UNIT
V
IVeREF+
Input current
CTSD16REFS = 0
3V
50
nA
Table 5-35. CTSD16, Input Range (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VID,FSR
Differential full-scale input
voltage range
VID = VI,A+ – VI,A–
VI,FSR
Single-ended full-scale input
voltage range
VID = VI,A+ – VR
negative input is tied to VR
Differential input voltage range
for specified performance (2)
VID
CTSD16REFS = 1
VCC
MIN
TYP
MAX
UNIT
–VR/Gain
+VR/Gain
V
VR –
VR/Gain
VR +
VR/Gain
V
CTSD16GAINx = 1
±928
CTSD16GAINx = 2
±464
CTSD16GAINx = 4
±232
CTSD16GAINx = 8
±116
CTSD16GAINx = 16
±58
VR –
(0.8 ×
VR/Gain)
mV
VR +
(0.8 ×
VR/Gain)
VI
Single-ended input voltage
range for specified performance
ZI
Input impedance
(pin Ax or ADx+ or ADx- to
AVSS)
CTSD16GAINx = 1, 16
3V
20
MΩ
ZID
Differential input impedance
(pin ADx+ to pin ADx-)
CTSD16GAINx = 1, 16
3V
35
MΩ
VI
Absolute input voltage range
AVSS
VCC
V
VIC
Common-mode input voltage
range
AVSS
VCC
V
(1)
(2)
V
All parameters pertain to each CTSD16 input.
The full-scale range is defined by VFSR+ = +VR/GAIN and VFSR- = -VR/GAIN; FSR = VFSR+ - VFSR- = 2xVR/GAIN. If VR is sourced
externally, the analog input range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VR is sourced
internally, the given VID ranges apply.
Table 5-36. CTSD16, Performance
CTSD16OSRx = 256, CTSD164REFS = 1
PARAMETER
fM
TEST CONDITIONS
VCC
MIN
modulator clock
TYP
1.024
CTSD16GAINx = 1, input ADx+
and ADx-(differential)
84
CTSD16GAINx = 2, input ADx+
and ADx- (differential)
SINAD
(1)
Signal-to-noise +
distortion ratio for
differential inputs
MAX
CTSD16GAINx = 4, input ADx+
and ADx- (differential)
UNIT
MHz
87
86
fIN = 50 Hz (1)
3V
85
CTSD16GAINx = 8, input ADx+
and ADx- (differential)
82
CTSD16GAINx = 16, input
ADx+ and ADx- (differential)
77
dB
The following voltages were applied to the CTSD16 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to CTSD16 input range).
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CTSD16, Performance (continued)
CTSD16OSRx = 256, CTSD164REFS = 1
PARAMETER
Signal-to-noise +
distortion ratio for
single-ended input
SINAD
TEST CONDITIONS
VCC
MIN
TYP
CTSD16GAINx = 1, input Ax
(single-ended)
83
CTSD16GAINx = 2, input Ax
(single-ended)
82
CTSD16GAINx = 4, input Ax
(single-ended)
fIN = 50 Hz (1)
3V
78
CTSD16GAINx = 8, input Ax
(single-ended)
72
CTSD16GAINx = 16, input Ax
(single-ended)
66
CTSD16GAINx = 1
Nominal gain
CTSD16GAINx = 4
UNIT
dB
1
CTSD16GAINx = 2
G
MAX
2
3V
4
CTSD16GAINx = 8
8
CTSD16GAINx = 16
16
EG
Gain error
CTSD16GAINx: 1,8,16 with external reference
(1.2 V)
3V
ΔEG/ ΔT
Gain error temperature
coefficient, internal
reference
CTSD16GAINx: 1,8,16.
3V
3
50
ppm/
°C
ΔEG/ ΔT
Gain error temperature
coefficient, external
reference
CTSD16GAIN: 1,8,16 with external reference (1.2
V)
3V
4
15
ppm/
°C
ΔEG/
ΔVCC
Gain error vs VCC
CTSD16GAINx: 1,8,16.
EOS
Offset error
ΔEOS/ΔT
Offset error
temperature coefficient
CTSD16GAINx = 1, 16
3V
±1
ΔEOS/ΔV
CC
Offset error vs VCC
CTSD16GAINx = 1, 16
3V
11
CMRR,50
Hz
Common-mode
rejection ratio at 50 Hz
AC PSRR
DC PSRR
52
AC power supply
rejection ratio
DC power supply
rejection ratio
Specifications
CTSD16GAINx = 1
CTSD16GAINx = 16
CTSD16GAINx = 1,
VID = 928 mV, fIN = 50 Hz
CTSD16GAINx = 16,
VID = 58 mV, fIN = 50 Hz
–1%
+1%
0.02
%/V
±4.1
3V
±3.4
±10
mV
ppm
FSR/
°C
µV/V
78
3V
dB
80
CTSD16GAINx: 1, VCC = 3 V ±50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
95
CTSD16GAINx: 8, VCC = 3 V ±50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
105
CTSD16GAINx: 16, VCC = 3 V ±50 mV × sin(2π
× fVcc × t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
105
CTSD16GAINx: (1, 8, 16), VCC = 2.2 V to 3.6 V,
(PSRR [dB] = –20 log(dVout/dVcc) with dVout
observed as change in the digital conversion
result; assumed to be dominated by reference)
90
dB
dB
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3
-0.2
2.5
Offset Voltage (V)
0
Offset (mV)
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-40
1.5
1
0.5
Gain = 1
Gain = 16
-20
2
0
20
40
60
Temperature (°C)
Average of four typical devices
80
100
0
0.25
0.55
Gain = 1
Figure 5-16. CTSD16 Offset Voltage vs Temperature
0.85 1.2
1.5
1.8
2.1
2.4
2.7
Common-Mode Voltage (V)
OSR = 256
DIfferential Signal = 300
Figure 5-17. CTSD16 Typical Offset Voltage vs Common-Mode
Voltage
90
85
SINAD (dB)
80
75
70
65
60
55
50
10
CTSD16REFS = 1
100
OSR
CTSD16GAINx = 1
1000
Figure 5-18. SINAD Performance vs OSR
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Table 5-37. Built-in Vcc Sense
PARAMETER
VCC,sense
AVCC divider
TEST CONDITIONS
CTSD16ON = 1, CTSD16INCH = 0111
MIN
0.95 ×
(AVCC / 2)
TYP
MAX
AVCC / 2
1.05 ×
(AVCC / 2)
UNIT
V
Table 5-38. Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vsensor
Temperature sensor output
voltage (1) (2)
CTSD16ON = 1, CTSD16INCH = 110,
VCC = 3 V, TA = 30ºC
800
mV
Isensor
Temperature sensor
quiescent current
consumption
CTSD16ON = 1, CTSD16INCH = 110,
TA = 85ºC
2
uA
(1)
(2)
54
The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
Specifications
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5.5.12 REF
Table 5-39. REF and REFBG, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IREFBG
Operating supply current into
AVCC terminal (1)
VCC = 3.0 V, REFON = 1 and REFOUT = 1
VREFBG
Bandgap output voltage
calibrated
VCC = 3.0 V,
VeREF+ ≤ 1.5 V if used
IREF
Operating supply current into
AVCC terminal (1)
VCC = 3.0 V, REFON=1
VREF
REFVSEL = {2} for 2.5 V, REFON = 1
Positive built-in reference voltage
REFVSEL = {1} for 2.0 V, REFON = 1
output
REFVSEL = {0} for 1.5 V, REFON = 1
MIN
1.146
DAC12SREFx=0, REFVSEL = {0} for 1.5 V
2.2
DAC12SREFx=0, REFVSEL = {1} for 2 V
2.3
DAC12SREFx=0, REFVSEL = {2} for 2.5 V
2.8
TYP
MAX
UNIT
110
130
µA
1.16
1.174
V
15
20
µA
2.5
±1%
2.0
±1%
1.5
±1%
V
AVCC(min)
AVCC minimum voltage, Positive
built-in reference active
PSRR_DC
Power supply rejection ratio (DC) VCC = 2.2 V to 3.6 V, TA = 25ºC
50
µV/V
PSRR_AC
Power supply rejection ratio (AC)
VCC = 2.2 V to 3.6 V, TA = 25ºC,
f = 1 kHz, ΔVpp = 100 mV
1.5
mV/V
TCREF+
Bandgap reference temperature
coefficient (2)
IVREF+ = 0 A
15
tSETTLE
Settling time of VREFBG reference
voltage (3)
AVCC = AVCC (min) through AVCC(max),
REFON = 0 → 1
CVREFBG
Capacitance at VREFBG terminal See
ILOAD
VREFBG maximum load current
REFOUT = REFON = 1
IL(VREFBG)
Load-current regulation,
VREFBG terminal (5)
I(VREF+) = +1 mA or –1 mA,
AVCC = AVCC (min),
REFON = REFOUT = 1
(1)
(2)
(3)
(4)
(5)
(4)
V
50 ppm/°C
120
µs
1
nF
1
mA
3.5 mV/mA
The internal reference current is supplied from terminal AVCC. Consumption is independent of the CTSD16ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
There is no capacitance required on VREFBG if the reference voltage is not used externally. However, TI recommends a capacitance
close to the maximum value to reduce any reference voltage noise.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other
external factors.
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5.5.13 DAC
Table 5-40. 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
TEST CONDITIONS
Analog supply voltage
VCC
AVCC = DVCC, AVSS = DVSS = 0 V
DAC12AMPx = 2, DAC12IR = 0,
DAC12OG = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREFBG = 1.16 V
Supply current, single DAC channel (1)
IDD
MIN
(2)
2.2
3V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
2.2 V to
3.6 V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
(1)
(2)
(3)
(4)
Power supply rejection ratio (3)
(4)
MAX
3.6
65
110
125
165
UNIT
V
µA
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
PSRR
TYP
DAC12_xDAT = 800h,
VeREF+ = 1.16 V or 1.5 V,
ΔAVCC = 100 mV
2.2 V to
3.6 V
DAC12_xDAT = 800h,
VeREF+ = 1.16 V or 2.5 V
ΔAVCC = 100 mV
3V
250
350
750
1100
70
dB
70
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications
Table 5-43.
PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT)
The internal reference is not used.
DAC VOUT
DAC Output
VR+
RLoad = ¥
Ideal transfer
function
AVCC
2
CLoad = 100 pF
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 5-19. Linearity Test Load Conditions and Gain/Offset Definition
56
Specifications
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Table 5-41. 12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
Resolution
12-bit monotonic
INL
Integral
nonlinearity (1)
VeREF+ = 1.16 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±2
±4
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±2
±4
DNL
Differential
nonlinearity (1)
VeREF+ = 1.16 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±0.4
±1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±0.4
±1
Without calibration
EO
12
(1) (2)
Offset voltage
With calibration
dE(O)/dT
Offset error
temperature
coefficient (1)
EG
Gain error
dE(G)/dT
Gain temperature
coefficient (1)
tOffset_Cal
Time for offset
calibration (3)
(1) (2)
VeREF+ = 1.16 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±21
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±21
VeREF+ = 1.16 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±1.5
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±1.5
2.2 V, 3 V
VeREF+ = 1.16 V
2.2 V, 3 V
±2.5
VeREF+ = 2.5 V
2.2 V, 3 V
±2.5
2.2 V, 3 V
LSB
±10
µV/°C
%FSR
ppm
of
FSR/
°C
10
165
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
(2)
(3)
LSB
mV
DAC12AMPx = 2
(1)
bits
With calibration
DAC12AMPx = 3, 5
UNIT
66
ms
16.5
Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of
the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may affect accuracy
and is not recommended.
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Table 5-42. 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
Output voltage
range (1) (see
Figure 5-20)
VO
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
TYP
0
0.005
AVCC –
0.05
AVCC
2.2 V, 3.6 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
Maximum DAC12
load capacitance
2.2 V, 3.6 V
IL(DAC12)
DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
Maximum DAC12 VO/P(DAC12) > AVCC – 0.3
load current
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V
2.2 V, 3.6 V
Output resistance RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
(see Figure 5-20) DAC12_xDAT = 0FFFh
0
0.1
AVCC –
0.13
AVCC
100
pF
–1
mA
1
2.2 V, 3.6 V
150
250
150
250
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1)
UNIT
V
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC12)
MAX
Ω
6
Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
ILoad
Max
RLoad
AVCC
DAC12
2
O/P(DAC12_x)
CLoad = 100 pF
Min
0.3
AVCC – 0.3 V
VOUT
AVCC
Figure 5-20. DAC12_x Output Resistance Tests
58
Specifications
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Table 5-43. 12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Reference input
voltage range
VeREF+
Ri(VREFBG),
Ri(VeREF+)
Ri(VREF+),
Ri(VeREF+)
(1)
(2)
(3)
(4)
(5)
(6)
TEST CONDITIONS
DAC12IR = 0 (1)
(2)
DAC12IR = 1 (3)
(4)
VCC
MIN
2.2 V to 3.6 V
DAC12_0 IR = DAC12_1 IR = 0
Reference input
resistance (5)
TYP
MAX
AVCC / 3
AVCC + 0.2
AVCC
AVCC + 0.2
20
DAC12_0 IR = 1, DAC12_1 IR = 0
V
MΩ
52
2.2 V, 3 V
DAC12_0 IR = 0, DAC12_1 IR = 1
UNIT
52
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx (6)
kΩ
26
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be
increased if performance can be maintained.
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
Table 5-44. 12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 5-21 and Figure 5-22), over recommended ranges of supply voltage and operating freeair temperature (unless otherwise noted)
PARAMETER
tON
DAC12 on time
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1)
(see Figure 5-21)
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
Settling time, full scale
DAC12_xDAT =
80h → F7Fh → 80h
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C-C)
Settling time, code to
code
DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12_xDAT =
80h → F7Fh → 80h (2)
Slew rate
2.2 V, 3 V
DAC12_xDAT =
800h → 7FFh → 800h
(1)
(2)
DAC12AMPx = 7
15
30
6
12
100
200
40
80
15
30
UNIT
µs
µs
µs
1
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
Glitch energy
120
2
DAC12AMPx = 4, 6, 7
DAC12AMPx = 3, 5
MAX
60
5
DAC12AMPx = 2
SR
TYP
0.05
0.35
0.35
1.10
1.50
5.20
2.2 V, 3 V
35
V/µs
nV-s
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-21.
Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
VOUT
DAC Output
ILoad
RLoad = 3 kW
Conversion 2
Conversion 3
±1/2 LSB
Glitch
Energy
AVCC
2
RO/P(DAC12.x)
±1/2 LSB
CLoad = 100 pF
tsettleLH
tsettleHL
Figure 5-21. Settling Time and Glitch Energy Testing
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Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRHL
tSRLH
Figure 5-22. Slew Rate Testing
Table 5-45. 12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and TA = 25°C (unless otherwise noted)
PARAMETER
BW–3dB
TEST CONDITIONS
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP
(see Figure 5-23)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
MIN
TYP
MAX
UNIT
40
2.2 V, 3 V
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
kHz
550
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle
Channel-to-channel
crosstalk (1) (see
Figure 5-24)
(1)
VCC
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle
–80
2.2 V, 3 V
dB
–80
RLoad = 3 kΩ, CLoad = 100 pF
RLoad = 3 kW
ILoad
VeREF+
AVCC
DAC12_x
2
DACx
AC
CLoad = 100 pF
DC
Figure 5-23. Test Conditions for 3-dB Bandwidth Specification
RLoad
ILoad
AVCC
DAC12_0
2
DAC0
DAC12_xDAT 080h
F7Fh
080h
F7Fh
080h
VOUT
CLoad = 100 pF
VREF+
VDAC12_yOUT
RLoad
ILoad
AVCC
DAC12_1
VDAC12_xOUT
2
DAC1
1/fToggle
CLoad = 100 pF
Figure 5-24. Crosstalk Test Conditions
60
Specifications
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5.5.14 Operational Amplifier
Table 5-46. Operational Amplifier, OA0, OA1, PGA Buffers
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC
Analog supply
voltage
AVCC = DVCC, AVSS = DVSS = 0 V
2.2
CCPCAP
External charge
pump capacitor to
AVSS.
Required when charge pump is enabled
20
ICP_PEAK
Charge pump peak
current
OARRI = 0h to 1h, ICP_LOAD = 0 μA
ICP
Charge pump
average current
OARRI = 1h, ICP_LOAD = 100 μA
tCP_EN_fast
OARRI = 0h to 1h, ICP_LOAD = 0 μA,
Charge pump enable AFE biases previously enabled and settled
time fast
which can be done with REFON=1 or other
modules requesting REFON.
50
μs
tCP_EN_slow
Charge pump enable OARRI = 0h to 1h, ICP_LOAD = 0 μA,
time slow
Includes AFE bias settling
75
μs
IOA
Supply current, per
opamp
IO = 0 mA,
OARRI = 0h (charge pump disabled)
VOS
Input offset voltage
Noninverting, unity gain
±2
mV
dVOS/dT
Input offset voltage
temperature drift
Noninverting, unity gain
±1
μV/°C
dVOS/dV
Input offset voltage
voltage drift
Noninverting, unity gain
±3
μV/V
Cin
Input capacitance
Differential
4
pF
Common mode
6
pF
PSRR_DC
Power supply
rejection ratio, DC
50
μV/V
VCM
Common mode
voltage range (2)
CMRR_DC
Common mode
rejection ratio, DC
en
Input voltage noise
density
AOL
Open-loop voltage
gain, DC
GBW
Gain-bandwidth
product
SR
22
3.6
V
24
nF
1.6
570 (1)
105 (1)
Noninverting, unity gain,
VINP = positive input of OA = 1 V
mA
710 (1)
μA
130 (1)
μA
OARRI = 0h,
Noninverting, unity gain
0.1
VCC - 1.0
V
OARRI = 1h,
Noninverting, unity gain
0.1
VCC - 0.1
V
Over common-mode voltage range
110
f = 100 Hz, OARRI = 0h or 1h
3.0 V
90
f = 50 kHz, OARRI = 0h or 1h
3.0 V
25
dB
nV/√Hz
95
dB
CL = 100 pF, OAM = 1h
800
kHz
Slew rate
Noninverting, unity gain,
CL = 100 pF, OAM = 1h
0.4
V/μs
tSETTLE
Settling time
Noninverting, unity gain,
2.0-V step, 0.1%, OAM = 1h
5.3
μs
VO
Voltage output swing –250 μA ≤ IO ≤ 250 μA,
from rail
Noninverting, unity gain (OAM = 1h)
(1)
(2)
3.0 V
5
55
mV
Refer to Table 5-47 to calculate total current from OA for different use cases.
The common-mode input range is measured with the OA in a unity-gain source-follower configuration. The input signal is swept from 0 V
to VCC, and the output of the OA is monitored. The minimum and maximum values represent when the input and output differ more than
10 mV, not including the offset, VOS.
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Operational Amplifier, OA0, OA1, PGA Buffers (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
Enable time fast
Noninverting, unity gain,
OAM = 0h transition to 1h,
AFE biases previously enabled and settled
which can be done with REFON=1 or other
modules requesting REFON (3)
tEN_SLOW
Enable time slow
Noninverting,unity gain,
OARRI = 0h transition to 1h,
OAM = 0h transition to 1h,
Includes AFE bias and charge pump
settling (3)
tDIS
Disable time
tEN_FAST
(3)
MIN
TYP
MAX
UNIT
3
7
μs
190
225
μs
μs
0.4
The AFE bias is used by several modules including the OA charge pump, OA, and CTSD16. Any of these modules will request the AFE
bias when enabled. The AFE bias is generated by the REF module, so enabling the REF module also enables the AFE bias.
Table 5-47 explains how to compute the total current, ITOTAL, when the OA and associated modules are used.
Refer to Table 5-33 for a similar table for the CTSD16. A "yes" means it must be included in computing ITOTAL.
As an example, assume that the application uses the CTS16D in rail-to-rail input mode (CTSD16RRI = 1) with
the internal reference (CTSD16REFS = 1) and OA0 and OA1 are enabled in rail-to-rail input modes, OARRI = 1.
The total current, ITOTAL, would be computed as follows:
ITOTAL = ICTSD16 + ICTSD16CLK+ ICP + IREFBG + 2 × IOA
700
160
650
140
600
120
500
Number of Units
Number of Units
550
450
400
350
300
250
100
80
60
200
40
150
100
20
50
0
0
0.4
0.6
0.8
1
1.2
1.5
1.6
1.8
2
2.2
2.4
2.6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Offset Voltage Drift (µV/°C)
Offset Voltage (mV)
Figure 5-25. OA Offset Voltage Sample Production Distribution
Figure 5-26. OA Offset Voltage Drift Sample Production
Distribution
Table 5-47. OA, Current Calculation
USE CASE NAME
USE CASE DETAILS
IOA
ICTSD16CLK
(1)
ICP
(2)
IREF
(3)
OA
OARRI = 0
yes
no
no
yes
OA with rail-to-rail input
OARRI = 1
yes
yes
yes
yes
Rail-to-rail input up, module off
(CTSD16SC = 0) AND
(CTSD16RRI = 1) AND
(CTSD16RRIBURST = 0) OR
((OARRI = 1 (for any OA))
AND (OAM = 0))
no
yes
yes
yes
(1)
(2)
(3)
62
Count this current only once no matter how many modules use it. CTSD16 and the charge pump also use this. This current is listed in
Table 5-32.
Count this current only once no matter how many modules use it. CTSD16 also uses this when rail-to-rail inputs are selected.
Count this current only once no matter how many modules use it. This current is listed in Table 5-46. If IREFBG is used, that includes the
IREF current.
Specifications
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5.5.15 Switches
Table 5-48. Ground Switches (GSW0A, GSW0B, GSW1A, GSW1B)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
TYP
2.2
TA = 0°C to 60°C
ILKG
Input leakage (1)
IIN
Input current switch to AVSS
RON
Switch ON resistance with switch closed
IIN = 100 µA,
TA = –40°C to 85°C
ROFF
Switch OFF resistance with switch open
TA = –40°C to 85°C,
Input signal frequency < 100 Hz
tON/OFF
Enable or disable time
TA = –40°C to 85°C
(1)
MIN
MAX
UNIT
3.6
±0.25
TA = –40°C to 85°C
±50
0
9.5
V
nA
100
µA
18.5
Ω
100
MΩ
0.25
µs
Ground switches are shared with general-purpose I/Os. This leakage includes all leakage seen at the device pin, not only leakage
caused by the switch itself.
Input Leakage Current (nA)
4
3.5
DVCC = 2.2 V
DVCC = 3 V
DVCC = 3.6 V
3
2.5
2
1.5
1
0.5
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Temperature (°C)
Average of three typical devices
Figure 5-27. Ground Switch Input Leakage Current vs Temperature
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Table 5-49. Operational Amplifier Switches
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
Supply voltage
ILKG
Input leakage (1)
IIN
Input current through switch
TEST CONDITIONS
TA = 0°C to 60°C
±0.25
±50
0
Switch ON resistance with switch closed (2)
ROFF
Switch OFF resistance with switch open
TA = –40°C to 85°C,
Input signal frequency < 100 Hz
tON/OFF
Enable or disable time
TA = –40°C to 85°C
UNIT
100
1
100
V
nA
µA
kΩ
MΩ
0.45
µs
This leakage includes all leakage seen at the device pin, not only leakage caused by the switch itself. It assumes a total of five switches
present and a shared digital I/O.
The resistance varies with input voltage range. This resistance represents the peak resistance at the worst case input range (see
Figure 5-29).
DVCC = 2.2 V
DVCC = 2.3 V
DVCC = 3 V
DVCC = 3.6 V
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
1400
Switch ON-Resistance – RON (W)
0.30
Input Leakage Current (nA)
MAX
3.6
TA = –40°C to 85°C
RON
(2)
TYP
2.2
IIN = 100 µA,
TA = –40°C to 85°C
(1)
MIN
1200
1000
800
600
400
200
0
TA = –40°C
TA = 25°C
TA = 85°C
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Temperature (°C)
Average of three typical devices
Common-Mode Voltage (V)
Average of three typical devices
Figure 5-29. OA Switch RON vs Common-Mode Voltage
Figure 5-28. OA Switch Input Leakage Current vs Temperature
64
Specifications
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5.5.16 Comparator
Table 5-50. Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
IAVCC_COMP
CBPWRMD = 00, CBON = 1, CBRSx = 00
Comparator operating
supply current into
AVCC, Excludes
CBPWRMD = 01, CBON = 1, CBRSx = 00
reference resistor ladder
IAVCC_REF
Quiescent current of
resistor ladder into
AVCC, Includes REF
module current
VIC
Common mode input
range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
tPD
tPD,filter
Series input resistance
Propagation delay,
response time
Propagation delay with
filter active
MAX
UNIT
V
40
2.2 V
30
50
3V
40
65
2.2 V,
3V
10
30
CBPWRMD = 10, CBON = 1, CBRSx = 00
2.2 V,
3V
0.5
1.3
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V,
3V
10
22
µA
0
VCC–1
V
CBPWRMD = 00
–20
20
CBPWRMD = 01, 10
–10
10
µA
5
ON (switch closed)
OFF (switch open)
3
mV
pF
4
50
kΩ
MΩ
CBPWRMD = 00, CBF = 0
450
CBPWRMD = 01, CBF = 0
600
CBPWRMD = 10, CBF = 0
50
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.35
0.6
1.5
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
0.6
1.0
1.8
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
1.0
1.8
3.4
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
1.8
3.4
6.5
ns
µs
µs
tEN_CMP
Comparator enable time
CBON = 0 to CBON = 1,
1
2
µs
tEN_REF
Resistor reference
enable time
CBON = 0 to CBON = 1
1.0
1.5
µs
TCCB_REF
Temperature coefficient
of VCB_REF
50
ppm/
°C
VCB_REF
Reference voltage for a
given tap
VIN = reference into resistor ladder, n = 0 to 31
VIN ×
(n+0.5)
/32
VIN ×
(n+1)
/32
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VIN ×
(n+1.5)
/32
Specifications
V
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5.5.17 USB
Table 5-51. Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VUSB = 3.3 V ±10%, IOH = –25 mA
VOL
Low-level output voltage
VUSB = 3.3 V ±10%, IOL = 25 mA
VIH
High-level input voltage
VUSB = 3.3 V ±10%
VIL
Low-level input voltage
VUSB = 3.3 V ±10%
MIN
MAX
2.4
UNIT
V
0.4
2.0
V
V
0.8
V
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
90
VCC = 3.0 V
TA = 25 ºC
IOL - Typical Low-Level Output Current - mA
80
VCC = 3.0 V
TA = 85 ºC
VCC = 1.8 V
TA = 25 ºC
70
60
50
VCC = 1.8 V
TA = 85 ºC
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VOL - Low-Level Output Voltage - V
Figure 5-30. Ports PU.0, PU.1 Typical Low-Level Output Characteristics
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
IOH - Typical High-Level Output Current - mA
-10
-20
-30
VCC = 1.8 V
TA = 85 ºC
-40
-50
VCC = 3.0 V
TA = 85 ºC
-60
VCC = 1.8 V
TA = 25 ºC
-70
VCC = 3.0 V
TA = 25 ºC
-80
-90
0.5
1
1.5
2
2.5
3
VOH - High-Level Output Voltage - V
Figure 5-31. Ports PU.0, PU.1 Typical High-Level Output Characteristics
66
Specifications
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SLAS874 – MAY 2015
TYPICAL PU.0, PU.1 INPUT THRESHOLD
2.0
T A = 25 °C, 85 °C
1.8
VIT+ , postive-going input threshold
Input Threshold - V
1.6
1.4
1.2
VIT- , negative-going input threshold
1.0
0.8
0.6
0.4
0.2
0.0
1.8
2.2
2.6
3
3.4
VUSB Supply Voltage, V USB - V
Figure 5-32. Ports PU.0, PU.1 Typical Input Threshold Characteristics
Table 5-52. USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
D+, D– single ended
USB 2.0 load conditions
VOL
D+, D– single ended
USB 2.0 load conditions
Z(DRV)
D+, D– impedance
Including external series resistor of 27 Ω
tRISE
Rise time
tFALL
Fall time
MIN
MAX
2.8
3.6
UNIT
V
0
0.3
V
28
44
Ω
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
4
20
ns
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
4
20
ns
Table 5-53. USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
MAX
V(CM)
Differential input common mode range
PARAMETER
0.8
2.5
Z(IN)
Input impedance
300
VCRS
Crossover voltage
1.3
VIL
Static SE input logic low level
0.8
VIH
Static SE input logic high level
2.0
V
VDI
Differential input voltage
0.2
V
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UNIT
V
kΩ
2.0
V
V
Specifications
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Table 5-54. USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.75
V
5.5
V
±9%
V
VLAUNCH
VBUS detection threshold
VBUS
USB bus voltage
VUSB
USB LDO output voltage
3.3
V18
Internal USB voltage (1)
1.8
IUSB_EXT
Maximum external current from VUSB terminal (2)
IDET
USB LDO current overload detection (3)
ISUSPEND
Operating supply current into VBUS terminal (4)
CBUS
VBUS terminal recommended capacitance
4.7
µF
CUSB
VUSB terminal recommended capacitance
220
nF
C18
V18 terminal recommended capacitance
220
nF
Normal operation
tENABLE
Settling time VUSB and V18
RPUR
Pullup resistance of PUR terminal
(1)
(2)
(3)
(4)
3.76
USB LDO is on
60
USB LDO is on, USB PLL disabled
Within 2%,
recommended capacitances
70
110
V
12
mA
100
mA
250
µA
2
ms
150
Ω
This voltage is for internal use only. No external DC loading should be applied.
This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
Table 5-55. USB-PLL (USB Phase-Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IPLL
Operating supply current
fPLL
PLL frequency
fUPD
PLL reference frequency
tLOCK
PLL lock time
tJitter
PLL jitter
68
Specifications
MIN
TYP
MAX
7
48
1.5
1000
UNIT
mA
MHz
3
MHz
2
ms
ps
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5.5.18 Flash
Table 5-56. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
11
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
6
11
mA
tCPT
Cumulative program time
See
(1)
16
104
Program and erase endurance
105
ms
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
Block program time for last byte or word
See
(2)
55
73
µs
Erase time for segment, mass erase, and bank erase when
available
See
(2)
23
32
ms
0
1
MHz
tBlock,
tBlock,
tSeg
N
Erase
fMCLK,MGR
(1)
(2)
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the state machine of the flash controller.
5.5.19 Debug and Emulation
Table 5-57. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)
2.2 V, 3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency (4-wire JTAG) (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
VCC
2.2 V
MIN
TYP
15
100
0
5
MHz
10
MHz
80
kΩ
3V
0
2.2 V, 3 V
45
60
µs
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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6 Detailed Description
6.1
Overview
The MSP430FG6626 and MSP430FG6625 are microcontroller configurations with a high-performance 16bit analog-to-digital converter (ADC), dual 12-bit digital-to-analog converters (DACs), dual low-power
operational amplifiers (OAs), a comparator (COMPB), two universal serial communication interfaces
(USCIs), USB 2.0, a hardware multiplier (MPY32), DMA, four 16-bit timers, a real-time clock (RTC)
module with alarm capabilities, an LCD driver, and up to 73 I/O pins.
The MSP430FG6426 and MSP430FG6425 are microcontroller configurations with a high-performance 16bit analog-to-digital converter (ADC), dual 12-bit digital-to-analog converters (DACs), dual low-power
operational amplifiers (OAs), a comparator (COMPB), two universal serial communication interfaces
(USCIs), a 3.3-V LDO, a hardware multiplier (MPY32), DMA, four 16-bit timers, a real-time clock (RTC)
module with alarm capabilities, an LCD driver, and up to 73 I/O pins.
6.2
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
70
Detailed Description
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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6.3
SLAS874 – MAY 2015
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 shows the
address modes.
Table 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
EXAMPLE
Dual operands, source-destination
ADD
Single operands, destination only
R4 + R5 → R5
R8
PC → (TOS), R8 → PC
CALL
Relative jump, un/conditional
OPERATION
R4,R5
JNE
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV &MEM, &TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect auto-increment
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
Detailed Description
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6.4
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Operating Modes
The devices have one active mode and seven software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's DC generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's DC generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's DC generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wake up from RST/NMI, RTC_B, P1, P2, P3, and P4
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake up from RST/NMI, P1, P2, P3, and P4
72
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6.5
SLAS874 – MAY 2015
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up, External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Comp_B
Comparator B interrupt flags (CBIV) (1) (3)
Maskable
0FFF8h
60
Timer TB0
TB0CCR0 CCIFG0
Maskable
0FFF6h
59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TBIV) (1) (3)
Maskable
0FFF4h
58
Watchdog Interval Timer Mode
WDTIFG
Maskable
0FFF2h
57
USCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3)
Maskable
0FFF0h
56
USCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3)
Maskable
0FFEEh
55
Timer TB0
CTSD16
CTSD16IFG0, CTSD16OVIFG0
Maskable
0FFECh
54
TA0CCR0 CCIFG0 (3)
Maskable
0FFEAh
53
Timer TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFE8h
52
USB_UBM (4)
USB interrupts (USBIV) (1) (3)
Maskable
0FFE6h
51
(5)
LDOOFFIG, LDOONIFG, LDOOVLIFG
DMA
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA4IFG, DMA5IFG (DMAIV) (1) (3)
Maskable
0FFE4h
50
Timer TA1
TA1CCR0 CCIFG0 (3)
Maskable
0FFE2h
49
Timer TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
Maskable
0FFE0h
48
P1IFG.0 to P1IFG.7 (P1IV) (1)
I/O Port P1
(3)
Maskable
0FFDEh
47
USCI_A1 Receive or Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3)
Maskable
0FFDCh
46
USCI_B1 Receive or Transmit
UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3)
Maskable
0FFDAh
45
I/O Port P2
(3)
(4)
(5)
(1) (3)
Timer TA0
LDO-PWR
(1)
(2)
(3)
P2IFG.0 to P2IFG.7 (P2IV)
(1) (3)
Maskable
0FFD8h
44
LCD_B
LCD_B Interrupt Flags (LCDBIV) (1)
Maskable
0FFD6h
43
RTC_B
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) (1) (3)
Maskable
0FFD4h
42
DAC12_A
DAC12_0IFG, DAC12_1IFG (1) (3)
Maskable
0FFD2h
41
Timer TA2
TA2CCR0 CCIFG0 (3)
Maskable
0FFD0h
40
Timer TA2
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1) (3)
Maskable
0FFCEh
39
I/O Port P3
P3IFG.0 to P3IFG.7 (P3IV) (1) (3)
Maskable
0FFCCh
38
I/O Port P4
P4IFG.0 to P4IFG.7 (P4IV) (1) (3)
Maskable
0FFCAh
37
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Only on devices with peripheral module USB (MSP430FG6626 and MSP430FG6625)
Only on devices with peripheral module LDO-PWR (MSP430FG6426 and MSP430FG6425)
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Table 6-3. Interrupt Sources, Flags, and Vectors (continued)
(6)
6.6
INTERRUPT SOURCE
INTERRUPT FLAG
Reserved
Reserved (6)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
0FFC8h
36
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
USB BSL
The devices MSP430FG6626 and MSP430FG6625 come pre-programmed with the USB BSL. Use of the
USB BSL requires external access to the six pins shown in Table 6-4. In addition to these pins, the
application must support external components necessary for normal USB operation; for example, the
proper crystal on XT2IN and XT2OUT, proper decoupling, and so on.
Table 6-4. USB BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
PU.0/DP
USB data terminal DP
PU.1/DM
USB data terminal DM
PUR
USB pullup resistor terminal
VBUS
USB bus power supply
VSSU
USB ground supply
NOTE
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is
pulled high externally, then the BSL is invoked. Therefore, unless the application is invoking
the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is
never used. TI recommends applying a 1-MΩ resistor to ground.
6.7
UART BSL
On devices without an USB module (MSP430FG642x) come pre-programmed with the UART BSL. A
UART BSL is also available for devices with the USB module (MSP430FG662x), and it can be
programmed by the user into the BSL memory by replacing the pre-programmed factory-supplied USB
BSL. Use of the UART BSL requires external access to the six pins shown in Table 6-5.
Table 6-5. UART BSL Pin Requirements and Functions
74
Detailed Description
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.1
Data transmit
P1.2
Data receive
VCC
Power supply
VSS
Ground supply
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6.8
6.8.1
SLAS874 – MAY 2015
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used
to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface
with MSP430 development tools and device programmers. The JTAG pin requirements are shown in
Table 6-6. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG
interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
Table 6-6. JTAG Pin Requirements and Functions
6.8.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
The Spy-Bi-Wire interface pin requirements are shown in Table 6-7. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).
For a complete description of the features of the JTAG interface and its implementation, see MSP430
Programming Via the JTAG Interface (SLAU320).
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
6.9
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.
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6.10 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data is lost. Features of the RAM include:
• RAM has n sectors. The size of a sector can be found in Section 6.14.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not
required.
6.11 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.
There are 8 bytes of backup RAM. It can be word-wise accessed through the control registers BAKMEM0,
BAKMEM1, BAKMEM2, and BAKMEM3.
6.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
6.12.1 Digital I/O
There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete except P5.2, and port PJ
contains four individual I/O ports.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise (P1 through P8) in pairs (PA through
PD).
76
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6.12.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2
(see Table 6-8).
Table 6-8. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT
-
Comparator_B output
PM_TB0CLK
Timer TB0 clock input
-
Reserved
-
Reserved
PM_DMAE0
DMAE0 Input
SVM output
1
2
PM_SVMOUT
-
PM_TB0OUTH
Timer TB0 high impedance input TB0OUTH
-
4
PM_TB0CCR0B
Timer TB0 CCR0 capture input CCI0B
Timer TB0: TB0.0 compare output Out0
5
PM_TB0CCR1B
Timer TB0 CCR1 capture input CCI1B
Timer TB0: TB0.1 compare output Out1
6
PM_TB0CCR2B
Timer TB0 CCR2 capture input CCI2B
Timer TB0: TB0.2 compare output Out2
7
PM_TB0CCR3B
Timer TB0 CCR3 capture input CCI3B
Timer TB0: TB0.3 compare output Out3
8
PM_TB0CCR4B
Timer TB0 CCR4 capture input CCI4B
Timer TB0: TB0.4 compare output Out4
9
PM_TB0CCR5B
Timer TB0 CCR5 capture input CCI5B
Timer TB0: TB0.5 compare output Out5
10
PM_TB0CCR6B
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.6 compare output Out6
3
11
12
13
14
15
16
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17
PM_MCLK
-
MCLK
18-30
Reserved
None
DVSS
31 (0FFh) (1)
(1)
OUTPUT PIN FUNCTION
PM_ANALOG
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when
applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read out value of 31.
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Table 6-9. Default Mapping
PIN
PxMAPy
MNEMONIC
P2.0/P2MAP0
PM_UCB0STE,
PM_UCA0CLK
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),
USCI_A0 clock input/output (direction controlled by USCI)
P2.1/P2MAP1
PM_UCB0SIMO,
PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
P2.2/P2MAP2
PM_UCB0SOMI,
PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P2.3/P2MAP3
PM_UCB0CLK,
PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
P2.4/P2MAP4
PM_UCA0TXD,
PM_UCA0SIMO
USCI_A0 UART TXD (direction controlled by USCI - output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
P2.5/P2MAP5/R23
PM_UCA0RXD,
PM_UCA0SOMI
USCI_A0 UART RXD (direction controlled by USCI - input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6/R03
PM_NONE
-
DVSS
P2.7/P2MAP7/LCDREF/R13
PM_NONE
-
DVSS
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
6.12.3 Oscillator and System Clock
The clock system in the MSP430FG662x and MSP430FG642x devices are supported by the Unified Clock
System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1
HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed
low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a highfrequency crystal oscillator XT2. The UCS module is designed to meet the requirements of both low
system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable
multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and
stabilizes in 3 µs (typical). The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally-controlled oscillator (DCO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.12.4 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit provides the proper internal reset signal to the device during power on and power off.
The SVS and SVM circuitry detect if the supply voltage drops below a user-selectable level and supports
both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the
device is not automatically reset). SVS and SVM circuitry is available on the primary supply and the core
supply.
6.12.5 Hardware Multiplier (MPY32)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned
multiplication as well as signed and unsigned multiply-and-accumulate operations.
78
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6.12.6 Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds,
minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal
calendar which compensates for months with less than 31 days and includes leap year correction. The
RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this
device supports operation in LPM3.5 mode and operation from a backup supply.
6.12.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.12.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
and power-up clear handling, NMI source selection and management, reset interrupt vector generators,
bootstrap loader entry mechanisms, and configuration management (device descriptors). SYS also
includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the
application.
Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
INTERRUPT EVENT
WORD ADDRESS
OFFSET
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (BOR)
04h
PMMSWBOR (BOR)
06h
LPM3.5 or LPM4.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
019Eh
PRIORITY
Highest
10h
12h
PMMSWPOR (POR)
14h
WDT time-out (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
Lowest
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Table 6-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
INTERRUPT EVENT
WORD ADDRESS
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
SYSSNIV, System NMI
SYSUNIV, User NMI
VMAIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
019Ah
80
Detailed Description
Highest
06h
08h
Reserved
0Ah to 1Eh
Reserved
Lowest
04h
BUSIFG
USB wait state time-out
Highest
0Ah
JMBINIFG
ACCVIFG
PRIORITY
08h
019Ch
No interrupt pending
SYSBERRIV, Bus Error
OFFSET
Lowest
00h
0198h
02h
Highest
04h to 1Eh
Lowest
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6.12.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in
Table 6-11. The USB timestamp generator is only available on devices with USB module
(MSP430FG662x).
Table 6-11. DMA Trigger Assignments (1)
TRIGGER
CHANNEL
0
1
1
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
7
TBCCR0 CCIFG
8
TBCCR2 CCIFG
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16
UCA0RXIFG
17
UCA0TXIFG
18
UCB0RXIFG
19
UCB0TXIFG
20
UCA1RXIFG
21
UCA1TXIFG
22
UCB1RXIFG
23
UCB1TXIFG
24
CTSD16IFG0
25
DAC12_0IFG
26
DAC12_1IFG
27
USB FNRXD (2)
28
USB ready (2)
30
4
5
DMA3IFG
DMA4IFG
MPY ready
DMA5IFG
31
(2)
3
DMAREQ
29
(1)
2
0
DMA0IFG
DMA1IFG
DMA2IFG
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
Only on devices with peripheral module USB (MSP430FG662x), otherwise reserved
(MSP430FG642x).
Detailed Description
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6.12.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI
module contains two portions, A and B.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.
The MSP430FG662x and MSP430FG642x include two complete USCI modules (n = 0 to 1).
6.12.11 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports
multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-12. Timer TA0 Signal Connections
INPUT PIN NUMBER
PZ
ZQW
DEVICE
INPUT
SIGNAL
34-P1.0
L5-P1.0
TA0CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
34-P1.0
L5-P1.0
TA0CLK
TACLK
35-P1.1
M5-P1.1
TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
TA0
OUTPUT PIN NUMBER
PZ
ZQW
35-P1.1
M5-P1.1
TA0.0
36-P1.2
J6-P1.2
TA0.1
CCI1A
36-P1.2
J6-P1.2
40-P1.6
J7-P1.6
TA0.1
CCI1B
40-P1.6
J7-P1.6
DVSS
GND
CCR1
TA1
TA0.1
DVCC
VCC
37-P1.3
H6-P1.3
TA0.2
CCI2A
37-P1.3
H6-P1.3
41-P1.7
M7-P1.7
TA0.2
CCI2B
41-P1.7
M7-P1.7
DVSS
GND
38-P1.4
M6-P1.4
39-P1.5
L6-P1.5
38-P1.4
39-P1.5
82
MODULE
INPUT
SIGNAL
M6-P1.4
L6-P1.5
Detailed Description
DVCC
VCC
TA0.3
CCI3A
DVSS
CCI3B
DVSS
GND
DVCC
VCC
TA0.4
CCI4A
DVSS
CCI4B
DVSS
GND
DVCC
VCC
CCR2
CCR3
CCR4
TA2
TA3
TA4
TA0.2
TA0.3
TA0.4
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6.12.12 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports
multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-13. Timer TA1 Signal Connections
INPUT PIN NUMBER
PZ
ZQW
DEVICE
INPUT
SIGNAL
42-P3.0
L7-P3.0
TA1CLK
MODULE
INPUT
SIGNAL
TACLK
ACLK
ACLK
SMCLK
SMCLK
42-P3.0
L7-P3.0
TA1CLK
TACLK
43-P3.1
H7-P3.1
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
44-P3.2
45-P3.3
M8-P3.2
L8-P3.3
DVCC
VCC
TA1.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
TA0
TA1
OUTPUT PIN NUMBER
PZ
ZQW
43-P3.1
H7-P3.1
44-P3.2
M8-P3.2
TA1.0
TA1.1
DAC12_A
DAC12_0, DAC12_1
(internal)
45-P3.3
CCR2
TA2
L8-P3.3
TA1.2
Detailed Description
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6.12.13 Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports
multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-14. Timer TA2 Signal Connections
INPUT PIN NUMBER
PZ
ZQW
DEVICE
INPUT
SIGNAL
46-P3.4
J8-P3.4
TA2CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
46-P3.4
J8-P3.4
TA2CLK
TACLK
47-P3.5
M9-P3.5
TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
48-P3.6
49-P3.7
84
MODULE
INPUT
SIGNAL
L9-P3.6
M10-P3.7
Detailed Description
DVCC
VCC
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
CCR2
TA0
TA1
TA2
OUTPUT PIN NUMBER
PZ
ZQW
47-P3.5
M9-P3.5
48-P3.6
L9-P3.6
49-P3.7
M10-P3.7
TA2.0
TA2.1
TA2.2
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6.12.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports
multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-15. Timer TB0 Signal Connections
INPUT PIN NUMBER
PZ
ZQW
58-P8.0
P2MAPx (1)
J11-P8.0
P2MAPx (1)
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
TB0CLK
TB0CLK
ACLK
ACLK
SMCLK
SMCLK
58-P8.0
P2MAPx (1)
J11-P8.0
P2MAPx (1)
TB0CLK
TB0CLK
50-P4.0
J9-P4.0
TB0.0
CCI0A
P2MAPx
(1)
51-P4.1
P2MAPx
(1)
P2MAPx
(1)
M11-P4.1
P2MAPx
(1)
TB0.0
CCI0B
DVSS
GND
DVCC
VCC
TB0.1
CCI1A
TB0.1
CCI1B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
OUTPUT PIN NUMBER
PZ
ZQW
50-P4.0
CCR0
TB0
TB0.0
P2MAPx
(1)
51-P4.1
CCR1
TB1
TB0.1
P2MAPx
(1)
J9-P4.0
P2MAPx (1)
M11-P4.1
P2MAPx (1)
52-P4.2
L10-P4.2
TB0.2
CCI2A
52-P4.2
L10-P4.2
P2MAPx (1)
P2MAPx (1)
TB0.2
CCI2B
P2MAPx (1)
P2MAPx (1)
DVSS
GND
53-P4.3
P2MAPx
(1)
M12-P4.3
P2MAPx
(1)
DVCC
VCC
TB0.3
CCI3A
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
CCR2
TB2
TB0.2
DAC12_A
DAC12_0, DAC12_1
(internal)
53-P4.3
CCR3
TB3
TB0.3
P2MAPx
(1)
M12-P4.3
P2MAPx (1)
54-P4.4
L12-P4.4
TB0.4
CCI4A
54-P4.4
L12-P4.4
P2MAPx (1)
P2MAPx (1)
TB0.4
CCI4B
P2MAPx (1)
P2MAPx (1)
DVSS
GND
DVCC
VCC
CCR4
TB4
TB0.4
55-P4.5
L11-P4.5
TB0.5
CCI5A
55-P4.5
L11-P4.5
P2MAPx (1)
P2MAPx (1)
TB0.5
CCI5B
P2MAPx (1)
P2MAPx (1)
DVSS
GND
CCR5
TB5
TB0.5
DVCC
VCC
56-P4.6
K11-P4.6
TB0.6
CCI6A
56-P4.6
K11-P4.6
P2MAPx (1)
P2MAPx (1)
TB0.6
CCI6B
P2MAPx (1)
P2MAPx (1)
DVSS
GND
DVCC
VCC
(1)
CCR6
TB6
TB0.6
Timer functions are selectable by the port mapping controller.
Detailed Description
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6.12.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.12.16 Signal Chain
All devices include all the building blocks to construct a complete signal chain. These blocks include two
digital-to-analog converter (DAC) channels, two integrated operational amplifiers (OAs), a sigma-delta
analog-to-digital converter (CTSD16), and low-ohmic switches (GSW). Figure 6-1 shows the various signal
chain blocks and their interconnections in the overall system.
86
Detailed Description
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SLAS874 – MAY 2015
NR
device boundary
P5.0/VREFBG/VeREF+
CTSD16
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP0
P5.1/A4/DAC0
P5.6/A5/DAC1
A0
A1
A2
A3
A4
A5
Temp
Sense
REFON
A6
AVCC
Sense
VBAT
Sense
+
A7
CTSD16REFS AND CTD16SC
BUF
Request to
shared reference
-
A8
+
AD0+
AD0-
+
PGA
BUF
-
AD1+
AD1-
OR
+
-
Delta
Sigma
Bandgap voltage
from shared reference
~1.16 V nominal
-
AD2+
AD2AD3+
AD3VREFBG/VeREF+
AD4+
AD4-
DAC0
AD4+
AD4-
VREFBG/VeREF+
OA0
P6.2/CB2/A2/OA0IP0
PSW
4
PSW0
PSW1
PSW2
DAC12_A
DAC12_0
12 bit
DAC12AMP>0 & !DAC12OPS
OAM
PSW3
+
P6.4/CB4/AD0+/OA0O
-
DAC12AMP>0 & DAC12OPS
NSW
5
P2.0/P2MAP0/DAC0
NSW0
NSW1
NSW2
NSW3
P5.1/A4/DAC0
NSW4
P5.6/A5/DAC1
P6.5/CB5/AD0-/OA0IN0
GSW0
P6.6/CB6/AD1+/G0SW0
GSW1
P6.7/CB7/AD1-/G0SW1
PSW
OA1
4
PSW0
PSW1
PSW2
OAM
PSW3
+
P7.4/CB8/AD2+/OA1O
-
DAC12_1
12 bit
DAC12AMP>0 & !DAC12OPS
DAC12AMP>0 & DAC12OPS
NSW
5
NSW0
P2.1/P2MAP1/DAC1
NSW1
NSW2
P6.3/CB3/A3/OA1IP0
NSW3
NSW4
P7.5/CB9/AD2-/OA1IN0
GSW0
P7.6/CB10/AD3+/G1SW0
GSW1
P7.7/CB11/AD3-/G1SW1
device boundary
NOTE: Refer to the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for additional module details.
Figure 6-1. Signal Chain
Detailed Description
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6.12.16.1 CTSD16
The CTSD16 module integrates a single sigma-delta ADC with ten external inputs and four internal inputs.
The converter is designed with a fully differential analog input pair and a programmable gain amplifier
input stage. The converter is based on second-order over-sampling sigma-delta modulators and digital
decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to
256.
The CTSD16 is proceeded by an analog multiplexer which is used for channel selection, followed by a
unity gain buffer stage useful when sampling high impedance sensors.
The CTSD16 can use as its reference the internal bandgap voltage from the REF module or an external
reference at the VeREF+ pin.
6.12.16.2 DAC12_A
The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are
present, they may be grouped together for synchronous operation. There are two complete channels
available, DAC12_0 and DAC12_1.
6.12.16.3 Operational Amplifiers (OA)
The device integrates two low power operational amplifiers. The operational amplifiers can perform signal
conditioning of low-level analog signals before conversion by the ADC. Each operational amplifier can be
individually controlled by software.
6.12.16.4 Ground Switches (GSW)
The device integrates four low-ohmic switches to ground that are individually controllable in software.
These can switch in and out various components in the measurement system.
6.12.17 REF Voltage Reference
The reference module (REF) generates all of the critical reference voltages that can be used by the
various analog peripherals in the device.
6.12.18 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.12.19 LCD_B
The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal
display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information.
Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux
LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its
integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by
software. The module also provides an automatic blinking capability for individual segments.
6.12.20 USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The
module supports full-speed operation of control, interrupt, and bulk transfers. The module includes an
integrated LDO, PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock
frequencies. USB RAM, when not used for USB communication, can be used by the system.
The USB module is only available on the MSP430FG662x devices.
88
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6.12.21 LDO and PU Port
The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire
MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.
Alternatively, the power system can supply power only to other components within the system, or it can be
unused altogether.
The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins can only
be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the
3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally.
The LDO-PWR module (LDO and PU Port) is only available on the MSP430FG6426 and MSP430FG6425
devices.
6.12.22 Embedded Emulation Module (EEM) (L Version)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
• Eight hardware triggers or breakpoints on memory access
• Two hardware triggers or breakpoints on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers or breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
Detailed Description
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6.12.23 Input/Output Schematics
6.12.23.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
S32...S39
LCDS32...LCDS39
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
Module X IN
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
90
Detailed Description
Set
Interrupt
Edge
Select
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Table 6-16. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
P1.0/TA0CLK/ACLK/
S39
0
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
FUNCTION
P1.0 (I/O)
Timer TA0.TA0CLK
1
2
3
4
5
P1.7/TA0.2/S32
(1)
6
7
LCDS32...39
0
0
0
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI0A capture input
0
1
0
Timer TA0.0 output
1
1
0
S38
X
X
1
P1.1 (I/O)
P1.2 (I/O)
I: 0; O: 1
0
0
Timer TA0.CCI1A capture input
0
1
0
Timer TA0.1 output
1
1
0
S37
X
X
1
P1.3 (I/O)
I: 0; O: 1
0
0
Timer TA0.CCI2A capture input
0
1
0
Timer TA0.2 output
1
1
0
P1.4 (I/O)
X
X
1
I: 0; O: 1
0
0
0
1
0
Timer TA0.3 output
1
1
0
S35
X
X
1
I: 0; O: 1
0
0
0
1
0
P1.5 (I/O)
Timer TA0.CCI4A capture input
P1.6/TA0.1/S33
P1SEL.x
S39
Timer TA0.CCI3A capture input
P1.5/TA0.4/S34
P1DIR.x
I: 0; O: 1
ACLK
S36
P1.4/TA0.3/S35
CONTROL BITS OR SIGNALS (1)
Timer TA0.4 output
1
1
0
S34
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI1B capture input
0
1
0
Timer TA0.1 output
1
1
0
S33
X
X
1
P1.6 (I/O)
P1.7 (I/O)
I: 0; O: 1
0
0
Timer TA0.CCI2B capture input
0
1
0
Timer TA0.2 output
1
1
0
S32
X
X
1
X = Don't care
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6.12.23.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
0
Dvss
1
From DAC12_A
2
Pad Logic
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
to LCD_B
from LCD_B
P2REN.x
P2DIR.x
0
P2OUT.x
0
1
1
Direction
0: Input
1: Output
1
From Port Mapping
DAC12AMPx>0
DVSS
DVCC
0
1
DAC12OPS
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
From Port Mapping
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
EN
To Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
92
Detailed Description
Set
Interrupt
Edge
Select
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Table 6-17. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
x
P2.0/P2MAP0/DAC0
0
FUNCTION
P2.0 (I/O)
Mapped secondary digital function
DAC0
P2.1/P2MAP1/DAC1
1
P2.1 (I/O)
Mapped secondary digital function
DAC1
P2.2/P2MAP2
2
P2.2 (I/O)
Mapped secondary digital function
P2.3/P2MAP3
3
P2.3 (I/O)
Mapped secondary digital function
P2.4/P2MAP4/R03
4
P2.4 (I/O)
Mapped secondary digital function
R03
P2.5/P2MAP5
5
P2.5 (I/O
Mapped secondary digital function
P2.6/P2MAP6/LCDREF
/R13
P2.7/P2MAP7/R23
(1)
6
7
P2.6 (I/O)
CONTROL BITS OR SIGNALS (1)
P2DIR.x
P2SEL.x
I: 0; O: 1
0
P2MAPx
X
1
≤ 19
= 31
X
X
I: 0; O: 1
0
X
1
≤ 19
= 31
X
X
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X
1
I: 0; O: 1
0
X
1
DAC12OPS
DAC12AMPx
X
0
X
0
1
>1
X
0
X
0
1
>1
X
0
X
0
X
0
X
0
X
0
≤ 19
X
0
= 31
X
0
X
0
X
0
≤ 19
≤ 19
≤ 19
I: 0; O: 1
0
X
0
Mapped secondary digital function
X
1
≤ 19
X
0
LCDREF/R13
X
1
= 31
X
0
P2.7 (I/O)
I: 0; O: 1
0
X
0
Mapped secondary digital function
X
1
≤ 19
X
0
R23
X
1
= 31
X
0
X = Don't care
Detailed Description
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6.12.23.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
S24...S31
LCDS24...LCDS31
P3REN.x
P3DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3OUT.x
DVSS
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
Module X IN
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
D
P3IE.x
EN
P3IRQ.x
Q
P3IFG.x
P3SEL.x
P3IES.x
94
Detailed Description
Set
Interrupt
Edge
Select
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SLAS874 – MAY 2015
Table 6-18. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
x
P3.0/TA1CLK/CBOUT/S31
0
FUNCTION
P3.0 (I/O)
Timer TA1.TA1CLK
P3.1/TA1.0/S30
1
P3.2/TA1.1/S29
2
P3.3/TA1.2/S28
3
4
5
P3.7/TA2.2/S24
(1)
6
7
LCDS24...31
0
0
0
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer TA1.CCI0A capture input
0
1
0
Timer TA1.0 output
1
1
0
S30
X
X
1
P3.1 (I/O)
P3.2 (I/O)
I: 0; O: 1
0
0
Timer TA1.CCI1A capture input
0
1
0
Timer TA1.1 output
1
1
0
S29
X
X
1
P3.3 (I/O)
I: 0; O: 1
0
0
Timer TA1.CCI2A capture input
0
1
0
Timer TA1.2 output
1
1
0
P3.4 (I/O)
X
X
1
I: 0; O: 1
0
0
0
1
0
SMCLK
1
1
0
S27
X
X
1
I: 0; O: 1
0
0
0
1
0
P3.5 (I/O)
Timer TA2.CCI0A capture input
P3.6/TA2.1/S25
P3SEL.x
S31
Timer TA2.TA2CLK
P3.5/TA2.0/S26
P3DIR.x
I: 0; O: 1
CBOUT
S28
P3.4/TA2CLK/SMCLK/S27
CONTROL BITS OR SIGNALS (1)
Timer TA2.0 output
1
1
0
S26
X
X
1
I: 0; O: 1
0
0
Timer TA2.CCI1A capture input
0
1
0
Timer TA2.1 output
1
1
1
S25
X
X
1
P3.6 (I/O)
P3.7 (I/O)
I: 0; O: 1
0
0
Timer TA2.CCI2A capture input
0
1
0
Timer TA2.2 output
1
1
0
S24
X
X
1
X = Don't care
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6.12.23.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
S16...S23
LCDS16...LCDS23
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
Bus
Keeper
EN
Module X IN
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
P4.7/TB0OUTH/SVMOUT/S16
D
P4IE.x
EN
P4IRQ.x
Q
P4IFG.x
P4SEL.x
P4IES.x
96
Detailed Description
Set
Interrupt
Edge
Select
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Table 6-19. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
P4.0/TB0.0/S23
x
0
FUNCTION
P4.0 (I/O)
Timer TB0.CCI0A capture input
Timer TB0.0 output
(2)
P4.2/TB0.2/S21
P4.3/TB0.3/S20
1
2
3
4
1
0
0
Timer TB0.CCI1A capture input
0
1
0
Timer TB0.1 output (2)
1
1
0
S22
X
X
1
P4.2 (I/O)
I: 0; O: 1
0
0
Timer TB0.CCI2A capture input
0
1
0
Timer TB0.2 output (2)
1
1
0
S21
X
X
1
P4.3 (I/O)
I: 0; O: 1
0
0
Timer TB0.CCI3A capture input
0
1
0
Timer TB0.3 output (2)
1
1
0
P4.4 (I/O)
(2)
P4.5 (I/O)
Timer TB0.5 output
(2)
(1)
(2)
7
X
X
1
I: 0; O: 1
0
0
0
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer TB0.CCI6A capture input
0
1
0
Timer TB0.6 output (2)
1
1
0
S17
X
X
1
S18
P4.7/TB0OUTH/
SVMOUT/S16
0
I: 0; O: 1
P4.1 (I/O)
Timer TB0.CCI5A capture input
6
1
0
S19
P4.6/TB0.6/S17
0
0
1
Timer TB0.4 output
5
LCDS16...23
0
X
Timer TB0.CCI4A capture input
P4.5/TB0.5/S18
P4SEL.x
1
S20
P4.4/TB0.4/S19
P4DIR.x
I: 0; O: 1
X
S23
P4.1/TB0.1/S22
CONTROL BITS OR SIGNALS (1)
P4.6 (I/O)
P4.7 (I/O)
I: 0; O: 1
0
0
Timer TB0.TB0OUTH
0
1
0
SVMOUT
1
1
0
S16
X
X
1
X = Don't care
Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.
Detailed Description
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6.12.23.5 Port P5, P5.0, Input/Output With Schmitt Trigger
Pad Logic
To/From
Reference
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
Module X OUT
1
P5.0/VREFBG/VeREF+
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Table 6-20. Port P5 (P5.0) Pin Functions
PIN NAME (P5.x)
P5.0/VREFBG/VeR
EF+
(1)
(2)
(3)
(4)
(5)
(6)
98
x
FUNCTION
0 P5.0 (I/O)
(4)
CONTROL BITS OR SIGNALS (1)
P5DIR.x
P5SEL.x
REFOUT
REFON (2)
CTSD16REFS (3)
I: 0; O: 1
0
X
X
X
VeREF+ (5)
X
1
0
X
0
VREFBG (6)
X
1
1
1
1
X = Don't care
If a module is requesting a reference then REFON need not be set to 1 for VREFBG to be selected on P5.0.
If CTSD16 is active, this bit must be set as shown in the table. Otherwise if set to 1, it will force VREFBG to be selected regardless of
REFOUT setting and if P5SEL.x is set to 0 it will cause possible contention on the I/O.
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF+ and used as the reference for the CTSD16 or DAC.
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The internal reference voltage signal, VREFBG, is available at the pin.
Detailed Description
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6.12.23.6 Port P5, P5.1 and P5.6, Input/Output With Schmitt Trigger
0
Dvss
1
From DAC12_A
2
Pad Logic
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
To ADC
INCHx = y
DAC12AMPx>0
DAC12OPS
P5REN.x
DVSS
0
DVCC
1
1
P5DIR.x
P5OUT.x
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5.1/A4/DAC0
P5.6/A5/DAC1
P5IN.x
Bus
Keeper
Detailed Description
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Table 6-21. Port P5 (P5.1 and P5.6) Pin Functions
PIN NAME (P6.x)
P5.1/A4/DAC0
x
FUNCTION
P5DIR.x
P5SEL.x
DAC12OPS
DAC12AMPx
I: 0; O: 1
0
X
0
X
1
X
0
DAC0
X
X
0
>1
1 P5.6(I/O)
I: 0; O: 1
0
X
0
X
1
X
0
X
X
0
>1
1 P5.1(I/O)
A4 (2)
P5.6/A5/DAC1
A5 (2)
(3)
(3)
DAC1
(1)
(2)
(3)
100
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.12.23.7 Port P5, P5.3 to P5.5, P5.7, Input/Output With Schmitt Trigger
Pad Logic
S40...S42
LCDS40...LCDS42
P5REN.x
P5DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5OUT.x
DVSS
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P5.7/DMAE0/RTCCLK
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Table 6-22. Port P5 (P5.3 to P5.5, P5.7) Pin Functions
PIN NAME (P5.x)
P5.3/COM1/S42
x
3
FUNCTION
P5.3 (I/O)
COM1
S42
P5.4/COM2/S41
4
P5.4 (I/O)
COM2
S41
P5.5/COM3/S40
P5.7/DMAE0/RTCCLK
(1)
5
7
CONTROL BITS OR SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
LCDS40...42
0
X
1
X
1
X
0
I: 0; O: 1
0
0
X
1
X
1
X
0
I: 0; O: 1
0
0
COM3
X
1
X
S40
X
0
1
P5.5 (I/O)
P5.7 (I/O)
I: 0; O: 1
0
na
DMAE0
0
1
na
RTCCLK
1
1
na
X = Don't care
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6.12.23.8 Port P6, P6.0 to P6.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6.0/CB0/A0
P6.1/CB1/A1
P6IN.x
Bus
Keeper
102
Detailed Description
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SLAS874 – MAY 2015
Table 6-23. Port P6 (P6.0 to P6.1) Pin Functions
PIN NAME (P6.x)
P6.0/CB0/A0
x
0
FUNCTION
P6.0 (I/O)
CB0
A0
P6.1/CB1/A1
1
(2) (3)
P6.1 (I/O)
CB1
A1
(1)
(2)
(3)
(2) (3)
CONTROL BITS OR SIGNALS (1)
P6DIR.x
P6SEL.x
CBPD.x
I: 0; O: 1
0
0
X
X
1
X
1
X
I: 0; O: 1
0
0
X
X
1
X
1
X
X = Don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.12.23.9 Port P6, P6.2 to P6.3, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP1
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OAx
-
104
Detailed Description
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SLAS874 – MAY 2015
Table 6-24. Port P6 (P6.2 to P6.3) Pin Functions
PIN NAME (P6.x)
P6.2/CB2/A2/OA0IP0
x
2
FUNCTION
P6SEL.x (2)
CBPD.x (2)
I: 0; O: 1
0
0
X
X
1
(3)
X
1
X
OA0IP0 (2)
X
1
X
P6.2 (I/O)
I: 0; O: 1
0
0
P6.2 (I/O)
CB2
A2
P6.3/CB3/A3/OA1IP0
3
CB3
(3)
(4)
P6DIR.x
X
X
1
(4)
X
1
X
OA1IP0 (2)
X
1
X
A3
(1)
(2)
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.12.23.10 Port P6, P6.4, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
OAMx
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.4/CB4/AD0+/OA0O
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
106
Detailed Description
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SLAS874 – MAY 2015
Table 6-25. Port P6 (P6.4) Pin Functions
PIN NAME (P6.x)
P6.4/CB4/AD0+/OA0O
x
4
FUNCTION
P6.4 (I/O)
CB4
AD0+
(4)
OA0O
(1)
(2)
(3)
(4)
CONTROL BITS OR SIGNALS (1)
P6DIR.x
P6SEL.x (2)
CBPD.x (2)
OAMx
I: 0; O: 1
0
0
0 (3)
X
X
1
0 (3)
X
1
X
0 (3)
X
X
X
= 1 (3)
X = Don't care
Setting the P6SEL.x bit, the CBPD.x bit, or the OAMx bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
Setting OAMx = 0 disables the operational amplifier and its output is high impedance. Setting OAMx = 1 enables the operational
amplifier output. Because the operational amplifier output is shared with the ADC channel, selection of the respective ADC channel
allows for direct measurement of the amplifier's output voltage.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.12.23.11 Port P6, P6.5, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.5/CB5/AD0-/OA0IN0
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
108
Detailed Description
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Table 6-26. Port P6 (P6.5) Pin Functions
PIN NAME (P6.x)
x
P6.5/CB5/AD0-/OA0IN0
5
FUNCTION
P6.5 (I/O)
CB5
AD0-
(3)
OA0IN0 (4)
(1)
(2)
(3)
(4)
CONTROL BITS OR SIGNALS (1)
P6SEL.x (2)
CBPD.x (2)
I: 0; O: 1
0
0
X
X
1
X
1
X
X
1
X
P6DIR.x
X = Don't care
Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
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6.12.23.12 Port P6, P6.6, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW0
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.6/CB6/AD1+/G0SW0
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
GSW0
GSW1
to P6.7
110
Detailed Description
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SLAS874 – MAY 2015
Table 6-27. Port P6 (P6.6) Pin Functions
PIN NAME (P6.x)
x
P6.6/CB6/AD1+/G0SW0
6
FUNCTION
P6.6 (I/O)
CB6
AD1+
(3)
G0SW0 (4)
(1)
(2)
(3)
(4)
CONTROL BITS OR SIGNALS (1)
P6SEL.x (2)
CBPD.x (2)
GSW0 (2)
I: 0; O: 1
0
0
0
X
X
1
0
X
1
X
0
X
X
X
1
P6DIR.x
X = Don't care
Setting the P6SEL.x bit, the CBPD.x bit, or the GSW0 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting GSW0 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so different
settings can impose different voltages on the pin. Application must ensure there are no conflicts.
Detailed Description
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6.12.23.13 Port P6, P6.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW1
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.7/CB7/AD1-/G0SW1
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
GSW0
to P6.6
GSW1
112
Detailed Description
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SLAS874 – MAY 2015
Table 6-28. Port P6 (P6.7) Pin Functions
PIN NAME (P6.x)
x
P6.7/CB7/AD1-/G0SW1
7
FUNCTION
P6.7 (I/O)
CB7
AD1-
(3)
G0SW1 (4)
(1)
(2)
(3)
(4)
CONTROL BITS OR SIGNALS (1)
P6SEL.x (2)
CBPD.x (2)
GSW1 (2)
I: 0; O: 1
0
0
0
X
X
1
0
X
1
X
0
X
X
X
1
P6DIR.x
X = Don't care
Setting the P6SEL.x bit, the CBPD.x bit, or the GSW0 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting GSW1 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so different
settings can impose different voltages on the pin. Application must ensure there are no conflicts.
Detailed Description
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6.12.23.14 Port P7, P7.2, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P7REN.2
P7DIR.2
DVSS
0
DVCC
1
1
0
1
P7OUT.2
P7DS.2
0: Low drive
1: High drive
P7SEL.2
P7.2/XT2IN
P7IN.2
Bus
Keeper
114
Detailed Description
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6.12.23.15 Port P7, P7.3, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P7REN.3
P7DIR.3
DVSS
0
DVCC
1
1
0
1
P7OUT.3
P7SEL.2
P7.3/XT2OUT
P7DS.3
0: Low drive
1: High drive
XT2BYPASS
P7SEL.3
P7IN.3
Bus
Keeper
Table 6-29. Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P7.x)
P7.2/XT2IN
x
2
FUNCTION
P7.2 (I/O)
XT2IN crystal mode (2)
XT2IN bypass mode
P7.3/XT2OUT
3
(2)
P7.3 (I/O)
XT2OUT crystal mode (3)
P7.3 (I/O)
(1)
(2)
(3)
(3)
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.2
P7SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
X = Don't care
Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.
Detailed Description
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6.12.23.16 Port P7, P7.4, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
OAMx
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.4/CB8/AD2+/OA1O
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
116
Detailed Description
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SLAS874 – MAY 2015
Table 6-30. Port P7 (P7.4) Pin Functions
PIN NAME (P6.x)
x
P7.4/CB8/AD2+/OA1O
4
FUNCTION
P7.4 (I/O)
CB8
AD2+
OA1O
(1)
(2)
(3)
(4)
(4)
CONTROL BITS OR SIGNALS (1)
P6DIR.x
P7SEL.x (2)
CBPD.x (2)
OAMx (2)
I: 0; O: 1
0
0
0 (3)
X
X
1
0 (3)
X
1
X
0 (3)
X
X
X
1 (3)
X = Don't care
Setting the P6SEL.x bit, the CBPD.x bit, or the OAMx bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
Setting OAMx = 0 disables the operational amplifier and its output is high impedance. Setting OAMx = 1 enables the operational
amplifier output. Because the operational amplifier output is shared with the ADC channel, selection of the respective ADC channel
allows for direct measurement of the amplifier's output voltage.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.12.23.17 Port P7, P7.5, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.5/CB9/AD2-/OA1IN0
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
118
Detailed Description
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SLAS874 – MAY 2015
Table 6-31. Port P7 (P7.5) Pin Functions
PIN NAME (P7.x)
P7.5/CB9/AD2-/OAIN0
x
5
FUNCTION
P7.5 (I/O)
CB9
AD2-
(3)
OAIN0 (2)
(1)
(2)
(3)
CONTROL BITS OR SIGNALS (1)
P7SEL.x (2)
CBPD.x (2)
I: 0; O: 1
0
0
X
X
1
X
1
X
X
1
X
P7DIR.x
X = Don't care
Setting the P7SEL.x bit or the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.12.23.18 Port P7, P7.6, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW0
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.6/CB10/AD3+/G1SW0
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
GSW0
GSW1
to P7.7
120
Detailed Description
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SLAS874 – MAY 2015
Table 6-32. Port P7 (P7.6) Pin Functions
PIN NAME (P7.x)
x
P7.6/CB10/AD3+/G1SW0
6
FUNCTION
P7.6 (I/O)
CB10
AD3+
(3)
G1SW0 (4)
(1)
(2)
(3)
(4)
CONTROL BITS OR SIGNALS (1)
P7SEL.x (2)
CBPD.x (2)
GSW0 (2)
I: 0; O: 1
0
0
0
X
X
1
0
X
1
X
0
X
X
X
1
P6DIR.x
X = Don't care
Setting the P7SEL.x bit, the CBPD.x bit, or the GSW0 disables the output driver and the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting GSW0 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so different
settings can impose different voltages on the pin. Application must ensure there are no conflicts.
Detailed Description
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6.12.23.19 Port P7, P7.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW1
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.7/CB11/AD3-/G1SW1
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
GSW0
to P7.6
GSW1
122
Detailed Description
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SLAS874 – MAY 2015
Table 6-33. Port P7 (P7.7) Pin Functions
PIN NAME (P7.x)
x
P7.7/CB11/AD3-/G1SW1
7
FUNCTION
P7.7 (I/O)
CB11
AD3-
(3)
G1SW1 (4)
(1)
(2)
(3)
(4)
CONTROL BITS OR SIGNALS (1)
P7SEL.x (2)
CBPD.x (2)
GSW1 (2)
I: 0; O: 1
0
0
0
X
X
1
0
X
1
X
0
X
X
X
1
P6DIR.x
X = Don't care
Setting the P7SEL.x bit, the CBPD.x bit, or the GSW1 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting GSW1 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so different
settings can impose different voltages on the pin. Application must ensure there are no conflicts.
Detailed Description
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6.12.23.20 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
Pad Logic
S8...S15
LCDS8...LCDS15
P8REN.x
P8DIR.x
0
From module
1
P8OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Bus
Keeper
P8.0/TB0CLK/S15
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO//UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
D
Module X IN
124
1
Detailed Description
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SLAS874 – MAY 2015
Table 6-34. Port P8 (P8.0 to P8.7) Pin Functions
PIN NAME (P9.x)
P8.0/TB0CLK/S15
x
0
FUNCTION
P8.0 (I/O)
Timer TB0.TB0CLK clock input
S15
P8.1/UCB1STE/UCA1CLK/S14
1
P8.1 (I/O)
UCB1STE/UCA1CLK
S14
P8.2/UCA1TXD/UCA1SIMO/S13
2
P8.2 (I/O)
UCA1TXD/UCA1SIMO
S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO/UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
3
4
5
6
7
P8DIR.x
P8SEL.x
LCDS8...16
I: 0; O: 1
0
0
0
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
UCA1RXD/UCA1SOMI
X
1
0
S12
X
X
1
P8.3 (I/O)
P8.4 (I/O)
I: 0; O: 1
0
0
UCB1CLK/UCA1STE
X
1
0
S11
X
X
1
P8.5 (I/O)
I: 0; O: 1
0
0
UCB1SIMO/UCB1SDA
X
1
0
S10
X
X
1
P8.6 (I/O)
I: 0; O: 1
0
0
UCB1SOMI/UCB1SCL
X
1
0
S9
X
X
1
I: 0; O: 1
0
0
X
X
1
P8.7 (I/O)
S8
(1)
CONTROL BITS OR SIGNALS (1)
X = Don't care
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6.12.23.21 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Pad Logic
S0...S7
LCDS0...LCDS7
P9REN.x
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P9DIR.x
P9OUT.x
P9.0/S7
P9.1/S6
P9.2/S5
P9.3/S4
P9.4/S3
P9.5/S2
P9.6/S1
P9.7/S0
P9DS.x
0: Low drive
1: High drive
P9IN.x
Bus
Keeper
Table 6-35. Port P9 (P9.0 to P9.7) Pin Functions
PIN NAME (P9.x)
P9.0/S7
x
0
FUNCTION
P9.0 (I/O)
S7
P9.1/S6
1
P9.1 (I/O)
S6
P9.2/S5
2
P9.2 (I/O)
S5
P9.3/S4
3
P9.4/S3
4
P9.3 (I/O)
S4
P9.4 (I/O)
S3
P9.5/S2
5
P9.5 (I/O)
S2
P9.6/S1
6
P9.6 (I/O)
S1
P9.7/S0
7
P9.7 (I/O)
S0
(1)
126
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
LCDS0...7
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = Don't care
Detailed Description
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SLAS874 – MAY 2015
6.12.23.22 Port PU.0/DP, PU.1/DM, PUR USB Ports for MSP430FG662x
PUSEL
PUOPE
USB output enable
PUOUT0
USB DP output
VUSB
VSSU
Pad Logic
0
1
0
PU.0/
DP
1
PUIN0
USB DP input
PUIPE
.
PUIN1
USB DM input
PUOUT1
0
USB DM output
1
PU.1/
DM
VUSB
VSSU
Pad Logic
PUREN
PUR
“1”
PUSEL
PURIN
Table 6-36. Port PU.0/DP, PU.1/DM Output Functions for MSP430FG662x
CONTROL BITS
PIN NAME
FUNCTION
PUSEL
PUDIR
PUOUT1
PUOUT0
PU.1/DM
PU.0/DP
0
0
X
X
Hi-Z
Hi-Z
Outputs off
0
1
0
0
0
0
Outputs enabled
0
1
0
1
0
1
Outputs enabled
0
1
1
0
1
0
Outputs enabled
0
1
1
1
1
1
Outputs enabled
1
X
X
X
DM
DP
Direction set by USB module
Detailed Description
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Table 6-37. Port PUR Input Functions
CONTROL BITS
128
Detailed Description
FUNCTION
PUSEL
PUREN
0
0
Input disabled
Pullup disabled
0
1
Input disabled
Pullup enabled
1
0
Input enabled
Pullup disabled
1
1
Input enabled
Pullup enabled
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6.12.23.23 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
6.12.23.24 Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.x
0: Low drive
1: High drive
From JTAG
1
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
To JTAG
D
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Table 6-38. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS OR
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
PJ.0 (I/O) (2)
I: 0; O: 1
TDO (3)
PJ.1/TDI/TCLK
1
X
PJ.1 (I/O) (2)
TDI/TCLK (3)
PJ.2/TMS
2
PJ.2 (I/O)
TMS (3)
PJ.3/TCK
3
130
(4)
X
(2)
I: 0; O: 1
(4)
X
PJ.3 (I/O) (2)
TCK (3)
(1)
(2)
(3)
(4)
I: 0; O: 1
I: 0; O: 1
(4)
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Detailed Description
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6.13 Device Descriptors
Table 6-39 summarizes the contents of the device descriptor tag-length-value (TLV) structure.
Table 6-39. Device Descriptor Table
Info Block
Die Record
CTSD16 Calibration
VALUE
DESCRIPTION
ADDRESS
SIZE
(bytes)
FG6626
FG6625
FG6426
FG6425
Info length
01A00h
1
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
Device ID
01A04h
2
8234h
8235h
8236h
8237h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
CTSD16 Calibration Tag
01A14h
1
1Dh
1Dh
1Dh
1Dh
CTSD16 Calibration length
01A15h
1
0Ch
0Ch
0Ch
0Ch
CTSD16 gain factor gain=1
01A16h
2
per unit
per unit
per unit
per unit
CTSD16 gain factor gain=16
01A18h
2
per unit
per unit
per unit
per unit
CTSD16 offset gain=1
01A1Ah
2
per unit
per unit
per unit
per unit
CTSD16 offset gain=16
01A1Ch
2
per unit
per unit
per unit
per unit
CTSD16 Internal Reference
Temp. Sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
CTSD16 Internal Reference
Temp. Sensor 85°C
01A20h
2
per unit
per unit
per unit
per unit
Detailed Description
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6.14 Memory
Table 6-40 summarizes the memory organization for all devices.
Table 6-40. Memory Organization (1) (2)
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
Total Size
128KB
00FFFFh–00FF80h
64KB
00FFFFh–00FF80h
128KB
00FFFFh–00FF80h
64KB
00FFFFh–00FF80h
Bank 3
32KB
0243FFH-01C400h
NA
32KB
0243FFH-01C400h
NA
Bank 2
32KB
01C3FFh-014400h
NA
32KB
01C3FFh-014400h
NA
Bank 1
32KB
0143FFh-00C400h
32KB
0143FFh-00C400h
32KB
0143FFh-00C400h
32KB
0143FFh-00C400h
Bank 0
32KB
00C3FFh-004400h
32KB
00C3FFh-004400h
32KB
00C3FFh-004400h
32KB
00C3FFh-004400h
Sector 3
2KB
0043FFh–003C00h
2KB
0043FFh–003C00h
2KB
0043FFh–003C00h
2KB
0043FFh–003C00h
Sector 2
2KB
003BFFh–003400h
2KB
003BFFh–003400h
2KB
003BFFh–003400h
2KB
003BFFh–003400h
Sector 1
2KB
0033FFh–002C00h
2KB
0033FFh–002C00h
2KB
0033FFh–002C00h
2KB
0033FFh–002C00h
Sector 0
2KB
002BFFh–002400h
2KB
002BFFh–002400h
2KB
002BFFh–002400h
2KB
002BFFh–002400h
RAM (3)
Sector 7
NA
NA
2 KB
0023FFh-001C00h
2KB
0023FFh-001C00h
USB RAM (4)
Sector 7
2KB
0023FFh-001C00h
2KB
0023FFh-001C00h
NA
NA
A
128 B
001BFFh–001B80h
128 B
001BFFh–001B80h
128 B
001BFFh–001B80h
128 B
001BFFh–001B80h
B
128 B
001B7Fh–001B00h
128 B
001B7Fh–001B00h
128 B
001B7Fh–001B00h
128 B
001B7Fh–001B00h
C
128 B
001AFFh–001A80h
128 B
001AFFh–001A80h
128 B
001AFFh–001A80h
128 B
001AFFh–001A80h
D
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
Info A
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
Size
4 KB
000FFFh–000000h
4KB
000FFFh–000000h
4KB
000FFFh–000000h
4KB
000FFFh–000000h
Memory (flash)
Main: interrupt vector
Main: code memory
RAM
TI factory memory
(ROM)
Information memory
(flash)
Bootstrap loader
(BSL) memory (flash)
Peripherals
(1)
(2)
(3)
(4)
132
N/A = Not available.
Backup RAM is accessed through the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
Only available on FG642x.
Only available on FG662x. USB RAM can be used as general-purpose RAM when not used for USB operation.
Detailed Description
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6.14.1 Peripheral File Map
Table 6-41 lists all of the the available peripherals and their base addresses. Table 6-42 through Table 678 list the registers and their offset addresses for each peripheral.
Table 6-41. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS RANGE (1)
Special Functions (see Table 6-42)
0100h
000h-01Fh
PMM (see Table 6-43)
0120h
000h-010h
Flash Control (see Table 6-44)
0140h
000h-00Fh
CRC16 (see Table 6-45)
0150h
000h-007h
RAM Control (see Table 6-46)
0158h
000h-001h
Watchdog (see Table 6-47)
015Ch
000h-001h
UCS (see Table 6-48)
0160h
000h-01Fh
SYS (see Table 6-49)
0180h
000h-01Fh
Shared Reference (see Table 6-50)
01B0h
000h-001h
000h-003h
Port Mapping Control (see Table 6-51)
01C0h
Port Mapping Port P2 (see Table 6-51)
01D0h
000h-007h
Port P1, P2 (see Table 6-52)
0200h
000h-01Fh
Port P3, P4 (see Table 6-53)
0220h
000h-01Fh
Port P5, P6 (see Table 6-54)
0240h
000h-00Bh
Port P7, P8 (see Table 6-55)
0260h
000h-00Bh
Port P9 (see Table 6-56)
0280h
000h-00Bh
Port PJ (see Table 6-57)
0320h
000h-01Fh
Timer TA0 (see Table 6-58)
0340h
000h-02Eh
Timer TA1 (see Table 6-59)
0380h
000h-02Eh
Timer TB0 (see Table 6-60)
03C0h
000h-02Eh
Timer TA2 (see Table 6-61)
0400h
000h-02Eh
Battery Backup (see Table 6-62)
0480h
000h-01Fh
RTC_B (see Table 6-63)
04A0h
000h-01Fh
32-Bit Hardware Multiplier (see Table 6-64)
04C0h
000h-02Fh
DMA General Control (see Table 6-65)
0500h
000h-00Fh
DMA Channel 0 (see Table 6-65)
0510h
000h-00Ah
DMA Channel 1 (see Table 6-65)
0520h
000h-00Ah
DMA Channel 2 (see Table 6-65)
0530h
000h-00Ah
DMA Channel 3 (see Table 6-65)
0540h
000h-00Ah
DMA Channel 4 (see Table 6-65)
0550h
000h-00Ah
DMA Channel 5 (see Table 6-65)
0560h
000h-00Ah
USCI_A0 (see Table 6-66)
05C0h
000h-01Fh
USCI_B0 (see Table 6-67)
05E0h
000h-01Fh
USCI_A1 (see Table 6-68)
0600h
000h-01Fh
USCI_B1 (see Table 6-69)
0620h
000h-01Fh
DAC12_A (see Table 6-70)
0780h
000h-01Fh
Comparator_B (see Table 6-71)
08C0h
000h-00Fh
USB configuration (see Table 6-72) (2)
0900h
000h-014h
USB control (see Table 6-73) (2)
0920h
000h-01Fh
0900h
000h-014h
LDO-PWR; LDO and Port U configuration (see Table 6-74)
(1)
(2)
(3)
(3)
For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Only on devices with peripheral module USB.
Only on devices with peripheral module LDO-PWR.
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Table 6-41. Peripherals (continued)
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS RANGE (1)
LCD_B control (see Table 6-75)
0A00h
000h-05Fh
CTSD16 (see Table 6-76)
0A80h
000h-05Fh
OA0 and GSW0 (see Table 6-77)
0AE0h
000h-00Fh
OA1 and GSW1 (see Table 6-78)
0AF0h
000h-00Fh
Table 6-42. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-43. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 6-44. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-45. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC result
CRC16INIRES
04h
Table 6-46. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-47. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-48. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
134
Detailed Description
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Table 6-48. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
Table 6-49. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootstrap loader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-50. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 6-51. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password register
PMAPPWD
00h
Port mapping control register
PMAPCTL
02h
Port P2.0 mapping register
P2MAP0
00h
Port P2.1 mapping register
P2MAP1
01h
Port P2.2 mapping register
P2MAP2
02h
Port P2.3 mapping register
P2MAP3
03h
Port P2.4 mapping register
P2MAP4
04h
Port P2.5 mapping register
P2MAP5
05h
Port P2.6 mapping register
P2MAP6
06h
Port P2.7 mapping register
P2MAP7
07h
Table 6-52. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
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Table 6-52. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-53. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P3 interrupt vector word
P3IV
0Eh
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt flag
P3IFG
1Ch
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt flag
P4IFG
1Dh
Table 6-54. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
136
Detailed Description
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Table 6-54. Port P5, P6 Registers (Base Address: 0240h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 6-55. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup/pulldown enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pullup/pulldown enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Table 6-56. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 pullup/pulldown enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Table 6-57. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Table 6-58. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Detailed Description
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Table 6-58. TA0 Registers (Base Address: 0340h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 3
TA0CCR3
18h
Capture/compare register 4
TA0CCR4
1Ah
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-59. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 6-60. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 register
TB0R
10h
Capture/compare register 0
TB0CCR0
12h
Capture/compare register 1
TB0CCR1
14h
Capture/compare register 2
TB0CCR2
16h
Capture/compare register 3
TB0CCR3
18h
Capture/compare register 4
TB0CCR4
1Ah
Capture/compare register 5
TB0CCR5
1Ch
Capture/compare register 6
TB0CCR6
1Eh
TB0 expansion register 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
138
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Table 6-61. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
Capture/compare control 2
TA2CCTL2
06h
TA2 counter register
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
Capture/compare register 2
TA2CCR2
16h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 6-62. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Battery Backup Memory 0
BAKMEM0
00h
Battery Backup Memory 1
BAKMEM1
02h
Battery Backup Memory 2
BAKMEM2
04h
Battery Backup Memory 3
BAKMEM3
06h
Battery Backup Control
BAKCTL
1Ch
Battery Charger Control
BAKCHCTL
1Eh
Table 6-63. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control register 0
RTCCTL0
00h
RTC control register 1
RTCCTL1
01h
RTC control register 2
RTCCTL2
02h
RTC control register 3
RTCCTL3
03h
RTC prescaler 0 control register
RTCPS0CTL
08h
RTC prescaler 1 control register
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds
RTCSEC
10h
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion register
BIN2BCD
1Ch
BCD-to-binary conversion register
BCD2BIN
1Eh
Detailed Description
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Table 6-64. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
Table 6-65. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA General Control: DMA module control 0
DMACTL0
00h
DMA General Control: DMA module control 1
DMACTL1
02h
DMA General Control: DMA module control 2
DMACTL2
04h
DMA General Control: DMA module control 3
DMACTL3
06h
DMA General Control: DMA module control 4
DMACTL4
08h
DMA General Control: DMA interrupt vector
DMAIV
0Ah
DMA Channel 0 control
DMA0CTL
00h
DMA Channel 0 source address low
DMA0SAL
02h
DMA Channel 0 source address high
DMA0SAH
04h
DMA Channel 0 destination address low
DMA0DAL
06h
DMA Channel 0 destination address high
DMA0DAH
08h
DMA Channel 0 transfer size
DMA0SZ
0Ah
DMA Channel 1 control
DMA1CTL
00h
DMA Channel 1 source address low
DMA1SAL
02h
DMA Channel 1 source address high
DMA1SAH
04h
DMA Channel 1 destination address low
DMA1DAL
06h
DMA Channel 1 destination address high
DMA1DAH
08h
DMA Channel 1 transfer size
DMA1SZ
0Ah
DMA Channel 2 control
DMA2CTL
00h
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Table 6-65. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA Channel 2 source address low
DMA2SAL
02h
DMA Channel 2 source address high
DMA2SAH
04h
DMA Channel 2 destination address low
DMA2DAL
06h
DMA Channel 2 destination address high
DMA2DAH
08h
DMA Channel 2 transfer size
DMA2SZ
0Ah
DMA Channel 3 control
DMA3CTL
00h
DMA Channel 3 source address low
DMA3SAL
02h
DMA Channel 3 source address high
DMA3SAH
04h
DMA Channel 3 destination address low
DMA3DAL
06h
DMA Channel 3 destination address high
DMA3DAH
08h
DMA Channel 3 transfer size
DMA3SZ
0Ah
DMA Channel 4 control
DMA4CTL
00h
DMA Channel 4 source address low
DMA4SAL
02h
DMA Channel 4 source address high
DMA4SAH
04h
DMA Channel 4 destination address low
DMA4DAL
06h
DMA Channel 4 destination address high
DMA4DAH
08h
DMA Channel 4 transfer size
DMA4SZ
0Ah
DMA Channel 5 control
DMA5CTL
00h
DMA Channel 5 source address low
DMA5SAL
02h
DMA Channel 5 source address high
DMA5SAH
04h
DMA Channel 5 destination address low
DMA5DAL
06h
DMA Channel 5 destination address high
DMA5DAH
08h
DMA Channel 5 transfer size
DMA5SZ
0Ah
Table 6-66. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA0CTL0
00h
USCI control 1
UCA0CTL1
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
Table 6-67. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB0CTL0
00h
USCI synchronous control 1
UCB0CTL1
01h
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Table 6-67. USCI_B0 Registers (Base Address: 05E0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Table 6-68. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA1CTL0
00h
USCI control 1
UCA1CTL1
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
UCA1MCTL
08h
USCI status
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
UCA1IE
1Ch
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt vector word
UCA1IV
1Eh
Table 6-69. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB1CTL0
00h
USCI synchronous control 1
UCB1CTL1
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
USCI interrupt enable
UCB1IE
1Ch
USCI interrupt flags
UCB1IFG
1Dh
USCI interrupt vector word
UCB1IV
1Eh
142
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Table 6-70. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DAC12_A channel 0 control register 0
DAC12_0CTL0
00h
DAC12_A channel 0 control register 1
DAC12_0CTL1
02h
DAC12_A channel 0 data register
DAC12_0DAT
04h
DAC12_A channel 0 calibration control register
DAC12_0CALCTL
06h
DAC12_A channel 0 calibration data register
DAC12_0CALDAT
08h
DAC12_A channel 1 control register 0
DAC12_1CTL0
10h
DAC12_A channel 1 control register 1
DAC12_1CTL1
12h
DAC12_A channel 1 data register
DAC12_1DAT
14h
DAC12_A channel 1 calibration control register
DAC12_1CALCTL
16h
DAC12_A channel 1 calibration data register
DAC12_1CALDAT
18h
DAC12_A interrupt vector word
DAC12IV
1Eh
Table 6-71. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control register 0
CBCTL0
00h
Comp_B control register 1
CBCTL1
02h
Comp_B control register 2
CBCTL2
04h
Comp_B control register 3
CBCTL3
06h
Comp_B interrupt register
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 6-72. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USB key/ID
USBKEYID
00h
USB module configuration
USBCNF
02h
USB PHY control
USBPHYCTL
04h
USB power control
USBPWRCTL
08h
USB power voltage setting
USBPWRVSR
0Ah
USB PLL control
USBPLLCTL
10h
USB PLL divider
USBPLLDIV
12h
USB PLL interrupts
USBPLLIR
14h
Table 6-73. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Input endpoint_0 configuration
USBIEPCNF_0
00h
Input endpoint_0 byte count
USBIEPBCNT_0
01h
Output endpoint_0 configuration
USBOEPCNFG_0
02h
Output endpoint_0 byte count
USBOEPBCNT_0
03h
Input endpoint interrupt enables
USBIEPIE
0Eh
Output endpoint interrupt enables
USBOEPIE
0Fh
Input endpoint interrupt flags
USBIEPIFG
10h
Output endpoint interrupt flags
USBOEPIFG
11h
USB interrupt vector
USBIV
12h
USB maintenance
USBMAINT
16h
Time stamp
USBTSREG
18h
USB frame number
USBFN
1Ah
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Table 6-73. USB Control Registers (Base Address: 0920h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
USB control
USBCTL
1Ch
USB interrupt enables
USBIE
1Dh
USB interrupt flags
USBIFG
1Eh
Function address
USBFUNADR
1Fh
Table 6-74. LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LDO key and ID register
LDOKEYPID
00h
PU port control
PUCTL
04h
LDO power control
LDOPWRCTL
08h
Table 6-75. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_B control register 0
LCDBCTL0
000h
LCD_B control register 1
LCDBCTL1
002h
LCD_B blinking control register
LCDBBLKCTL
004h
LCD_B memory control register
LCDBMEMCTL
006h
LCD_B voltage control register
LCDBVCTL
008h
LCD_B port control register 0
LCDBPCTL0
00Ah
LCD_B port control register 1
LCDBPCTL1
00Ch
LCD_B port control register 2
LCDBPCTL2
00Eh
LCD_B charge pump control register
LCDBCTL0
012h
LCD_B interrupt vector word
LCDBIV
01Eh
LCD_B memory 1
LCDM1
020h
LCD_B memory 2
LCDM2
021h
⋮
⋮
⋮
LCD_B memory 22
LCDM22
035h
LCD_B blinking memory 1
LCDBM1
040h
LCD_B blinking memory 2
LCDBM2
041h
⋮
⋮
LCD_B blinking memory 22
⋮
LCDBM22
055h
Table 6-76. CTSD16 Registers (Base Address: 0A80h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CTSD16 Control
CTSD16CTL
00h
CTSD16 Channel 0 Control
CTSD16CCTL0
02h
CTSD16 Channel 0 Input Control
CTSD16INCTL0
04h
CTSD16 Channel 0 Preload
CTSD16PRE0
06h
CTSD16 Interrupt Flag Register
CTSD16IFG
2Ch
CTSD16 Interrupt Enable Register
CTSD16IE
2Eh
CTSD16 Interrupt Vector
CTSD16IV
30h
CTSD16 Channel 0 Conversion Memory
CTSD16MEM0
32h
144
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Table 6-77. OA0 Registers (Base Address: 0AE0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OA0 Control 0 register
OA0CTL0
00h
OA0 Positive Input Terminal Switches
OA0PSW
02h
OA0 Negative Input Terminal Switches
OA0NSW
04h
OA0 Ground Switches
OA0GSW
0Eh
Table 6-78. OA1 Registers (Base Address: 0AF0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OA1 Control 0 register
OA1CTL0
00h
OA1 Positive Input Terminal Switches
OA1PSW
02h
OA1 Negative Input Terminal Switches
OA1NSW
04h
OA1 Ground Switches
OA1GSW
0Eh
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6.15 Identification
6.15.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 8.2.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.13.
6.15.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 8.2.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.13.
6.15.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320).
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor
to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up
time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a
few millimeters). Additionally, separated grounds with a single-point connection are recommend for better
noise isolation from digital to analog circuits on the board and are especially recommended to achieve
high analog accuracy.
DVCC
Digital
Power Supply
Decoupling
1 µF
+
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
1 µF
+
100 nF
AVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz)
on the XT1 pins, a high-frequency crystal on the XT2 pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN and XT2IN input pins that meet the specifications
of the respective oscillator if the appropriate XT1BYPASS or XT2BYPASS mode is selected. In this case,
the associated XOUT and XT2OUT pins can be used for other purposes. If they are left unused, they must
be terminated according to Table 4-4.
Figure 7-2 shows a typical connection diagram.
Applications, Implementation, and Layout
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XIN
or
XT2IN
CL1
XOUT
or
XT2OUT
CL2
Figure 7-2. Typical Crystal Connection
See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on
selecting, testing, and designing a crystal oscillator with the MSP430 devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide (SLAU278).
148
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VCC
Important to connect
MSP430FGxxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
C2
10 µF
C3
0.1 µF
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
2.2 nF
See Note B
A.
B.
AVSS/DVSS
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FGxxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kΩ
See Note B
C2
10 µF
C3
0.1 µF
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
2.2 nF
See Note B
A.
B.
AVSS/DVSS
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the device family user’s guide (SLAU208) for more information on the referenced control registers
and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.5.
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7.1.6
SLAS874 – MAY 2015
General Layout Recommendations
•
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the
application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
Refer to the Circuit Board Layout Techniques design guide (SLOA089) for a detailed discussion of
PCB layout considerations. This document is written primarily about op amps, but the guidelines are
generally applicable for all mixed-signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
(SLAA530) for guidelines.
Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Section 5.1, Absolute Maximum Ratings. Exceeding the specified limits may cause
malfunction of the device including erroneous writes to RAM and flash.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
CTSD16 Peripheral
For internal connections between signal chain modules such as CTSD16, OA, and DAC12, see
Section 6.12.16. When internal connections are available, they should be chosen over external
connections to reduce noise and save pins.
Solid decoupling on both the digital and analog supply are also required (best with two capacitors, one 10
μF and one 100 nF, as shown in Section 7.1.1).
VREFBG/VeREF+
(see Note A)
1 nF
22 nF
CPCAP
(see Note B)
AVSS
A.
B.
The capacitor reduces noise when using internal VREFBG setting. This pin is also used for the external reference input
for the CTSD16 or DAC, and when doing so the capacitor is not needed. Because of the shared signal path and pin,
the internal and external references (VREFBG and VeREF+, respectively) cannot be used at the same time.
The capacitor on CPCAP is required when the charge pump is enabled. The charge pump can be enabled by rail-torail operation of the CTSD16 or by the OA module. See the register settings for each module in the MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208) for enabling this operation.
Figure 7-5. CTSD16 Partial Schematic
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7.2.1.1
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Example Measurement Schematic – Differential Input
Vm
<10 kHz
RC filter
(see Note A)
R1
R2
R1
A.
AD0+
CTSD16
Vin
AD0–
TI recommends an external RC antialiasing low-pass filter for the CTSD16 to prevent aliasing of the input signal. The
cutoff frequency should be <10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff frequency may be set to
a lower frequency for applications that have lower bandwidth requirements. It is up to the user to determine the
configuration and type of low-pass filter used.
Figure 7-6. CTSD16 Measurement Schematic – Differential Input
7.2.1.2
Example Measurement Schematic – Single-Ended Input
Vm
<10 kHz
RC filter
(see Note A)
R1
A0 or
AD0+
CTSD16
R2
AD0–
VREFBG/VeREF+
A.
TI recommends an external RC antialiasing low-pass filter for the CTSD16 to prevent aliasing of the input signal. The
cutoff frequency should be <10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff frequency may be set to
a lower frequency for applications that have lower bandwidth requirements. It is up to the user to determine the
configuration and type of low-pass filter used.
Figure 7-7. CTSD16 Measurement Schematic – Single-Ended Input
7.2.1.3
Design Requirements
As with any high-resolution ADC, appropriate printed circuit board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. Therefore, solid
decoupling on both the digital and analog supply is required (best with two capacitors, one 10 μF and one
100 nF, as shown in Section 7.1.1).
In addition to grounding, ripple and noise spikes on the power-supply lines due to digital switching or
switching power supplies can corrupt the conversion result. TI recommends a noise-free design using
separate analog and digital ground planes with a single-point connection to achieve high accuracy.
If the internal reference is used, the reference voltage should be buffered externally by connecting a small
(approximately 1 nF) capacitor to the VREFBG pin to reduce the noise on the reference.
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The CTSD16 has a fixed 1.024-MHz clock (fM). Fault flags for this oscillator are described in the CTSD16
and UCS section of the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Rail-to-rail operation mode is available when the OA module is used to buffer the CTSD16 inputs. For
more information, see the CTSD16 and the OA modules in the MSP430x5xx and MSP430x6xx Family
User's Guide (SLAU208).
7.2.1.4
Detailed Design Procedure
7.2.1.4.1 OSR and Sampling Frequency
A simple equation guides the relationship between effective sampling frequency and oversampling ratio
(OSR) for CTSD16.
fs =
fm
OSR
(1)
Where
• fs = effective sampling frequency
• fm = modulation frequency
For the CTSD16, the modulation frequency is set to 1.024 MHz. Using Equation 1 with an example OSR
of 256, the effective sampling frequency would be 4 kHz. The OSR value also affects the number of bits in
the digital filter output. See the CTSD16 chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208) for additional information and available OSR values.
7.2.1.4.2 Differential Input Range Explanation
The following equations can give guidance on the input range for the CTSD16 while using an external
reference. Keep in mind the absolute bounds of an external reference as mentioned in the specifications
section of this module. The external and internal references cannot be used at the same time, because
they share the same signal path and pin. For internal reference ranges, see Section 5.5.11.
+VR
GAIN
–VR
VFSR– =
GAIN
VFSR+ =
(2)
(3)
VR
Full-Scale Range = VFSR+ – VFSR– = 2 ×
GAIN
VID = 0.8 VFSR– to 0.8 VFSR+ , with externally sourced VR
(4)
(5)
Where
• VFSR is the full-scale range voltage
• VID is the differential input voltage
• VR is the reference voltage
The differential input voltage range with internal voltage reference at different GAIN settings is given in
Section 5.5.11. Using Equation 2 through Equation 5, determine the absolute maximum differential input
ranges for the CTSD16 with a given external voltage reference. Equation 6 corresponds to the example
circuit in Figure 7-6 and can be used after a range is chosen to limit differential input voltage to acceptable
levels by solving for the external resistors R1 and R2.
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Vin = Vm ×
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R2
×
R2 + 2R1
1
R
1 + eff
2Rin
(6)
Where
• Reff = (R2 × 2R1) / ((R2 + 2R1)
• Vin is the differential voltage input to CTSD16
• Vm is the voltage to measure
• Rin is the internal resistance of the CTSD16 (see Section 5.5.11)
7.2.1.4.3 Single-Ended Input Mode
The CTSD16 has six single-ended analog inputs and four differential inputs that can be placed in singleended mode by the CTSDINCHx bits in the CTSD16INCTLx registers. These single-ended modes use the
fully differential path of the CTSD16 by internally tying the negative input to the VREFBG/VeREF+ signal. This
means for the differential inputs in single-ended mode, the external pin normally tied to the negative input
can be used for its alternate functions. Equation 7 through Equation 10 apply for full-scale range while in
single-ended mode.
VR
GAIN
VR
VFSR– = VR –
GAIN
VFSR+ = VR +
(7)
(8)
VR ö æ
VR ö
VR
æ
Full-Scale Range = VFSR+ – VFSR– = ç VR +
÷ – ç VR –
÷ =2×
GAIN ø è
GAIN ø
GAIN
è
(9)
æ V ö
æ V ö
VI = VR – 0.8 × ç R ÷ to VR + 0.8 × ç R ÷
è GAIN ø
è GAIN ø
(10)
Where
• VFSR is the full-scale range voltage
• VI is the single-ended input voltage range for data-sheet specified performance
• VR is the reference voltage
To ensure the measured voltage is within the single-ended voltage range, a simple voltage divider circuit
can be used to condition the desired input signal. In single-ended mode, additional error may be
introduced by noise when compared to a fully differential measurement. Equation 11 corresponds to the
example circuit in Figure 7-7 and can be used after a range is chosen to limit differential input voltage to
acceptable levels by solving for the external resistors R1 and R2.
Vin = Vm ×
R2
R1 + R2
(11)
Where
• Vin is the single-ended voltage input to CTSD16
• Vm is the voltage to measure
7.2.1.4.4 Offset Calibration
In some applications, it is necessary to calibrate the module for offset error. This module allows an easy
way to do this by providing internal connections from input to VREF or DAC0. To short AD4+ and AD4- to
VREF or DAC0, change the CTSD16INCHx setting for each channel to 0x11 for VREF and 0x12 for
DAC0. This allows calibration of the CTSD16 input stage by what is measured from the ideal value. The
total signal chain offset depends on the impedance of the external circuitry; thus, the actual offset seen at
any of the analog inputs may be different.
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7.2.1.5
SLAS874 – MAY 2015
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins. Avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
The analog differential input signals must be routed closely together to minimize the effect of noise on the
resulting signal.
7.2.2
Operational Amplifier With Ground Switches Peripheral
For internal connections between signal chain modules such as CTSD16, OA, and DAC12, see
Section 6.12.16. When internal connections are available, they should be chosen over external
connections to reduce noise and save pins.
Solid decoupling on both the digital and analog supply are also required (best with two capacitors, one 10
μF and one 100 nF, as shown in Section 7.1.1).
7.2.2.1
Reference Schematic
CPCAP
(see Note A)
22 nF
AVSS
A.
The capacitor on CPCAP is required when the charge pump is enabled. The charge pump can be enabled by rail-torail operation of the PGA buffers of the CTSD16 or by the OA module. See the register settings for each module in
the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for enabling this operation.
Figure 7-8. RTC_B with Battery Backup Partial Schematic
7.2.2.2
Design Requirements
As with any analog signals, appropriate printed circuit board layout and grounding techniques should be
followed to eliminate ground loops, unwanted parasitic effects, and noise.
In addition to grounding, ripple and noise spikes on the power-supply lines due to digital switching or
switching power supplies can corrupt the signal. TI recommends a noise-free design using separate
analog and digital ground planes with a single-point connection to achieve high accuracy. For more
information about noise and its effects on op amps, see Noise Analysis in Operational Amplifiers
(SLVA043).
Rail-to-rail operation mode is available with the OA module at the cost of increased current. This should
be used when OA input is near the AVCC rail. Refer to the VCM specification (see Section 5.5.14) to see if
rail-to-rail operation is required for your application. For more information, see the OA chapter of the
MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Ground switches are also available for use. See Section 6.12.16 for connections. These ground switches
provide a low ohmic connection to ground to both internal connections and to the external pin. When a
ground switch is active, the Digital I/O logic for the corresponding pin is ignored.
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7.2.2.3
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Detailed Design Procedure
Operational amplifiers are a diverse and useful tool in many applications. Some common configurations
that might prove to be useful to the user are transimpedance amplifiers to convert currents to voltage,
voltage-gain amplifiers, and buffering configurations. For more information about how to design these
circuits along with other common configurations, see the following application notes.
• Op Amps for Everyone Design Guide (SLOD006)
• Handbook of Operational Amplifier Applications (SBOA092)
• Understanding Basic Analog – Ideal Op Amps (SLAA068)
• An Applications Guide for Op Amps (SNOA621)
7.2.2.4
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-8) should be placed as close as
possible to the respective device pins. Avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal. Avoid routing analog input signals close to a highfrequency pin (for example, a high-frequency PWM), because the high-frequency switching can be
coupled into the analog signal. When possible, use internal connections to other modules to limit the
potential of error introduction.
7.2.3
RTC_B With Battery Backup System
If not using a separate battery backup supply in the system, see Section 4.5 for VBAT and VBAK
connections.
7.2.3.1
Partial Schematic
CBAK
VBAK
–
+
VBAT
BAT
(see Note A)
A.
BAT can be a battery or super-capacitor. See Section 5.5.8 for specifications.
Figure 7-9. OA Partial Schematic
7.2.3.2
Retaining an Accurate Real-Time Clock (RTC) Through Main Supply Interrupts
The RTC_B module with Battery Backup System is designed to keep an accurate RTC during main supply
interruptions and during low-power modes. For more details on when the Backup Battery System
engages, see the Battery Backup System chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208). See Using the MSP430 RTC_B Module With Battery Backup Supply (SLAA665) for
more information and example code on how to keep an accurate RTC through power loss.
7.2.3.3
Charging Super-Capacitors With Built-In Resistive Charger
In applications that use a super-capacitor instead of a battery for secondary supply, the charging circuit
functionality of the Battery Backup System can be used to charge the super-capacitor. The resistive
charger circuit connects VBAT to DVCC with selectable resistor values found in Section 5.5.8. This means
that if DVCC is not present, you cannot use this feature to charge a super-capacitor connected to VBAT.
The CTSD16 module can be used to sense the voltage level on VBAT divided by a factor of three. Typical
values during VBAT sensing are listed in Section 5.5.8. Channel A8 of the CTSD16 is routed internally for
this. See the CTSD16 chapter of the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for
more information. The BAKADC bit in the BAKCTL register must also be enabled for this feature to
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operate. Additionally, RTC interrupts can be used to wake up from LPMx.5 states to charge the supercapacitor. While in an LPMx.5 state, the super-capacitor on VBAT drains. This means that the "wakeup to
charge" interrupt interval must be designed so that charging starts before the leftover charge in the supercapacitor is too small to accommodate the worst-case backup time if the system were to suddenly lose
power. To estimate this time, use Equation 12 for capacitor discharge in an RC circuit.
–t
V(t) = VO e RC
(12)
Where
• • VO = initial voltage of capacitor
• t = time
• R = circuit resistance
• C = capacitance
Because the operational current is given for when RTC is operating within the specifications section, R
can be replaced with VO/ILPM3.5 by Ohm's Law. By setting V(t) to the minimum voltage for RTC operation
while in backup supply, VO as voltage of capacitor when fully charged, and C as the super-capacitor
capacitance, the estimated RTC operation time can be calculated. If periodic wakeups from LPM3.5 are
not desirable for a given application, external means of charging the super-capacitor must be implemented
by the user.
For a detailed list of when the secondary supply VBAT powers the backup-supplied subsystem, see the
Battery Backup System chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
7.2.4
LCD_B Peripheral
7.2.4.1
Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and also whether the on-chip charge pump is employed. For any
display used, there is flexibility as to how the segment (Sx) and common (COMx) signals are connected to
the MCU which (assuming that the correct choices are made) can be advantageous for the PCB layout
and for the design of the application software.
Because LCD connections are application specific, it is difficult to provide a single one-fits-all schematic.
However for an example of a schematic using the LCD_B module with an MSP430F6638, see the TI
Design Flow Meter host MCU board with segment LCD and prepayment or dual RF option (TIDMFLOWMETER_DUALRF).
7.2.4.2
Design Requirements
Due to the flexibility of the LCD_B peripheral module to accommodate various segment-based LCDs,
selecting the right display for the application in combination with determining specific design requirements
is often an iterative process. There can be well-defined requirements in terms of how many individually
addressable LCD segments need to be controlled, what the requirements for LCD contrast are, which
device pins are available for LCD use and which are required by other application functions, and what the
power budget is, to name just a few. TI strongly recommends reviewing the LCD_B peripheral module
chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) during the initial design
requirements and decision process. The following table provides a brief overview over different choices
that can be made and their impact.
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OPTION OR FEATURE
IMPACT OR USE CASE
Multiplexed LCD
•
•
•
•
•
Enable displays with more segments
Use fewer device pins
LCD contrast decreases as mux level increases
Power consumption increases with mux level
Requires multiple intermediate bias voltages
Static LCD
•
•
•
•
Limited number of segments that can be addressed
Use a relatively large number of device pins
Use the least amount of power
Use only VCC and GND to drive LCD signals
Internal Bias Generation
•
•
•
Simpler solution – no external circuitry
Independent of VLCD source
Somewhat higher power consumption
•
•
•
Requires external resistor ladder divider
Resistor size depends on display
Ability to adjust drive strength to optimize tradeoff between power consumption and good drive of large
segments (high capacitive load)
External resistor ladder divider can be stabilized through capacitors to reduce ripple
External Bias Generation
•
•
Internal Charge Pump
7.2.4.3
•
•
•
Helps ensure a constant level of contrast despite decaying supply voltage conditions (battery-powered
applications)
Programmable voltage levels allow software-driven contrast control
Requires an external capacitor on the LCDCAP pin
Higher current consumption than simply using VCC for the LCD driver
Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the
LCD_B peripheral module and the display itself. Two basic design processes can be employed for this
step, although in reality often a balanced co-design approach is necessary:
• PCB layout-driven design
• Software-driven design
In the PCB layout-driven design process, the segment Sx and common COMx signals are connected to
respective MSP430 device pins so that the routing of the PCB can be optimized to minimize signal
crossings and to keep signals on one side of the PCB only, typically the top layer. For example, using a
multiplexed LCD, it is possible to arbitrarily connect the Sx and COMx signals between the LCD and the
MSP430 device as long as segment lines are swapped with segment lines and common lines are
swapped with common lines. It is also possible to not contiguously connect all segment lines but rather
skip LCD_B module segment connections to optimize layout or to allow access to other functions that may
be multiplexed on a particular device port pin. Employing a purely layout-driven design approach,
however, can result in the LCD_B module control bits that are responsible for turning on and off segments
to appear scattered throughout the memory map of the LCD controller (LCDMx registers). This approach
potentially places a rather large burden on the software design that may also result in increased energy
consumption due to the computational overhead required to work with the LCD.
The other extreme is a purely software-driven approach that starts with the idea that control bits for LCD
segments that are frequently turned on and off together should be co-located in memory in the same
LCDMx register or in adjacent registers. For example, in case of a 4-mux display that contains several 7segment digits, from a software perspective it can be very desirable to control all 7 segments of each digit
though a single byte-wide access to an LCDMx register. And consecutive segments are mapped to
consecutive LCDMx registers. This allows use of simple look-up tables or software loops to output
numbers on an LCD, reducing computational overhead and optimizing the energy consumption of an
application. Establishing the most convenient memory layout must be performed in conjunction with the
specific LCD that is being used to understand its design constraints in terms of which segment and which
common signals are connected to, for example, a digit.
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For design information regarding the LCD controller input voltage selection including internal and external
options, contrast control, and bias generation, refer to the LCD_B controller chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
For additional design information, see the application report Designing With MSP430 and Segment LCD
(SLAA654).
7.2.4.4
Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is
enabled and should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent
any noise coupling. TI recommends keeping the LCD signal traces on one side of the PCB grouped
together in a bus-like fashion. A ground plane underneath the LCD traces and guard traces employed
alongside the LCD traces can provide shielding.
If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP
pin should be located as close as possible to the MCU. The capacitor should be connected to the device
using a short and direct trace and also have a solid connection to the ground plane that is supplying the
VSS pins of the MCU.
For an example layout of the LCD_B module with an MSP430F6638, see the TI Design Flow Meter host
MCU board with segment LCD and prepayment or dual RF option (TIDM-FLOWMETER_DUALRF).
Applications, Implementation, and Layout
Submit Documentation Feedback
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SLAS874 – MAY 2015
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8 Device and Documentation Support
8.1
Device Support
8.1.1
Getting Started
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.1.2
Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
8.1.2.1
Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock
Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430Xv2
Yes
Yes
8+2
Yes
Yes
Yes
Yes
No
8.1.2.2
Recommended Hardware Options
8.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
Package
Target Board and Programmer Bundle
Target Board Only
100-pin LQFP (PZ)
MSP-FET430U100AUSB
MSP-TS430PZ100AUSB
8.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
8.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
8.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
8.1.2.3
Features
Provider
Program up to eight devices at a time. Works with PC or standalone.
Texas Instruments
Recommended Software Options
8.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open-source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
160
Device and Documentation Support
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG6626 MSP430FG6625 MSP430FG6426 MSP430FG6425
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
www.ti.com
SLAS874 – MAY 2015
8.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a standalone package.
8.1.2.3.3 SYS/BIOS
SYS/BIOS is an advanced real-time operating system for the MSP430 microcontrollers. It features
preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time
analysis. SYS/BIOS is available free of charge and is provided with full source code.
8.1.2.3.4 MSP430 USB Developer's Package
The MSP430 USB Developer's Package (MSP430USBDEVPACK) is an easy-to-use USB stack
implementation for the MSP430 microcontrollers.
8.1.2.3.5 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for
an IDE.
8.1.3
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FG6626 MSP430FG6625 MSP430FG6426 MSP430FG6425
Copyright © 2015, Texas Instruments Incorporated
161
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
www.ti.com
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
MSP 430 F 5 438 A I ZQW T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
430 MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
TI’s Low-Power Microcontroller Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz with LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 8-1. Device Nomenclature
162
Device and Documentation Support
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG6626 MSP430FG6625 MSP430FG6426 MSP430FG6425
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
www.ti.com
8.2
SLAS874 – MAY 2015
Documentation Support
The following documents describe the MSP430FG662x and MSP430FG642x devices. Copies of these
documents are available on the Internet at www.ti.com.
8.3
SLAU208
MSP430x5xx and MSP430x6xx Family User's Guide. Detailed information on the modules
and peripherals available in this device family.
SLAZ667
MSP430FG6626 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revision of the device.
SLAZ668
MSP430FG6625 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revision of the device.
SLAZ669
MSP430FG6426 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revision of the device.
SLAZ670
MSP430FG6425 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revision of the device.
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FG6626
Click here
Click here
Click here
Click here
Click here
MSP430FG6625
Click here
Click here
Click here
Click here
Click here
MSP430FG6426
Click here
Click here
Click here
Click here
Click here
MSP430FG6425
Click here
Click here
Click here
Click here
Click here
8.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.5
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FG6626 MSP430FG6625 MSP430FG6426 MSP430FG6425
Copyright © 2015, Texas Instruments Incorporated
163
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
8.6
www.ti.com
Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.7
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
164
Mechanical, Packaging, and Orderable Information
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG6626 MSP430FG6625 MSP430FG6426 MSP430FG6425
PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FG6425IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FG6425
MSP430FG6425IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG6425
MSP430FG6426IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FG6426
MSP430FG6426IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG6426
MSP430FG6625IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FG6625
MSP430FG6625IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG6625
MSP430FG6626IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FG6626
MSP430FG6626IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FG6626
MSP430FG6626IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG6626
MSP430FG6626IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG6626
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2015
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430FG6425IPZR
MSP430FG6425IZQWR
MSP430FG6426IPZR
MSP430FG6426IZQWR
MSP430FG6625IPZR
MSP430FG6625IZQWR
MSP430FG6626IPZR
Package Package Pins
Type Drawing
LQFP
BGA MI
CROSTA
R JUNI
OR
LQFP
BGA MI
CROSTA
R JUNI
OR
LQFP
BGA MI
CROSTA
R JUNI
OR
LQFP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430FG6626IZQWR
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG6626IZQWT
BGA MI
CROSTA
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
R JUNI
OR
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FG6425IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG6425IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG6426IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG6426IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG6625IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG6625IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG6626IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG6626IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG6626IZQWT
BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Products
Applications
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Amplifiers
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