LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 LMH6559 High-Speed, Closed-Loop Buffer Check for Samples: LMH6559 FEATURES DESCRIPTION • • • • • • • The LMH6559 is a high-speed, closed-loop buffer designed for applications requiring the processing of very high frequency signals. While offering a small signal bandwidth of 1750MHz, and an ultra high slew rate of 4580V/μs the LMH6559 consumes only 10mA of quiescent current. Total harmonic distortion into a load of 100Ω at 20MHz is −52dBc. The LMH6559 is configured internally for a loop gain of one. Input resistance is 200kΩ and output resistance is but 1.2Ω. These characteristics make the LMH6559 an ideal choice for the distribution of high frequency signals on printed circuit boards. Differential gain and phase specifications of 0.06% and 0.02° respectively at 3.58MHz make the LMH6559 well suited for the buffering of video signals. 1 2 Closed-Loop Buffer 1750MHz Small Signal Bandwidth 4580V/μs Slew Rate 0.06% / 0.02° Differential Gain/Phase −52dBc THD at 20MHz Single Supply Operation (3V Min.) 75mA Output Current APPLICATIONS • • • • • • • • Video Switching and Routing Test Point Drivers High Frequency Active Filters Wideband DC Clamping Buffers High-Speed Peak Detector Circuits Transmission Systems Telecommunications Test Equipment and Instrumentation The device is fabricated on Texas Instruments' highspeed VIP10 process using TI's proven high performance circuit architectures. Typical Schematic VCC 10nF 10k: 1 100nF 100nF 4 LMH6559 8 50: 5 50: 10k: Figure 1. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) ESD Tolerance (3) Human Body Model 2000V Machine Model 200V See (4), (5) and Output Short Circuit Duration Supply Voltage (V+ – V−) 13V + Infrared or Convection (20 sec.) 235°C Wave Soldering (10 sec.) 260°C −65°C to +150°C Storage Temperature Range Junction Temperature (1) (2) (3) (4) (5) (6) − V +0.8V, V −0.8V Voltage at Input/Output Pins Soldering Information (6) +150°C Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PC board. Operating Ratings (1) Supply Voltage (V+ - V−) 3 - 10V Temperature Range (2) (3) −40°C to +85°C Package Thermal Resistance (2) (3) (1) (2) (3) 2 8-Pin SOIC 172°C/W 5-Pin SOT-23 235°C/W Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PC board. Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. There is no specification of parametric performance as indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications section for information on temperature de-rating of this device. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 ±5V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = +5V, V− = −5V, VO = VCM = 0V and RL = 100Ω to 0V. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units Frequency Domain Response SSBW Small Signal Bandwidth VO < 0.5VPP 1750 GFN Gain Flatness < 0.1dB VO < 0.5VPP 200 MHz MHz FPBW Full Power Bandwidth (−3dB) VO = 2VPP (+10dBm) 1050 MHZ DG Differential Gain RL = 150Ω to 0V, f = 3.58 MHz 0.06 % DP Differential Phase RL = 150Ω to 0V, f = 3.58 MHz 0.02 deg 3.3V Step (20-80%) 0.4 ns 0.5 ns ns Time Domain Response tr Rise Time tf Fall Time ts Settling Time to ±0.1% 3.3V Step 9 OS Overshoot 1V Step 4 % SR Slew Rate See (3) 4580 V/µs Distortion And Noise Performance HD2 2nd Harmonic Distortion VO = 2VPP, f = 20MHz −58 dBc HD3 3rd Harmonic Distortion VO = 2VPP, f = 20MHz −53 dBc THD Total Harmonic Distortion VO = 2VPP, f = 20MHz −52 dBc en Input-Referred Voltage Noise f = 1MHz 5.7 nV/√Hz CP 1dB Compression point f = 10MHz +23 dBm SNR Signal to Noise Ratio f > 100kHz, BW = 5MHz, VO = 350mVrms 89 dB (1) (2) (3) All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Slew rate is the average of the positive and negative slew rate. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 3 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com ±5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = +5V, V− = −5V, VO = VCM = 0V and RL = 100Ω to 0V. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min Typ VO = 100mVPP RL = 100Ω to 0V .97 .996 VO = 100mVPP RL = 2kΩ to 0V .99 .998 (1) (2) Max (1) Units Static, DC Performance ACL Small Signal Voltage Gain VOS Input Offset Voltage 3 TC VOS Temperature Coefficient Input Offset Voltage See (4) IB Input Bias Current See (5) TC IB Temperature Coefficient Input Bias Current ROUT Output Resistance V/V 20 25 mV 23 μV/°C −3 μA See (4) −3.6 nA/°C RL = 100Ω to 0V, f = 100kHz 1.2 RL = 100Ω to 0V, f = 10MHz 1.3 PSRR Power Supply Rejection Ratio VS = ±5V to VS = ±5.25V IS Supply Current No Load −10 −14 48 44 Ω 63 10 dB 14 17 mA Miscellaneous Performance RIN Input Resistance 200 kΩ CIN Input Capacitance 1.7 pF VO Output Swing Positive Output Swing Negative ISC IO (4) (5) 4 Output Short Circuit Current Linear Output Current RL = 100Ω to 0V 3.20 3.18 3.45 RL = 2kΩ to 0V 3.55 3.54 3.65 V RL = 100Ω to 0V −3.45 −3.20 −3.18 RL = 2kΩ to 0V −3.65 −3.55 −3.54 Sourcing: VIN = +VS, VO = 0V −83 Sinking: VIN = −VS, VO = 0V 83 Sourcing: VIN - VO = 0.5V (5) −50 −43 −74 Sinking: VIN - VO = −0.5V (5) 50 43 74 V mA mA Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 5V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units Frequency Domain Response SSBW Small Signal Bandwidth VO < 0.5VPP 745 GFN Gain Flatness < 0.1dB VO < 0.5VPP 90 MHz MHz FPBW Full Power Bandwidth (−3dB) VO = 2VPP (+10dBm) 485 MHZ DG Differential Gain RL = 150Ω to V+/2, f = 3.58 MHz 0.29 % DP Differential Phase RL = 150Ω to V+/2, f = 3.58 MHz 0.06 deg 2.3VPP Step (20-80%) 0.6 ns 0.9 ns 9.6 ns Time Domain Response tr Rise Time tf Fall Time ts Settling Time to ±0.1% 2.3V Step OS Overshoot 1V Step SR Slew Rate 3 % See (3) 2070 V/µs Distortion And Noise Performance HD2 2nd Harmonic Distortion VO = 2VPP, f = 20MHz −53 dBc HD3 3rd Harmonic Distortion VO = 2VPP, f = 20MHz −56 dBc THD Total Harmonic Distortion VO = 2VPP, f = 20MHz −52 dBc en Input-Referred Voltage Noise f = 1MHz 4.0 nV/√Hz CP 1dB Compression point f = 10MHz +7 dBm SNR Signal to Noise Ratio f > 100kHz, BW = 5MHz, VO = 350mVrms 92 dB Static, DC Performance ACL Small Signal Voltage Gain VO = 100mVPP RL = 100Ω to V+/2 .97 .996 VO = 100mVPP RL = 2kΩ to V+/2 .99 .998 VOS Input Offset Voltage 1.52 TC VOS Temperature Coefficient Input Offset Voltage See (4) IB Input Bias Current See (5) TC IB Temperature Coefficient Input Bias Current ROUT Output Resistance −2.7 μA See (4) 1.6 nA/°C RL = 100Ω to V+/2, f = 100kHz 1.4 RL = 100Ω to V+/2, f = 10MHz 1.6 VS = +5V to VS = +5.5V, VIN = VS/2 IS Supply Current No Load (5) mV μV/°C Power Supply Rejection Ratio (3) (4) 12 16 23 PSRR (1) (2) V/V −5 −8 48 44 Ω 68 4.7 dB 7 8.5 mA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Slew rate is the average of the positive and negative slew rate. Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 5 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units Miscellaneous Performance RIN Input Resistance 200 kΩ CIN Input Capacitance 2.0 pF VO Output Swing Positive Output Swing Negative ISC Output short circuit Current IO (6) Linear Output Current RL = 100Ω to V+/2 3.80 3.75 3.88 RL = 2kΩ to V+/2 3.94 3.92 3.98 V RL = 100Ω to V+/2 1.12 1.20 1.25 RL = 2kΩ to V+/2 1.03 1.06 1.09 Sourcing: VIN = +VS, VO = V+/2 −57 Sinking: VIN = −VS, VO = V+/2 26 Sourcing: VIN - VO = 0.5V (6) −50 −43 −64 Sinking: VIN - VO = −0.5V (6) 30 23 42 V mA mA Positive current corresponds to current flowing into the device. 3V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units Frequency Domain Response SSBW Small Signal Bandwidth VO < 0.5VPP 315 MHz GFN Gain Flatness < 0.1dB VO < 0.5VPP 44 MHz FPBW Full Power Bandwidth (−3dB) VO = 1VPP (+4.5dBm) 265 MHZ 1.0V Step (20-80%) 0.8 ns 1.2 ns 10 ns Time Domain Response tr Rise Time tf Fall Time ts Settling Time to ±0.1% 1V Step OS Overshoot 0.5V Step 0 % SR Slew Rate See (3) 770 V/µs VO = 2VPP, f = 20MHz −74 dBc dBc Distortion And Noise Performance HD2 2nd Harmonic Distortion rd HD3 3 Harmonic Distortion VO = 2VPP, f = 20MHz −57 THD Total Harmonic Distortion VO = 2VPP, f = 20MHz −56 dBc en Input-Referred Voltage Noise f = 1MHz 3.9 nV/Hz CP 1dB Compression point f = 10MHz +4 dBm SNR Signal to Noise Ratio f > 100kHz, BW = 5MHz, VO = 350mVrms 92 dB (1) (2) (3) 6 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Slew rate is the average of the positive and negative slew rate. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 3V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes. Symbol Min Typ VO = 100mVPP RL = 100Ω to V+/2 .97 .995 VO = 100mVPP RL = 2kΩ to V+/2 .99 .998 Parameter Conditions (1) (2) Max (1) Units Static, DC Performance ACL Small Signal Voltage Gain VOS Input Offset Voltage 1 TC VOS Temperature Coefficient Input Offset Voltage See (4) IB Input Bias Current See (5) TC IB Temperature Coefficient Input Bias Current ROUT Output Resistance V/V 7 9 mV 3.5 μV/°C −1.5 μA See (4) 0.46 nA/°C RL = 100Ω to V+/2, f = 100kHz 1.8 RL = 100Ω to V+/2, f = 10MHz 2.3 −3 −3.5 PSRR Power Supply Rejection Ratio VS = +3V to VS = +3.5V, VIN = V+/2 IS Supply Current No Load 48 46 Ω 68 2.4 dB 3.5 4.5 mA Miscellaneous Performance RIN Input Resistance 200 kΩ CIN Input Capacitance 2.3 pF VO Output Swing Positive Output Swing Negative ISC IO (4) (5) Output Short Circuit Current Linear Output Current + RL = 100Ω to V /2 2.02 1.95 2.07 RL = 2kΩ to V+/2 2.12 2.02 2.17 V RL = 100Ω to V+/2 .930 .970 1.050 RL = 2kΩ to V+/2 .830 .880 .980 Sourcing: VIN = +VS, VO = V+/2 −32 Sinking: VIN = −VS, VO = V+/2 15 Sourcing: VIN - VO = 0.5V (5) −20 −13 −28 Sinking: VIN - VO = −0.5V (5) 12 8 17 V mA mA Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 7 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAMS VCC 1 2 NC 8 7 VOUT VOUT 3 6 4 5 VIN VCC 2 NC NC VEE Figure 2. 8-Pin SOIC (Top View) See Package Number D (R-PDSO-G8) 8 5 NC VEE NC 1 3 4 VIN Figure 3. 5-Pin SOT-23 (Top View) See Package Number DBV (R-PDSO_G5) Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 Typical Performance Charac teristics At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified. Frequency Response Frequency Response Over Temperature 3 3 RL = 100: VS = 10V -40°C 0 GAIN (dB) 0 GAIN (dB) -3 VS = 5V -6 25°C -3 85°C 125°C -6 -9 VS = 10V VS = 3V RL = 100: -9 -12 10M 1G 2G 100M 100M 1G Figure 4. Figure 5. Gain Flatness Differential Gain and Phase 1.0 0.036 0.12 VS = 10V RL = 100: 0.10 0.5 DIFF GAIN (%) 10V 0.0 5V 0.030 RL =150: f =3.58MHz 0.08 +0.1dB GAIN (dB) 2G 3G FREQUENCY (Hz) FREQUENCY (Hz) 0.024 0.06 0.018 GAIN 0.04 0.012 0.02 0.006 -0.1dB -0.5 0 0 -0.02 3V DIFF PHASE (°) 1M -0.006 PHASE -0.04 -1.0 1M 10M 100M -700 -525 -350 -175 1G Figure 6. Figure 7. Differential Gain and Phase Transient Response Positive 0.140 2.0 0.120 1.5 VS = 5V 0.20 0.080 GAIN 0.15 0.10 1.0 0.100 0.060 PHASE 0.05 0.040 VOUT (V) DIFF GAIN (%) 0.25 RL = 150: f = 3.58MHz DIFF PHASE (°) 0.30 0.5 0 -0.5 -1.0 0.020 -1.5 -0.000 -2.0 -0.020 -0.05 -700 -525 -350 -175 0 175 350 525 700 DC OUTPUT VOLTAGE (mV) -2.5 0 -0.012 175 350 525 700 DC OUTPUT VOLTAGE (mV) FREQUENCY (Hz) 0.35 0 Figure 8. VS = 10V STEP = 3.3V RL = 100: 0 1 2 3 4 TIME (ns) 5 6 Figure 9. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 9 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com Typical Performance Charac teristics (continued) − + At TJ = 25°C; V = +5V; V = −5V; Unless otherwise specified. Transient Response Negative Transient Response Positive for Various VSUPPLY 2.5 2.0 1.5 VS = 10V STEP = 3.3V 2.0 1.0 RL = 100: 1.5 1.0 VOUT (V) VOUT (V) 0.5 0 -0.5 -1.0 0.5 VS = 5V, STEP 2.3VPP 0.0 -0.5 VS = 3V, STEP 1VPP -1.0 -1.5 -1.5 -2.0 -2.0 -2.5 -2.5 0 1 2 3 4 5 0 6 VS = 3V, STEP 1VPP -0.5 VS = 5V, STEP 2.3VPP THD -40 2 VS = 10V, STEP 3.3VPP nd HD -50 3 -60 rd HD -70 -80 th 4 HD -100 0 2 4 6 8 10 TIME (ns) 12 14 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 16 VOUT (VPP) Figure 12. Figure 13. Harmonic Distortion vs. VOUT @ 10MHz Harmonic Distortion vs. VOUT @ 20MHz 0 0 VS = 10V -10 RL = 100: -20 THD -30 2 nd DISTORTION (dBc) DISTORTION (dBc) 16 -30 -90 -2.5 HD -50 -60 -70 3 rd HD -80 VS = 10V RL = 100: -30 -40 THD rd 3 HD -50 -60 -70 2 nd HD -80 th 4 HD -90 -100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 th -90 4 HD -100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VOUT (VPP) VOUT (VPP) Figure 14. 10 14 RL = 100: -20 -2.0 -40 12 VS = 10V -10 -1.5 -20 10 Harmonic Distortion vs. VOUT @ 5MHz RL = 100: 0.0 -10 8 0 1.0 -1.0 6 Figure 11. 1.5 0.5 4 Figure 10. VS = 10V, STEP 3.3VPP 2.0 2 TIME (ns) DISTORTION (dBc) 2.5 RL = 100: TIME (ns) Transient Response Negative for Various VSUPPLY VOUT (V) VS = 10V, STEP 3.3VPP Figure 15. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 Typical Performance Charac teristics (continued) − + At TJ = 25°C; V = +5V; V = −5V; Unless otherwise specified. THD vs. VOUT for Various Frequencies Voltage Noise 40 -40 VS = 10V 1MHz 35 -45 5MHz NOISE (nV/ Hz ) 30 -50 THD (dBc) RL = 100: 10MHz -55 -60 20MHz 25 20 15 10 10MHz -65 VS = 10V 5 RL = 100: 0 100 -70 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 10k 1k VOUT (VPP) Figure 16. Linearity VOUT vs. VIN VOS vs. VSUPPLY for 3 Units 5 VS = 10V 3 1 VOS (mV) 10 5 0 -1 250MHz 0 -3 -4 750MHz -10 UNIT 1 -2 500MHz -5 UNIT 3 2 50MHz -15 -10 T = 25°C 4 10MHz RL = 100: 15 OUTPUT (dBm) 10M 1M Figure 17. 25 20 100k FREQUENCY (Hz) UNIT 2 -5 -6 -5 0 10 5 INPUT (dBm) 15 20 3 4 5 6 7 8 9 10 VSUPPLY (V) Figure 18. Figure 19. VOS vs. VSUPPLY for Unit 1 VOS vs. VSUPPLY for Unit 2 0 0.5 0 -1 125°C -0.5 VOS (mV) -1 VOS (mV) -40°C -2 -40°C 85°C -1.5 -2 25°C -3 -4 -5 -2.5 125°C 85°C -6 -3 25°C -7 -3.5 3 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10 VSUPPLY (V) VSUPPLY (V) Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 11 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com Typical Performance Charac teristics (continued) − + At TJ = 25°C; V = +5V; V = −5V; Unless otherwise specified. IB vs. VSUPPLY (1) VOS vs. VSUPPLY for Unit 3 6 0 -1 5 125°C -2 4 -3 IB (PA) VOS (mV) 85°C 3 -40°C 2 -40°C -4 -5 25°C 1 -6 25°C 85°C 0 -7 -1 -8 125°C 3 4 5 6 7 8 9 10 3 4 7 8 Figure 22. Figure 23. ROUT vs. Frequency 9 10 PSRR vs. Frequency 80 70 14 VS = 3V 12 60 PSRR (dB) 10 VS = 5V 8 VS = 10V 6 50 40 30 4 20 2 10 0 100k 1M 10M VS = 10V RL = 100: 0 100 100M 100k 10k 1k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Figure 25. ISUPPLY vs. VSUPPLY 10M 100M ISUPPLY vs. VIN 12 14 125°C 12 10 85°C 8 6 -40°C 4 11 125°C 10 85°C ISUPPLY (mA) ISUPPLY (mA) 6 VSUPPLY (V) 16 ROUT (:) 5 VSUPPLY (V) 25°C 9 8 -40°C 7 25°C 2 6 0 5 VS = 10V 3 4 5 6 7 8 9 10 VSUPPLY (V) 12 2 4 6 8 10 VIN (V) Figure 26. (1) 0 Figure 27. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 Typical Performance Charac teristics (continued) − + At TJ = 25°C; V = +5V; V = −5V; Unless otherwise specified. VOUT vs. IOUT Sinking VOUT vs. IOUT Sourcing 4.5 0 VS = ±5V -0.5 4 VIN = -4V 3.5 125°C -1.5 VOUT (V) VOUT (V) -1 85°C -2 25°C -2.5 -3 -40°C 3 2.5 25°C 2 85°C 1.5 -40°C 125°C -.35 1 -4 0.5 -4.5 0 VS = ±5V 0 20 40 60 80 VIN = +4V 0 100 -40 -20 ISINK (mA) Figure 28. IO Sinking vs. VSUPPLY 80 -30 85°C -50 IO (mA) IO (mA) VOUT = VSUPPLY/2 VIN = VOUT +0.5V -40 25°C 50 125°C 40 125°C 85°C -60 -70 30 -40°C -80 20 VOUT = VSUPPLY/2 10 -90 VIN = VOUT - 0.5V -40°C 0 25°C -100 3 4 5 6 7 8 9 10 3 4 5 VSUPPLY (V) 6 7 8 9 10 VSUPPLY (V) Figure 30. Figure 31. Small Signal Pulse Response Large Signal Pulse Response @ VS = 3V 0.6 0.4 VS = 10V 0.3 0.4 0.2 VS = 5V 0.2 0.1 VS = 3V 0 VS = 3V -0.1 VOUT (V) VOUT (V) -100 IO Sourcing vs. VSUPPLY -20 60 -80 Figure 29. 90 70 -60 ISOURCE (mA) VPULSE = 1VPP 0 RL = 100: -0.2 -0.4 -0.2 RL = 100: -0.3 -0.6 VPULSE = 0.5VPP -0.8 -0.4 0 5 10 15 20 TIME (ns) 25 30 35 0 10 20 30 40 50 TIME (ns) Figure 32. Figure 33. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 13 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com Typical Performance Charac teristics (continued) − + At TJ = 25°C; V = +5V; V = −5V; Unless otherwise specified. Large Signal Pulse Response @ VS = 5V Large Signal Pulse Response @ VS = 10V 2.0 1.5 1.5 1.0 1.0 VOUT (V) VOUT (V) 0.5 VPULSE = 2.3VPP 0 RL = 100: -0.5 0.5 VPULSE = 3.3VPP 0 RL = 100: -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.5 -2.0 0 14 10 20 30 40 50 0 10 20 30 TIME (ns) TIME (ns) Figure 34. Figure 35. Submit Documentation Feedback 40 50 Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 APPLICATION NOTES USING BUFFERS A buffer is an electronic device delivering current gain but no voltage gain. It is used in cases where low impedances need to be driven and more drive current is required. Buffers need a flat frequency response and small propagation delay. Furthermore, the buffer needs to be stable under resistive, capacitive and inductive loads. High frequency buffer applications require that the buffer be able to drive transmission lines and cables directly. IN WHAT SITUATION WILL WE USE A BUFFER? In case of a signal source not having a low output impedance one can increase the output drive capability by using a buffer. For example, an oscillator might stop working or have frequency shift which is unacceptably high when loaded heavily. A buffer should be used in that situation. Also in the case of feeding a signal to an A/D converter it is recommended that the signal source be isolated from the A/D converter. Using a buffer assures a low output impedance, the delivery of a stable signal to the converter, and accommodation of the complex and varying capacitive loads that the A/D converter presents to the OpAmp. Optimum value is often found by experimentation for the particular application. The use of buffers is strongly recommended for the handling of high frequency signals, for the distribution of signals through transmission lines or on pcb's, or for the driving of external equipment. There are several driving options: • Use one buffer to drive one transmission line (see Figure 36) • Use one buffer to drive to multiple points on one transmission line (see Figure 37) • Use one buffer to drive several transmission lines each driving a different receiver. (see Figure 38) Z0 R = Z0 INPUT E A =1X A B R = Z0 Figure 36. D B A INPUT Z0 E A =1X R = Z0 C Figure 37. Z0 R = Z0 E OPEN END A INPUT B A =1X OPEN END OPEN END Figure 38. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 15 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com In these three options it is seen that there is more than one preferred method to reach an (end) point on a transmission line. Until a certain point the designer can make his own choice but the designer should keep in mind never to break the rules about high frequency transport of signals. An explanation follows in the text below. TRANSMISSION LINES Introduction to transmission lines. The following is an overview of transmission line theory. Transmission lines can be used to send signals from DC to very high frequencies. At all points across the transmission line, Ohm's law must apply. For very high frequencies, parasitic behavior of the PCB or cables comes into play. The type of cable used must match the application. For example an audio cable looks like a coax cable but is unusable for radar frequencies at 10GHz. In this case one have to use special coax cables with lower attenuation and radiation characteristics. Normally a pcb trace is used to connect components on a pcb board together. An important considerations is the amount of current carried by these pcb traces. Wider pcb traces are required for higher current densities and for applications where very low series resistance is needed. When routed over a ground plane, pcb traces have a defined Characteristic Impedance. In many design situations characteristic impedance is not utilized. In the case of high frequency transmission, however it is necessary to match the load impedance to the line characteristic impedance (more on this later). Each trace is associated with a certain amount of series resistance and series inductance plus each trace exhibits parallel capacitance to the ground plane. The combination of these parameters defines the line's characteristic impedance. The formula with which we calculate this impedance is as follows: Z0 = √(L/C) In this formula L and C are the value/unit length, and R is assumed to be zero. C and L are unknown in many cases so we have to follow other steps to calculate the Z0. The characteristic impedance is a function of the geometry of the cross section of the line. In (Figure 39) we see three cross sections of commonly used transmission lines. D W S h d COAX CABLE d PARALLEL WIRE TRACK OVER GROUND Figure 39. Z0 can be calculated by knowing some of the physical dimensions of the pcb line, such as pcb thickness, width of the trace and εr, relative dielectric constant. The formula given in transmission line theory for calculating Z0 is as follows: 87 x ln Z= H r + 1.41) (5.98 x h) (th + 0.8W) where • • • • εr= relative dielectric constant h= pcb height W= trace width th= thickness of the copper (1) If we ignore the thickness of the copper in comparison to the width of the trace then we have the following equation: 16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 87 Z= x ln H r + 1.41) (5.98 x h) (0.8W) (2) With this formula it is possible to calculate the line impedance vs. the trace width. Figure 40 shows the impedance associated with a given line width. Using the same formula it is also possible to calculate what happens when εr varies over a certain range of values. Varying the εr over a range of 1 to 10 gives a variation for the Characteristic Impedance of about 40Ω from 80Ω to 38Ω. Most transmission lines are designed to have 50Ω or 75Ω impedance. The reason for that is that in many cases the pcb trace has to connect to a cable whose impedance is either 50Ω or 75Ω. As shown εr and the line width influence this value. VARIATION OF Hr 2.3 3.6 120 110 100 IMPEDANCE (:) 90 4.9 6.2 7.5 8.8 10.1 120 VARIABLE TRACE WIDTH 110 Hr = 4.7 100 h = 1.6mm 90 80 80 70 70 60 60 50 40 50 30 VARIABLE RELATIVE DIELECTRIC 20 CONSTANT WIDTH = 2.85mm 10 h = 1.6mm 0 1.5 2.0 2.5 3.0 3.5 0.5 1.0 30 40 IMPEDANCE (:) 1.0 20 10 0 4.0 TRACE WIDTH (mm) Figure 40. Next, there will be a discussion of some issues associated with the interaction of the transmission line at the source and at the load. Connecting A Load Using A Transmission Line In most cases, it is unrealistic to think that we can place a driver or buffer so close to the load that we don't need a transmission line to transport the signal. The pcb trace length between a driver and the load may affect operation depending upon the operating frequency. Sometimes it is possible to do measurements by connecting the DUT directly to the analyzer. As frequencies become higher the short lines from the DUT to the analyzer become long lines. When this happens there is a need to use transmission lines. The next point to examine is what happens when the load is connected to the transmission line. When driving a load, it is important to match the line and load impedance, otherwise reflections will occur and this phenomena will distort the signal. If a transient is applied at T = 0 (Figure 41, trace A) the resultant waveform may be observed at the start point of the transmission line. At this point (begin) on the transmission line the voltage increases to (V) and the wave front travels along the transmission line and arrives at the load at T = 10. At any point across along the line I = V/Z0, where Z0 is the impedance of the transmission line. For an applied transient of 2V with Z0 = 50Ω the current from the buffer output stage is 40mA. Many vintage opamps cannot deliver this level of current because of an output current limitation of about 20mA or even less. At T = 10 the wave front arrives at the load. Since the load is perfectly matched to the transmission line all of the current traveling across the line will be absorbed and there will be no reflections. In this case source and load voltages are exactly the same. When the load and the transmission line have unequal values of impedance a different situation results. Remember there is another basic which says that energy cannot be lost. The power in the transmission line is P = V2/R. In our example the total power is 22/50 = 80mW. Assume a load of 75Ω. In that case a power of 80mW arrives at the 75Ω load and causes a voltage of the proper amplitude to maintain the incoming power. V= (P x R) = (80 x 10-3 x 75) = 2.45V (3) Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 17 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com The voltage wavefront of 2.45V will now set about traveling back over the transmission line towards the source, thereby resulting in a reflection caused by the mismatch. On the other hand if the load is less then 50Ω the backwards traveling wavefront is subtracted from the incoming voltage of 2V. Assume the load is 40Ω. Then the voltage across the load is: (80 x 10-3 x 40) = 1.79V (4) This voltage is now traveling backwards through the line toward the start point. In the case of a sinewave interferences develop between the incoming waveform and the backwards-going reflections, thus distorting the signal. If there is no load at all at the end point the complete transient of 2V is reflected and travels backwards to the beginning of the line. In this case the current at the endpoint is zero and the maximum voltage is reflected. In the case of a short at the end of the line the current is at maximum and the voltage is zero. BEGIN END TRANSMISSION LINE LENGTH V V/2 A 0 | V/2 B 0 V V/2 C 0 V V/2 D 0 V V/2 E 0 0 2 6 4 8 10 TIME Figure 41. Using Serial And Parallel Termination Many applications, such as video, use a series resistance between the driver and the transmission line (see Figure 36). In this case the transmission line is terminated with the characteristic impedance at both ends of the line. See Figure 41 trace B. The voltage traveling through the transmission line is half the voltage seen at the output of the buffer, because the series resistor in combination with Z0 forms a two-to-one voltage divider. The result is a loss of 6dB. For video applications, amplifier gain is set to 2 in order to realize an overall gain of 1. Many operational amplifiers have a relatively flat frequency response when set to a gain of two compared to unity gain. In trace B it is seen that, if the voltage reaches the end of the transmission line, the line is perfectly matched and no reflections will occur. The end point voltage stays at half the output voltage of the opamp or buffer. 18 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 Driving More Than One Input Another transmission line possibility is to route the trace via several points along a transmission line (Figure 37) This is only possible if care is taken to observe certain restrictions. Failure to do so will result in impedance discontinuities that will cause distortion of the signal. In the configuration of Figure 37 there is a transmission line connected to the buffer output and the end of the line is terminated with Z0. We have seen in the Connecting A Load Using A Transmission Line section that for the condition above, the signal throughout the entire transmission line has the same value, that the value is the nominal value initiated by the opamp output, and no reflections occur at the end point. Because of the lack of reflections no interferences will occur. Consequently the signal has every where on the line the same amplitude. This allows the possibility of feeding this signal to the input port of any device which has high ohmic impedance and low input capacitance. In doing so keep in mind that the transient arrives at different times at the connected points in the transmission line. The speed of light in vacuum, which is about 3 * 108 m/sec, reduces through a transmission line or a cable down to a value of about 2 * 108 m/sec. The distance the signal will travel in 1ns is calculated by solving the following formula: S = V*t where • • • S = distance V = speed in the cable t = time (5) 8 −9 This calculation gives the following result: s = 2*10 * 1*10 = 0.2m That is for each nanosecond the wave front shifts 20cm over the length of the transmission line. Keep in mind that in a distance of just 2cm the time displacement is already 100ps. Using Serial Termination To More Than One Transmission Line Another way to reach several points via a transmission line is to start several lines from one buffer output (see Figure 38). This is possible only if the output can deliver the needed current into the sum of all transmission lines. As can be seen in this figure there is a series termination used at the beginning of the transmission line and the end of the line has no termination. This means that only the signal at the endpoint is usable because at all other points the reflected signal will cause distortion over the line. Only at the endpoint will the measured signal be the same as at the startpoint. Referring to Figure 41 trace C, the signal at the beginning of the line has a value of V/2 and at T = 0 this voltage starts traveling towards the end of the transmission line. Once at the endpoint the line has no termination and 100% reflection will occur. At T = 10 the reflection causes the signal to jump to 2V and to start traveling back along the line to the buffer (see Figure 41 trace D). Once the wavefront reaches the series termination resistor, provided the termination value is Z0, the wavefront undergoes total absorption by the termination. This is only true if the output impedance of the buffer/driver is low in comparison to the characteristic impedance Z0. At this moment the voltage in the whole transmission line has the nominal value of 2V (see Figure 41 trace E). If the three transmission lines each have a different length the particular point in time at which the voltage at the series termination resistor jumps to 2V is different for each case. However, this transient is not transferred to the other lines because the output of the buffer is low and this transient is highly attenuated by the combination of the termination resistor and the output impedance of the buffer. A simple calculation illustrates the point. Assume that the output impedance is 5Ω. For the frequency of interest the attenuation is VB/VA = 55/5 = 11, where A and B are the points in Figure 38. In this case the voltage caused by the reflection is 2/11 = 0.18V. This voltage is transferred to the remaining transmission lines in sequence and following the same rules as before this voltage is seen at the end points of those lines. The lower the output resistance the higher the decoupling between the different lines. Furthermore one can see that at the endpoint of these transmission lines there is a normal transient equal to the original transient at the beginning point. However at all other points of the transmission line there is a step voltage at different distances from the startpoint depending at what point this is measured (see trace D). Measuring The Length Of A Transmission Line An open transmission line can be used to measure the length of a particular transmission line. As can be seen in Figure 42 the line of interest has a certain length. A transient is applied at T = 0 and at that point in time the wavefront starts traveling with an amplitude of V/2 towards the end of the line where it is reflected back to the startpoint. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 19 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com A INPUT R = Z0 B Z0 E A =1X BEGIN END TRANSMISSION LINE LENGTH V V/2 0 0 3 2 TIME (ns) 1 4 5 Figure 42. To calculate the length of the line it is necessary to measure immediately after the series termination resistor. The voltage at that point remains at half nominal voltage, thus V/2, until the reflection returns and the voltage jumps to V. During an interval of 5ns the signal travels to the end of the line where the wave front is reflected and returns to the measurement point. During the time interval when the wavefront is traveling to the end of the transmission line and back the voltage has a value of V/2. This interval is 10ns. The length can be calculated with the following formula: S = (V*T)/2 8 S= -9 (2 x 10 ) x (10 x 10 ) 2 = 1mtr (6) As calculated before in the Driving More Than One Input section the signal travels 20cm/ns so in 5ns this distance indicated distance is 1m. So this example is easily verified. APPLYING A CAPACITIVE LOAD The assumption of pure resistance for the purpose of connecting the output stage of a buffer or opamp to a load is appropriate as a first approximation. Unfortunately that is only a part of the truth. Associated with this resistor is a capacitor in parallel and an inductor in series. Any capacitance such as CL-1 which is connected directly to the output stage is active in the loop gain as seen in Figure 43. Output capacitance, present also at the minus input in the case of a buffer, causes an increasing phase shift leading to instability or even oscillation in the circuit. RIN + - V V + RSERIES - CL-1 CL-2 BUFFER INTERNAL CONNECTIONS Figure 43. Unfortunately the leads of the output capacitor also contain series inductors which become more and more important at high frequencies. At a certain frequency this series capacitor and inductor forms an LC combination which becomes series resonant. At the resonant frequency the reactive component vanishes leaving only the ohmic resistance (R-1 or R-2) of the series L/C combination. (see Figure 44). 20 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 + RIN RSERIES V + - V - BUFFER INTERNAL CONNECTIONS CL-1 CL-2 L-1 L-2 R-1 R-2 Figure 44. Consider a frequency sweep over the entire spectrum for which the LMH6559 high frequency buffer is active. In the first instance peaking occurs due to the parasitic capacitance connected at the load whereas at higher frequencies the effects of the series combination of L and C become noticeable. This causes a distinctive dip in the output frequency sweep and this dip varies depending upon the particular capacitor as seen in Figure 45. 12 6 CL = 47pF 0 CL = 22pF GAIN (dB) -6 CL = 10pF -12 CL = 4.7pF -18 -24 CL = 0pF -30 -36 -42 VS = 10V -48 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 45. To minimize peaking due to CL a series resistor for the purpose of isolation from the output stage should be used. A low valued resistor will minimize the influence of such a load capacitor. In a 50Ω system as is common in high frequency circuits a 50Ω series resistor is often used. Usage of the series resistor, as seen in Figure 46 eliminates the peaking but not the dip. The dip will vary with the particular capacitor. Using a resistor in series with a capacitor creates in a single pole situation a 6dB/oct rolloff. However, at high frequencies the internal inductance is appreciable and forms a series LC combination with the capacitor. Choice of a higher valued resistor, for example 500 to 1kΩ, and a capacitor of hundreds of pF's provides the expected response at lower frequencies. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 21 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com 6 CL = 0pF 0 -6 CL = 10pF, RS = 50: GAIN (dB) -12 CL = 47pF, RS = 50: -18 CL = 100pF, RS = 50: -24 -30 -36 -42 VS = 10V -48 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 46. USING GROUND PLANES The use of ground planes is recommended both for providing a low impedance path to ground (or to one of the other supply voltages) and also for forming effective controlled impedance transmission lines for the high frequency signal flow on the board. Multilayer boards often make use of inner conductive layers for routing supply voltages. These supply voltage layers form a complete plane rather than using discrete traces to connect the different points together for the specified supply. Signal traces on the other hand are routed on outside layers both top and bottom. This allows for easy access for measurement purposes. Fortunately, only very high density boards have signal layers in the middle of the board. In an earlier section, the formula for Z0 was derived as: (5.98 x h) (0.8W) 87 Z= x ln Hr + 1.41) (7) The width of a trace is determined by the thickness of the board. In the case of a multilayer board the thickness is the space between the trace and the first supply plane under this trace layer. By common practice, layers do not have to be evenly divided in the construction of a pcb. Refer to Figure 47. The design of a transmission line design over a pcb is based upon the thickness of the different internal layers and the εr of the board material. The pcb manufacturer can supply information about important specifications. For example, a nominal 1.6mm thick pcb produces a 50Ω trace for a calculated width of 2.9mm. If this layer has a thickness of 0.35mm and for the same εr, the trace width for 50Ω should be of 0.63mm, as calculated from Equation 8, a derivation from Equation 7. w= 5.98 x h e A ZO x (Hr + 1.41) where A = 22 87 (8) Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 TRACK WIDTH HEIGHT OVER GROUND PLANE (w) (h) UPPER TRACK LAYER INNER LAYER A TOTAL PCB HEIGHT INNER LAYER B BOTTOM TRACK LAYER Figure 47. Using a trace over a ground plane has big advantages over the use of a standard single or double sided board. The main advantage is that the electric field generated by the signal transported over this trace is fixed between the trace and the ground plane e.g. there is almost no possibility of radiation (see Figure 48). TRACKWIDTH GROUNDPLANE Figure 48. This effect works to both sides because the circuit will not generate radiation but the circuit is also not sensible if exposed to a certain radiation level. The same is also noticeable when placing components flat on the printed circuit board. Standard through hole components when placed upright can act as an antenna causing an electric field which could be picked up by a nearby upright component. If placed directly at the surface of the pcb this influence is much lower. The Effect Of Variation For εr When using pcb material the εr has a certain shift over the used frequency spectrum, so if necessary to work with very accurate trace impedances one must taken into account for which frequency region the design has to be functional. Figure 49 (Courtesy of Islola Corporation) gives an example what the drift in εr will be when using the pcb material produced by Isola. If working at frequencies of 100MHz then a 50Ω trace has a width of 3.04mm for standard 1.6mm FR4 pcb material, and the same trace needs a width of 3.14mm. for frequencies around 10GHz. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 23 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com RELATIVE DIELECTRIC CONSTANT (Hr 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 1M RESIN = 40% RESIN = 45% RESIN = 50% RESIN = 55% RESIN = 60% 10M 100M 1G 10G FREQUENCY (Hz) Figure 49. Routing Power Traces Power line traces routed over a pcb should be kept together for best practice. If not a ground loop will occur which may cause more sensitivity to radiation. Also additional ground trace length may lead to more ringing on digital signals. Careful attention to power line distribution leads to improved overall circuit performance. This is especially valid for analog circuits which are more sensitive to spurious noise and other unwanted signals. + V GND Figure 50. As demonstrated in Figure 50 the power lines are routed from both sides on the pcb. In this case a current loop is created as indicated by the dotted line. This loop can act as an antenna for high frequency signals which makes the circuit sensitive to RF radiation. A better way to route the power traces can be seen in the following setup. (see Figure 51) 24 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 V + GND Figure 51. In this arrangement the power lines have been routed in order to avoid ground loops and to minimize sensitivity to noise etc. The same technique is valid when routing a high frequent signal over a board which has no ground plane. In that case is it good practice to route the high frequency signal alongside a ground trace. A still better way to create a pcb carrying high frequency signals is to use a pcb with a ground plane or planes. Discontinuities In A Ground Plane A ground plane with traces routed over this plane results in the build up of an electric field between the trace and the ground plane as seen in Figure 48. This field is build up over the entire routing of the trace. For the highest performance the ground plane should not be interrupted because to do so will cause the field lines to follow a roundabout path. In Figure 52 it was necessary to interrupt the ground plane with a crossing trace. This interruption causes the return current to follow a longer route than the signal path follows to overcome the discontinuity. RETURN PATH + V SIGNAL IN GND Figure 52. If needed it is possible to bypass the interruption with traces that are parallel to the signal trace in order to reduce the negative effects of the discontinuity in the ground plane. In doing so, the current in the ground plane closely follows the signal trace on the return path as can be seen in Figure 53. Care must be taken not to place too many traces in the ground plane or the ground plane effectively vanishes such that even bypasses are unsuccessful in reducing negative effects. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 25 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com RETURN PATH + SIGNAL IN V GND Figure 53. If the overall density becomes too high it is better to make a design which contains additional metal layers such that the ground planes actually function as ground planes. The costs for such a pcb are increased but the payoff is in overall effectiveness and ease of design. Ground Planes At Top And Bottom Layer Of A PCB In addition to the bottom layer ground plane another useful practice is to leave as much copper as possible at the top layer. This is done to reduce the amount of copper to be removed from the top layer in the chemical process. This causes less pollution of the chemical baths allowing the manufacturer to make more pcb's with a certain amount of chemicals. Connecting this upper copper to ground provides additional shielding and signal performance is enhanced. For lower frequencies this is specifically true. However, at higher frequencies other effects become more and more important such that unwanted coupling may result in a reduction in the bandwidth of a circuit. In the design of a test circuit for the LMH6559 this effect was clearly noticeable and the useful bandwidth was reduced from 1500MHz to around 850MHz. 3 VS = 10V 0 GAIN (dB) WITH COPPER FIELD -3 -6 -9 -12 10M 100M FREQUENCY (Hz) 1G 2G Figure 54. As can be seen in Figure 54 the presence of a copper field close to the transmission line to and from the buffer causes unwanted coupling effects which can be seen in the dip at about 850MHz. This dip has a depth of about 5dB for the case when all of the unused space is filled with copper. In case of only one area being filled with copper this dip is about 9dB. 26 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 LMH6559 www.ti.com SNOSA57C – APRIL 2003 – REVISED MARCH 2013 PCB Board Layout And Component Selection Sound practice in the area of high frequency design requires that both active and passive components be used for the purposes for which they were designed. It is possible to amplify signals at frequencies of several hundreds of MHz using standard through hole resistors. Surface mount devices, however, are better suited for this purpose. Surface mount resistors and capacitors are smaller and therefore parasitics are of lower value and therefore have less influence on the properties of the amplifier. Another important issue is the pcb itself, which is no longer a simple carrier for all the parts and a medium to interconnect them. The pcb board becomes a real component itself and consequently contributes its own high frequency properties to the overall performance of the circuit. Sound practice dictates that a design have at least one ground plane on a pcb which provides a low impedance path for all decoupling capacitors and other ground connections. Care should be taken especially that on- board transmission lines have the same impedance as the cables to which they are connected - 50Ω for most applications and 75Ω in case of video and cable TV applications. Such transmission lines usually require much wider traces on a standard double sided PCB board than needed for a 'normal' trace. Another important issue is that inputs and outputs must not 'see' each other. This occurs if inputs and outputs are routed together over the pcb with only a small amount of physical separation, particularly when there is a high differential in signal level between them. Furthermore components should be placed as flat and low as possible on the surface of the PCB. For higher frequencies a long lead can act as a coil, a capacitor or an antenna. A pair of leads can even form a transformer. Careful design of the pcb avoids oscillations or other unwanted behaviors. For ultra high frequency designs only surface mount components will give acceptable results. (for more information see OA-15 (Literature Number SNOA367). TI suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Device Package Evaluation Board Part Number LMH6559MA SOIC CLC730245 LMH6559MAX SOIC CLC730245 LMH6559MF SOT-23 CLC730136 LMH6559MFX SOT-23 CLC730136 These free evaluation boards are shipped when a device sample request is placed with Texas Instruments. POWER SEQUENCING OF THE LMH6559 Caution should be exercised in applying power to the LMH6559. When the negative power supply pin is left floating it is recommended that other pins, such as positive supply and signal input should also be left unconnected. If the ground is floating while other pins are connected the input circuitry is effectively biased to ground, with a mostly low ohmic resistor, while the positive power supply is capable of delivering significant current through the circuit. This causes a high input bias current to flow which degrades the input junction. The result is an input bias current which is out of specification. When using inductive relays in an application care should be taken to connect first both power connections before connecting the bias resistor to the input. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 27 LMH6559 SNOSA57C – APRIL 2003 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 28 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 27 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6559 PACKAGE OPTION ADDENDUM www.ti.com 4-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMH6559MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH6559MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH65 59MA LMH6559MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH65 59MA LMH6559MF ACTIVE SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 LMH6559MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 B05A LMH6559MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 B05A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Jan-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jan-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6559MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6559MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6559MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jan-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6559MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6559MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6559MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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