AD AD7656ABSTZ-RL 250 ksps, 6-channel, simultaneous sampling, bipolar 16-bit adc Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
6 independent analog-to-digital converters (ADCs)
True bipolar analog inputs
Pin-/software-selectable ranges: ±10 V or ±5 V
Fast throughput rate: 250 kSPS
iCMOS® process technology
Low power: 140 mW at 250 kSPS with 5 V supplies
Wide input bandwidth
86.5 dB SNR at 50 kHz input frequency
On-chip reference and reference buffers
Parallel, serial, and daisy-chain interface modes
High speed serial interface
Serial peripheral interface (SPI)/QSPI™/MICROWIRE®/DSP
compatible
Power-down mode: 100 mW maximum
64-lead LQFP
Improved power supply sequencing (PSS) robustness
CONVST A
VDD
CONVST B CONVST C AVCC
CLK
OSC
REF
DVCC
CS
SER/PAR/SEL
VDRIVE
CONTROL
LOGIC
STBY
BUF
V1
T/H
16-BIT SAR
V2
T/H
16-BIT SAR
OUTPUT
DRIVERS
DB8/DOUT A
SCLK
OUTPUT
DRIVERS
BUF
V3
T/H
V4
T/H
16-BIT SAR
OUTPUT
DRIVERS
DB10/DOUT C
OUTPUT
DRIVERS
DATA/
CONTROL
LINES
16-BIT SAR
BUF
V5
T/H
16-BIT SAR
V6
T/H
16-BIT SAR
DB9/DOUT B
RD
WR/REFEN/DIS
APPLICATIONS
AD7656A
VSS
Power line monitoring systems
Instrumentation and control systems
Multi-axis positioning systems
AGND
DGND
11127-001
Data Sheet
250 kSPS, 6-Channel, Simultaneous
Sampling, Bipolar 16-Bit ADC
AD7656A
Figure 1.
GENERAL DESCRIPTION
The AD7656A1 contains six 16-bit, fast, low power, successive
approximation analog-to-digital converters (ADCs) all in the
one package that is designed on the iCMOS® process (industrial
CMOS). iCMOS is a process combining high voltage silicon
with submicron CMOS and complementary bipolar technologies.
It enables the development of a wide range of high performance
analog ICs, capable of 33 V operation in a footprint that no
previous generation of high voltage devices could achieve. Unlike
analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, which dramatically reduces power
consumption and package size.
The AD7656A features throughput rates of up to 250 kSPS. It
contains wide bandwidth (12 MHz), track-and-hold amplifiers
that can handle input frequencies up to 12 MHz.
1
The conversion process and data acquisition are controlled
using CONVST x signals and an internal oscillator. Three
CONVST x pins (CONVST A, CONVST B, and CONVST C)
allow independent, simultaneous sampling of the three ADC
pairs. The AD7656A has a high speed parallel and serial interface,
allowing the device to interface with microprocessors or digital
signal processors (DSPs). In serial interface mode, the AD7656A
has a daisy-chain feature that allows multiple ADCs to connect
to a single serial interface. The AD7656A can accommodate
true bipolar input signals in the ±4 × VREF range and ±2 × VREF
range. The AD7656A also contains an on-chip 2.5 V reference.
Multifunction pin names may be referenced by their relevant
function only.
PRODUCT HIGHLIGHTS
1.
2.
3.
Six 16-bit, 250 kSPS ADCs on board.
Six true bipolar, high impedance analog inputs.
Parallel and high speed serial interfaces.
Protected by U.S. Patent No. 6,731,232.
Rev. 0
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Last Content Update: 04/14/2017
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DOCUMENTATION
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Application Notes
• Symbols and Footprints
• AN-893: Configuring the AD7656/AD7657/AD7658 for
Serial and Daisy-Chain Interface Modes of Operation
DISCUSSIONS
• AN-931: Understanding PulSAR ADC Support Circuitry
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Data Sheet
• AD7656A: 250 kSPS, 6-Channel, Simultaneous Sampling,
Bipolar 16-Bit ADC Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
User Guides
• UG-535: Evaluating the AD7656/AD7657/AD7658, 250
kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-/14-/
12-Bit ADCs
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AD7656A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Applications ....................................................................................... 1
Converter Details ....................................................................... 15
Functional Block Diagram .............................................................. 1
ADC Transfer Function ............................................................. 16
General Description ......................................................................... 1
Reference Section ....................................................................... 16
Product Highlights ........................................................................... 1
Typical Connection Diagram ................................................... 16
Revision History ............................................................................... 2
Driving the Analog Inputs ........................................................ 17
Specifications..................................................................................... 3
Interface Section ......................................................................... 17
Timing Specifications .................................................................. 5
Software Selection of ADCs ...................................................... 19
Absolute Maximum Ratings ............................................................ 6
Serial Read Operation................................................................ 21
Power Supply Sequencing ........................................................... 6
Daisy-Chain Mode (DCEN = 1, SER/PAR/SEL = 1) ............. 21
Thermal Resistance ...................................................................... 6
Application Hints ........................................................................... 24
ESD Caution .................................................................................. 6
Layout .......................................................................................... 24
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 25
Typical Performance Characteristics ........................................... 10
Ordering Guide .......................................................................... 25
Terminology .................................................................................... 13
REVISION HISTORY
12/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
AD7656A
SPECIFICATIONS
VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, and VDRIVE = 2.7 V to 5.25 V. For the ±4 × VREF range,
VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to −16.5 V. fSAMPLE =
250 kSPS, and TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD) 1
Signal-to-Noise Ratio (SNR)1
Total Harmonic Distortion (THD)1
RANGE Pin = 0
RANGE Pin = 1
Peak Harmonic or Spurious Noise (SFDR)1
Intermodulation Distortion (IMD)1
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Channel-to-Channel Isolation1
Full Power Bandwidth
DC ACCURACY
Resolution
No Missing Codes
Min
Typ
84
85
85.5
86.5
−90
−92
−100
−100
10
4
35
−100
12
2
16
15
16
±3
±1
±0.22%
Positive Full-Scale Error1
Positive Full-Scale Error Matching1
Bipolar Zero-Scale Error1
Bipolar Zero-Scale Error Matching1
Negative Full-Scale Error1
Negative Full-Scale Error Matching1
ANALOG INPUT
±0.004%
±0.22%
−4 × VREF
−2 × VREF
DC Leakage Current
Input Capacitance 2
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
Input Capacitance2
Reference Output Voltage
Long-Term Stability
Reference Temperature Coefficient
Unit
dB
dB
dB
dB
dB
dB
Test Conditions/Comments
fIN = 50 kHz sine wave
VDD/VSS = ±6 V to ±11 V
VDD/VSS = ±12 V to ±16.5 V
fa = 50 kHz, fb = 49 kHz
−112
−107
Integral Nonlinearity1
Input Voltage Ranges
Max
±0.75
±0.35
±0.023
±0.038
±0.75
±0.35
+4 × VREF
+2 × VREF
±1
10
14
2.5
3
±1
18.5
2.49
2.51
150
25
6
Rev. 0 | Page 3 of 28
dB
dB
ns
ns
ps
dB
MHz
MHz
Bits
Bits
Bits
LSB
LSB
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
V
V
µA
pF
pF
V
µA
pF
V
ppm
ppm/°C
ppm/°C
fIN on unselected channels up to 100 kHz
At −3 dB
At −0.1 dB
At 25°C
See Table 6 for the minimum VDD/VSS
for each range
RANGE pin = 0
RANGE pin = 1
±4 × VREF range when in track mode
±2 × VREF range when in track mode
REFEN/DIS = 1 3
1000 hours
AD7656A
Parameter
LOGIC INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)2
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Floating State Output Capacitance2
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time1, 2
Throughput Rate
POWER REQUIREMENTS
VDD Range
VSS Range
AVCC
DVCC
VDRIVE
ITOTAL 4
Normal Mode (Static)
Data Sheet
Min
Typ
Max
Unit
0.3 × VDRIVE
±1
10
V
V
µA
pF
0.2
±1
10
V
V
µA
pF
3.1
550
250
µs
ns
kSPS
16.5
−16.5
5.25
5.25
5.25
V
V
V
V
V
28
mA
26
mA
0.25
0.25
7
mA
mA
mA
80
mA
143
140
35
100
mW
mW
mW
mW
0.7 × VDRIVE
VDRIVE − 0.2
6
−6
4.75
4.75
2.7
Normal Mode (Operational)
ISS (Operational)
IDD (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
Power Dissipation
Normal Mode (Static)
Normal Mode (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
See the Terminology section.
Sample tested during initial release to ensure compliance.
3
Multifunction pin names may be referenced by their relevant function only.
4
Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC.
1
2
Rev. 0 | Page 4 of 28
Test Conditions/Comments
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 µA
ISINK = 200 µA
Parallel interface mode only
For the 4 × VREF range, VDD = 11 V to 16.5 V
For the 4 × VREF range, VSS = −11 V to −16.5 V
Digital inputs = 0 V or VDRIVE
AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE =
5.25 V, VDD = 16.5 V, VSS = −16.5 V
VSS = −16.5 V, fSAMPLE = 250 kSPS
VDD = 16.5 V, fSAMPLE = 250 kSPS
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
SCLK on or off, AVCC = DVCC = VDRIVE =
5.25 V, VDD = 16.5 V, VSS = −16.5 V
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS
Data Sheet
AD7656A
TIMING SPECIFICATIONS
AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the
±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V, and for the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to
−16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and
timed from a voltage level of 1.6 V.
Table 2.
Parameter
PARALLEL INTERFACE MODE
tCONVERT
tQUIET
tACQ
t1
t10
tWAKE-UP
PARALLEL WRITE OPERATION
t11
t12
t13
t14
t15
PARALLEL READ OPERATION
t2
t3
t4
t5
t6
t7
t8
t9
SERIAL INTERFACE MODE
fSCLK
t16
t17 2
t18
t19
t20
t21
2
Unit
Description 1
3
150
3
150
µs typ
ns min
550
60
25
2
550
60
25
2
ns min
ns min
ns min
ms max
25
25
µs max
Conversion time, internal clock
Minimum quiet time required between bus relinquish
and start of next conversion
Acquisition time
CONVST x high to BUSY high
Minimum CONVST x low pulse
STBY rising edge to CONVST x rising edge, not
shown in figures
Partial power-down mode
15
0
5
5
5
15
0
5
5
5
ns min
ns min
ns min
ns min
ns min
WR pulse width
CS to WR setup time
CS to WR hold time
Data setup time before WR rising edge
Data hold after WR rising edge
0
0
0
45
45
10
12
6
0
0
0
36
36
10
12
6
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
BUSY to RD delay
CS to RD setup time
CS to RD hold time
RD pulse width
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
Frequency of serial read clock
Delay from CS until SDATA three-state disabled
Data access time after SCLK rising edge/CS falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK falling edge
CS rising edge to SDATA high impedance
Multifunction pin names may be referenced by their relevant function only.
A buffer is used on the data output pins for this measurement.
200µA
TO OUTPUT
PIN
IOL
1.6V
CL
25pF
200µA
IOH
11127-002
1
Limit at TMIN, TMAX
VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 28
AD7656A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
POWER SUPPLY SEQUENCING
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to AGND, DGND
VSS to AGND, DGND
VDD to AVCC
AVCC to AGND, DGND
DVCC to AVCC
DVCC to DGND, AGND
AGND to DGND
VDRIVE to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
REFIN/REFOUT to AGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Pb/Sn Temperature, Soldering
Reflow (10 sec to 30 sec)
Pb-Free Temperature, Soldering Reflow
1
Rating
0 V to +16.5 V
0 V to −16.5 V
AVCC + 0.7 V to 16.5 V
−0.3 V to +7 V
−0.3 V to AVCC + 0.3 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to DVCC + 0.3 V
VSS + 1 V to VDD − 1 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
±10 mA
−40°C to +85°C
−65°C to +150°C
150°C
Simultaneous application of VDD and VSS is necessary to
guarantee reliability of the device. In the cases where
simultaneous application cannot be guaranteed, VDD must power
up before VSS. When a negative voltage is applied to the analog
inputs before VDD and VSS are fully powered up, a 560 Ω resistor
must be placed on the analog inputs.
A number of sequencing combinations can lead to temporary
high current states; however, when all supplies are powered up,
the device returns to normal operating currents. The analog
input (AIN) coming before AVCC causes temporary high current
on the analog inputs. Digital inputs before DVCC, and DVCC
before other supplies, also cause temporary high current states.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.
Table 4. Thermal Resistance
Package Type
64-Lead LQFP
240(0)°C
260(0)°C
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 28
θJA
45
θJC
11
Unit
°C/W
Data Sheet
AD7656A
1
DB13
2
DB12
3
AVCC
AGND
AGND
REFIN/REFOUT
AGND
REFCAPA
REFCAPB
AGND
REFCAPC
64 63 62 61 60 59 58
DB14/REFBUF EN/DIS
AGND
AGND
AVCC
H/S SEL
SER/PAR/SEL
WR/REFEN/DIS
DB15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
57 56 55 54 53 52 51 50 49
48 V6
PIN 1
47 AVCC
46 AVCC
DB11
4
45 V5
DB10/DOUT C
5
44 AGND
DB9/DOUT B
6
DB8/DOUT A
7
DGND
8
VDRIVE
9
43 AGND
AD7656A
42 V4
TOP VIEW
(Not to Scale)
41 AVCC
40 AVCC
39 V3
DB7/HBEN/DCEN 10
DB6/SCLK 11
38 AGND
DB5/DCIN A 12
37 AGND
DB4/DCIN B 13
36 V2
DB3/DCIN C 14
35 AVCC
DB2/SEL C 15
34 AVCC
33 V1
DB1/SEL B 16
11127-003
VDD
AGND
VSS
W/B
RESET
RANGE
DVCC
DGND
STBY
CONVST A
CONVST B
CONVST C
RD
CS
BUSY
DB0/SEL A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions 1
Pin No.
1
Mnemonic
DB14/REFBUFEN/DIS
2, 3, 64
DB13, DB12, DB15
4
DB11
5
DB10/DOUT C
6
DB9/DOUT B
7
DB8/DOUT A
8, 25
DGND
9
VDRIVE
Description
Data Bit 14/Reference Buffer Enable and Disable. When SER/PAR/SEL = 0, this pin acts as a threestate digital input/output pin.
Data Bit 13, Data Bit 12, and Data Bit 15. When SER/PAR/SEL = 0, these pins act as three-state parallel
digital input/output pins. When CS and RD are low, these pins are used to output the conversion
result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR/SEL =
1, tie these pins to DGND.
Data Bit 11/Digital Ground. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR/SEL = 1, tie this pin to DGND.
Data Bit 10/Serial Data Output C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR/SEL = 1 and SEL C = 1, this pin takes on its DOUT C function and outputs
serial conversion data. this pin configures the serial interface to have three DOUT x output lines.
Data Bit 9/Serial Data Output B. When SER/PAR/SEL = 0, Pin 6 acts as a three-state parallel digital
output pin. When SER/PAR/SEL = 1 and SEL B = 1, Pin 6 takes on its DOUT B function and outputs
serial conversion data. this pin configures the serial interface to have two DOUT x output lines.
Data Bit 8/Serial Data Output A. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR/SEL = 1 and SEL A = 1, this pin takes on its DOUT A function and outputs
serial conversion data.
Digital Ground. These pins are the ground reference point for all digital circuitry on the AD7656A.
Connect both DGND pins to the DGND plane of a system. Ideally, the DGND and AGND voltages are at
the same potential and must not be more than 0.3 V apart, even on a transient basis.
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the
interface. Nominally, it is at the same supply as the supply of the host interface. Decouple this pin to
DGND, and place 10 µF and 100 nF decoupling capacitors on the VDRIVE pin.
Rev. 0 | Page 7 of 28
AD7656A
Data Sheet
Pin No.
10
Mnemonic
DB7/HBEN/DCEN
11
DB6/SCLK
12
DB5/DCIN A
13
DB4/DCIN B
14
DB3/DCIN C
15
DB2/SEL C
16
DB1/SEL B
17
DB0/SEL A
18
BUSY
19
CS
20
RD
21, 22, 23
CONVST C,
CONVST B,
CONVST A
24
STBY
26
DVCC
Description
Data Bit 7/High Byte Enable/Daisy-Chain Enable. When operating in parallel word mode (SER/PAR/SEL
= 0 and W/B = 0), Pin 10 takes on its Data Bit 7 function. When operating in parallel byte mode
(SER/PAR/SEL = 0 and W/B = 1), Pin 10 takes on its HBEN function. When in this mode and the HBEN
pin is logic high, the data is output MSB byte first on DB15 to DB8. When the HBEN pin is logic low,
the data is output LSB byte first on DB15 to DB8. When operating in serial mode (SER/PAR/SEL = 1),
Pin 10 takes on its DCEN function. When the DCEN pin is logic high, the AD7656A operates in daisychain mode with DB5 to DB3 taking on their DCIN A to DCIN C function. When operating in serial
mode but not in daisy-chain mode, tie DCEN to DGND.
Data Bit 6/Serial Clock. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR/SEL = 1, this pin takes on its SCLK input function; it is the read serial clock for the serial
transfer.
Data Bit 5/Daisy-Chain Input A. When SER/PAR/SEL is low, this pin acts as a three-state parallel
digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When
operating in serial mode but not in daisy-chain mode, tie this pin to DGND.
Data Bit 4/Daisy-Chain Input B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When
operating in serial mode but not in daisy-chain mode, tie this pin to DGND.
Data Bit 3/Daisy-Chain Input C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When
operating in serial mode but not in daisy-chain mode, tie this pin to DGND.
Data Bit 2/Select DOUT C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR/SEL = 1, this pin takes on its SEL C function; it is used to configure the serial
interface. If this pin is 1, the serial interface operates with three DOUT output pins and enables
DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data
output pin. Leave unused serial DOUT pins unconnected.
Data Bit 1/Select DOUT B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR/SEL = 1, this pin takes on its SEL B function; it is used to configure the serial
interface. If this pin is 1, the serial interface operates with two or three DOUT x output pins and
enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial
data output pin and only one DOUT output pin, DOUT A, is used. Leave unused serial DOUT pins
unconnected.
Data Bit 0/Select DOUT A. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR/SEL = 1, Pin 17 takes on its SEL A function; it is used to configure the serial
interface. If this pin is 1, the serial interface operates with one, two, or three DOUT x output pins and
enables DOUT A as a serial output. When operating in serial mode, this pin must always be 1.
Busy Output. This pin transitions high when a conversion is started and remains high until the
conversion is complete and the conversion data is latched into the output data registers. Do not
initiate a new conversion on the AD7656A when the BUSY signal is high.
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low
in parallel mode, the output bus is enabled and the conversion result is output on the parallel data
bus lines. When both CS and WR are logic low in parallel mode, DB15 to DB8 are used to write data
to the on-chip control register. In serial mode, the CS is used to frame the serial read transfer and
clock out the MSB of the serial output data.
Read Data. When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial
mode, hold the RD line low.
Conversion Start Input C, Conversion Start Input B, and Conversion Start Input A. These logic inputs
are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions
on V1 and V2, CONVST B is used to initiate simultaneous conversions on V3 and V4, and CONVST C is
used to initiate simultaneous conversions on V5 and V6. When CONVST x switches from low to high,
the track-and-hold switch on the selected ADC pair switches from track to hold, and the conversion
is initiated. These inputs can also be used to place the ADC pairs into partial power-down mode.
Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is
high for normal operation and low for standby operation.
Digital Power, 4.75 V to 5.25 V. Ideally, the DVCC and AVCC voltages are at the same potential and must
not be more than 0.3 V apart, even on a transient basis. Decouple this supply to DGND, and place
10 µF and 100 nF decoupling capacitors on the DVCC pin.
Rev. 0 | Page 8 of 28
Data Sheet
Pin No.
27
Mnemonic
RANGE
28
RESET
29
W/B
30
VSS
31
VDD
32, 37, 38, 43,
44, 49, 52, 53,
55, 57, 59
AGND
33, 36, 39,
42, 45, 48
V1 to V6
34, 35, 40,
41, 46, 47,
50, 60
AVCC
51
REFIN/REFOUT
54, 56, 58
REFCAPA, REFCAPB,
REFCAPC
61
SER/PAR/SEL
62
H/S SEL
63
WR/REFEN/DIS
1
AD7656A
Description
Analog Input Range Selection. Logic input. The logic level on this pin determines the input range
of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the
next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the
next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge
of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is
determined by the RNGA, RNGB, and RNGC bits in the control register.
Reset Input. When set to logic high, this pin resets the AD7656A, and the current conversion, if
any, is aborted. The internal register is set to all 0s. In hardware mode, the AD7656A is configured
depending on the logic levels on the hardware select pins. In all modes, after power-up, the device
must receive a RESET pulse. The reset high pulse is typically 100 ns wide. After the RESET pulse, the
AD7656A needs to see a valid CONVST pulse to initiate a conversion; this typically consists of a highto-low CONVST edge followed by a low-to-high CONVST edge. During the RESET pulse, the CONVST x
signal must be high.
Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656A using
the parallel data lines DB15 to DB0. When this pin is logic high, byte mode is enabled. In this mode,
data is transferred using data lines DB15 to DB8 and DB7 takes on its HBEN function. To obtain the
16-bit conversion result, 2-byte reads are required. In serial mode, tie this pin to DGND.
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. Place
10 µF and 100 nF decoupling capacitors on the VSS pin.
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. Place
10 µF and 100 nF decoupling capacitors on the VDD pin.
Analog Ground. Ground reference point for all analog circuitry on the AD7656A. Refer all analog input
signals and any external reference signal to the AGND voltage. Connect all AGND pins to the AGND
plane of a system. Ideally, the AGND and DGND voltages are at the same potential and must not be
more than 0.3 V apart, even on a transient basis.
Analog Input 1 to Analog Input 6. These are six single-ended analog inputs. In hardware mode,
the analog input range on these channels is determined by the RANGE pin. In software mode, it
is determined by Bit RNGC to Bit RNGA of the control register (see Table 9).
Analog Supply Voltage, 4.75 V to 5.25 V. The AVCC pin is the supply voltage for the ADC cores. Ideally,
the AVCC and DVCC voltages are at the same potential and must not be more than 0.3 V apart, even
on a transient basis. Decouple these supply pins to AGND, and place 10 µF and 100 nF decoupling
capacitors on the AVCC pins.
Reference Input/Reference Output. The on-chip reference is available on Pin 51 for external use to
the AD7656A. Alternatively, the internal reference can be disabled and an external reference can be
applied to this input. See the Reference Section. When the internal reference is enabled, decouple
Pin 51 using at least a 10 µF decoupling capacitor.
Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are
connected to these pins, which decouples the reference buffer for each ADC pair. Decouple each
REFCAPx pin to AGND using 10 µF and 100 nF capacitors.
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is
high, the serial interface mode is selected. In serial mode, DB10 to DB8 take on their DOUT C to
DOUT A function, DB0 to DB2 take on their DOUT select function, and DB7 takes on its DCEN
function. In serial mode, tie DB15 and DB13 to DB11 to DGND
Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656A operates in hardware
select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST x pins.
When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the
control register. In serial mode, CONVST A is used to initiate conversions on the selected ADC pairs.
Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low,
DB15 to DB8 are used to write data to the internal control register. When the H/S SEL pin is low, this
pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal
reference is disabled, and an external reference must be applied to the REFIN/REFOUT pin. When
H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin must be
decoupled. See the Reference Section.
Multifunction pin names may be referenced by their relevant function only.
Rev. 0 | Page 9 of 28
AD7656A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
2.0
VDD/VSS = ±15V
AVCC/DVCC/VDRIVE = +5V
INTERNAL REFERENCE
±10V RANGE
TA = 25°C
fS = 250kSPS
fIN = 50kHz
SNR = +87.33dB
SINAD = +87.251dB
THD = –104.32dB
SFDR = –104.13dB
–40
–80
1.0
–100
0.5
0
–0.5
11127-004
–140
–160
0
25
50
75
100
125
FREQUENCY (kHz)
90
VDD/VSS = ±12V
AVCC/DVCC/VDRIVE = +5V
INTERNAL REFERENCE
±5V RANGE
TA = 25°C
fS = 250kSPS
fIN = 50kHz
SNR = +86.252dB
SINAD = +86.196dB
THD = –105.11dB
SFDR = –98.189dB
80
75
AVCC/DVCC/
VDRIVE = +5V
VDD/VSS = ±5.25V
±5V RANGE
–100
70
–120
65 f
SAMPLE = 250kSPS
INTERNAL REFERENCE
TA = 25°C
60
10
11127-005
–140
–160
0
25
50
75
100
125
1000
100
ANALOG INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. SINAD vs. Analog Input Frequency
Figure 5. FFT for ±5 V Range
–60
2.0
AVCC/DVCC/VDRIVE = +5V
VDD/VSS = ±12V
1.5 fSAMPLE = 250kSPS
2 × VREF RANGE
1.0 INL WCP = 0.64LSB
INL WCN = –0.76LSB
–70
–80
THD (dB)
0.5
0
–0.5
–90
fSAMPLE = 250kSPS
INTERNAL REFERENCE
TA = 25°C
AVCC/DVCC/VDRIVE = +5V
VDD/VSS = ±5.25V
±5V RANGE
AVCC/DVCC/
VDRIVE = +4.75V
VDD/VSS = ±10V
±10V RANGE
AVCC/DVCC/
VDRIVE = +5V
VDD/VSS = ±12V
±5V RANGE
–100
AVCC/DVCC/
VDRIVE = +5.25V
VDD/VSS = ±16.5V
±10V RANGE
–1.0
–110
–1.5
11127-006
INL (LSB)
AVCC/DVCC/
VDRIVE = +5V
VDD/VSS = ±12V
±5V RANGE
AVCC/DVCC/
VDRIVE = +4.75 V
VDD/VSS = ±10V
±10V RANGE
11127-012
–80
60k 65535
AVCC/DVCC/VDRIVE = +5.25V
VDD/VSS = ±16.5V
±10V RANGE
85
SINAD (dB)
(dB)
–60
50k
Figure 7. Typical DNL
0
–40
40k
CODE
Figure 4. FFT for ±10 V Range
–20
11127-007
AVCC/DVCC/VDRIVE = +5V
–1.0 V /V = ±12V
DD SS
fSAMPLE = 250kSPS
2
× VREF RANGE
–1.5
DNL WCP = 0.81LSB
DNL WCN = –0.57LSB
–2.0
0
10k
20k
30k
–120
–2.0
0
10k
20k
30k
40k
50k
60k 65535
–120
10
100
ANALOG INPUT FREQUENCY (kHz)
CODE
Figure 9. THD vs. Analog Input Frequency
Figure 6. Typical INL
Rev. 0 | Page 10 of 28
11127-013
(dB)
–60
1.5
DNL (LSB)
–20
1000
Data Sheet
AD7656A
–60
3.20
VDD/VSS = ±16.5V
AVCC/DVCC/VDRIVE = +5.25V
TA = 25°C
–70 INTERNAL
REFERENCE
±4 × VREF RANGE
CONVERSION TIME (µs)
3.10
RSOURCE = 1000Ω
–90
RSOURCE = 100Ω
RSOURCE = 220Ω
3.05
3.00
2.95
2.90
2.85
RSOURCE = 10Ω
RSOURCE = 50Ω
–120
10
11127-017
2.80
–110
11127-014
2.75
2.70
–55
100
–35
–15
5
ANALOG INPUT FREQUENCY (kHz)
Figure 10. THD vs. Analog Input Frequency for Various Source Impedances,
±4 × VREF Range
RSOURCE = 100Ω
–100
–110
RSOURCE = 220Ω
125
105
RSOURCE = 50Ω
RSOURCE = 10Ω
–120
10
VDD/VSS = ±15V
AVCC/DVCC/VDRIVE = +5V
INTERNAL REFERENCE
8192 SAMPLES
2806
2500
2000
1532
1500
1000
500
11127-015
THD (dB)
RSOURCE = 1000Ω
–80
–90
392
0
0
–5
100
168
57
–4
–3
–2
ANALOG INPUT FREQUENCY (kHz)
–1
0
1
25
0
2
3
CODE
Figure 11. THD vs. Analog Input Frequency for Various Source Impedances,
±2 × VREF Range
Figure 14. Histogram of Codes
2.510
100
fSAMPLE = 250kSPS
±2 × VREF RANGE
INTERNAL REFERENCE
TA = 25°C
fIN = 10kHz
100nF ON VDD AND VSS
AVCC/DVCC/VDRIVE = +5V
VDD/VSS = ±12V
90
2.506
80
PSRR (dB)
2.504
2.502
2.500
70
VSS
60
2.498
VDD
2.496
2.494
2.492
–55
–35
–15
5
25
45
65
85
105
125
40
30
11127-019
50
11127-016
REFERENCE VOLTAGE (V)
85
3212
3000
–70
2.508
65
3500
VDD/VSS = ±12V
AVCC/DVCC/VDRIVE = +5V
TA = 25°C
INTERNAL REFERENCE
±2 × VREF RANGE
NUMBER OF OCCURRENCES
–60
45
Figure 13. Conversion Time vs. Temperature
–40
–50
25
TEMPERATURE (°C)
11127-018
THD (dB)
–80
–100
AVCC/DVCC/VDRIVE = +5V
VDD/VSS = ±12V
3.15
80
130
180
230
280
330
380
430
SUPPLY RIPPLE FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 12. Reference Voltage vs. Temperature
Figure 15. PSRR vs. Supply Ripple Frequency
Rev. 0 | Page 11 of 28
480
530
AD7656A
Data Sheet
120
86.5
86.0
SNR (dB)
85.5
±5V RANGE
AVCC/DVCC/VDRIVE = +5V
VDD/VSS = ±12V
±10V RANGE
AVCC/DVCC/VDRIVE = +5.25V
VDD/VSS = ±16.5V
85.0
84.5
83.5 fSAMPLE = 250kSPS
fIN = 50kHz
INTERNAL REFERENCE
83.0
–40
–20
0
20
40
11127-020
84.0
60
80
100
120
110
100
90
80
AVCC/DVCC/VDRIVE = 5V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REFERENCE
±2 × VREF RANGE
30kHz ON SELECTED CHANNEL
70
60
0
140
20
40
60
80
140
120
100
FREQUENCY OF INPUT NOISE (kHz)
TEMPERATURE (°C)
Figure 16. SNR vs. Temperature
Figure 18. Channel-to-Channel Isolation
30
–100
–101
11127-022
CHANNEL-TO-CHANNEL ISOLATION (dB)
87.0
fSAMPLE = 250kSPS
fIN = 50kHz
INTERNAL REFERENCE
25
–103
–104
±5V RANGE
AVCC/DVCC/VDRIVE = +5V
VDD/VSS = ±12V
–105
–107
–40
–20
0
20
40
60
80
20
±5V RANGE
15
10
AVCC/DVCC/VDRIVE = +5V
fSAMPLE = 250kSPS
FOR ±5V RANGE VDD/VSS = ±12V
FOR ±10V RANGE VDD/VSS = ±16.5V
5
–106
11127-021
THD (dB)
±10V RANGE
AVCC/DVCC/VDRIVE = +5.25V
VDD/VSS = ±16.5V
100
120
140
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Dynamic Current vs. Temperature
Figure 17. THD vs. Temperature
Rev. 0 | Page 12 of 28
11127-023
DYNAMIC CURRENT (mA)
±10V RANGE
–102
100
Data Sheet
AD7656A
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a ½ LSB below
the first code transition and full scale at ½ LSB above the last
code transition.
Signal-to-Noise-and-Distortion (SINAD) Ratio
The SINAD ratio is the measured ratio of signal-to-noise-anddistortion at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fSAMPLE/2, excluding dc).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
The ratio depends on the number of quantization levels in the
digitization process: the more levels, the smaller the quantization
noise. The theoretical SINAD ratio for an ideal N-bit converter
with a sine wave input is given by
Bipolar Zero-Scale Error
The bipolar zero-scale error is the deviation of the midscale
transition (all 1s to all 0s) from the ideal VIN voltage, that is,
AGND − 1 LSB.
SINAD = (6.02 N + 1.76) dB
Therefore, SINAD is 98 dB for a 16-bit converter.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the
fundamental. For the AD7656A, it is defined as
Bipolar Zero-Scale Error Matching
The bipolar zero-scale error matching is the difference in
bipolar zero-code error between any two input channels.
Positive Full-Scale Error
The positive full-scale error is the deviation of the last code
transition (011 … 110) to (011 … 111) from the ideal (4 × VREF –
1 LSB or 2 × VREF − 1 LSB) after adjusting for the bipolar zero
scale error.
Positive Full-Scale Error Matching
The positive full-scale error matching is the difference in
positive full-scale error between any two input channels.
Negative Full-Scale Error
The negative full-scale error is the deviation of the first code
transition (10 … 000) to (10 … 001) from the ideal (−4 × VREF +
1 LSB or −2 × VREF + 1 LSB) after adjusting for the bipolar zerocode error.
Negative Full-Scale Error Matching
The negative full-scale error matching is the difference in
negative full-scale error between any two input channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of the conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1 LSB, after the end of the conversion.
See the Track-and-Hold Amplifiers section for more details.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.
THD (dB) = 20 log
V2 2 + V3 2 + V 4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through sixth harmonics.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the ratio of the rms value
of the next largest component in the ADC output spectrum (up
to fSAMPLE/2, excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it is determined by a
noise peak.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities create distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for
which neither m nor n are equal to 0. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The AD7656A is tested using the CCIF standard in which two
input frequencies near the maximum input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in decibels.
Rev. 0 | Page 13 of 28
AD7656A
Data Sheet
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
100 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 30 kHz signal.
Figure 15 shows the power supply rejection ratio vs. supply
ripple frequency for the AD7656A. The power supply rejection
ratio is defined as the ratio of the power in the ADC output at the
full-scale frequency, f, to the power of a 200 mV p-p sine wave
applied to the VDD and VSS supplies of the fSAMPLE of the ADC.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. Power supply rejection is the
maximum change in the full-scale transition point due to a change
in power supply voltage from the nominal value. See the Typical
Performance Characteristics section.
where:
Pf is equal to the power at frequency f in the ADC output.
PfS is equal to the power at frequency fS coupled onto the VDD
and VSS supplies.
PSRR (dB) = 10 log (Pf/PfS)
Percent Full-Scale Ratio (% FSR)
%FSR is calculated using the full theoretical span of the ADC.
Rev. 0 | Page 14 of 28
Data Sheet
AD7656A
THEORY OF OPERATION
CONVERTER DETAILS
Analog Input
The AD7656A is a high speed, low power converter that allows
the simultaneous sampling of six on-chip analog-to-digital
converts (ADCs). The analog inputs on the AD7656A can
accept true bipolar input signals. The RANGE pin/RNGx bits
are used to select either ±4 × VREF or ±2 × VREF as the input
range for the next conversion.
The AD7656A can handle true bipolar input voltages. The logic
level on the RANGE pin or the value written to the RNGx bits
in the control register determines the analog input range on the
AD7656A for the next conversion. When the RANGE pin or
RNGx bit is 1, the analog input range for the next conversion is
±2 × VREF. When the RANGE pin or RNGx bit is 0, the analog
input range for the next conversion is ±4 × VREF.
A conversion is initiated on the AD7656A by pulsing the
CONVST x input. On the rising edge of CONVST x, the trackand-hold amplifier of the selected ADC pair is placed into hold
mode and the conversions are started. After the rising edge of
CONVST x, the BUSY signal goes high to indicate that the
conversion is taking place. The conversion clock for the
AD7656A is internally generated, and the conversion time for
the device is 3 µs. The BUSY signal returns low to indicate the
end of conversion. On the falling edge of BUSY, the track-andhold amplifier returns to track mode. Data can be read from the
output register via the parallel or serial interface.
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7656A allow the ADCs
to accurately convert an input sine wave of full-scale amplitude
to 16-bit resolution. The input bandwidth of the track-and-hold
amplifiers is greater than the Nyquist rate of the ADC, even
when the AD7656A is operating at its maximum throughput
rate. The device can handle input frequencies of up to 12 MHz.
The track-and-hold amplifiers sample their respective inputs
simultaneously on the rising edge of CONVST x. The aperture time
(that is, the delay time between the external CONVST x signal
actually entering hold) for the track-and-hold is 10 ns. This is well
matched across all six track-and-hold amplifiers on one device and
from device to device. This allows more than six ADCs to be
sampled simultaneously. The end of the conversion is signaled by
the falling edge of BUSY, and it is at this point that the track-andhold amplifiers return to track mode and the acquisition time
begins.
VDD
VDD_INTERNAL
D1
R1
C2
V1
C1
D2
VSS_INTERNAL
11127-024
The AD7656A contains six successive approximation (SAR)
ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference,
reference buffers, and high speed parallel and serial interfaces.
The AD7656A allows the simultaneous sampling of all six ADCs
when the three CONVST x pins (CONVST A, CONVST B, and
CONVST C) are tied together. Alternatively, the six ADCs can be
grouped into three pairs. Each pair has an associated CONVST
signal used to initiate simultaneous sampling on each ADC pair,
on four ADCs, or on all six ADCs. CONVST A is used to initiate
simultaneous sampling on V1 and V2, CONVST B is used to
initiate simultaneous sampling on V3 and V4, and CONVST C
is used to initiate simultaneous sampling on V5 and V6.
VSS
Figure 20. Equivalent Analog Input Structure
Figure 20 shows an equivalent circuit of the analog input of
structure of the AD7656A. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the VDD and
VSS supply rail limits by more than VSS + 1 V and VDD − 1 V.
Signals exceeding this value cause these diode to become forwardbiased and to start conducting into the substrate. The maximum
current these diodes can conduct without causing irreversible
damage to the device is 10 mA. Capacitor C1 in Figure 20 is
typically about 4 pF and can be attributed primarily to pin
capacitance. Resistor R1 is a lumped component made up of the
on resistance of a switch (that is, track-and-hold switch). This
resistor is typically about 25 Ω. Capacitor C2 is the ADC
sampling capacitor and has a capacitance of 10 pF typically.
The AD7656A requires VDD and VSS dual supplies for the high
voltage analog input structures. These supplies must be greater
than the analog input range (see Table 6 for the requirements on
these supplies for each analog input range). The AD7656A
requires a low voltage AVCC supply of 4.75 V to 5.25 V to power
the ADC core, a DVCC supply of 4.75 V to 5.25 V for the digital
power, and a VDRIVE supply of 2.7 V to 5.25 V for the interface
power.
To meet the specified performance when using the minimum
supply voltage for the selected analog input range, it may be
necessary to reduce the throughput rate from the maximum
throughput rate.
Table 6. Minimum VDD/VSS Supply Voltage Requirements
Analog Input
Range (V)
±4 × VREF
±4 × VREF
±2 × VREF
±2 × VREF
Rev. 0 | Page 15 of 28
Reference
Voltage (V)
2.5
3.0
2.5
3.0
Full-Scale
Input (V)
±10
±12
±5
±6
Minimum
VDD/VSS (V)
±11
±13
±6
±7
AD7656A
Data Sheet
ADC TRANSFER FUNCTION
operating in external reference mode with the internal reference
buffers enabled. The internal reference can be enabled in either
hardware or software mode. To enable the internal reference in
hardware mode, set the H/S SEL pin to 0 and the REFEN/DIS pin to 1.
To enable the internal reference in software mode, set the H/S SEL
pin to 1 and write to the control register to set DB9 of the
control register to 1. For the internal reference mode, decouple
the REFIN/REFOUT pin using 10 µF and 100 nF capacitors.
The output coding of the AD7656A is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is
FSR/65,536 for the AD7656A. The ideal transfer characteristic
is shown in Figure 21.
The AD7656A contains three on-chip reference buffers. Each of
the three ADC pairs has an associated reference buffer. These
reference buffers require external decoupling capacitors on the
REFCAPA, REFCAPB, and REFCAPC pins.Place 10 µF and
100 nF decoupling capacitors on these REFCAPx pins. The
internal reference buffers can be disabled in software mode by
writing to Bit DB8 in the internal control register. If the serial
interface is selected, the internal reference buffers can be disabled
in hardware mode by setting the DB14/REFBUFEN/DIS pin high. If
the internal reference and its buffers are disabled, apply an
external buffered reference to the REFCAPx pins.
000...001
000...000
111...111
–FSR/2 + 1/2LSB
AGND – 1LSB
11127-025
100...010
100...001
100...000
+FSR/2 – 3/2LSB
ANALOG INPUT
Figure 21. Transfer Characteristic
The LSB size is dependent on the analog input range selected
(see Table 7).
TYPICAL CONNECTION DIAGRAM
Figure 22 shows the typical connection diagram for the AD7656A.
There are eight AVCC supply pins on the device. The AVCC supply
is the supply that is used for the AD7656A conversion process;
therefore, it must be well decoupled. Individually decouple each
AVCC supply pin with a 10 µF tantalum capacitor and a 100 nF
ceramic capacitor. The AD7656A can operate with the internal
reference or an externally applied reference. In this configuration,
the device is configured to operate with the external reference.
The REFIN/REFOUT pin is decoupled with a 10 µF and 100 nF
capacitor pair. The three internal reference buffers are enabled.
Each of the REFCAPx pins is decoupled with the 10 µF and
100 nF capacitor pair.
Table 7. LSB Size for Each Analog Input Range
Input Range (V)
±10
±5
LSB Size (mV)
0.305
0.152
Full Scale Range
20 V/65,536
10 V/65,536
REFERENCE SECTION
Either the REFIN/REFOUT pin allows access to the 2.5 V reference
of the AD7656A, or it allows an external reference to be connected,
providing the reference source for the conversions of the device.
The AD7656A can accommodate a 2.5 V to 3 V external reference
range. When using an external reference, the internal reference
must be disabled. After a reset, the AD7656A defaults to
DVCC
A N A L OG SUPPLY
VOLTAGE 5V1
+
10µF
+11.0V TO +16.5V2
SUPPLY
10µF
+
100nF
100nF
AGND AVCC DVCC
VDD
DGND
100nF
DIGITAL SUPPLY
VOLTAGE +3V OR +5V
+
10µF
100nF
+
10µF
VDRIVE DGND
DB0 TO DB15
PARALLEL
INTERFACE
MICROPROCESSOR/
MICROCONTROLLER/
DSP
AGND
10µF
+
100nF
CONVST A, CONVST B, CONVST C
REFCAPA, REFCAPB, REFCAPC
CS
RD
AGND
BUSY
AD7656A
2.5V
REF
10µF
+
100nF
SER/PAR/SEL
H/S SEL
W/B
RANGE
AGND
SIX ANALOG
INPUTS
–11.0V TO –16.5V2
SUPPLY
10µF
RESET
REFIN/REFOUT
VS S
+
STBY
100nF
VDRIVE
AGND
1DECOUPLING SHOWN ON THE AV
CC PIN APPLIES TO EACH AVCC PIN.
2SEE THE POWER SUPPLY SEQUENCING SECTION.
Figure 22. Typical Connection Diagram
Rev. 0 | Page 16 of 28
11127-122
ADC CODE
011...111
011...110
Data Sheet
AD7656A
Six of the AVCC supply pins are used as the supply to the six ADC
cores on the AD7656A and, as a result, are used for the conversion
process. Each analog input pin is surrounded by an AVCC supply
pin and an AGND pin. These AVCC and AGND pins are the supply
and ground for the individual ADC cores. For example, Pin 33 is
V1, Pin 34 is the AVCC supply for ADC Core 1, and Pin 32 is
AGND for ADC Core 1. An alternative reduced decoupling
solution is to group these six AVCC supply pins into three pairs,
Pin 34 and Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47.
For the AD7656A, a 100 µF decoupling capacitor can be placed
on each of the pin pairs. Decouple all of the other supply and
reference pins with a 10 µF decoupling capacitor.
If the same supply is being used for the AVCC supply and DVCC
supply, place a ferrite or small RC filter between the supply pins.
The AGND pins are connected to the analog ground plane of the
system. The DGND pins are connected to the digital ground plane
in the system. Connect the AGND and DGND planes together
at one place in the system. Make this connection as close as
possible to the AD7656A in the system.
The VDRIVE supply is connected to the same supply as the processor.
The voltage on VDRIVE controls the voltage value of the output
logic signals.
Decouple the VDD and VSS signals with a minimum 10 µF
decoupling capacitor. These supplies are used for the high voltage
analog input structures on the AD7656A analog inputs.
DRIVING THE ANALOG INPUTS
Together, the driver amplifier and the analog input circuit
used for the AD7656A must settle for a full-scale step input to
a 16-bit level (0.0015%), which is within the specified 550 ns
acquisition time of the AD7656A. The noise generated by the
driver amplifier must be kept as low as possible to preserve the
SNR and transition noise performance of the AD7656A. In
addition, the driver needs to have a THD performance suitable
for the AD7656A.
INTERFACE SECTION
The AD7656A provides two interface options: a parallel interface
and a high speed serial interface. The required interface mode is
selected via the SER/PAR SEL pin. The parallel interface can
operate in word (W/B = 0) or byte (W/B = 1) mode. The
interface modes are discussed in the following sections.
Parallel Interface (SER/PAR/SEL = 0)
The AD7656A consists of six 16-bit ADCs. A simultaneous sample
of all six ADCs can be performed by connecting all three CONVST x
pins together (CONVST A, CONVST B, and CONVST C). The
AD7656A needs to see a CONVST x pulse to initiate a conversion;
this typically consists of a falling CONVST x edge followed by a
rising CONVST x edge. The rising edge of CONVST x initiates
simultaneous conversions on the selected ADCs. The AD7656A
contains an on-chip oscillator that is used to perform the
conversions. The conversion time, tCONVERT, is 3 µs. The BUSY signal
goes low to indicate the end of conversion. The falling edge of
the BUSY signal is used to place the track-and-hold amplifier
into track mode. The AD7656A also allows the six ADCs to be
converted simultaneously in pairs by pulsing the three
CONVST x pins independently. CONVST A is used to initiate
simultaneous conversions on V1 and V2, CONVST B is used to
initiate simultaneous conversions on V3 and V4, and CONVST C
is used to initiate simultaneous conversions on V5 and V6. The
conversion results from the simultaneously sampled ADCs are
stored in the output data registers.
Data can be read from the AD7656A via the parallel data bus
with standard CS and RD signals (W/B = 0). To read the data
over the parallel bus, tie SER/PAR SEL low. The CS and RD
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, the DB0 to DB15 pins, leave
their high impedance state when both CS and RD are logic low.
The AD8021 meets all these requirements. The AD8021 needs an
external compensation capacitor of 10 pF. If a dual version of the
AD8021 is required, the AD8022 can be used. The AD8610 and the
AD797 can also be used to drive the AD7656A.
Rev. 0 | Page 17 of 28
AD7656A
Data Sheet
t10
CONVST A,
CONVST B,
CONVST C
tCONVERT
tACQ
BUSY
t4
CS
t3
t5
t9
t2
DATA
t7
t6
V1
V2
V3
V4
t8
V5
tQUIET
11127-027
RD
V6
Figure 23. Parallel Interface Timing Diagram (W/B = 0)
CS
t4
t3
t5
DB15 TO DB8
t8
t7
t6
LOW BYTE
HIGH BYTE
11127-028
RD
t9
Figure 24. Parallel Interface—Read Cycle for Byte Mode of Operation (W/B = 1, HBEN = 0)
The CS signal can be permanently tied low, and the RD signal can
be used to access the conversion results. A read operation can take
place after the BUSY signal goes low. The number of required
read operations depends on the number of ADCs that are
simultaneously sampled (see Figure 23). If CONVST A and
CONVST B are simultaneously brought low, four read operations
are required to obtain the conversion results from V1, V2, V3, and
V4. If CONVST A and CONVST C are simultaneously brought
low, four read operations are required to obtain the conversion
results from V1, V2, V5, and V6. The conversion results are
output in ascending order.
When using the three CONVST x signals to independently initiate
conversions on the three ADC pairs, ensure that a conversion is
not initiated on a channel pair when the BUSY signal is high. It is
also recommended not to initiate a conversion during a read
sequence because doing so can affect the performance of the
conversion. For the specified performance, it is recommended to
perform the read after the conversion. For unused input
channel pairs, tie the associated CONVST x pin to VDRIVE.
If there is only an 8-bit bus available, the AD7656A interface can
be configured to operate in byte mode (W/B = 1). In this
configuration, the DB7/HBEN/DCEN pin takes on its HBEN
function. Each channel conversion result from the AD7656A
can be accessed in two read operations, with eight bits of data
provided on DB15 to DB8 for each of the read operations (see
Figure 24). The HBEN pin determines whether the read
operation first accesses the high byte or the low byte of the
16-bit conversion result. To always access the low byte first on
DB15 to DB8, tie the HBEN pin low. To always access the high
byte first on DB15 to DB8, tie the HBEN pin high. In byte mode
when all three CONVST x pins are pulsed together to initiate
simultaneous conversions on all six ADCs, 12 read operations
are necessary to read back the six 16-bit conversion results.
Leave DB6 to DB0 unconnected in byte mode.
Rev. 0 | Page 18 of 28
Data Sheet
AD7656A
SOFTWARE SELECTION OF ADCS
The AD7656A control register allows individual ranges to be
programmed on each ADC pair. DB12 to DB10 bits in the
control register are used to program the range on each ADC pair.
The H/S SEL pin determines the source of the combination of
ADCs that are to be simultaneously sampled. When the H/S SEL
pin is logic low, the combination of channels to be simultaneously
sampled is determined by the CONVST A, CONVST B, and
CONVST C pins. When the H/S SEL pin is logic high, the
combination of channels selected for simultaneous sampling is
determined by the contents of the DB15 to DB13 bits in the
control register. In this mode, a write to the control register is
necessary.
After a reset occurs on the AD7656A, the control register
contains all zeros.
The CONVST A signal is used to initiate a simultaneous
conversion on the combination of channels selected via the
control register. The CONVST B and CONVST C signals can be
tied low when operating in software mode (H/S SEL = 1). The
number of read pulses required depends on the number of
ADCs selected in the control register and on whether the
devices are operating in word or byte mode. The conversion
results are output in ascending order.
The control register is an 8-bit write-only register. Data is
written to this register using the CS and WR pins and the DB15
to DB8 data pins (see Figure 25). The control register is detailed
in Table 8. To select an ADC pair to be simultaneously sampled,
set the corresponding data line high during the write operation.
During the write operation, Data Bus Bit DB15 to Data Bus
Bit DB8 are bidirectional and become inputs to the control
register when RD is logic high and CS and WR are logic low.
The logic state on DB15 through DB8 is latched into the control
register when WR goes logic high.
CS
WR
t12
t13
t11
t15
DB15 TO DB8
11127-029
t14
DATA
Figure 25. Parallel Interface—Write Cycle for Word Mode (W/B= 0)
Table 8. Control Register Bits (Default All 0s)
DB15
VC
DB14
VB
DB13
VA
DB12
RNGC
DB11
RNGB
DB10
RNGA
DB9
REFEN
DB8
REFBUF
Table 9. Control Register Bit Function Descriptions (Default All 0s)
Bit
DB15
Mnemonic
VC
DB14
VB
DB13
VA
DB12
RNGC
DB11
RNGB
DB10
RNGA
DB9
REFEN
DB8
REFBUF
Description
This bit selects the V5 and V6 analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are
simultaneously converted on the next CONVST A rising edge.
This bit selects the V3 and V4 analog inputs for the next conversion. When this bit is set to 1, V3 and V4 are
simultaneously converted on the next CONVST B rising edge.
This bit selects the V1 and V2 analog inputs for the next conversion. When this bit is set to 1, V1 and V2 are
simultaneously converted on the next CONVST C rising edge.
This bit selects the analog input range for the V5 and V6 analog inputs. When this bit is set to 1, the ±2 × VREF range is
selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion.
This bit selects the analog input range for the V3 and V4 analog inputs. When this bit is set to 1, the ±2 × VREF range is
selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion.
This bit selects the analog input range for the V1 and V2 analog inputs. When this bit is set to 1, the ±2 × VREF range is
selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion.
This bit selects the internal reference or an external reference. When this bit is set to 0, the external reference mode is
selected. When this bit is set to 1, the internal reference is selected.
This bit selects between using the internal reference buffers and choosing to bypass these reference buffers. When this
bit is set to 0, the internal reference buffers are enabled and decoupling is required on the REFCAPx pins. When this bit is
set to 1, the internal reference buffers are disabled and a buffered reference is applied to the REFCAPx pins.
Rev. 0 | Page 19 of 28
AD7656A
Data Sheet
Changing the Analog Input Range (H/S SEL = 0)
Figure 26 shows six simultaneous conversions and the read
sequence using three DOUT x lines. Also in Figure 26, 32 SCLK
transfers are used to access data from the AD7656A; however,
two 16 SCLK individually framed transfers with the CS signal
can also be used to access the data on the three DOUT x lines.
When the serial interface is selected and the conversion data
clocks out on all three DOUTx lines, tie DB0/SEL A, DB1/SEL B,
and DB2/SEL C to VDRIVE. These pins are used to enable the
DOUT A to DOUT C lines, respectively.
The AD7656A RANGE pin allows the user to select either ±2 ×
VREF or ±4 × VREF as the analog input range for the six analog
inputs. When the H/S SEL pin is low, the logic state of the
RANGE pin is sampled on the falling edge of the BUSY signal
to determine the range for the next simultaneous conversion.
When the RANGE pin is logic high at the falling edge of the
BUSY signal, the range for the next conversion is ±2 × VREF.
When the RANGE pin is logic low at the falling edge of the
BUSY signal, the range for the next conversion is ±4 × VREF.
After a RESET pulse, the range is updated on the first falling
BUSY edge after the RESET pulse.
If it is required to clock conversion data out on two data out lines,
use DOUT A and DOUT B. To enable DOUT A and DOUT B,
tie DB0/SEL A and DB1/SEL B to VDRIVE and tie DB2/SEL C low.
When six simultaneous conversions are performed and only two
DOUT x lines are used, a 48 SCLK transfer can be used to
access the data from the AD7656A. The read sequence is shown
in Figure 27 for a simultaneous conversion on all six ADCs
using two DOUT x lines. If a simultaneous conversion occurred
on all six ADCs, only two DOUT x lines are used to read the
results from the AD7656A. DOUT A clocks out the result from
V1, V2, and V5, and DOUT B clocks out the results from V3,
V4, and V6.
Changing the Analog Input Range (H/S SEL = 1)
When the H/S SEL pin is high, the range can be changed by
writing to the control register. Bits[DB12:DB10] in the control
register are used to select the analog input ranges for the next
conversion. Each analog input pair has an associated range bit,
allowing independent ranges to be programmed on each ADC
pair. When the RNGx bit is set to 1, the range for the next
conversion is ±2 × VREF. When the RNGx bit is set to 0, the
range for the next conversion is ±4 × VREF.
Data can also be clocked out using just one DOUT x line, in which
case, use DOUT A to access the conversion data. To configure the
AD7656A to operate in this mode, tie DB0/SEL A to VDRIVE and
tie DB1/SEL B and DB2/SEL C low. The disadvantage of using
only one DOUT x line is that the throughput rate is reduced.
Data can be accessed from the AD7656A using one 96-SCLK
transfer, three 32-SCLK individually framed transfers, or six 16SCLK individually framed transfers. In serial mode, tie the RD
signal low. Leave the unused DOUT x line(s) unconnected in serial
mode.
Serial Interface (SER/PAR/SEL = 1)
By pulsing one, two, or all three CONVST x signals, the AD7656A
use their on-chip trimmed oscillator to simultaneously convert
the selected channel pairs on the rising edge of CONVST x.
After the rising edge of CONVST x, the BUSY signal goes high
to indicate that the conversion has started. It returns low when
the conversion is complete 3 µs later. The output register is
loaded with the new conversion results, and data can be read
from the AD7656A. To read the data back from the device over
the serial interface, tie SER/PAR high. The CS and SCLK signals
are used to transfer data from the AD7656A. The device has three
DOUT x pins: DOUT A, DOUT B, and DOUT C. Data can be
read back from the device using one, two, or all three DOUT x
lines.
CONVST A,
CONVST B,
CONVST C
tCONVERT
tACQ
BUSY
CS
32
16
SCLK
V1
V2
DOUT B
V3
V4
DOUT C
V5
V6
Figure 26. Serial Interface with Three DOUT x Lines
Rev. 0 | Page 20 of 28
11127-030
tQUIET
DOUT A
Data Sheet
AD7656A
CS
48
DOUT A
V1
V2
V5
DOUT B
V3
V4
V6
11127-031
SCLK
Figure 27. Serial Interface with Two DOUT x Lines
t1
t2
BUSY
ACQUISITION
t10
tACQ
tCONVERT
ACQUISITION
CONVERSION
tQUIET
CS
SCLK
t19
t16
t18
t17
t20
t21
DB15
DOUT A,
DOUT B,
DOUT C
DB14
DB13
DB1
DB0
11127-032
CONVST A,
CONVST B,
CONVST C
Figure 28. Serial Read Operation
CONVERT
DIGITAL HOST
CONVST x
CONVST x
DOUT A
DCIN A
DOUT A
DATA IN1
DOUT B
DCIN B
DOUT B
DATA IN2
AD7656A
SCLK
AD7656A
SCLK
CS
CS
SCLK
DCEN = 0
DEVICE 2
DCEN = 1
DEVICE 1
11127-033
CS
Figure 29. Daisy-Chain Configuration
SERIAL READ OPERATION
Figure 28 shows the timing diagram for reading data from the
AD7656A serial interface. The SCLK input signal provides the
clock source for the serial interface. The CS signal goes low to
access data from the AD7656A. The falling edge of CS takes
the bus out of a three-state condition and clocks out the MSB of
the 16-bit conversion result. The ADCs output 16 bits for each
conversion result; the data stream of the AD7656A consists of
16 bits of conversion data provided MSB first.
The first bit of the conversion result is valid on the first SCLK
falling edge after the CS falling edge. The subsequent 15 data
bits are clocked out on the rising edge of the SCLK signal. Data
is valid on the SCLK falling edge. To access each conversion result,
provide 16 clock pulses to the AD7656A. Figure 28 shows how a
16-SCLK read is used to access the conversion results.
DAISY-CHAIN MODE (DCEN = 1, SER/PAR/SEL = 1)
When reading conversion data back from the AD7656A using
their three, two, and one DOUT x pins, it is possible to configure
the device to operate in daisy-chain mode using the DCEN pin.
This daisy-chain feature allows multiple AD7656A devices to be
cascaded together and is useful for reducing the component
count and wiring connections. An example connection of two
devices is shown in Figure 29. This configuration shows the use
of two DOUT x lines. Simultaneous sampling of the 12 analog
inputs is possible by using a common CONVST x signal. The
DB5, DB4, and DB3 pins are used as the DCIN A to DCIN C data
input pins for the daisy-chain mode.
Rev. 0 | Page 21 of 28
AD7656A
Data Sheet
During the first 48 SCLKs, Device 1 transfers data into the digital
host. DOUT A on Device 1 transfers conversion data from V1,
V2, and V5. DOUT B on Device 1 transfers conversion data from
V3, V4, and V6. During the last 48-SCLKs, Device 2 clocks out
zeros and Device 1 shifts the data clocked in from Device 2 during
the first 48 SCLKs into the digital host. This example can also
be implemented using six 16-SCLK individually framed transfers if
DCEN remains high during the transfers.
The rising edge of CONVST x is used to initiate a conversion on
the AD7656A. After the BUSY signal has gone low to indicate
that the conversion is complete, the user can begin to read the data
from the two devices. Figure 30 shows the serial timing diagram
when operating two AD7656A devices in daisy-chain mode.
The CS falling edge is used to frame the serial transfer from the
AD7656A to take the bus out of three-state and to clock out the
MSB of the first conversion result. In the example shown in
Figure 30, all 12 ADC channels are simultaneously sampled. Two
DOUT x lines are used to read the conversion results in this
example. CS frames a 96-SCLK transfer. During the first 48 SCLKs,
the conversion data is transferred from Device 2 to Device 1.
DOUT A on Device 2 transfers conversion data from V1, V2,
and V5 into DCIN A in Device 1. DOUT B on Device 2 transfers
conversion results from V3, V4, and V6 to DCIN B in Device 1.
Figure 31 shows the timing if two AD7656A devices are configured
in daisy-chain mode and are operating with three DOUT x
lines. Assuming a simultaneous sampling of all 12 inputs
occurs, the CS frames a 64-SCLK transfer during the read
operation. During the first 32 SCLKs of this transfer, the
conversion results from Device 1 are clocked into the digital
host, and the conversion results from Device 2 are clocked into
Device 1. During the last 32 SCLKs of the transfer, the
conversion results from Device 2 are clocked out of Device 1
and into the digital host. Device 2 clocks out zeros.
CONVST A,
CONVST B,
CONVST C
BUSY
CS
1
2
3
15
16
17
31
32
33
47
48
49
63
64
65
94
95
96
SCLK
MSB V1
LSB V1
MSB V2
LSB V2
MSB V5
LSB V5
MSB V1
LSB V1
MSB V2
LSB V5
DEVICE 1, DOUT B
MSB V3
LSB V3
MSB V4
LSB V4
MSB V6
LSB V6
MSB V3
LSB V3
MSB V4
LSB V6
DEVICE 2, DOUT A
MSB V1
LSB V1
MSB V2
LSB V2
MSB V5
LSB V5
DEVICE 2, DOUT B
MSB V3
LSB V3
MSB V4
LSB V4
MSB V6
LSB V6
11127-034
DEVICE 1, DOUT A
Figure 30. Daisy-Chain Serial Interface Timing with Two DOUT x Lines
CONVST A,
CONVST B,
CONVST C
BUSY
CS
1
2
3
15
16
17
31
32
33
47
48
49
63
64
DEVICE 1, DOUT A
MSB V1
LSB V1
MSB V2
LSB V2
MSB V1
LSB V1
MSB V2
LSB V2
DEVICE 1, DOUT B
MSB V3
LSB V3
MSB V4
LSB V4
MSB V3
LSB V3
MSB V4
LSB V4
DEVICE 1, DOUT C
MSB V5
LSB V5
MSB V6
LSB V6
MSB V5
LSB V5
MSB V6
LSB V6
DEVICE 2, DOUT A
MSB V1
LSB V1
MSB V2
LSB V2
DEVICE 2, DOUT B
MSB V3
LSB V3
MSB V4
LSB V4
DEVICE 2, DOUT C
MSB V5
LSB V5
MSB V6
LSB V6
Figure 31. Daisy-Chain Serial Interface Timing with Three DOUT x Lines
Rev. 0 | Page 22 of 28
11127-035
SCLK
Data Sheet
AD7656A
Standby/Partial Power-Down Modes of Operation
(SER/PAR/SEL = 0 or SER/PAR/SEL = 1)
Each ADC pair can be individually placed into partial powerdown mode by bringing the CONVST x signal low before the
falling edge of BUSY. Bring the CONVST x signal high to power
up the ADC pair and place the track-and-hold amplifier into
track mode. After the power-up time from the partial powerdown has elapsed, the CONVST x signal typically receives a
rising edge to initiate a valid conversion. In partial power-down
mode, the reference buffers remain powered up. While an ADC
pair is in partial power-down mode, conversions can still occur
on the other ADCs.
The AD7656A has a power-down mode whereby the device can
be placed into a low power mode consuming 100 mW maximum.
The AD7656A is placed into standby mode by bringing the
logic input STBY low and can be powered up again for normal
operation by bringing STBY logic high. The output data buffers
are still operational when the AD7656A is in standby mode,
meaning the user can continue to access the conversion results
of the device. This standby feature can be used to reduce the
average power consumed by the AD7656A when operating at
lower throughput rates. The AD7656A can be placed into standby
at the end of each conversion when BUSY goes low and taken out
of standby again prior to the next conversion. The wake-up
time is when the AD7656A comes out of standby mode. The
wake-up time limits the maximum throughput rate at which the
AD7656A can operate when powering down between
conversions. See the Specifications section.
Rev. 0 | Page 23 of 28
AD7656A
Data Sheet
APPLICATION HINTS
LAYOUT
Design the printed circuit board (PCB) that houses the AD7656A
so that the analog and digital sections are separated and confined
to different areas of the board.
Use at least one ground plane. The ground plane can be common
or split between the digital and analog sections. In the case of
the split plane, join the digital and analog ground planes in only
one place, preferably underneath the AD7656A, or at least as
close as possible to the device.
If the AD7656A is in a system where multiple devices require
analog-to-digital ground connections, still make the connection
at only one point, a star ground point, and established it as close
as possible to the AD7656A. Make good connections to the
ground plane. Avoid sharing one connection for multiple
ground pins. Use individual vias or multiple vias to the ground
plane for each ground pin.
Avoid running digital lines under the device because doing so
couples noise onto the die. Allow the analog ground plane to
run under the AD7656A to avoid noise coupling. Shield fast
switching signals, like CONVST x or clocks, with digital ground
to avoid radiating noise to other sections of the board, and
ensure that they never run near the analog signal paths. Avoid
crossover of digital and analog signals. Run traces in close
proximity on the board at right angles to each other to reduce
the effect of feedthrough through the board.
For the power supply lines to the AVCC, DVCC, VDRIVE, VDD, and
VSS pins on the AD7656A use as large a trace as possible to
provide low impedance paths and to reduce the effect of glitches
on the power supply lines. Establish good connections between
the AD7656A supply pins and the power tracks on the board;
involve the use of a single via or multiple vias for each supply
pin.
Good decoupling is also important to lower the supply impedance
presented to the AD7656A and to reduce the magnitude of the
supply spikes. Place decoupling ceramic capacitors, typically
100 nF, on all of the power supply pins, VDD, VSS, AVCC, DVCC,
and VDRIVE. Place these decoupling capacitors close to, but
ideally right up against, these pins and their corresponding
ground pins. Additionally, place low ESR 10 µF capacitors on
each of the supply pins. Avoid sharing these capacitors between
pins. Use big vias to connect the capacitors to the power and
ground planes. Use wide, short traces between the via and the
capacitor pad, or place the via adjacent to the capacitor pad to
minimize parasitic inductances. Recommended decoupling
capacitors are 100 nF, low ESR, ceramic capacitors and 10 µF, low
ESR, tantalum capacitors for the AVCC decoupling. Place a large
tantalum decoupling capacitor where the AVCC supply enters
the board.
An alternative reduced decoupling arrangement is outlined in
the Typical Connection Diagram section. This decoupling
arrangement groups the AVCC supply pins into pairs and allows
the decoupling capacitors to be shared between the supply pairs.
Group the six AVCC core supply pins into three pairs, Pin 34 and
Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. Connect the
supply pins in each pair together; their location on the AD7656A
pin configuration easily facilitates this. For the AD7656A, decouple
each pair with a 100 µF capacitor. For this minimum decoupling
configuration, decouple all other supply and reference pins with
a 10 µF decoupling capacitor.
Rev. 0 | Page 24 of 28
Data Sheet
AD7656A
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
VIEW A
16
33
32
17
VIEW A
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 32. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD7656ABSTZ
AD7656ABSTZ-RL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
Package Option
ST-64-2
ST-64-2
AD7656A
Data Sheet
NOTES
Rev. 0 | Page 26 of 28
Data Sheet
AD7656A
NOTES
Rev. 0 | Page 27 of 28
AD7656A
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11127-0-12/13(0)
Rev. 0 | Page 28 of 28