MGA-683P8 Low Noise And High Linearity Active Bias Low Noise Amplifier Data Sheet Description Features Avago Technologies’ MGA-683P8 is an economical, easyto-use GaAs MMIC Low Noise Amplifier (LNA). The LNA has low noise and high linearity achieved through the use of Avago Technologies’ proprietary 0.25 m GaAs Enhancement-mode pHEMT process. It is housed in a miniature 2.0 x 2.0 x 0.75 mm3 8-pin Quad-Flat-Non-Lead (QFN) package. It is designed for optimum use from 450 MHz up to 2 GHz. The compact footprint and low profile coupled with low noise, high gain and high linearity make the MGA-683P8 an ideal choice as a low noise amplifier for cellular infrastructure for GSM and CDMA. For optimum performance at higher frequency from 1.5 GHz to 4 GHz, the MGA-684P8 is recommended. Both MGA-683P8 and MGA-684P8 share the same package and pinout. Pin Configuration and Package Marking [8] [2] 83X [3] [7] [6] [5] [4] Top View Pin 1 Pin 2 Pin 3 Pin 4 – Vbias – RFinput – Not Used – Not Used Specifications 900 MHz; 5 V, 40 mA 17.8 dB Gain 0.56 dB Noise Figure More than 20 dB Input Return Loss 32.8 dBm Output IP3 21.5 dBm Output Power at 1dB gain compression Applications 2.0 x 2.0 x 0.75 mm3 8-lead QFN [1] Low noise Figure High linearity performance GaAs E-pHEMT Technology[1] Low cost small package size: 2.0 x 2.0 x 0.75 mm3 Excellent uniformity in product specifications Tape-and-Reel packaging option available [8] [7] [1] [2] [6] [5] [3] [4] Low noise amplifier for cellular infrastructure for GSM and CDMA. Other low noise application. Repeater, Metrocell/Picocell application. Simplified Schematic Bottom View Vdd C5 Pin 5 – Not Used Pin 6 – Not Used Pin 7 – RFoutput/Vdd Pin 8 – Not Used Centre tab - Ground Note: Package marking provides orientation and identification “83” = Device Code “X” = Month Code R1 C1 C4 L2 L1 L3 Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 90 V (Class A) ESD Human Body Model = 500 V (Class 1B) Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. R2 C3 RFin C6 Rbias [1] [8] [2] [7] [3] [6] [4] [5] C2 RFout Note: The schematic is shown with the assumption that similar PCB is used for both MGA-683P8 and MGA-684P8. Detail of the components needed for this product is shown in Table 1. Enhancement mode technology employs positive gate voltage, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices. Good RF practice requires all unused pins to be earthed. Absolute Maximum Rating [1] TA=25° C Thermal Resistance Symbol Parameter Units Absolute Maximum Vdd Device Voltage, RF output to ground V 5.5 Idd Drain Current mA 90 Pmax CW RF Input Power (Vdd = 5.0 V, Id = 54 mA) dBm +20 Pdiss Total Power Dissipation [2] W 0.495 Tj Junction Temperature °C 150 Tstg Storage Temperature °C -65 to 150 Thermal Resistance [3] (Vdd = 5.0 V, Idd = 40 mA) jc = 72°C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red Measurement Technique. 3. Power dissipation with unit turned on. Board temperature TB is 25° C. Derate at 13.89 mW/°C for TB > 114° C. Electrical Specifications [1, 4] RF performance at TA = 25° C, Vdd = 5 V, Rbias = 12 kOhm, 900 MHz, measured on demo board in Figure 5 with component list in Table 1 for 900 MHz matching. Symbol Parameter and Test Condition Units Min. Typ. Max. Idd Drain Current mA 25 40.3 53 Gain Gain dB 16.3 17.8 19.3 OIP3 [2] Output Third Order Intercept Point dBm 28.5 32.8 NF [3] Noise Figure dB 0.56 OP1dB Output Power at 1dB Gain Compression dBm 21.5 IRL Input Return Loss, 50 source dB 24 ORL Output Return Loss, 50 load dB 13 REV ISOL Reverse Isolation dB 21 0.8 Notes: 1. Measurements at 900 MHz obtained using demo board described in Figure 1. 2. OIP3 test condition: FRF1 = 900 MHz, FRF2 = 901 MHz with input power of -10 dBm per tone. 3. For NF data, board losses of the input have not been de-embedded. 4. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application note for more details. 2 Product Consistency Distribution Charts LSL LSL USL USLUSL Id Max : 53 Min : 25 Mean : 40.3 Noise Figure Max : 0.8 Mean : 0.56 30 40 0.5 50 Figure 1. Idd @ 900 MHz, Mean = 40.3 LSL 28 0.8 USL Gain Max : 19.3 Min : 16.3 Mean : 17.8 OIP3 Min : 28.5 Mean : 32.8 27 0.7 Figure 2. Noise Figure @ 900 MHz, Mean = 0.56 LSL 26 0.6 29 30 31 Figure 3. OIP3 @ 900 MHz, Mean = 32.8 32 33 34 35 36 37 16 17 18 19 Figure 4. Gain @ 900 MHz, Mean = 17.8 Notes: 1. Distribution data samples are 500 samples taken from 3 different wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Circuit Losses have not been de-embedded from the actual measurements. 3 Gnd Vdd Vbias Jul 10 Demo Board Schematic Gnd Demo Board Layout C5 NU Rbias Vdd Rbias 12KΩ C6 4.7uF C5 C3 4.7uF C6 R1 R2 L1 L2 C3 R2 9.1Ω R1 0Ω C4 27pF C4 C1 L1 15nH C2 L3 RFin L3 18nH Rapala W MGA-68XP8 Avago Technologies L2 33nH C1 8.2pF [1] [8] [2] [7] [3] [6] [4] [5] C2 100pF RFout Figure 5. Demo Board Layout Diagram Figure 6. Demo Board Schematic Diagram – Recommended PCB material is 10 mils Rogers RO4350. Notes: The schematic is shown with the assumption that similar PCB is used for both MGA-683P8 and MGA-68P8. Detail of the components needed for this product is shown in Table 1. – Suggested component values may vary according to layout and PCB material. Table 1. Component list for 900 MHz matching Part Size Value Detail Part Number C1 0402 8.2 pF Murata GRM15 C2 0402 100 pF Murata GRM15 L1 0402 15 nH Toko LL1005 L2 0402 33 nH Toko LL1005 L3 0402 18 nH Toko LL1005 C4 0402 27 pF Murata GRM15 C3, C6 0402 4.7 F Murata GRM15 Rbias 0402 12 KOhm KOA RK73 R1 0402 0 Ohm KOA RK73 R2 0402 9.1 Ohm KOA RK73 Notes: C2 is a blocking capacitor L2 output match for OIP3 L1, C1 and L3 are used for IRL matching. C3, C4 and C6 are bypass capacitors C5 is not use for this product R2 is stabilizing resistor Rbias is the biasing resistor 4 MGA-683P8 Typical Performance in Demoboard RF performance at TA = 25° C, Vdd = 5 V, measured on demo board in Figure 5 with component list in Table1 for 900 MHz matching, unless otherwise stated. 25 1.2 -40° C 25° C 85° C 0.8 0.6 0.4 0 500 1000 Frequency (MHz) 1500 10 0 2000 Figure 7. NF vs Frequency vs Temperature 0 500 1000 Frequency (MHz) 1500 2000 Figure 8. Gain vs Frequency vs Temperature 38 23.5 36 22.5 34 21.5 P1dB (dBm) OIP3 (dBm) 15 5 0.2 32 30 -40° C 25° C 85° C 28 20.5 19.5 -40° C 25° C 85° C 18.5 26 17.5 0 500 1000 Frequency (MHz) Figure 9. OIP3 vs Frequency vs Temperature 5 -40° C 25° C 85° C 20 Gain (dB) NF (dB) 1 1500 2000 0 500 1000 Frequency (MHz) Figure 10. OP1dB vs Frequency vs Temperature 1500 2000 30 10 K-factor IRL,ORL,Gain,Rev Isol (dB) 20 0 -10 Rev Isol IRL ORL Gain -20 -30 -40 0 1000 2000 3000 4000 Frequency (MHz) 5000 6000 Figure 11. Input Return Loss, Output Return Loss, Gain, Reverse Isolation vs Frequency 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -40° C 25° C 85° C 0 2 4 6 8 10 12 Frequency (GHz) 14 16 0 -40°C 25°C 85°C -5 -5 -15 ORL (dB) IRL (dB) -10 -20 -25 -30 -20 -40 0 500 1000 Frequency (MHz) 1500 2000 Figure 13. Input Return Loss vs Frequency vs Temperature 70 60 50 40 30 6 7 8 Figure 15. Idd vs Rbias 9 10 11 12 13 14 Rbias (Kohm) 15 16 0 500 1000 Frequency (MHz) 1500 Figure 14. Output Return Loss vs Frequency vs Temperature 80 20 -10 -15 -40°C 25°C 85°C 35 Idd (mA) 20 Figure 12. K-factor vs Frequency vs Temperature 0 6 18 17 18 2000 MGA-683P8 Typical Scattering Parameters, Vdd = 5 V Freq GHz S11 S21 S12 S22 Mag. Ang. dB Mag. Ang. Mag. Ang. Mag. Ang. 0.10 0.78 -39.85 28.64 27.04 149.39 0.02 61.61 0.33 -37.71 0.50 0.28 -91.85 21.88 12.41 109.78 0.05 57.18 0.09 -4.96 0.90 0.18 -116.24 17.98 7.92 90.98 0.08 59.30 0.14 -15.82 1.00 0.15 -125.00 17.18 7.22 87.35 0.09 59.00 0.14 -19.87 1.50 0.10 -142.26 14.00 5.01 71.80 0.12 55.32 0.20 -41.56 2.00 0.08 -158.00 11.67 3.83 58.64 0.16 49.50 0.20 -61.44 2.50 0.06 -177.30 9.81 3.09 46.91 0.19 42.91 0.21 -80.22 3.00 0.04 168.68 8.28 2.59 36.14 0.23 36.14 0.23 -95.46 4.00 0.00 -108.56 5.94 1.98 16.53 0.30 22.23 0.25 -119.00 5.00 0.03 -73.16 4.23 1.63 -1.82 0.36 7.81 0.25 -143.80 6.00 0.04 -151.00 2.90 1.40 -19.09 0.42 -6.77 0.25 -170.44 7.00 0.06 -158.00 1.80 1.23 -35.70 0.47 -21.90 0.26 166.00 8.00 0.12 -156.52 0.83 1.10 -51.10 0.52 -36.75 0.30 150.48 9.00 0.17 -162.00 0.01 1.00 -65.36 0.56 -51.21 0.34 138.44 10.00 0.20 -178.00 -0.60 0.93 -79.22 0.60 -66.02 0.35 124.40 11.00 0.21 155.00 -1.06 0.89 -93.53 0.64 -81.83 0.33 104.00 12.00 0.22 123.32 -1.55 0.84 -109.00 0.66 -98.70 0.34 78.63 13.00 0.26 103.28 -2.14 0.78 -123.00 0.66 -115.00 0.38 62.36 14.00 0.32 94.32 -2.66 0.74 -136.00 0.66 -130.00 0.42 59.90 15.00 0.39 84.02 -2.96 0.71 -147.00 0.67 -143.00 0.43 59.92 16.00 0.42 66.23 -3.10 0.70 -160.00 0.68 -158.00 0.40 49.93 17.00 0.43 44.22 -3.53 0.67 -175.88 0.66 -176.00 0.40 27.05 18.00 0.48 28.22 -4.50 0.60 169.00 0.60 167.00 0.48 10.42 19.00 0.57 16.40 -5.59 0.53 156.04 0.53 153.00 0.56 7.77 20.00 0.61 5.40 -6.14 0.49 145.00 0.50 140.00 0.60 6.82 20.0 0.62 5.97 -6.14 0.49 145.85 0.50 140.18 0.60 6.77 Typical Noise Parameters, Vdd=5V Freq Fmin Γopt Γopt GHz dB Mag. Ang. Rn/50 0.5 0.46 0.207 -35.1 0.054 0.7 0.379 0.185 -14.7 0.75 0.366 0.18 0.8 0.356 0.9 0.343 1.7 1.9 [1] RFinput Reference Plane bias [8] [2] [7] 0.06 [3] -10.2 0.055 [4] [6] [5] 0.175 -5 0.0494 0.164 -4.2 0.0432 0.5 0.079 88.9 0.0594 0.55 0.059 125.3 0.0466 RFoutput Reference Plane Figure 16. Notes: 1. The Fmin values are based on noise figure measurements at 100 different impedances using Focus source pull test system. From these measurements a true Fmin is calculated. 2. Scattering and noise parameters are measured on coplanar waveguide made on 0.010 inch thick ROGER 4350. The input reference plane is at the end of the RFinput pin and the output reference plane is at the end of the RFoutput pin as shown in Figure 16. 7 SLP4X4 Package PIN 1 DOT BY MARKING 2.00±0.050 0.203 Ref. 2.00±0.050 83X 0.000–0.05 0.75±0.05 TOP VIEW SIDE VIEW 0.60±0.050 Exp. DAP PIN #1 IDENTIFICATION R0.100 0.35±0.050 1.20±0.050 Exp. DAP 0.50 Bsc 0.25±0.050 BOTTOM VIEW Part Number Ordering Information Part Number No. of Devices Container MGA-683P8-BLKG 100 Antistatic Bag MGA-683P8-TR1G 3000 7 inch Reel 8 1.50 Ref. Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold ash and metal burr. PCB Land Pattern and Stencil Design 2.20 2.16 1.75 0.563x 0.502x 1.75 0.00 0.80 0.506x 1.50 0.258x 0.21 0.228x 0.1702x 0.458x 0.05 (all SM gaps) 0.303x 0.408x R0.154x PCB Land Pattern Stencil Design 1.75 0.563x 0.506x 0.50 Metal surface 0.21 1.50 Soldermask Open R0.154x 0.172x Combines PCB & Stencil Design All Dimension are in millimeters 9 1.72 0.482x 1.50 1.20 0.50 0.506x Device Orientation REEL 4 mm 8 mm 83X CARRIER TAPE USER FEED DIRECTION 83X COVER TAPE Tape Dimensions D P PO P2 E F W + + D1 t1 Tt KO 10° MAX AO DESCRIPTION LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER PERFORATION DIAMETER PITCH POSITION CARRIER TAPE WIDTH CAVITY COVER TAPE DISTANCE 10 10° MAX BO THICKNESS WIDTH TAPE THICKNESS CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) SYMBOL A0 B0 K0 P D1 D P0 E W t1 C Tt F SIZE (mm) 2.30 ± 0.05 2.30 ± 0.05 1.00 ± 0.05 4.00 ± 0.10 1.00 + 0.25 1.50 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 8.00 ± 0.30 8.00 ± 0.10 0.254 ± 0.02 5.4 ± 0.10 0.062 ± 0.001 3.50 ± 0.05 SIZE (INCHES) 0.091 ± 0.004 0.091 ± 0.004 0.039 ± 0.002 0.157 ± 0.004 0.039 + 0.002 0.060 ± 0.004 0.157 ± 0.004 0.069 ± 0.004 0.315 ± 0.012 0.315 ± 0.004 0.010 ± 0.0008 0.205 ± 0.004 0.0025 ± 0.0004 0.138 ± 0.002 P2 2.00 ± 0.05 0.079 ± 0.002 83X 83X Reel Dimensions – 7 inch 6.25mm EMBOSSED LETTERS LETTERING THICKNESS: 1.6mm SLOT HOLE "a" SEE DETAIL "X" Ø178.0±0.5 SLOT HOLE "b" FRONT BACK 6 PS SLOT HOLE(2x) 180° APART. 6 PS RECYCLE LOGO SLOT HOLE "a": 3.0±0.5mm(1x) SLOT HOLE "b": 2.5±0.5mm(1x) FRONT VIEW 12.4 45° 1.5 MIN. +1.5* -0.0 +0.5 Ø13.0 -0.2 Ø20.2 MIN. ° R10.65 120 65° R5.2 45° EMBOSSED RIBS RAISED: 0.25mm, WIDTH: 1.25mm Ø178.0±0.5 Ø51.2±0.3 BACK VIEW For product information and a complete list of distributors, please go to our web site: DETAIL "X" 18.0* MAX. SEE DETAIL "Y" www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-2945EN - May 23, 2012 3.5 DETAIL "Y" (Slot Hole) 1.0 Ø55.0±0.5 BACK Ø178.0±0.5 FRONT