Rohm BM1050AF-G Quasi-resonant control dc/dc Datasheet

Datasheet
Quasi-Resonant Control DC/DC
converter and Power Factor Correction
converter IC for AC/DC Converter
BM1050AF-G
●General Description
BM1050AF is compounded LSI of Power Factor Correction
converter (PFC) for harmonic solution and DC/DC converter
(DC/DC). Because DC/DC operates on Quasi-resonant
method, DC/DC contributes to Low EMI.
BM1050AF built in a HV starter circuit that tolerates 650V.
Because of putting the current sense resistors externally
both the PFC part and the DC/DC part, IC enables power
supply design free.
In the PFC part, IC adopts peak current control operation.
Suitable application is proposed by a various protection
circuit, such as the multiplier with a revision circuit on the AC
voltage falls, the load regulation revision circuit, and the
maximum power feed-forward circuit, etc.
Moreover, the frequency hopping function is built in and it
contributes to low EMI.
The Quasi-resonant system of a DC/DC part contributes to
low EMI because PFC operates by soft switching.
A burst mode is built in, so the power is reduced at light load.
Various protection functions, such as a soft start function, a
burst function, an over-current limiting for every cycle,
overvoltage protection, and over current protection, are built
in. The pin for communicated control with a controller and the
external stop pin are prepared; it proposes the system that
can be adapted for various applications.
●Features
 Quasi-resonant circuit + PFC circuit
 Built-in HV Starter circuit
 Low consumption current (typ.10uA) when starter
circuit is OFF.
 Quasi resonant circuit
Max operating frequency(120kHz)
Frequency reduction function
Over-current limiting variable function
Pulse-by-pulse over-current protection circuit
Built-in Soft start
Voltage protection function (brown out) during low
input
ZT pin Over Voltage Protection
Output overload protection (auto recovery /latch
switching enabled)
250nsec Leading-Edge Blanking
 Power Factor Correction circuit
Peak current control (65kHz)
Frequency hopping function
Per-cycle over current protection circuit
Maximum power revision
the multiplier with a revision circuit when the AC
voltage falls
the load change measure circuit
 Selectable protection method by LATCH/AUTOR
terminal.
LATCH/AUTOR=H : Latch
LATCH/AUTOR=L : Auto recovery
 External stop function (COMP pin)
 AC input voltage stop detected function (ACDET)
 Built-in PFC stop terminal (PFCON/OFF)
●Basic specifications
 Operating Power Supply Voltage Range:
VCC：8.5 to 24.0V
 Operating Current:
QR ON (PFC OFF)：1.20mA(pulse on)
QR ON (PFC OFF)：1.00mA(pulse off)
QR ON (PFC ON)：1.80mA(pulse on)
●Package(s)
SOP24 15.0mm×5.40mm ×1.80mm pitch1.27mm
(Typ.)
(Typ.)
(TYP.)
（TYP.）
 Oscillation Frequency QR part :120kHz(FB=2.0V typ)
 Operating Temperature: -40℃ to +85℃

●Typical Application Circuit(s)
●Applications
TV, AC adapters, printers, LED lighting
Figure 1. Application circuit
○Product structure：Silicon monolithic integrated circuit
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TSZ22111・14・001
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TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●Absolute Maximum Ratings (Ta = 25℃)
Parameter
Maximum applied voltage 1
Maximum applied voltage 2
Symbol
Vmax1
Vmax2
Rating
650
30
Unit
V
V
Maximum applied voltage 3
Vmax3
5.5
V
Maximum applied voltage 4
output peak current 1
output peak current 2
QR_ZT pin current 1
QR_ZT pin current 2
Allowable dissipation
Operating temperature range
Maximum junction temperature
Storage temperature range
Vmax4
IOH
IOL
ISZT1
ISZT2
Pd
Topr
Tjmax
Tstr
15
-0.5
1.0
-2.0
3.0
687.6 (Note1)
-40 ～ +85
150
-55 ～ +150
V
A
A
mA
mA
mW
o
C
o
C
o
C
Conditions
VH_IN
VCC, QR_SEL
P_BO, P_VSEO, P_VS, P_BOPK
P_CS,PFCON/OFF,COMP,
ACDET, ACTIMER,QR_CS, QR_ZT,
QR_FB,LATCH/AUTOR, VREF
GCLAMP, P_OUT, QR_OUT
QR_OUT, P_OUT
QR_OUT, P_OUT
(Note1) When mounted (on 70 mm × 70 mm, 1.6 mm thick, glass epoxy on single-layer substrate).
Reduce to 5.5 mW/C when Ta = 25C or above.
●Operating Conditions (Ta = 25℃)
Parameter
Power supply voltage range 1
Power supply voltage range 2
Power supply voltage range 3
Symbol
VCC
VH_IN
P_BO
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TSZ22111・15・001
Rating
8.5～24.0
80～600
0.0～1.8
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Unit
V
V
V
Conditions
VCC
VH_IN
P_BO
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●Electrical Characteristics (Unless otherwise noted, Ta=25, VH_IN=320Vdc, VCC=12V)
Specifications
Parameter
Symbol
Unit
Minimum
Standard Maximum
Conditions
［Circuit current］
Circuit current (ON) 1
ION1
0.700
1.200
1.700
mA
VCC=12.0V
(QR=ON, PFC=OFF)
QR_FB=1.0V
(during pulse operation)
Circuit current (ON) 2
ION2
0.700
1.000
1.300
mA
VCC=12.0V
(QR =ON, PFC=OFF)
QR_FB=VREF
(during
pulse
operation
when OFF)
Circuit current (ON) 3
ION3
0.800
1.800
2.800
mA
VCC=12.0V
(QR =ON, PFC=ON)
QR_FB=1.0V
(during pulse operation)
Start current 1
Start current 2
ISTART1
ISTART2
0.100
1.000
0.500
3.000
1.000
5.000
mA
mA
OFF Current
ISTART3
-
10
16
uA
VSC
0.400
0.800
1.400
V
VREF output voltage
VREF output capacitor
GCLAMP voltage 1
GCLAMP voltage 2
VREF1
CREF
GCL1
GCL2
3.500
0.68
11.0
11.0
4.000
1.00
12.5
12.5
4.500
2.20
14.0
14.0
V
uF
V
V
VREF UVLO 1
VRUVLO1
77.5
（3.100V）
87.5
(3.500V)
97.5
(3.900V)
%
VREF UVLO 2
VRUVLO2
52.5
(2.100V)
62.5
(2.500V)
72.5
(2.900V)
%
VREF UVLO hysteresis
VRUVLO3
-
VCC UVLO voltage 1
VCC UVLO voltage 2
VCC UVLO hysteresis
VCC OVP voltage 1
VCC OVP voltage 2
VCC OVP hysteresis
Brown out detection voltage 1
Brown out detection voltage 2
Brown out hysteresis
Brown out detection
delay time 1
Brown out detection
delay time 2
Brown out detection
delay time 3
VUVLO1
VUVLO2
VUVLO3
VOVP1
VOVP2
VOVP3
VBO1
VBO2
VBO3
［Start circuit Block］
VH voltage switched
start current
VCC= 0V
VCC=10V
Input current from VH_IN
terminal after releasing
UVLO
［VREF Block］
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TSZ22111・15・001
-
%
12.50
5.50
24.0
20.0
0.350
-
25
（1.000V）
13.50
7.00
6.50
27.0
23.0
4.0
0.400
0.200
0.200
14.50
8.50
30.0
26.0
0.450
-
V
V
V
V
V
V
V
V
V
TBO1
21.8
32.0
42.2
ms
TBO2
87.0
128.0
169.0
ms
TBO3
170
250
330
ms
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VCC=15V
VCC=22V
When VREF rise
The ratio of VREF pin
voltage.
When VREF drop
The ratio of VREF pin
voltage.
VRUVLO3= VRUVLO1- VRUVLO2
VCC rise
VCC drop
VUVLO3= VUVLO1- VUVLO2
VCC rise
VCC drop
VOVP3= VOVP1 - VOVP2
P_BO rise
P_BO drop
VBO3 = VBO1－VBO2
Times until ACDET logic
change ( ACTIMER=L)
Times until ACDET logic
change ( ACTIMER=H)
Times until PFC and QR
stop
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●Electrical Characteristics (Unless otherwise noted ,Ta=25,VH_IN=320Vdc,VCC=12V)
Specifications
Parameter
Symbol
Unit
Minimum
Standard Maximum
［ACDET pin characteristics］
ACDET pin ON resister
RACDET
50
100
200
Ω
［ACTIMER pin characteristics］
ACTIMER pin input L level
VACTIMEL
0.3
V
ACTIMER pin input H level
VACTIMEH
1.2
V
ACTIMER pin
RACTIMEH
165
330
500
kΩ
pull-down resistor
［PFCON/OFF pin characteristics］
PFCON/OFF pin input L level
VPON/OFFL
0.3
V
PFCON/OFF pin input H level
VPON/OFFH
1.2
V
PFCON/OFF pin
RPON/OFFH
50
100
150
kΩ
pull-down resistor
PFCON/OFF pin timer time
TPFCON/OFF
0.50
1.50
3.00
ms
［LATCH/AUTOR pin characteristics］
LATCH/AUTOR pin
0.3
V
VMODEL
input L level
LATCH/AUTOR pin
1.2
V
VMODEH
input H level
LATCH/AUTOR pin
50
100
150
kΩ
RMODEH
pull-down resistor
Conditions
PFC = ON
PFC = OFF
[COMP pin characteristics]
COMP pin detection voltage
COMP pin pull-up resistor
External Thermistor resistor
Latch release voltage
（VCC pin voltage）
VCOMP
RCOMP
RT
0.370
19.4
3.32
0.500
25.9
3.70
0.630
32.3
4.08
V
kΩ
kΩ
VLATCHOFF
-
VUVLO2 -0.5
-
V
TCOMP
70
150
240
us
Latch mask time
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TSZ02201-0F2F0A200140-1-2
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Datasheet
BM1050AF-G
●Electrical Characteristics (Unless otherwise noted Ta=25, VH_IN=320Vdc, VCC=12V)
Specifications
Parameter
Symbol
Unit
Minimum
Standard Maximum
Conditions
[Quasi-resonant Control Block]
[Quasi-resonant DC/DC converter Block (turn off)]
QR_FB pin pull-up resistance
RFB
15
20
25
kΩ
CS over-current
detect voltage 1A
Vlim1A
0.950
1.000
1.050
V
Izt<1.0mA
CS over-current
detect voltage 1B
Vlim1B
0.630
0.700
0.770
V
Izt>1.0mA
CS over-current
detect voltage 1C
Vlim1C
-
0.250
-
V
Izt<1.0mA
CS over-current
detect voltage 1D
Vlim1D
-
0.750
-
V
Vlim2A
-
0.150
-
V
IZT
0.800
1.000
1.200
mA
TLEB
-
0.250
-
us
TOFF
Tmin
-
0.250
0.500
-
us
us
CS over-current
detect voltage 2A
CS switched ZT current
CS Leading
Edge Blanking time
Turn off time
Minimum ON width
Izt<1.0mA
QR_FB=0.3V (Izt<1.0mA)
*1
TLEB＋TOFF
[Quasi-resonant DC/DC converter Block (turn on)]
Maximum operating
frequency 1
Maximum operating
frequency 2
Frequency reduction
start FB voltage
Frequency reduction
end FB voltage
FSW1
106
120
134
KHz
QR_FB=2.00V
FSW2
24
30
36
KHz
QR_FB=0.50V
VFBSW1
1.15
1.250
1.350
V
VFBSW2
0.35
0.50
0.65
V
AVCS
1.70
2.00
2.30
V/V
ZT comparator voltage 1
VZT1
60
100
ZT comparator voltage 2
VZT2
300
400
ZT trigger timeout period
TZTOUT
15
[Quasi-resonant DC/DC converter protection functions]
Soft start time1
TSS1
0.60
1.00
Soft start time2
TSS2
2.60
4.00
FB OLP Voltage 1a
VFOLP1A
2.5
2.8
FB OLP Voltage 1b
VFOLP1B
2.6
140
500
-
mV
mV
us
1.40
5.40
3.1
-
ms
ms
V
V
FB OLP Voltage 2a
VFOLP2A
3.3
3.6
3.9
V
FB OLP Voltage 2b
VFOLP2B
-
3.4
-
V
FB OLP mode switched
external connected resistor
RFOLP2
90
100
110
kΩ
FB OLP timer
ZT OVP Voltage
TFOLP
VZTL
44
3.2
64
3.5
84
3.8
ms
V
RPOUT
5
15
30
Ω
RNOUT
2
5
10
Ω
RMASK
-
150
-
Ω
Voltage gain
⊿V (QR_FB)/⊿V
（QR_CS）
QR_ZT drop
QR_ZT rise
Count from final ZT trigger
Operate QR_FB rise
Operate QR_FB drop
Switched latch / Auto
recovery rise
Switched latch / Auto
recovery drop
QR_FB
pin
external
resistance value (during
latch mode)
[QR_OUT pin]
QR_OUT pin
PMOS ON resistor
QR_OUT pin
NMOS ON resistor
[QR_SEL pin]
QR_SEL pin Ron
*1 Pulse is applied to QR_CS pin
*2 Pulse is applied to QR_ZT pin
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TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●Electrical Characteristics (Unless otherwise noted Ta=25, VH_IN=320Vdc, VCC=12V)
Specifications
Parameter
Symbol
Unit
Minimum
Standard Maximum
Conditions
[Power Factor Correction（PFC）controller block]
[Power Factor Correction (PFC) Gm amplifier block]
P_VS pin pull-up current
Gm amplifier normal voltage
Gm amplifier
trans-conductance
Maximum Gm amplifier
source current
Maximum Gm amplifier
sink current
IP_VS
VVSAMP
2.460
0.50
2.500
2.540
uA
V
VVSGM
30.8
44.0
57.2
uS
IVSAMP1
15
25
35
uA
P_VS=1.0V
IVSAMP2
24
40
56
uA
P_VS=3.5V
1.800
1.00
V
uA
[Power Factor Correction (PFC) input voltage monitor block]
P_BO input voltage range
P_BO pin leak current
VP_BOIN
IBOLEAK
0.000
-1.00
0.00
[Power Factor Correction (PFC) input voltage peak detect block]
P_BOPK max charge current
P_BOPK max
discharge current
IBOPKCHG
36
72
144
uA
IBOPKDIS
0.1
0.2
0.4
uA
0.54
226
128
0.71
271
168
mV
mV
65
4.0
125
500
94.0
70
175
98.0
KHz
KHz
Hz
ns
%
15
5
30
10
Ω
Ω
[Power Factor Correction (PFC) multiplier block]
Multiplier constant
P_VSEO stop voltage 1
P_VSEO stop voltage 2
KMULTI
VVSEO1
VVSEO2
0.37
181
88
BOPK=0.56V
BOPK=1.30V
[Power Factor Correction (PFC) Oscillation frequency block]
PFC Oscillation frequency
PFC Frequency hopping width
PFC hopping frequency
Minimum Pulse width
Maximum DUTY
FPSW1
FPSWEL
FPCH
Tmin
Dmax
60
75
90.0
[Power Factor Correction (PFC) Driver block]
P_OUT pin PMOS ON resistor
P_OUT pin NMOS ON resistor
RPPOUT
RPNOUT
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TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●Electrical Characteristics (Unless otherwise noted Ta=25, VH_IN=320Vdc, VCC=12V)
Specifications
Parameter
Symbol
Unit
Minimum
Standard
Maximum
Conditions
[Power Factor Correction (PFC) controller block ]
[Power Factor Correction (PFC) protection function block ]
Leading Edge Blanking time
P_CS over current limit
voltage 1
P_CS over current limit
voltage 2
TPLEB
-
250
-
ns
VPCS1
0.93
1.16
1.40
V
P_BOPK=0.56V
VPCS2
0.48
0.60
0.72
V
P_BOPK=1.30V
P_VS short protection voltage
VP_SHORT
0.200
(-92%)
0.300
（-88%）
0.400
(-84%)
V
QR power-limit P_VS voltage1
VPFCON
QR power limit P_VS voltage2
VPFCOFF
1.800
(-28%)
1.100
(-56%)
2.000
(-20%)
1.250
(-50%)
2.200
(-12%)
1.400
(-44%)
P_VS QR power
limit hysteresis
VPFCHYS
-
0.750
(30%)
-
V
P_VS gain rise voltage
VPGUP
2.050
(-18%)
2.450
(-2%)
V
P_VS gain fall voltage
VPOVP1
-
-
V
VPOVP2
-
2. 250
（-10%）
2.625
（+5%）
2.725
（+9%）
-
V
TPOVP2
16
32
48
ms
P_VS over voltage
protection voltage
P_VS over voltage
protection timer
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Figure of () is comparison
with P_VS standard voltage
2.5V
Figure of () is the ratio of
P_VS standard voltage 2.5V
Figure of () is the ratio of
P_VS standard voltage 2.5V
V
V
Figure of () is the ratio of
P_VS standard voltage 2.5V
Figure of () is the ratio of
P_VS standard voltage 2.5V
Figure of () is the ratio of
P_VS standard voltage 2.5V
Figure of () is the ratio of
P_VS standard voltage 2.5V
The time to detect P_VS
over voltage protection
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●PIN Configure
Table 1. I/O Pin Functions
NO
1
PIN
P_BO
I/O
Function
I
Input AC Voltage monitor pin
I/O
PFC gm amplifier output pin
2
P_VSEO
3
P_VS
I
PFC Output voltage monitor pin
4
P_BOPK
O
Connected capacitor to the pin
5
P_CS
I
PFC Coil current monitor pin
6
PFCON/OFF
I
PFC ON/OFF control input pin
7
COMP
I
External latch stop pin
8
ACDET
O
Input AC voltage state communication pin
9
ACTIMER
10
GND
I
I/O
Brown out detection time setting input pin
GND
11
P_OUT
O
PFC Output drive pin
12
GCLAMP
I/O
Gate H level clamp pin
13
VCC
I/O
Power supply pin
14
QR_OUT
O
Quasi-resonant Output drive pin
15
QR_SEL
O
Quasi-resonant Mask pin
16
GND
I/O
GND
17
QR_CS
I
Quasi-resonant Over current detected pin
18
QR_FB
I
Quasi-resonant Feedback detected pin
19
QR_ZT
I
Quasi-resonant Zero cross detected pin
20
LATCH/AUTOR
I
Protection mode switched input pin
21
VREF
O
Internal power supply pin
22
-
-
-
23
-
-
-
24
VH_IN
I
AC Input voltage applied pin
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ESD protection system
VCC
GND
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
-
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
●I/O Equivalent Circuit Diagram
Figure 2. I/O Equivalent Circuit Diagram
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TSZ02201-0F2F0A200140-1-2
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Datasheet
BM1050AF-G
●Block Diagram
+
AC
FUSE
Diode
Bridge
Filter
85-265Vac
P_VS
-
BD9212F
BD92XX
AND
AND
+
-
Internal
Supply
100k
+
+
-
AND
QR_ZT
+
+
-
OR
+
0.5V
GateClamp
+
-
ERROR
AMP
1/VBOPK
+
MIN ON
WIDTH
Internal CLK
65kHz±4.0kHz
+
-
RAMP
+
*K2
×
*K3
+
+
-
S
Q
MAX DUTY
94%
15Ω
AND
R
OR
PRE
Driver
+
-
1MΩ
5Ω
P_VS
+
+
+
*K1
Leading Edge
Blanking
(250ns)
+
3.50V
STOP
QR_ZT
+
100mV
/400mV
1 shot
AND
7V
ZT Blanking
OUT(H->L) 0.60us
NOUT
OR
TimeOut
( 15 usec )
MAX Blanking
Frequency
(120kHz)
+
+
-
S
AND
OR
POUT
Q
1.25V
15Ω
R
BURST_OH
+
-
20kΩ
0.50V
+
-
1MΩ
FB/2
200kΩ
1.00V
+
5Ω
Soft
Start
OSC
+
-
PRE
Driver
NOUT
Timer
(64ms)
FBOLP_OH
200kΩ
AND
SS1ms
SS4ms
CURRENT SENSE (V-V Change)
Normal : ×1.0
Leading Edge
Blanking
(250ns)
Figure 3. Block Diagram
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TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
AND
AND
+
-
Internal
Supply
100k
+
+
-
AND
+
+
-
OR
+
0.5V
GateClamp
+
-
1/VBOPK
+
MIN ON
WIDTH
Internal CLK
65kHz±4.0kHz
+
-
RAMP
+
*K2
×
*K3
Q
MAX DUTY
94%
15Ω
+
+
-
S
AND
R
OR
PRE
Driver
+
-
1MΩ
5Ω
+
+
+
*K1
Leading Edge
Blanking
(250ns)
+
3.50V
STOP
+
100mV
/400mV
1 shot
AND
7V
ZT Blanking
OUT(H->L) 0.60us
NOUT
OR
TimeOut
( 15 usec )
AND
MAX Blanking
Frequency
(120kHz)
+
+
-
S
OR
POUT
Q
1.25V
20kΩ
15Ω
BURST_OH
+
0.50V
+
-
200kΩ
1.00V
PRE
Driver
NOUT
1MΩ
5Ω
Soft
Start
OSC
+
-
FB/2
AND
Timer
(64ms)
FBOLP_OH
200kΩ
R
+
SS1ms
SS4ms
CURRENT SENSE (V-V Change)
Normal : ×1.0
Leading Edge
Blanking
(250ns)
Figure 3-2. Block Diagram
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BM1050AF-G
●Explanation of each block
(1) Starter block (24pin)
BM1050AF built in the starter circuit that withstands 650V. For that, application used the IC is enabled faster start time and
low standby power. After start-up, consumption power is idling current ISTART3（typ=10uA）only.
Reference of start-up time is shown in Figure 6.
It can start-up less than 0.1sec when Cvcc=10uF.
Figure 4. Start Circuit Block Diagram
1.0
0.9
0.8
Start time[sec]
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
5
10
15
20
25
30
35
40
45
50
Cvcc [uF]
Figure 5. Start-up current vs VCC voltage
Figure 6. Start time vs Cvcc (Reference values）
*Start current flows from VH_IN pin to VCC pin.
ex) When Vac=100V; consumption power of start-up circuit only.
PVH＝100V*√2*10uA=1.41mW
ex) When Vac=240V; consumption power of start-up circuit only.
PVH＝240V*√2*10uA=3.38mW
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(2) Start sequence
The start sequence of IC operates DC/DC part, next PFC part (See the figure 7).
A : Input voltage VH is applied.
B : Charge current flows from VH_IN pin to the VCC pin capacitor. Then VCC pin voltage rises.
C : Monitor the AC voltage by P_BO pin. And confirm normal state by releasing brown out.
D :When VUVLO1（typ=13.5V） < VCC pin, release the inside UVLO and ON the inside regulator VREF.
E : When VRUVLO1（typ=87.5%） < VREF pin, release the inside VREFUVLO.
F : If the ‘E’ state continues constant period, DC/DC part starts because it recognizes normal state.
When the switching starts, VOUT voltage rises.
When the DC/DC start-up, please set external parts to be regulated output voltage within the TFOLP period (64ms .typ ).
[QR start-up operation]
G: This IC adjusts over current limiter of DC/DC by operation of soft start 1 against over voltage and current rising.
That term continues Tss1 (typ=1ms).
H: This IC adjusts over current limiter of DC/DC by operation of soft start 2 against over voltage and current rising.
Soft start 2 operation continues power limiter operation until P_VS pin voltage > VPFCON (2.00V typ) and TSS2（typ=4ms） .
This IC operates the state that maximum power of QR is 50% at this state.
I: If secondary voltage is setting value, QR_FB pin voltage is constant value corresponded load by current from photo coupler.
At normal state, QR_FB voltage is QR_FB<VFBOLP1B (2.60V typ).
[PFC start up operation]
J: At the point in I time, This IC recognizes that the part of DC/DC operation is normal, Part of PFC starts operation.
K: If P_VS pin voltage is upper VP_SHORT (typ = 0.3V), this IC judges short detection normal.
L: P_VSEO voltage rises from 0V to prevent from over rising voltage and current at PFC part.
At this time P_OUT pin DUTY increase from 0% with P_VSEO voltage increasing.
Figure 7. Start sequences Timing chart
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About figure7, condition is PFCON/OFF=L.
Start up operation is shown at figure8, 9 by the state shift figure.
Figure 8 is LATCH/AUTOR=L (auto return operation), and figure 9 is LATCH/AUTOR=H (LATCH operation)
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Figure 8. Diagram of state machine (LATCH/AUTOR=L)
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Figure 9. Diagram of state machine (LATCH/AUTOR=H)
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(3) VCC protection function and VREF pin function
(3-1) VCC pin protection function(13pin)
BM1050AF built in VCC low voltage protection function of VCCUVLO (Under Voltage Lock Out) and over voltage protection
function of VCC OVP (Over Voltage Protection).
This function monitors VCC pin and prevent VCC pin from destroying switching MOSFET at abnormal voltage.
VCCUVLO is auto recovery comparator that has voltage hysteresis. VCCOVP operates as latch mode comparator in the
LATCH/AUTOR=H and as auto return comparator in the LATCH/AUTOR=L.
VCC<VLATCHOFF (typ = Vuvlo1 - 0.5) is condition of latch release (reset) after detection of latch operation by VCCOVP.
Refer to the operation figure10.
VCCOVP built in mask time TCOMP (typ=150us), in case of continuing VCCOVP 150us, operates over voltage detection.
By this function, this IC masks pin generated surge etc.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Figure10. VCC UVLO / OVP (LATCH/AUTOR=H at Latch stop)
A:VH input, VCC voltage rise
B:VCC>Vuvlo1,DC/DC operation start
C:VCC<Vuvlo2,DC/DC operation stop
D:VCC>Vuvlo1,DC/DC operation start
E:VCC voltage decreases until starting DC/DC switching
F:VCC rise
F:When VCC>Vovp1,DC/DC operation is stopped. Switching is stopped by internal latch signal.
G:Then DC/DC operation is stopped, power supply is lost from auxiliary, VCC voltage downs.
H:VCC<Vuvlo2, VCC voltage rises for dropping IC's consumption current.
I:VCC>Vuvlo1, this IC dose not operate DC/DC for latch operation. VCC voltage drops because of dropping of IC's consumption
current.
J:same of H
K:same of I
L:same of J
M:VH is open(the state is outlet out).VCC drops.
N:VCC <VCOMP, latch releases.
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(3-2) VREF pin function(21pin)
VREF pin is internal regulator output pin.
The use of VREF pin is IC's internal supply and connection of LATCH/AUTOR pin changing.
This pin needs an external capacitance, please use the capacitance following table.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Parameter
Table 2. VREF pin output capacitor capacitance
Specification
Symbol
Unit
Minimum
Standard Maximum
VREF Output Capacitor
CREF
0.68
1.00
2.20
Conditions
uF
(3-3) VREF pin protection function(21pin)
VREF pin built in low voltage protection function VREF UVLO (Under Voltage Protection).
This IC prevents from error operating at the time, VREF starts up and VREF is low, by this function.
Figure11. VREF UVLO Function
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（3-4）Blown out function(1 pin)
BM1050AF built in blown out function. This function is that this IC stops DCDC operating at the time when input AC voltage is
low. Show the example figure12. This IC divides input voltage by the resistance, and input P_BO pin.
This IC detects from circuit normal state, and starts DC/DC operation the time when P_BO pin exceeds Vbo1(0.4V typ).
ACDET=L after TBO1(typ.32ms) or Tbo2(typ.128ms) from P_BO pin drops from VBO2(0.2V typ).
Moreover, if TBO3 (typ.250ms) passes from P_BO<VBO2, DC/DC part and PFC part is stopped.
About every resistance of fugure12, because P_BO pin is used PFC operation, please set Rbo1=4Mohm,Rbo2=16kohm for
operating the range of P_BO pin voltage 0~1.8V. In this case, by the following formula, P_BO=0V~0.56V at the case AC100V,
P_BO=0V~1.237V at the case AC220V.
P_BO =（ 2 × VAC
Then
２× VAC >> VF1
P_BO = ２× VAC ×
VF1）
×
RBO2
RBO1 + RBO2
R BO2
R BO1 + R BO2
Figure12. Block Diagram of Blown out Function
Figure13. Detection Way of Blown out Function
A : P_BO > VBO1(typ.0.4V) 、ACDET=L->H
B: After 150us from A DC/DC part starts up.
C:QR_FB<VFCLP1B（typ.2.6V）. PFC part starts up.
D: If PFC output is larger than constant voltage, ACTIMER=L->H.
E: P_BO<VBO2 (typ.0.2V) Timer start operation by detection blown out protection.
F:After TBO1(typ.32ms) or TBO２(typ.128ms) from E, ACDET=H->L. It is possible to set TBO1 and TBO２ at ACTIMER pin
G:After TBO2(typ.250ms) from E, DC/DC part and PFC part are OFF
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(4)Controller part
(4-1)ACDET pin (8pin)
ACDET pin is NMOS open drain output. It monitors AC voltage, and is used for controlling secondary micon.
Show the using example figure14, 15. Please set VIN is H voltage of micon.
ACDET=L ： Abnormal state（P_BO < 0.2V）
ACDET=H ： Normal state
Figure14. Using Example of ACDET Pin
Figure15. Explanation of ACDET Pin
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Next, show an easy sequence.
Figure16. At applied AC Input Voltage（P_BO voltage<0.4V）
Because P_BO < 0.4V, DC/DC part is OFF.
VCC voltage>13.5V
Figure17. At applied AC Input Voltage（P_BO voltage >0.4V）
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A：Detect P_BO＞0.4V, Quasi resonance starts operation After 150μs
B：PFC start up
C：PFC output stabilized
*About PFC operation, by the micon, is able to be controlled using PFCON/OFF pin.
Figure18. At
AC Power Supply OFF
A：Detect P_BO＜0.2V, internal ACDET timer operates. At this time, output of PWC downs.
B：After 32ms （ACTIMER=L） from the point A, ACDET pin voltage is H->L, send to the μ-controller abnormal signals.
C：After 250ms from the point of A,PFC and Quasi Resonant are stopped
Figure19.
At AC Power Supply the case of operation moment stop
The case of AC voltage is OFF suddenly, constant area is masked.
The time of constant area of masking is depends on ACTIMER pin.
The case of ACTIMER pin=L, Mask time=32ms、 the case of ACTIMER pin=H, mask time=128ms.
The moment of AC voltage momentary power interruption, because PFC output voltage is down by corresponding to load,
please watch out.
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(4-3) PFCON/OFF pin
PFCON/OFF pin is NMOS gate input pin. Refer to following the functions.
An internal timer is integrated for noise protection on PFCON/OFF pin.
After TPFCON/OFF(typ.1ms) from PFCON/OFF H→L, PFCON/OFF L operation starts. At PFCON/OFF L→H, internal timer is not
integrated.
function1）PFC circuit operation is OFF control.
In order to reduce standby power, IC controls PFC part operation at PFCON/OFF pin.
function2）QR_SEL pin is Hi-z→L
Refer to example of using at figure 20.
PFCON/OFF=L ： DC/DC part＝ON、 PFC part＝ON、QR_SEL＝Hi-Z
PFCON/OFF=H ： DC/DC part＝ON、 PFC part＝OFF、QR_SEL=L
VREF
LOGIC
PFC
ON/OFF
uCOM
PC
Controlled by Nch OPEN-drain
Plimary Side
Figure20.
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Using example of PFCON/OFF pin
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(4-4) LATCH/AUTOR pin
LATCH/AUTOR pin is NMOS gate input pin. Refer to example of using at figure21.
Operation setting of protection function is shown at table3.
LATCH/AUTOR=L ： Auto recovery
LATCH/AUTOR=H ： Latch
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Figure21. Using example of LATCH/AUTOR pin
ITEM
VREFUVLO
VCCUVLO
VCCOVP
blown out
QR_FB_OLP1
QR_FB_OLP2
QR_ZT OVP
P_VS short
protection
P_VS GAIN
increasing
P_VS OVP1
P_VS OVP2
COMP function
LATCH/AUTOR=GND
Contents
detection
method
VREF PIN
Low voltage protection
function
VCC PIN
Low voltage protection
function
VCC PIN
Over voltage protection
function
Input AC voltage
Low voltage protection
function
QR_FB pin
Over current protection
function
QR_FB pin
Over current protection
function
QR_ZT pin
Over voltage protection
function
P_VS pin
Short protection
function
P_VS pin
Low voltage gain
increasing function
P_VS pin
Over voltage protection
function1
P_VS pin
Over voltage protection
function2
COMP pin
Protection function
operation
at detection
PFC part, DC/DC
part operation
stops
PFC part, DC/DC
VCC<7.0V
part operation
（VCC falling）
stops
VCC>27V state
PFC part, DC/DC
continues between part operation
150us（VCC rising） stops
P_BO＜0.2V state PFC part, DC/DC
continues between part operation
250ms
stops
（QR_FB>2.8V）state
continues between DC/DC part
operation stops
250ms（QR_FB
VREF<2.5V
（VREF falling）
）
QR_FB>3.6V
（QR_FB rising）
DC/DC part
operation stops
QR_ZT>3.5V state
continues between DC/DC part
operation stops
150us（QR_ZT
）
P_VS<0.30V
PFC part
（P_VS falling）
operation stops
LATCH/AUTOR
release
mothod
operaetion
at detection
VREF>3.5V
（VREFrising）
VCC>13.5V
（VCC rising）
VCC<23.0V
（VCCfalling）
P_BO>0.4V
（P_BOrising）
PFC partDC/DC
part
enable to operate
PFC partDC/DC
part
enable to operate
PFC partDC/DC
VCC>27V
part
（VCC rising）
enable to operate
PFC partDC/DC
part
enable to operate
QR_FB<2.6V
（QR_FB falling）
normal operation
QR_FB<3.4V
（QR_FB falling）
normal operation
same as LATCH/AUTOR=GND
PFC part, DC/DC
VCC<6.5V
part latch operation
（VCC falling）
stops
same as LATCH/AUTOR=GND
same as LATCH/AUTOR=GND
normal operation
same as LATCH/AUTOR=GND
P_VS>2.625V
（P_VS rising）
GM AMP GAIN
falling
P_VS<2.625V
（P_VS falling）
normal operation
P_VS<2.600V
（P_VS falling）
normal operation
COMP>0.50V
（COMP rising）
normal operation
PFC part,
DC/DCpart enable
to operate
same as LATCH/AUTOR=GND
P_VS>0.30V
（P_VS rising）
normal operation
operaetion
at detection
same as LATCH/AUTOR=GND
normal operation
P_VS>2.25V
（P_VS rising）
COMP<0.5V state PFC part, DC/DC
continues between part operation
150us（COMP
stops
）
release
mothod
QR_ZT<3.5V
（QR_ZT falling）
GM AMP GAIN
increasing
PFC part stops
operation
at detection
QR_ZT>3.5V state PFC part, DC/DC
continues between part latch operation VCC<6.5V
（VCC falling）
150us（QR_ZT
stops
）
same as LATCH/AUTOR=GND
P_VS<2.25V
（P_VS falling）
P_VS>2.725V
（P_VS rising）
detection
method
normal operation
same as LATCH/AUTOR=GND
PFC part, DC/DC
P_VS>2.725V
VCC<6.5V
part latch operation
（P_VS rising）
（VCC下降時）
stops
COMP<0.5V state PFC part, DC/DC
VCC<6.5V
continues between part latch operation
（VCC falling）
150us（COMP
stops
）
normal operation
normal operation
Table 3. List of Protection Function Operation Setting by LATCH/AUTOR pin
*Comparator level of protection function is shown by TYP value.
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(4-5) ACTIMER pin
ACTIMER pin is NMOS gate input pin. Show example of using figure 22, 23
Set the detect timer of AC voltage drop. （please refer to ACDET pin page）
Figure22.
ACTIMER=GND
ACTIMER=VREF
Using example of ACTIMER pin
: 32ms Timer
:128ms Timer
Figure23. AC power at the case momentary power interruption OFF
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(4-6) COMP pin（external stop control function）
COMP pin is stop control pin. When COMP pin voltage drops from VCOMP (0.5V. typ), COMP pin stops PFC and DC/DC part
operation.
This IC built in TCOMP (150us .typ) until stopping switching, prevent from stopping by noise.
COMP pin is in pull-up resistor RCOMP (25.9kΩ. typ), When COMP pin is the state of pull-down with lower resistance than
RT(3.70kΩ.typ), COMP pin detects abnormal. Show application examples at the figure24, 25, and 26.
Temperature protection by NTC thermister
By putting a thermister at the COMP pin, it is possible to stop latch on temperature rising.
The case of this application, please design thermister resister is RT(3.70kΩ.typ) on temperature detection.
（Figure24 and 25 is application circuit that latch on Ta=110℃）
Resister value R [kΩ]
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
20.0
18.0
16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0.0
RTt(typ3.7kΩ)
Detect
0
20
40
60
80
100
120
140
160
180
200
Temparature T[℃ ]
Figure 24. Temperature Protection Application
Figure 25. Temperature–Thermistor Resistor characteristic
Secondary over- voltage protection
This IC can detect secondary over-voltage by putting photo coupler to COMP pin.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Figure26.Output Over Voltage Protection Application
Table 4. Changes of COMP function Operation by LATCH/AUTOR pin
LATCH/AUTOR=GND
ITEM
COMP function
contents
COMP pin
protection function
detection
method
operation
at detection
LATCH/AUTOR=VREF
release
mothod
operaetion
at detection
COMP<0.5V state
PFC part, DC/DC
COMP>0.50V
continues between
part operation stops （COMP rising）
150us（COMP falling）
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detection
method
operation
at detection
release
mothod
COMP<0.5V state PFC part, DC/DC
P_VCC<6.5V
continues between part latch operation
（P_VCC falling）
150us（COMP falling） stops
operaetion
at detection
normal operation
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Datasheet
BM1050AF-G
(5)Quasi-Resonant DC/DC converter function
Part of quasi-resonant DC/DC uses PFM(Pulse Frequency Modulation)mode control.
The QR_FB pin, QR_ZT pin and QR_CS pin are monitored to provide a system optimized for DC/DC."
The switching MOSFET ON width (turn OFF) is controlled via the QR_FB pin and QR_CS pin, and the OFF width(turn ON).
Show following detail explanation. (refer to figure27).
Figure27.
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(5-1) Determination of ON width (turn OFF)
ON width is controlled via the QR_FB pin and QR_CS pin.
The QR_FB pin voltage is compared with the IC internal voltage Vlim1 (1.0V typ) and, as is shown in Figure28.
And the comparator level changes linearly.
The QR_CS pin is also used for the pulse-by-pulse over current limiter circuit.
By changing voltage at the QR_FB pin, DC/DC results in changes of the maximum blanking frequency and
over-current limiter level.
・mode1: Burst operation
・mode2: Frequency reduction operation(reduces maximum frequency)
・mode3: Maximum frequency operation(operates at maximum frequency)
・mode4: Overload operation(pulse operation is stopped when overload is detected)
(a)
Izt<1.0mA
(b) Izt>1.0mA
Figure 28. Relation of QR_FB pin, over current limiter and maximum frequency
The over current limiter level is adjusted, when the input voltage is changed, operate the soft start function.
In this case, the Vlim1 and Vlim2 values are as listed below."
Table 5. current protection voltage of Quasi-resonant DC/DC
Soft start
AC=100V
AC=230V
Vlim1
Vlim2
Vlim1
Vlim2
Start～1ms
0.250V ( 25.0%)
0.039V ( 3.9%)
0.176V ( 17.6%)
0.026V ( 2.6%)
1ms～PFC Start &4ms
0.750V ( 75.0%)
0.113V ( 11.3%)
0.525V ( 52.5%)
0.079V ( 7.9%)
PFC Start & 4ms～
1.000V (100.0%)
0.150V ( 15.0%)
0.700V ( 70.0%)
0.105V ( 10.5%)
*( ) is AC=100V, these show relative value of compare with Vlim1（1.0Vtyp） of normal operation.
This table is separated AC100V and AC230V for the function of QR_CS current changing function that is shown （4-3）.
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(5-2)LEB(Leading Edge Blanking)function
When the switching MOSFET is turned ON, surge current occurs at each capacitor charge /discharge or drive current.
For that, QR_CS voltage rise temporarily, over current limiter may be detected errors.
To prevent detection errors blanking time is built in to mask TLEB (typ=250ns).
This blanking function enables a reduction of CS pin filtering.
(5-3) CS over current protection function
When the AC input voltage (VHIN) is high, the ON time is reduced and the operating frequency increases. As a result, the
maximum rated power is increased for a constant over current limiter level. As a countermeasure, DC/DC is switched over
current detected level.
AC input voltage detection method is that monitoring QR_ZT current.
When MOSFET is turn ON, the auxiliary voltage (Va) is the minus voltage that depends on input voltage（VH）.
QR_ZT pin is clamped about 0V internal IC.
Following is the formula for that case.
Refer to the block figure29. See the graph figure30 and 31.
Izt ＝ （Va－Vzt）/Rzｔ1 ≒ Va/Rzｔ1 ＝ VH * Na/Np /Rzｔ1
Rzt1 ＝ Va/Izt
For that, VH voltage is set by the resistance value of Rzt1. Then, QR_ZT bottom detection voltage is decided, Please set timing
by Czt.
NOUT
+
+
-
1 shot
+
AND
-
TimeOut
( 15 usec )
7V
ZT Blanking
OUT(H->L)
0.60us
100mV
/400mV
+
-
POUT
AND
S Q
NOUT
FBOLP_OH
PRE
Driver
AND
OR
MAX
Blanking
Frequency
(120kHz)
+
OR
NOUT
R
1.25V
20k
+
-
0.30V
+
-
Timer
(250ms)
FBOLP_OH
+
-
200kΩ
200kΩ
Soft Start
FB/2 1.00V
SS1ms
-
SS4ms
+
CURRENT SENSE (V-V Change)
Normal : ×1.0
Leading Edge
Blanking
Figure 29. Diagram of CS switching current
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Figure 30. QR_CS Switching QR_FB Voltage VS QR_CS Voltage Figure 31. QR_CS Switching Izt Current VS QR_CS
Voltage
ex) setting method（operate changing AC100V and AC220V）
AC100V 141V±42V（±30％ margin）
AC220V 308V±62V（±20％ margin）
The case of above, Between 182V～246V, operates changing of CS current => Operate VH＝214VH
Np=100, Na=15
Va=Vin*Na/Np = 214V*15/100 *(-1) = -32.1V
Rzc = Va/ IZT = -32.1V/-1mA = 32.1kΩ
By the above explanation, Rzt=32KΩ
Figure 32. Example of Over current limiter of CS switching
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(5-4) Determination of OFF width(turn ON)
OFF width is controlled at the QR_ZT pin.
When switching is OFF, the power stored in the coil is supplied to the secondary-side output capacitor.
When this power supply ends there is no more current flowing to secondary side, so the switching MOS drain pin voltage drops.
Consequently, the voltage on the auxiliary coil side also drops.
A voltage that was resistance-divided from the QR_ZT pin by Rzt1 and Rat2 is applied. When this voltage level drops to
Vzt1(100mV typ) or below, switching is turned ON the QR_ZT comparator. Since bottom status is detected at the QR_ZT pin,
time constants are generated using Czt, Rzt1, and Rzt2.
Additionally, a QR_ZT trigger mask function (described in section 5-5) and a QR_ZT time out function
(described in section 5-6) are built in.
(5-5)QR_ZT trigger mask function
The QR_ZT trigger mask function is shown below figure33.
When switching is set ON -> OFF, super position of noise may occur at the QR_ZT pin.
At such times, the QR_ZT comparator is masked for the Tztmask time to prevent QR_ZT comparator operation errors.
Figure 33. ZT trigger mask Function
A: QR_OUT OFF=>ON
B: QR_OUT ON=>OFF
C: Because of generation of QR_ZT pin noise, TZTMASK doesn’t operate the QR_ZT comparator.
D: Same as A
E: Same as B
F: Same as C
G: Same as A
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BM1050AF-G
(5-6)ZT time out function(Figeure34)
After the ZT comparator is detected, this function forcibly turns switching ON if the following is not detected, even when Tztout
(15us typ) has elapsed.
If, the secondary output voltage is low, the auxiliary coil voltage VA is reduced, and the QR_ZT pin voltage drops below Vzt1
(100mVtyp).
In such cases, this function turns switching ON forcibly.
As for Tztout, since 15 us (typ) = 66.7kHz, when the maximum frequency is in frequency reduction mode, the QR_ZT timeout time
depends on the frequency reduction mode
Figure 34. ZT Time out Function
A:
B:
C:
D:
E:
F:
G:
H:
QR_ZT＜VZT1 、DC/DC is ON. Count maximum frequency at this point.
DC/DC ON=>OFF
Because noise is generated at QR_ZT pin, TZTMASK doesn’t operate QR_ZT comparator.
DC/DC OFF=>ON
Same as B
Same as C
Count maximum frequency
Because 1cycle>TZTOUT, forcibly be DC/DC OFF=>ON
(5-7)Soft start operations
Normally, when the power supply is turned ON, a large current flows to the AC/DC power supply. The BM1050AF builds-in a
soft start function to prevent large changes in the output voltage and output current during startup.
this function is reset when the VCC pin voltage is at VUVLO2(7.0V typ) or below, soft start is performed again at the next AC
power-on.
During a soft start, the following post-startup operations are performed. (See turn OFF described in section 5-1)
Start to 1ms -> Set to 25% when CS limiter value is normal
1ms PFC normal status -> Set to 75% when CS limiter value is normal
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(5-8)Overload protection function/Overload protection mode switching
The overload protection function monitors the overload status of the secondary output current at the FB pin, and fixes the OUT
pin at low level when overload status is detected.
During overload status, current no longer flows to the photocoupler, so the QR_FB pin voltage rises.
When this status continues for the TFOLP time (64ms typ), it is considered an over load, and the OUT pin is fixed at low level.
Once the QR_FB pin voltage exceeds VFOLP1a (2.8V typ), if it drops to lower than VFOLP1b (2.6V typ) during the TFOLP time (64ms typ),
the overload protection timer is reset. At startup, the QR_FB voltage is pulled up to the internal voltage by pull-up resistor, and
operation starts once the voltage reaches VFOLP1a (2.8V typ) or above. Therefore, the design must set the QR_EB voltage at or
below the VFOLP1b (2.6V typ) voltage within the TFOLP (64ms typ) time. In other words, the secondary output voltage start time must
be set to within TFOLP (64ms typ) after IC startup.
When an overload is detected, either auto recovery mode or latch mode can be selected for the BM1050AF.When pull-down
resistance RFOLP (100kΩ typ)is attached to QR_FB pin, latch mode is set. Do not attach any RFOLP value other than 100kΩtyp,
since that would prevent latching due to the IC7s internal resistance ratio.
To release latching after selecting latch mode, first unplug the power supply, and then set VCC<VLATCH (typ=6.5V) to release
latching.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
(5-9)QR_ZT pin OVP(Over Voltage Protection)
An OVP（Over Voltage Protection) function is built in for the QR_ZT pin.
When the QR_ZT pin voltage reaches VZLT (TYP=3.5V),over voltage status is detected. QR_ZT pin OVP protection performed
latch mode.
A mask time defined as TLATCH (TYP=150us) is built in for the QR_ZT pin OVP function. When QR_ZT OVP status continues for
150us, overvoltage is detected. This function masks any surges (etc.) that occur at the pin. See the illustration in Figure 35.
(Like VCC OVP, TLATCH (TYP=150us) is built in)
Figure 35. ZTOVP and Latch mask Function
A: DC/DC pulse operates. QR_ZT pin operates too.
B: QR_ZT pin voltage＞VZTL (TYP=3.5V)
C: QR_ZT pin voltage＞VZTL (TYP=3.5V) state within TCOMP（typ=150us）, returns to normal DC/DC operation.
D: QR_ZT pin voltage＞VZTL (TYP=3.5V)
E: QR_ZT pin voltage＞VZTL (TYP=3.5V) state continues TCOMP（typ=150us）, operates latch and DC/DC OFF.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
(5-10) Quasi-resonant DC/DC block protection operation mode
Show every protection function operation mode table 6.
FB pin over load protection function is able to change AUTR/LATCH by FB pin pull down resistance.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Table 6. Protection Circuit Operation Mode of Quasi-resonant DC/DC
LATCH/AUTOR=GND
ITEM
contents
detecti on
m ethod
opera ti on
a t detecti on
rel ea s e
mothod
LATCH/AUTOR=VREF
opera eti on
a t detecti on
detecti on
m ethod
opera ti on
a t detecti on
rel ea s e
mothod
QR_FB_OLP1
QR_FB pin
over current protection
function
QR_FB>2.8V state
continues 250ms
（QR_FB rising）
DC/DC part
operation stop
QR_FB<2.6V
（QR_FB falling）
normal operation
same as LATCH/AUTOR=GND
QR_FB_OLP2
QR_FB pin
over current protection
function
QR_FB>3.6V
（QR_FB rising）
DC/DC part
operation stop
QR_FB<3.4V
（QR_FB falling）
normal operation
same as LATCH/AUTOR=GND
QR_ZT OVP
QR_ZT ipn
over voltage protection
function
QR_ZT>3.5V state
continue 150us
（QR_QR_ZTrising）
DC/DC part
operation stop
QR_ZT<3.5V
（QR_ZT falling）
normal operation
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QR_ZT>3.5V state
continues 150us
（QR_ZT rising）
DC/DC part
LATCH operation
stop
VCC<6.5V
（VCC falling）
opera eti on
a t detecti on
normal operation
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
(6)Power Factor Correction Circuit (PFC: Power Factor Correction)Part
Power Factor Correction Circuit is peak current control method of fixed frequency.
It is possible to supply proper system as PFC by monitoring P_VS pin, P_CS pin, and P_BO.
It is possible to control the MOSFET ON width by monitoring output voltage at P_VS pin, AC input voltage at P_BO pin, and
MOSFET current at P_CS pin.
The switching frequency is FPSW1(typ=65kH),built in frequency hopping function (±4kHz),and contribute to low EMI. Following is
detail explanation of PFC (reference figure36).
+
Diode
Bridge
AC
85-265Vac
CM
P_VS
-
I
P_BOPK
Peak
Hold
P_BO
IO
VSOVP2_OK
+
2.725V(+9%)
VSOVP1_OK
+
2.625V(+5%)
+
-
VSGUP_OK
Internal CLK
65kHz±4kHz
*K3
VM = K1*V(P_BO)* K2*V(P_VS)*K3/V(P_BOPK)*K4
≒K * V(P_BO) * V(P_VS) / V(P_BOPK)
*K2
2.25V(-10%)
+
-
GCLAMP
1/V
×
*K4
MIN ON
WIDTH
VPFC_ON
15Ω
OR
R
AND
I
P_VS
1MΩ
5Ω
*K1
VPCS
2.500V
O
P_GND
IO
0.30V(-88%)
+
O
PRE
Driver
NGB
2.00V(-20%) / 1.25V(-50%)
+
VSSHORT_OK
P_VS
P_OUT
Q
MAX DUTY
94%
+
GCLAMP
IO
S
+
0.01uF
P_VSEO
P_CS
Leading Edge
Blanking
(250ns)
I
RS
Figure 36. Diagram of PFC block
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BM1050AF-G
(6-1) gm AMP
P_VS pin monitors a divide voltage between resistors of PFC output voltage. P_VS pin is piled up ripple voltage of AC
frequency (50kHz/60kHz).
The gmAMP filters this ripple voltage and controls the voltage level of P_VSEO, by responding to error of P_VS pin voltage
P_VS pin voltage and internal reference voltage VVSAMP (typ 2.5V).
Please set cut-off frequency of filter at P_VSEO pin showed in figure 37, to about 5~10Hz.
Gm constant is designed 44[uA/V].
Figure 37. Diagram of gmAMP
(6-2)Monitor of input voltage
PFC is monitored AC input voltage at the P_BO pin.
Because the range of input voltage at P_BO pin is 0~1.8V, please select Rbo1 and Rbo2 to set P_BO voltage in the range.
Refer to block figure at figure38.
Figure 38. Diagram of Input Voltage Monitor
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(6-3)Maximum power limiting function
PFC maximum power is also larger as input voltage is larger.
To compensate this maximum power, PFC built-in Maximum power limiting.
Maximum power is in proportion to the square of output of multiplier V_MULT, so it is possible to correct that maximum power
depends on input voltage by dividing P_BO voltage by P_BOPK voltage which is peak voltage of P_BO pin.
0.01uF
I
PEAK
HOLD
P_BO
IO
P_BOPK
1/V
VM = K1* V(P_BO) * K2* V(P_VS)/{K3*V(P_BOPK)}*K4
≒K * V(P_BO) * V(P_VS )/V(P_BOPK)
*K2
P_ VS
I
×
*K3
P_VS
+
*K1
2.500V
O
P_ VSEO
Figure 39. Diagram of Maximum Power Restriction Function
(6-4)Multiplier
A multiplier is calculated gmAMP output voltage and P_BO pin voltage, and P_BOPK pin voltage.
Following is formula of Multiplier output.
VMULT 
K1  V(P_BO)  K 2  V(P_VSEO)
K 3  V(P_BOPK)
 K  V(P_BO)  V(P_VSEO)/（V(P_BOPK)）
VMULT: Multiplier output voltage K: Multiplier constant
(6-5) Switching frequency
Switching frequency is averaged typ.65kHz. MAX DUTY is DMAX (typ 94%), always the period has OFF width.
PFC built in frequency hopping function, frequency changes every 500us. The amplitude is FPSWEL (typ=±4kHz)
The cycle is FPCH (typ = 125Hz)( figure40).
By this function, frequency spectrums are diffused, and contribute to low EMI.
Switching Frequency
[kHz]
69 kHz
65 kHz
61 kHz
125 Hz
Time
Figure 40. Frequency Hopping Function
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(6-6)LEB(Leading Edge Blanking) function
When the switching MOSFET is turned ON, surge current occurs at each capacitor charge /discharge or drive current.
For that, P_CS voltage rise temporarily, over current limiter may be detected errors.
To prevent detection errors blanking time is built in during TPLEB (typ=250ns) from P_OUT pin changing L →H..
This blanking function enables a reduction of P_CS pin noise filter.
P_CS Over current
detection Voltage[V]
(6-7) Over current protection function
P_CS pin built in over current protection function for MOSFET. This function operates in pulse by pulse, and detects over
current. Over current detection voltage is changed by P_BOPK pin voltage. Over current detection voltage is VPCS1 (typ = 1.16V)
at P_BOPK voltage =0.56V, VPCS2 (typ = 0.60V) at P_BOPK voltage = 1.30V.
Show figure41 changing of over current detection voltage by P_BOPK pin voltage.
Over-current detection value IPCS is decided IPCS=VPCS/Rs by external resistance Rs at figure42.
Figure 41. Over-current detection Voltage - P_BOPK Voltage Peculiarity
Leading Edge
Blanking
(250ns)
+
-
Figure 42. Diagram of Over current Protection
(6-8)P_VS short protection function
PFC built in short protection function at P_VS. Switching is stopped at P_VS voltage<VP_SHORT (0.30Vtyp).
Figure 43.
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(6-9) Gain increase function in P_VS low voltage
Dropping output voltage by suddenly load change, because PFC voltage response is slow, output voltage is low for a long time.
Therefore, PFC is speed up voltage control loop gain when P_VS pin voltage is low up to VPGUP(typ = 2.25V)(Output voltage 10%). In the operation, ON-duty at P_OUT pin increases, PFC prevents from output voltage dropping for a long time.
This operation is stopped when P_VS pin voltage is upper than VGUP (typ=2.25V).
(6-10)P_VS first over voltage protection function
In case of output voltage is rise by starting up or output load suddenly change, because PFC voltage response is slow, output
voltage is high for a long time. Therefore, PFC is speed up voltage control loop gain when P_VS pin voltage is rise VP_OVP1
(typ=2.625). In this operation, ON-duty at P_OUT pin decrease, PFC prevents from output voltage rising for a long time.
This operation is stopped when P_VS pin voltage is lower than Vp_ovp1(typ=2.625V).
(6-11)P_VS second over voltage protection function
PFC built in second over voltage protection, for the case that P_VS voltage exceeds over first over voltage protection voltage
VP_OVP1. It is possible to switch Latch protection (LATCH/AUTOR=H) or auto recovery (LATCH/AUTOR=L) by LATCH/AUTOR pin.
In case of latch operation, P_VS pin voltage exceeds VP_OVP2 (typ=2.725V)(output voltage pulse9%) during TP_OVP2a (Typ=32ms),
PFC switching is stopped.
In case of auto recovery, P_VS pin voltage is exceeded VP_OVP2 (typ=2.725V), switching is stopped instantly. When P_VS pin
voltage decrease lower than VP_OVP2 (typ=2.725V), switching operation is re-start. Refer to figure44.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Figure 44. VS Second Over Voltage Protection (at auto recovery mode)
Figure 45. Operation of P_VS Second Over Voltage Protection (at latch mode)
Switching is stopped by second over voltage protection in the case that the P_VS pin loop of output voltage is open loop.
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(6-12)PFC burst operation
PFC built-in burst operation for preventing PFC output voltage from rising at light load.
This function is that PFC monitors P_VSEO pin at light load, switched burst operation or not.
Burst operation voltage depends on P_BOPK voltage.
In case of P_BOPK voltage = 0.56V, burst function operates when P_VSEO voltage is lower than
VSEO=VP_BURST (0.266V typ). In case of P_BOPK voltage = 1.30V, burst function operates when P_VSEO voltage is lower than
VSEO=V P_BURST1 (0.128V typ)
Refer to the change of burst voltage for P_BOPK voltage figure46.
Figure 46. Diagram of P_VSEO burst voltage by P_BOPK voltage
(6-13) Operation mode of PFC block protection
Show operation mode every protection function at Table7.
(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.
Table 7.
Protection Circuit Operation mode of PFC
LATCH/AUTOR=GND
ITEM
contents
detecti on
method
opera ti on
a t detecti on
LATCH/AUTOR=VREF
rel ea s e
mothod
opera eti on
a t detecti on
detecti on
m ethod
opera ti on
a t detecti on
rel ea s e
mothod
P_VS SHORT
PROTECTION
P_VS PIN
P_VS<0.30V
short protection function （P_VS falling）
PFCpart
operation stop
P_VS>0.30V
（P_VS rising）
normal operation
Same as LATCH/AUTOR=GND
P_VS GAIN
INCREASING
P_VS PIN
P_VS<2.25V
low voltage gain increasing
（P_VS falling）
function
GMAMP GAIN
INCREASE
P_VS>2.25V
（P_VSrising）
normal operation
Same as LATCH/AUTOR=GND
P_VS OVP1
P_VS PIN
over voltage protection
function1
GM AMPGAIN
DECREASE
P_VS<2.625V
（P_VS falling）
normal operation
P_VS OVP2
P_VS PIN
over voltage protection
function2
P_VS>2.625V
（P_VS rising）
P_VS>2.725V
（P_VS rising）
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PFC part
operation stop
P_VS<2.725V
（P_VS falling）
normal operation
38/47
opera eti on
a t detecti on
Same as LATCH/AUTOR=GND
P_VS>2.725V
（P_VS rising）
PFC part, DC/DC
part latch operation
stops
VCC<6.5V
（VCC falling）
normal operation
TSZ02201-0F2F0A200140-1-2
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Datasheet
BM1050AF-G
● Basic Characteristics (This data is for reference only and is not guaranteed.)
1.3
1.5
1.3
1.1
2.8
Circuit current (ON)3 [mA ]
Circuit current (ON) 2 [mA ]
Circuit current (ON) 1 [mA ]
1.7
1.2
1.1
1.0
0.9
0.9
2.4
2.0
1.6
1.2
0.8
0.7
0.7
‐40
‐20
0
20
40
60
80
0.8
‐40
100
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Ta [℃]
Fig-47-1 Circuit current (ON) 1
40
60
80
100
Ta [℃]
Fig-47-2 Circuit current (ON) 2
Fig-47-3 Circuit current (ON) 3
5.0
0.5
4.0
13.0
3.5
OFF Current [uA ]
0.7
15.0
4.5
Start current 2 [mA ]
Start current 1 [mA ]
0.9
3.0
2.5
11.0
9.0
2.0
0.3
7.0
1.5
0.1
1.0
‐40
‐20
0
20
40
60
80
100
5.0
‐40
‐20
0
20
Ta [℃]
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Fig-47-4 Start current 1
Fig-47-5 Start current 2
1.4
40
60
80
100
Ta [℃]
Fig-47-6 OFF Current
14.0
4.5
1.2
13.5
4.3
1.0
0.8
GCLAMP Voltage1[V]
4.2
VREF voltage[V]
VH voltage switched start current [V]
4.4
4.1
4.0
3.9
3.8
0.6
12.5
12.0
3.7
11.5
3.6
0.4
11.0
3.5
‐40
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
40
60
80
‐40
100
‐20
0
20
Fig-47-8
14.0
13.5
VREF output voltage
Fig-47-9
8.5
30.0
8.0
29.0
VCC OVP voltage 1 [V]
VCC UVLO voltage 2 [V]
14.5
40
60
80
100
Ta [℃]
Ta [℃]
Fig-47-7 VH voltage switched start current
VCC UVLO voltage 1 V]
13.0
7.5
7.0
GCLAMP voltage 1
28.0
27.0
6.5
26.0
6.0
25.0
13.0
5.5
12.5
‐40
‐20
0
20
40
60
80
24.0
‐40
100
‐20
0
20
60
80
100
‐40
Fig-47-11 VCC UVLO voltage 2
26.0
25.0
Brown out 1[V]
24.0
23.0
22.0
0.25
0.43
0.23
0.41
0.39
20
40
60
80
100
Ta [℃]
Fig-47-13 VCC OVP voltage 2
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TSZ22111・15・001
40
60
80
100
0.21
0.19
0.17
0.35
20.0
0
20
Fig-47-12 VCC OVP voltage 1
0.45
0.37
21.0
‐20
0
Ta [℃]
Brown out2[V]
Fig-47-10 VCC UVLO voltage 1
‐40
‐20
Ta [℃]
Ta [℃]
VCC OVP voltage 2 [V]
40
0.15
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-14 Brown out detection voltage 1
39/47
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-15 Brown out detection voltage 2
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
● Basic Characteristics (This data is for reference only and is not guaranteed.)
0.25
42
167
157
0.21
0.19
Brown out delay2[ms]
37
Brown out delay1[ms]
Brown out hysterisis[V]
0.23
32
27
0.17
147
137
127
117
107
97
0.15
22
‐40
‐20
0
20
40
60
80
100
87
‐40
‐20
0
20
40
60
80
‐40
100
Fig-47-16 Brown out hysteresis
40
60
80
100
1.2
190
1.1
270
250
230
170
1.0
150
0.9
130
110
210
90
190
70
170
50
‐40
‐20
0
20
40
60
80
ACTIMER Vth[V]
290
ACDET RON[ohm]
Brown out delay3[ms]
20
Fig-47-17 Brown out detection delay time 1 Fig-47-18 Brown out detection delay time 2
310
100
0.8
0.7
0.6
0.5
0.4
0.3
‐40
‐20
0
20
Ta [℃]
40
60
80
‐40
100
‐20
0
20
Fig-47-20 ACDET pin ON resister
1.0
365
315
265
0.9
0.8
0.7
0.6
0.5
215
80
100
150
PFCON/OFF pulldown[kohm]
415
PFCON/OFF Vth[V]
1.1
60
Fig-47-21 ACTIMER pin input level
1.2
465
40
Ta [℃]
Ta [℃]
Fig-47-19 Brown out detection delay time 3
ACTIMER Pulldown[kohm]
0
Ta [℃]
330
130
110
90
70
0.4
165
0.3
‐40
‐20
0
20
40
60
80
100
50
‐40
‐20
0
20
Ta [℃]
40
60
80
100
‐40
‐20
0
20
Ta [℃]
1.2
40
60
80
100
Ta [℃]
Fig-47-22 ACTIMER pin pull-down res. Fig-47-23 PFCON/OFF pin input level
Fig-47-24 PFCON/OFF pin pull-down res.
150
0.62
1.0
0.9
0.8
0.7
0.6
0.5
130
0.57
COMP Vth[V]
LATCH/AUTOR pulldown[kohm]
1.1
LATCH/AUTOR Vth[V]
‐20
Ta [℃]
Ta [℃]
110
90
70
0.52
0.47
0.42
0.4
0.3
50
‐40
‐20
0
20
40
60
80
100
0.37
‐40
‐20
0
20
Ta [℃]
40
60
80
100
‐40
‐20
0
20
Ta [℃]
40
Ta [℃]
60
80
100
Fig-47-25 LATCH/AUTOR pin input level Fig-47-26 LATCH/AUTOR pin pull-down res. Fig-47-27 COMP pin detection voltage
8.0
4.0
29.4
27.4
25.4
23.4
21.4
7.5
3.9
Latch Release voltage[V]
Thermister resistor[kohm]
COMP pin pull‐up resistor [kohm]
31.4
3.8
3.7
3.6
3.5
3.3
‐40
‐20
0
20
40
Ta [℃]
60
80
100
Fig-47-28 COMP pin pull-up resistor
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
6.5
6.0
5.5
3.4
19.4
7.0
5.0
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-29 External Thermistor resistor
40/47
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-30 Latch release voltage2
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
● Basic Characteristics (This data is for reference only and is not guaranteed.)
25
1.05
230
1.04
190
170
150
130
110
23
1.03
CS over current detect1A[V]
QR_FB pullup resistor[kohm]
Latch Mask time[us]
210
21
19
17
1.02
1.01
1.00
0.99
0.98
0.97
90
0.96
70
15
‐40
‐20
0
20
40
60
80
100
0.95
‐40
‐20
0
20
40
Ta [℃]
80
100
‐40
‐20
0
20
Ta [℃]
Fig-47-31 Latch mask time
40
60
80
100
Ta [℃]
Fig-47-32 QR_FB pin pull-up resistance
Fig-47-33 CS over-current detect voltage 1A
0.85
0.30
0.77
0.29
0.75
0.73
0.71
0.69
0.67
CS over current detect 1D[V]
0.28
CS over current detect 1C[V]
CS over current detect1B[V]
60
0.27
0.26
0.25
0.24
0.23
0.22
0.65
0.80
0.75
0.70
0.21
0.63
0.65
0.20
‐40
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
40
60
80
‐40
100
‐20
0
20
Ta [℃]
40
60
80
100
Ta [℃]
Fig-47-34 CS over-current detect vol.1B Fig-47-35 CS over-current detect vol.1C Fig-47-36 CS over-current detect vol.1D
0.15
0.10
0.05
1.20
0.50
1.10
0.40
QR CS blanking timer[us]
0.20
CS switched ZT current[uA]
CS over current detect 2A[V]
0.25
1.00
0.90
0.30
0.20
0.80
‐40
‐20
0
20
40
60
80
100
0.10
‐40
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Ta [℃]
Fig-47-37 CS over-current detect vol. 2A
40
60
80
100
Ta [℃]
Fig-47-38 CS switched ZT current
Fig-47-39 CS Leading Edge Blanking time
36
0.75
131
34
0.55
0.45
126
121
116
0.35
111
0.25
106
‐40
‐20
0
20
40
60
80
QR Max frequency2 [kHz]
QR Max Frequency1[kHz]
QR Minimum ON time[us]
0.65
0
20
60
80
100
‐40
1.25
1.20
0.65
2.30
0.60
2.20
0.55
2.10
0.50
40
20
60
80
100
Ta [℃]
Fig-47-43 Freq. reduction start FB voltage
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
40
60
80
100
2.00
0.45
1.90
0.40
1.80
0.35
1.15
20
0
Fig-47-42 Maximum operating frequency 2
GAIN[V/V]
Frequency reduction end FB voltage [V]
1.30
0
‐20
Ta [℃]
Fig-47-41 Maximum operating frequency 1
1.35
Frequency reduction start FB voltage [V]
40
Ta [℃]
Fig-47-40 Minimum ON width
‐20
28
24
‐20
Ta [℃]
‐40
30
26
‐40
100
32
1.70
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-44 Freq. reduction end FB voltage
41/47
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-45 Voltage gain
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
● Basic Characteristics (This data is for reference only and is not guaranteed.)
140
1.4
30
1.3
130
25
1.2
110
100
90
Soft Start timer[ms]
ZT TimeOut[us]
ZT comparator voltage1[V]
120
20
15
1.1
1.0
0.9
0.8
80
10
0.7
70
5
60
‐40
‐20
0
20
40
60
80
0.6
‐40
100
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Ta [℃]
Fig-47-46 ZT comparator voltage 1
Fig-47-47 ZT trigger timeout period
3.1
3.9
3.0
3.8
2.9
3.7
40
60
80
100
Ta [℃]
Fig-47-48 Soft start time
84
2.8
3.6
2.7
3.5
2.6
3.4
2.5
FBOLP timer[ms]
FB OLP 2a[V]
FB OLP 1a[V]
74
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
40
60
80
‐40
100
‐20
0
20
Fig-47-50 FB OLP Voltage 2a
3.8
40
60
80
100
Ta [℃]
Ta [℃]
Fig-47-49 FB OLP Voltage 1a
Fig-47-51 FB OLP timer
10.0
30.0
QR_OUT pin NMOS ON resistor [ohm]
3.6
3.5
3.4
3.3
QR_OUT pin PMOS ON resistor [ohm]
9.0
3.7
ZT OVP Voltage [V]
54
44
3.3
‐40
64
8.0
7.0
6.0
5.0
4.0
3.0
2.0
3.2
‐40
‐20
0
20
40
60
80
20.0
15.0
10.0
5.0
‐40
100
25.0
‐20
0
20
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Ta [℃]
Fig-47-52 ZT OVP Voltage
40
60
80
100
Ta [℃]
Fig-47-53 QR_OUT pin PMOS ON resistor
Fig-47-54 QR_OUT pin NMOS ON resistor
2.54
56
0.9
0.8
0.7
0.6
0.5
2.53
Gm amplifier trans‐conductance [uS]
Gm amplifier normal voltage [V]
P_VS pin pull‐up current [uA]
1.0
2.52
2.51
2.50
2.49
0.4
0.3
2.48
‐40
‐20
0
20
40
60
80
46
41
36
31
‐40
100
51
‐20
0
20
Ta [℃]
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Fig-47-55 P_VS pin pull-up current
40
60
80
100
Ta [℃]
Fig-47-56 Gm amplifier normal voltage
Fig-47-57 Gm amplifier trans-conductance
25
271
54
21
19
17
15
P_VSEO stop voltage 1 [mV]
Maximum Gm amplifier sink current [uA]
Maximum Gm amplifier source current [uA]
261
23
49
44
39
34
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-58 Max. Gm amplifier source current
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
241
231
221
211
201
29
191
24
‐40
251
181
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-59 Max. Gm amplifier sink current
42/47
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-60 P_VSEO stop voltage1
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
● Basic Characteristics (This data is for reference only and is not guaranteed.)
168
750
70
148
138
128
118
108
PFC Minimum Pulse width [ns]
PFC Oscillation frequency [kHz]
P_VSEO stop voltage 2[mV]
158
68
66
64
62
650
550
450
350
98
88
60
‐40
‐20
0
20
40
60
80
100
250
‐40
‐20
0
20
Ta [℃]
40
60
80
100
‐40
‐20
0
20
Ta [℃]
Fig-47-61 P_VSEO stop voltage 2
40
60
80
100
Ta [℃]
Fig-47-62 PFC Oscillation frequency
Fig-47-63 PFC Min. Pulse width
98
96
95
94
93
92
P_CS over current limit voltage 2[V]
1.3
P_CS over current limit voltage 1[V]
PFC Maximum DUTY [%]
97
1.2
1.1
1.0
0.68
0.63
0.58
0.53
91
0.9
90
‐40
‐20
0
20
40
60
80
0.48
‐40
100
‐20
0
20
60
80
100
P_VS gain rise voltage [V ]
0.35
0.30
0.25
0.20
2.45
2.83
2.40
2.78
2.35
2.73
2.30
2.68
2.25
2.20
2.15
2.10
2.05
0
20
40
0
20
60
80
40
60
80
100
Fig-47-65 P_CS over current limit voltage1 Fig-47-66 P_CS over current limit voltage 2
0.40
‐20
‐20
Ta [℃]
P_VS gain fall voltage [V ]
Fig-47-64 PFC Maximum DUTY
‐40
‐40
Ta [℃]
Ta [℃]
P_VS short protection voltage[V]
40
100
2.63
2.58
2.53
2.48
2.43
‐40
‐20
0
20
Ta [℃]
40
60
80
100
‐40
‐20
Ta [℃]
Fig-47-67 P_VS short protection voltage
Fig-47-68
0
20
40
60
80
100
Ta [℃]
P_VS gain rise voltage
Fig-47-69 P_VS gain fall voltage
2.93
P_VS over voltage protection timer [mS ]
P_VS over voltage protection voltage [V ]
46
2.88
2.83
2.78
2.73
2.68
2.63
2.58
2.53
41
36
31
26
21
16
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-70 P_VS over voltage protection voltage
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
‐40
‐20
0
20
40
60
80
100
Ta [℃]
Fig-47-71 P_VS over voltage protection timer
43/47
TSZ02201-0F2F0A200140-1-2
10.Apr.2015 Rev.003
Datasheet
BM1050AF-G
● Thermal loss
The thermal design should set operation for the following conditions.
(Since the temperature shown below is the guaranteed temperature, be sure to take a margin into account.)
1. The ambient temperature Ta must be 85℃ or less.
2. The IC’s loss must be within the allowable dissipation Pd.
The thermal abatement characteristics are as follows. (Figure 47)
1000
900
800
700
Pd[mW]
600
500
400
300
200
100
0
0
25
50
75
100
125
150
Ta[℃]
Figure 48. SOP24 Temperature reduction peculiarity
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Datasheet
BM1050AF-G
● Use-related cautions
(1) Absolute maximum ratings
Damage may occur if the absolute maximum ratings such as for applied voltage or operating temperature range are exceeded,
and since the type of damage (short, open circuit, etc.) cannot be determined, in cases where a particular mode that may
exceed the absolute maximum ratings is considered, use of a physical safety measure such as a fuse should be investigated.
(2) Power supply and ground lines
In the board pattern design, power supply and ground lines should be routed so as to achieve low impedance. If there are
multiple power supply and ground lines, be careful with regard to interference caused by common impedance in the routing
pattern. With regard to ground lines in particular, be careful regarding the separation of large current routes and small signal
routes, including the external circuits. Also, with regard to all of the LSI’s power supply pins, in addition to inserting capacitors
between the power supply and ground pins, when using capacitors there can be problems such as capacitance losses at low
temperature, so check thoroughly as to whether there are any problems with the characteristics of the capacitor to be used
before determining constants.
(3) Ground potential
The ground pin’s potential should be set to the minimum potential in relation to the operation mode.
(4) Pin shorting and attachment errors
When attaching ICs to the set board, be careful to avoid errors in the IC’s orientation or position. If such attachment errors
occur, the IC may become damaged. Also, damage may occur if foreign matter gets between pins, between a pin and a power
supply line, or between ground lines.
(5) Operation in strong magnetic fields
Note with caution that these products may become damaged when used in a strong magnetic field.
(6) Input pins
In IC structures, parasitic elements are inevitably formed according to the relation to potential. When parasitic elements are
active, they can interfere with circuit operations, can cause operation faults, and can even result in damage. Accordingly, be
careful to avoid use methods that enable parasitic elements to become active, such as when a voltage that is lower than the
ground voltage is applied to an input pin. Also, do not apply voltage to an input pin when there is no power supply voltage being
applied to the IC. In fact, even if a power supply voltage is being applied, the voltage applied to each input pin should be either
below the power supply voltage or within the guaranteed values in the electrical characteristics.
(7) External capacitors
When a ceramic capacitor is used as an external capacitor, consider possible reduction to below the nominal capacitance due
to current bias and capacitance fluctuation due to temperature and the like before determining constants.
(8) Thermal design
The thermal design should fully consider allowable dissipation (Pd) under actual use conditions.
Also, use these products within ranges that do not put output Tr beyond the rated voltage and ASO.
(9) Rush current
In a CMOS IC, momentary rush current may flow if the internal logic is undefined when the power supply is turned ON, so
caution is needed with regard to the power supply coupling capacitance, the width of power supply and GND pattern wires, and
how they are laid out.
(10) Handling of test pins and unused pins
Test pins and unused pins should be handled so as not to cause problems in actual use conditions, according to the
descriptions in the function manual, application notes, etc. Contact us regarding pins that are not described.
(11) Document contents
Documents such as application notes are design documents used when designing applications, and as such their contents are
not guaranteed. Before finalizing an application, perform a thorough study and evaluation, including for external parts.
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TSZ22111・15・001
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TSZ02201-0F2F0A200140-1-2
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Datasheet
BM1050AF-G
●Ordering Information
B
M
1
0
5
0
A
Product name
F
-
Package
F
: SOP24
GE2
Packaging and
forming specification
E2: Embossed tape and reel
●Physical Dimension Tape and Reel Information
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
1pin
Reel
)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
●Marking Diagram
1PIN
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TSZ22111・15・001
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Datasheet
BM1050AF-G
Revision History
Date
Revision
15.Mar.2013
7.Feb.2014
11.Apr.2015
001
002
003
11.Apr.2015
11.Apr.2015
11.Apr.2015
003
003
003
Changes
New Release
Correction of errors
P13, P16, P17, P23, P25, P31, P32, P37, P38
The note external application of VREF when the latch mode is used.
P12 Figure4->Figure6 (Reference of start-up time)
P25 Figure25->Figure24
P25 Figure26->Figure25
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Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
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