AD ADA4622-1BRZ-R7 30 v, 8 mhz, low bias current, single-supply, rro, precision op amp Datasheet

PIN CONFIGURATIONS
Next generation of the AD820/AD822
Wide gain bandwidth product: 8 MHz typical
High slew rate: +23 V/μs/−18 V/μs typical
Low input bias current: ±10 pA maximum at TA = 25°C
Low offset voltage
A grade: ±0.8 mV maximum at TA = 25°C
B grade: ±0.35 mV maximum at TA = 25°C
Low offset voltage drift
A grade: ±2 μV/°C typical, ±15 μV/°C maximum
B grade: ±2 μV/°C typical, ±5 μV/°C maximum
Input voltage range includes Pin V−
Rail-to-rail output
Electromagnetic interference rejection ratio (EMIRR)
90 dB typical at f = 1000 MHz and f = 2400 MHz
Industry-standard package and pinouts
APPLICATIONS
NIC
1
8
DISABLE
–IN
2
ADA4622-1
7
V+
+IN
3
TOP VIEW
(Not to Scale)
6
OUT
V–
4
5
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
13502-401
FEATURES
Figure 1. 8-Lead SOIC Pin Configuration, ADA4622-1 (See the Pin
Configurations and Function Descriptions Section for Additional Pin
Configurations)
OUT A 1
–IN A 2
+IN A 3
V– 4
ADA4622-2
TOP VIEW
(Not to Scale)
8
V+
7
OUT B
6
–IN B
5
+IN B
13502-001
Data Sheet
30 V, 8 MHz, Low Bias Current,
Single-Supply, RRO, Precision Op Amps
ADA4622-1/ADA4622-2
Figure 2. 8-Lead MSOP Pin Configuration, ADA4622-2 (See the Pin
Configurations and Function Descriptions Section for Additional Pin
Configurations)
High output impedance sensor interfaces
Photodiode sensor interfaces
Transimpedance amplifiers
ADC drivers
Precision filters and signal conditioning
GENERAL DESCRIPTION
The ADA4622-1/ADA4622-2 are the next generation of the
AD820 and the AD822 single-supply, rail-to-rail output (RRO),
precision junction field effect transistors (JFET) input op amps.
The ADA4622-1/ADA4622-2 include many improvements
that make them desirable as an upgrade without compromising
the flexibility and ease of use that makes the AD820 and the
AD822 useful for a wide variety of applications.
The input voltage range includes the negative supply and the
output swings rail-to-rail. Input EMI filters increase the signal
robustness in the face of closely located switching noise sources.
The speed, in terms of bandwidth and slew rate, increases along
with a strong output drive to improve settling time performance
and enable the devices to drive the inputs of modern single-ended,
successive approximation register (SAR) analog-to-digital
converters (ADCs).
Rev. B
Voltage noise is reduced; while keeping the supply current the
same as the AD820 and the AD822, broadband noise is reduced by
25%, and 1/f is reduced by half. DC precision in the ADA4622-1/
ADA4622-2 improved from the AD820 and the AD822 with
half the offset and a maximum thermal drift specification added
to the ADA4622-1/ADA4622-2. The common-mode rejection
ratio (CMRR) is improved from the AD820 and the AD822 to
make the ADA4622-1/ADA4622-2 more suitable when used in
noninverting gain and difference amplifier configurations.
The ADA4622-1/ADA4622-2 are specified for operation over the
extended industrial temperature range of −40°C to +125°C and
operates from 5 V to 30 V with specifications at +5 V, ±5 V, and
±15 V. The ADA4622-1 is available in a 5-lead SOT-23 package
and an 8-lead LFCSP package, and the ADA4622-2 is available in
an 8-lead SOIC package, an 8-lead MSOP package, and an 8-lead
LFCSP package.
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ADA4622-1/ADA4622-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Characteristics .................................................................. 24
Applications ....................................................................................... 1
Output Characteristics............................................................... 25
Pin Configurations ........................................................................... 1
Shutdown Operation.................................................................. 26
General Description ......................................................................... 1
Applications Information .............................................................. 27
Revision History ............................................................................... 2
Recommended Power Solution ................................................ 27
Specifications..................................................................................... 3
Maximum Power Dissipation ................................................... 27
Electrical Characteristics, VSY = ±15 V...................................... 3
Second-Order Low-Pass Filter.................................................. 27
Electrical Characteristics, VSY = ±5 V ........................................ 5
Wideband Photodiode Preamplifier ........................................ 27
Electrical Characteristics, VSY = 5 V .......................................... 7
Peak Detector .............................................................................. 30
Absolute Maximum Ratings............................................................ 9
Multiplexing Inputs .................................................................... 30
Thermal Resistance ...................................................................... 9
Full Wave Rectifier ..................................................................... 31
ESD Caution .................................................................................. 9
Outline Dimensions ....................................................................... 32
Pin Configurations and Function Descriptions ......................... 10
Ordering Guide .......................................................................... 34
Typical Performance Characteristics ........................................... 12
Theory Of Operation ..................................................................... 24
REVISION HISTORY
2/2017—Rev. A to Rev. B
Added ADA4622-1 ........................................................ Throughout
Changed AD822 to AD820/AD822 ............................ Throughout
Changed ADA4622-2 to ADA4622-1/ADA4622-2 .. Throughout
Changed 7.5 MHz to 8 MHz in Product Title .............................. 1
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 5 ............................................................................ 9
Added Figure 3, Table 6, Figure 4, and Table 7; Renumbered
Sequentially ..................................................................................... 10
Changes to Figure 11 and Figure 12 ............................................. 12
Added Figure 13.............................................................................. 12
Added Figure 78.............................................................................. 23
Added Shutdown Operation and Figure 86 to Figure 89 .......... 26
Added Multiplexing Inputs Section, Figure 99, and Figure 100 ..... 30
Added Full Wave Rectifier Section, Figure 101, and Figure 102 .... 31
Updated Outline Dimensions ....................................................... 32
Change to Ordering Guide ............................................................ 34
2/2016—Rev. 0 to Rev. A
Added 8-Lead LFCSP......................................................... Universal
Changes to General Description Section .......................................1
Changes to Settling Time to 0.1% Parameter and Settling Time
to 0.01% Parameter, Table 1 .............................................................4
Changes to Table 5.............................................................................9
Added Pin Configurations and Function Descriptions Section,
Figure 2, Figure 3, Table 6, Figure 4, and Table 7; Renumbered
Sequentially ..................................................................................... 10
Changes to Figure 9 ........................................................................ 11
Changes to Input Characteristics Section ................................... 23
Changes to Recommended Power Solution Section ................. 25
Changes to Wideband Photodiode Preamplifier Section ......... 26
Change to Figure 85 ....................................................................... 26
Change to Figure 86 ....................................................................... 27
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 30
10/2015—Revision 0: Initial Version
Rev. B | Page 2 of 34
Data Sheet
ADA4622-1/ADA4622-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, VSY = ±15 V
Supply voltage (VSY) = ±15 V, common-mode voltage (VCM) = output voltage (VOUT) = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
A Grade
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
+0.04
±0.8
±2
±0.35
±1
±0.8
±1
mV
mV
mV
mV
mV
mV
±15
±5
±10
±1.5
µV/°C
µV/°C
pA
nA
pA
pA
nA
V
VOS
−40°C < TA < +125°C
B Grade
ADA4622-1
ADA4622-2
Offset Voltage Match
Offset Voltage Drift
A Grade
B Grade
Input Bias Current
+0.04
−40°C < TA < +125°C
−40°C < TA < +125°C
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
±2
±2
+2
IB
−40°C < TA < +125°C
VCM = −15 V
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
A Grade
IVR
CMRR
−15
±10
±0.5
+14
−40°C < TA < +125°C
B Grade
Large Signal Voltage Gain
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage
High
Low
AVO
CINDM
CINCM
RDIFF
RCM
VOH
VOL
Output Current
Short-Circuit Current
IOUT
ISC
Closed-Loop Output Impedance
ZOUT
−15.2
VCM = −15 V to +12 V
−40°C < TA < +125°C
VCM = −15 V to +12 V
−40°C < TA < +125°C
RL = 10 kΩ, VOUT = −14.5 V to +14.5 V
−40°C < TA < +125°C
RL = 1 kΩ, VOUT = −14 V to +14 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode
84
81
87
85
117
109
102
93
ISOURCE = 1 mA
−40°C < TA < +125°C
ISOURCE = 15 mA
−40°C < TA < +125°C
ISINK = 1 mA
−40°C < TA < +125°C
ISINK = 15 mA
−40°C < TA < +125°C
VDROPOUT < 1 V
Sourcing
Sinking
f = 1 kHz, gain (AV) = 1
AV = 10
AV = 100
14.95
14.9
14.3
14.1
Rev. B | Page 3 of 34
100
dB
dB
dB
dB
dB
dB
dB
dB
pF
pF
Ω
Ω
100
122
110
0.4
3.6
1013
1013
14.97
14.5
−14.955
−14.685
20
42
−51
0.1
0.4
3
−14.935
−14.88
−14.55
−14.25
V
V
V
V
V
V
V
V
mA
mA
mA
Ω
Ω
Ω
ADA4622-1/ADA4622-2
Parameter
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
ADA4622-1
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
PSRR
VSY = ±4 V to ±18 V
−40°C < TA < +125°C
87
81
103
715
ADA4622-2
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time
To 0.1%
To 0.01%
EMI REJECTION RATIO
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion + Noise
Bandwidth (BW) = 80 kHz
BW = 500 kHz
MATCHING SPECIFICATIONS
Maximum Offset Voltage over
Temperature
Offset Voltage Temperature Drift
Input Bias Current
CROSSTALK
Unit
dB
dB
ISY
60
µA
µA
µA
µA
µA
23
−18
8
7
15.5
53
V/µs
V/µs
MHz
MHz
MHz
Degrees
1.5
2
µs
µs
90
90
dB
dB
0.75
30
15
12.5
12
0.8
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
0.0003
0.00035
%
%
0.5
mV
−40°C < TA < +125°C
Shutdown Current
DYNAMIC PERFORMANCE
Slew Rate
Max
665
−40°C < TA < +125°C
ADA4622-1 only
SR
GBP
UGC
−3 dB
ФM
tS
EMIRR
eN p-p
eN
iN
THD + N
VOUT = ±12.5 V, RL = 2 kΩ,
load capacitor (CL) = 100 pF, AV = 1
Low to high transition
High to low transition
AV = 100, CL = 35 pF
AV = 1
AV = 1
Input voltage (VIN) = 10 V step, RL = 2 kΩ,
CL = 15 pF, AV = −1
VIN = 100 mV p-p
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
AV = 1, f = 10 Hz to 20 kHz,
VIN = 7 V rms at 1 kHz
2.5
0.5
CS
750
775
700
725
RL = 5 kΩ, VIN = 20 V p-p
f = 1 kHz
f = 100 kHz
Rev. B | Page 4 of 34
−112
−72
5
µV/°C
pA
dB
dB
Data Sheet
ADA4622-1/ADA4622-2
ELECTRICAL CHARACTERISTICS, VSY = ±5 V
VSY = ±5 V, VCM = VOUT = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
A Grade
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
+0.04
±0.8
±2
±0.35
±1
±0.8
±1
mV
mV
mV
mV
mV
mV
±15
±5
±10
±1.5
µV/°C
µV/°C
pA
nA
pA
pA
nA
V
VOS
−40°C < TA < +125°C
B Grade
ADA4622-1
ADA4622-2
Offset Voltage Match
Offset Voltage Drift
A Grade
B Grade
Input Bias Current
+0.04
−40°C < TA < +125°C
−40°C < TA < +125°C
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
±2
±2
+2
IB
−40°C < TA < +125°C
VCM = V−
Input Offset Current
−5
IOS
±10
±0.5
+4
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
A Grade
IVR
CMRR
B Grade
Large Signal Voltage Gain
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage
High
Low
AVO
CINDM
CINCM
RDIFF
RCM
VOH
VOL
Output Current
Short-Circuit Current
IOUT
ISC
Closed-Loop Output Impedance
ZOUT
−5.2
VCM = − 5 V to +2 V
−40°C < TA < +125°C
VCM = − 5 V to +2 V
−40°C < TA < +125°C
RL = 10 kΩ, VOUT = −4.4 V to +4.4 V
−40°C < TA < +125°C
RL = 1 kΩ, VOUT = −4.4 V to +4.4 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode
75
73
78
75
113
105
100
91
ISOURCE = 1 mA
−40°C < TA < +125°C
ISOURCE = 15 mA
−40°C < TA < +125°C
ISINK = 1 mA
−40°C < TA < +125°C
ISINK = 15 mA
−40°C < TA < +125°C
VDROPOUT < 1 V
Sourcing
Sinking
f = 1 kHz, AV = 1
AV = 10
AV = 100
4.95
4.9
4.3
4.1
Rev. B | Page 5 of 34
91
dB
dB
dB
dB
dB
dB
dB
dB
pF
pF
Ω
Ω
91
118
105
0.4
3.6
1013
1013
4.97
4.51
−4.955
−4.685
20
31
−40
0.1
0.4
4
−4.935
−4.88
−4.55
−4.25
V
V
V
V
V
V
V
V
mA
mA
mA
Ω
Ω
Ω
ADA4622-1/ADA4622-2
Parameter
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
ADA4622-1
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
PSRR
VSY = ±4 V to ±18 V
−40°C < TA < +125°C
87
81
103
660
ADA4622-2
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time
To 0.1%
To 0.01%
EMI REJECTION RATIO
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion + Noise
BW = 80 kHz
BW = 500 kHz
MATCHING SPECIFICATIONS
Maximum Offset Voltage over
Temperature
Offset Voltage Temperature Drift
Input Bias Current
CROSSTALK
Unit
dB
dB
ISY
50
µA
µA
µA
µA
µA
21
−16
7.8
6.5
10
50
V/µs
V/µs
MHz
MHz
MHz
Degrees
1.5
2
µs
µs
90
90
dB
dB
0.75
30
15
12.5
12
0.8
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
0.0005
0.0008
%
%
0.5
mV
−40°C < TA < +125°C
Shutdown Current
DYNAMIC PERFORMANCE
Slew Rate
Max
610
−40°C < TA < +125°C
ADA4622-1 only
SR
GBP
UGC
−3 dB
ФM
tS
EMIRR
eN p-p
eN
iN
THD + N
VOUT = ±3 V, RL = 2 kΩ, CL = 100 pF,
AV = 1
Low to high transition
High to low transition
AV = 100, CL = 35 pF
AV = 1
AV = 1
VIN = 8 V step, RL = 2 kΩ, CL = 15 pF,
AV = −1
VIN = 100 mV p-p
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
AV = 1, f = 10 Hz to 20 kHz,
VIN = 1.5 V rms at 1 kHz
2.5
0.5
CS
725
750
675
700
RL = 5 kΩ, VIN = 6 V p-p
f = 1 kHz
f = 100 kHz
Rev. B | Page 6 of 34
−112
−72
5
µV/°C
pA
dB
dB
Data Sheet
ADA4622-1/ADA4622-2
ELECTRICAL CHARACTERISTICS, VSY = 5 V
VSY = 5 V, VCM = 0 V, VOUT = VSY/2, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
A Grade
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
+0.04
±0.8
±2
±0.35
±1
±0.8
±1
mV
mV
mV
mV
mV
mV
±15
±5
±10
±1.5
±10
±0.5
+4
µV/°C
µV/°C
pA
nA
pA
nA
V
VOS
−40°C < TA < +125°C
B Grade
ADA4622-1
ADA4622-2
Offset Voltage Match
Offset Voltage Drift
A Grade
B Grade
Input Bias Current
+0.04
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
A Grade
IVR
CMRR
−40°C < TA < +125°C
−40°C < TA < +125°C
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
±2
±2
2
−40°C < TA < +125°C
−40°C < TA < +125°C
B Grade
Large Signal Voltage Gain
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage
High
Low
AVO
CINDM
CINCM
RDIFF
RCM
VOH
VOL
Output Current
Short-Circuit Current
IOUT
ISC
Closed-Loop Output Impedance
ZOUT
−0.2
VCM = 0 V to 2 V
−40°C < TA < +125°C
VCM = 0 V to 2 V
−40°C < TA < +125°C
RL = 10 kΩ to V−, VOUT = 0.2 V to 4.6 V
−40°C < TA < +125°C
RL = 1 kΩ to V−, VOUT = 0.2 V to 4.6 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode
70
67
73
70
110
99
96
87
ISOURCE = 1 mA
−40°C < TA < +125°C
ISOURCE = 15 mA
−40°C < TA < +125°C
ISINK = 1 mA
−40°C < TA < +125°C
ISINK = 15 mA
−40°C < TA < +125°C
VDROPOUT < 1 V
Sourcing
Sinking
f = 1 kHz, AV = 1
AV = 10
AV = 100
4.95
4.9
4.3
4.1
Rev. B | Page 7 of 34
87
dB
dB
dB
dB
dB
dB
dB
dB
pF
pF
Ω
Ω
87
115
104
0.4
3.6
1013
1013
4.97
4.5
−14.955
−14.69
20
27
−35
0.1
0.6
5
−14.935
−14.88
−14.55
−14.25
V
V
V
V
V
V
V
V
mA
mA
mA
Ω
Ω
Ω
ADA4622-1/ADA4622-2
Parameter
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
ADA4622-1
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
PSRR
VSY = 4 V to 15 V
−40°C < TA < +125°C
80
74
95
650
ADA4622-2
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time
To 0.1%
To 0.01%
EMI REJECTION RATIO
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion + Noise
BW = 80 kHz
BW = 500 kHz
MATCHING SPECIFICATIONS
Maximum Offset Voltage over
Temperature
Offset Voltage Temperature Drift
Input Bias Current
CROSSTALK
Unit
dB
dB
ISY
50
µA
µA
µA
µA
µA
20
−15
7.2
6
9
50
V/µs
V/µs
MHz
MHz
MHz
Degrees
1.5
2.0
µs
µs
90
90
dB
dB
0.75
30
15
12.5
12
0.8
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
0.0025
0.0025
%
%
0.5
mV
−40°C < TA < +125°C
Shutdown Current
DYNAMIC PERFORMANCE
Slew Rate
Max
600
−40°C < TA < +125°C
ADA4622-1 only
SR
GBP
UGC
−3 dB
ФM
tS
EMIRR
eN p-p
eN
iN
THD + N
VOUT = 0.5 V to 3.5 V, RL = 2 kΩ,
CL = 100 pF, AV = 1
Low to high transition
High to low transition
AV = 100, CL = 35 pF
AV = 1
AV = 1
VIN = 4 V step, RL = 2 kΩ, CL = 15 pF,
AV = −1
VIN = 100 mV p-p
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
AV = 1, f = 10 Hz to 20 kHz,
VIN = 0.5 V rms at 1 kHz
2.5
0.5
CS
700
725
650
675
RL = 5 kΩ, VIN = 3 V p-p
f = 1 kHz
f = 100 kHz
Rev. B | Page 8 of 34
−112
−72
5
µV/°C
pA
dB
dB
Data Sheet
ADA4622-1/ADA4622-2
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature, Soldering (10 sec)
ESD Rating, Human Body Model (HBM)
Rating
36 V
(V−) − 0.3 V to
(V+) + 0.2 V
36 V
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
4 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 5. Thermal Resistance1
Package Type
8-Lead SOIC
1-Layer JEDEC Board
2-Layer JEDEC Board
8-Lead MSOP
1-Layer JEDEC Board
2-Layer JEDEC Board
8-Lead LFCSP
1-Layer JEDEC Board
2-Layer JEDEC Board
2-Layer JEDEC Board with 2 × 2 Vias
5-Lead SOT-23
1-Layer JEDEC Board
2-Layer JEDEC Board
θJA
θJC2
Unit
180
120
63
N/A
°C/W
°C/W
265
185
115
N/A
°C/W
°C/W
272
145
55
63
N/A
N/A
°C/W
°C/W
°C/W
538
339
82
N/A
°C/W
°C/W
Thermal impedance simulated values are based on a JEDEC thermal test
board. See JEDEC JESD51.
2
N/A means not applicable.
1
ESD CAUTION
Rev. B | Page 9 of 34
ADA4622-1/ADA4622-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT 1
V+
4
–IN
TOP VIEW
(Not to Scale)
+IN 3
13502-202
V– 2
5
ADA4622-1
Figure 3. 5-Lead SOT-23 Pin Configuration, ADA4622-1
Table 6. 5-Lead SOT-23 Pin Function Descriptions, ADA4622-1
Mnemonic
OUT
V−
+IN
−IN
V+
Description
Output
Negative Supply Voltage
Noninverting Input
Inverting Input
Positive Supply Voltage
NIC
1
8
DISABLE
–IN
2
ADA4622-1
7
V+
+IN
3
TOP VIEW
(Not to Scale)
6
OUT
V–
4
5
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
13502-203
Pin No.
1
2
3
4
5
Figure 4. 8-Lead SOIC Pin Configuration, ADA4622-1
Table 7. 8-Lead SOIC Pin Function Descriptions, ADA4622-1
Pin No.
1, 5
2
3
4
6
7
8
Mnemonic
NIC
−IN
+IN
V−
OUT
V+
DISABLE
Description
Not Internally Connected
Inverting Input
Noninverting Input
Negative Supply Voltage
Output
Positive Supply Voltage
Disable Input (Active Low)
Rev. B | Page 10 of 34
ADA4622-1/ADA4622-2
OUT A 1
ADA4622-2
–IN A 2
TOP VIEW
(Not to Scale)
+IN A 3
V– 4
8
V+
7
OUT B
6
–IN B
5
+IN B
13502-101
Data Sheet
Figure 5. 8-Lead MSOP Pin Configuration, ADA4622-2
ADA4622-2
OUT A 1
2
+IN A 3
V–
8
V+
7 OUT B
TOP VIEW
(Not to Scale) 6 –IN B
4
5
+IN B
13502-201
–IN A
Figure 6. 8-Lead SOIC Pin Configuration, ADA4622-2
Table 8. 8-Lead MSOP and 8-Lead SOIC Pin Function Descriptions, ADA4622-2
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
Description
Output, Channel A
Inverting Input, Channel A
Noninverting Input, Channel A
Negative Supply Voltage
Noninverting Input, Channel B
Inverting Input, Channel B
Output, Channel B
Positive Supply Voltage
OUT A 1
–IN A 2
+IN A 3
8 V+
ADA4622-2
TOP VIEW
(Not to Scale)
7 OUT B
6 –IN B
5 +IN B
V– 4
NOTES
1. IT IS RECOMMENDED TO CONNECT THE
EXPOSED PAD TO THE V+ PIN.
13502-102
Pin No.
1
2
3
4
5
6
7
8
Figure 7. 8-Lead LFCSP Pin Configuration, ADA4622-2
Table 9. 8-Lead LFCSP Pin Function Descriptions, ADA4622-2
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
EPAD
Description
Output, Channel A.
Inverting Input, Channel A.
Noninverting Input, Channel A.
Negative Supply Voltage.
Noninverting Input, Channel B.
Inverting Input, Channel B.
Output, Channel B.
Positive Supply Voltage.
Exposed Pad. It is recommended to connect the exposed pad to the V+ pin.
Rev. B | Page 11 of 34
ADA4622-1/ADA4622-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
VSY = ±15V
Figure 8. Input Offset Voltage (VOS) Distribution, VSY = ±15 V
–10.0
–7.5
–5.0
–2.5
0
2.5
5.0
7.5
10.0
TCVOS (µV/°C)
13502-011
NUMBER OF AMPLIFIERS
VOS (mV)
13502-002
NUMBER OF AMPLIFIERS
VCM = 0V
VOUT = 0V
VSY = ±15V
Figure 11. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +85°C),
VSY = ±15 V
VCM = 0V
VOUT = 0V
VSY = ±5V
Figure 9. Input Offset Voltage (VOS) Distribution, VSY = ±5 V
–10.0
–7.5
–5.0
–2.5
0
2.5
5.0
7.5
10.0
TCVOS (µV/°C)
13502-012
VOS (mV)
13502-003
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
VSY = ±5V
Figure 12. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C),
VSY = ±5 V
VCM = 0V
VOUT = 2.5V
VSY = 5V
Figure 10. Input Offset Voltage (VOS) Distribution, VSY = 5 V
–10.0
–7.5
–5.0
–2.5
0
2.5
TCVOS (µV/°C)
5.0
7.5
10.0
13502-013
VOS (mV)
13502-004
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
VSY = 5V
Figure 13. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C),
VSY = 5 V
Rev. B | Page 12 of 34
Data Sheet
ADA4622-1/ADA4622-2
1000
VSY = ±15V
0
13502-008
–500
13502-014
NUMBER OF AMPLIFIERS
VOS (µV)
500
VCM = 0V
VOUT = 0V
VSY = ±15V
–1000
–15
–10
–5
0
5
10
15
IB (pA)
VCM (V)
Figure 14. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±15 V
Figure 17. Input Bias Current (IB) Distribution, VSY = ±15 V
1000
VCM = 0V
VOUT = 0V
VSY = ±5V
VSY = ±5V
0
–1000
–5
13502-009
–500
13502-015
NUMBER OF AMPLIFIERS
VOS (µV)
500
–4
–3
–2
–1
0
1
2
3
4
5
IB (pA)
VCM (V)
Figure 15. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±5 V
Figure 18. Input Bias Current (IB) Distribution, VSY = ±5 V
1000
VCM = 0V
VOUT = 2.5V
VSY = 5V
VSY = 5V
NUMBER OF AMPLIFIERS
0
13502-010
–500
–1000
0
0.5
1.0
1.5
2.0
2.5
3.0
VCM (V)
3.5
4.0
4.5
13502-016
VOS (µV)
500
5.0
IB (pA)
Figure 16. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 5 V
Rev. B | Page 13 of 34
Figure 19. Input Bias Current (IB) Distribution, VSY = 5 V
ADA4622-1/ADA4622-2
Data Sheet
10
VSY = ±15V
VSY = ±15V
–40°C
+25°C
+85°C
+125°C
VOL (V)
IB (pA)
0
–10
–30
–15
–10
–5
0
5
10
15
ILOAD (A)
VCM (V)
Figure 20. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM),
VSY = ±15 V
13502-020
13502-017
–20
Figure 23. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±15 V
4
VSY = ±5V
VSY = ±5V
2
–40°C
+25°C
+85°C
+125°C
IB (pA)
VOL (V)
0
–2
–3
–2
–1
0
1
2
3
4
5
ILOAD (A)
VCM (V)
Figure 21. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM), VSY = ±5 V
Figure 24. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±5 V
VSY = 5V
VOL (V)
VSY = 5V
0.5
1.0
1.5
2.0
2.5
VCM (V)
3.0
3.5
4.0
4.5
5.0
13502-019
IB (pA)
0
13502-021
–4
Figure 22. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM), VSY = 5 V
–40°C
+25°C
+85°C
+125°C
ILOAD (A)
13502-022
–6
–5
13502-018
–4
Figure 25. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = 5 V
Rev. B | Page 14 of 34
Data Sheet
ADA4622-1/ADA4622-2
VSY = ±15V
VSY = ±15V
VSY = ±5V
VSY = 5V
13502-026
GAIN (dB)
ILOAD (A)
13502-023
LOAD RESISTANCE (kΩ)
Figure 26. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±15 V
Figure 29. Open-Loop Gain (AVO) vs. Load Resistance
225
120
VSY = ±5V
80
135
60
90
40
45
20
0
0
–45
–20
–90
–40
10
Figure 27. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±5 V
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–135
100M
Figure 30. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V
225
120
180
80
135
60
90
40
45
20
0
ILOAD (A)
13502-025
GAIN (dB)
–40°C
+25°C
+85°C
+125°C
100
0
–45
–20
–90
–40
10
Figure 28. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = 5 V
Rev. B | Page 15 of 34
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–135
100M
Figure 31. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V
PHASE (Degrees)
VSY = ±5V
VSY = 5V
VOL (V)
13502-027
180
GAIN (dB)
ILOAD (A)
13502-024
VOL (V)
–40°C
+25°C
+85°C
+125°C
100
PHASE (Degrees)
VSY = ±15V
13502-028
VOH (V)
–40°C
+25°C
+85°C
+125°C
ADA4622-1/ADA4622-2
Data Sheet
225
60
100
180
50
80
135
40
60
90
40
45
20
0
VSY = 5V
GAIN (dB)
PHASE (Degrees)
10
–20
–90
–10
1k
10k
100k
FREQUENCY (Hz)
1M
13502-029
0
100
–135
100M
10M
AV = +10
20
–45
–40
10
AV = +100
30
0
AV = +1
–20
10
60
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 32. Open-Loop Gain and Phase vs. Frequency, VSY = 5 V
Figure 35. Closed-Loop Gain vs. Frequency, VSY = 5 V
1000
VSY = ±15V
VSY = ±15V
50
OUTPUT IMPEDANCE (Ω)
GAIN (dB)
100
AV = +100
40
30
AV = +10
20
10
AV = +1
0
10
GAIN = 100
1
GAIN = 10
0.1
100
1k
10k
100k
1M
10M
0.01
10
100M
100
13502-033
–20
10
GAIN = 1
13502-030
–10
1k
FREQUENCY (Hz)
60
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. Closed-Loop Gain vs. Frequency, VSY = ±15 V
Figure 36. Output Impedance vs. Frequency, VSY = ±15 V
1000
VSY = ±5V
VSY = ±5V
50
100
OUTPUT IMPEDANCE (Ω)
AV = +100
40
30
AV = +10
20
10
AV = +1
0
10
GAIN = 100
1
GAIN = 10
0.1
–20
10
GAIN = 1
100
1k
10k
100k
1M
10M
0.01
10
100M
FREQUENCY (Hz)
100
13502-034
–10
13502-031
GAIN (dB)
GAIN (dB)
VSY = 5V
13502-032
120
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 34. Closed-Loop Gain vs. Frequency, VSY = ±5 V
Figure 37. Output Impedance vs. Frequency, VSY = ±5 V
Rev. B | Page 16 of 34
10M
Data Sheet
100
VSY = 5V
VSY = 5V
100
80
10
60
CMRR (dB)
GAIN = 100
1
40
GAIN = 10
0.1
20
0.01
10
13502-035
GAIN = 1
100
1k
10k
100k
1M
0
10
10M
13502-038
OUTPUT IMPEDANCE (Ω)
1000
ADA4622-1/ADA4622-2
100
1k
FREQUENCY (Hz)
10k
100k
1M
10M
100M
10M
100M
FREQUENCY (Hz)
Figure 38. Output Impedance vs. Frequency, VSY = 5 V
Figure 41. CMRR vs. Frequency, VSY = 5 V
120
120
VSY = ±15V
VSY = ±15V
100
100
80
PSRR (dB)
60
40
+PSRR
40
–PSRR
20
20
0
13502-036
0
10
60
100
1k
10k
100k
1M
10M
13502-039
CMRR (dB)
80
–20
100M
10
100
1k
FREQUENCY (Hz)
Figure 39. CMRR vs. Frequency, VSY = ±15 V
120
VSY = ±5V
VSY = ±5V
100
100
80
80
60
60
+PSRR
40
–PSRR
40
20
20
0
100
1k
10k
100k
1M
10M
13502-040
PSRR (dB)
120
13502-037
CMRR (dB)
1M
Figure 42. PSRR vs. Frequency, VSY = ±15 V
140
0
10
10k
100k
FREQUENCY (Hz)
–20
100M
10
FREQUENCY (Hz)
Figure 40. CMRR vs. Frequency, VSY = ±5 V
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 43. PSRR vs. Frequency, VSY = ±5 V
Rev. B | Page 17 of 34
10M
100M
ADA4622-1/ADA4622-2
Data Sheet
120
60
VSY = 5V
VSY = 5V
100
50
80
OVERSHOOT (%)
–PSRR
40
20
+OS
–OS
30
20
10
13502-041
0
–20
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
100M
1
100
1000
Figure 47. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = 5 V
15
VSY = ±15V
VSY = ±15V
VIN = ±10V
45
10
40
35
5
VOLTAGE (V)
30
+OS
–OS
25
20
0
–5
15
10
13502-042
–10
5
0
1
10
100
13502-045
OVERSHOOT (%)
10
LOAD CAPACITANCE (pF)
Figure 44. PSRR vs. Frequency, VSY = 5 V
50
40
13502-044
PSRR (dB)
+PSRR
60
–15
1000
0
1
2
3
4
LOAD CAPACITANCE (pF)
Figure 45. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = ±15 V
50
5
6
7
8
9
10
TIME (µs)
Figure 48. Large Signal Transient Response, VSY = ±15 V
4
VSY = ±5V
45
40
VSY = ±5V
VIN = ±3V
2
VOLTAGE (V)
OVERSHOOT (%)
35
30
+OS
–OS
25
20
0
15
–2
5
0
1
10
100
13502-046
13502-043
10
–4
1000
0
LOAD CAPACITANCE (pF)
1
2
3
4
5
6
7
8
9
TIME (µs)
Figure 46. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = ±5 V
Rev. B | Page 18 of 34
Figure 49. Large Signal Transient Response, VSY = ±5 V
10
Data Sheet
ADA4622-1/ADA4622-2
4
4
VSY = ±5V
VIN = ±50mV p-p
VSY = 5V
VIN = 0.5V TO 3.5V
3
VOLTAGE (V)
2
2
1
13502-047
1
0
0
1
2
3
4
5
6
7
8
9
13502-050
VOLTAGE (V)
3
0
10
0
1
2
3
4
TIME (µs)
Figure 50. Large Signal Transient Response, VSY = 5 V
6
7
8
9
10
Figure 53. Small Signal Transient Response, VSY = ±5 V
3
0.35
VSY = 5V
VIN = 0.2V TO 0.3V
2
VSY = ±2.5V
VIN = ±2V
0.30
VOLTAGE (V)
1
VOLTAGE (V)
5
TIME (µs)
0
0.25
–1
0.20
–3
0
1
2
3
4
5
6
7
8
9
13502-051
13502-048
–2
0.15
10
0
1
2
3
4
TIME (µs)
5
6
7
8
9
10
TIME (µs)
Figure 51. Large Signal Transient Response, VSY = ±2.5 V
Figure 54. Small Signal Transient Response, VSY = 5 V
4
5
20
VSY = ±15V
–2
0
10
–5
0
–10
–10
–4
0
1
2
3
4
5
6
7
8
9
–15
10
TIME (µs)
0
1
2
3
4
5
6
7
8
9
–20
10
TIME (µs)
Figure 52. Small Signal Transient Response, VSY = ±15 V
Figure 55. Negative Overload Recovery, AV = −10, VSY = ±15 V
Rev. B | Page 19 of 34
13502-052
INPUT VOLTAGE (V)
0
13502-049
VOLTAGE (V)
2
OUTPUT VOLTAGE (V)
VSY = ±15V
VIN = ±50mV p-p
ADA4622-1/ADA4622-2
0
–2
0
9
–1
6
–2
3
–3
0
–3
1
2
3
4
5
6
7
8
9
–6
10
–4
0
1
2
3
4
TIME (µs)
–1.0
–1
–1.5
INPUT VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
–0.5
0.5
–2
1
2
3
4
5
6
7
8
9
13502-054
INPUT VOLTAGE (V)
1
0
7
8
–3
10
9
Figure 59. Positive Overload Recovery, AV = −10, VSY = ±5 V
2
VSY = ±2.5V
0
–2.0
6
TIME (µs)
Figure 56. Negative Overload Recovery, AV = −10, VSY = ±5 V
0.5
5
–3
10
5
VSY = ±2.5V
0
4
–0.5
3
–1.0
2
–1.5
1
–2.0
0
–2.5
0
1
2
3
4
TIME (µs)
5
6
7
8
OUTPUT VOLTAGE (V)
0
13502-057
–3
12
VSY = ±5V
OUTPUT VOLTAGE (V)
–1
INPUT VOLTAGE (V)
3
OUTPUT VOLTAGE (V)
0
1
13502-056
6
VSY = ±5V
13502-053
INPUT VOLTAGE (V)
1
Data Sheet
–1
10
9
TIME (µs)
Figure 57. Negative Overload Recovery, AV = −10, VSY = ±2.5 V
Figure 60. Positive Overload Recovery, AV = −10, VSY = ±2.5 V
35
5
10
0.09
5
0.08
5
–10
–15
0
1
2
3
4
5
6
7
8
9
–5
10
0.07
-5
0.06
–10
0.05
–15
0.04
–20
0.03
–25
TIME (µs)
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
Figure 58. Positive Overload Recovery, AV = −10, VSY = ±15 V
Figure 61. Positive Settling Time, AV = −10, VSY = ±15 V
Rev. B | Page 20 of 34
0.02
OUTPUT VOLTAGE (V)
15
VSY = ±15V
VIN = ±5V
0
13502-058
–5
INPUT VOLTAGE (V)
25
OUTPUT VOLTAGE (V)
0
13502-055
INPUT VOLTAGE (V)
VSY = ±15V
ADA4622-1/ADA4622-2
0.09
8
4
0.08
4
0.07
0
–0.02
–4
–0.03
–8
–0.04
–12
–0.05
–16
–0.06
–8
0.05
–12
0.04
–16
0.03
1
2
3
4
5
6
7
8
9
10
0.02
–20
0
1
2
3
4
TIME (µs)
0.05
0
0.04
–2
0.03
–6
0.02
–8
0.01
–10
0
2
3
4
5
6
7
8
–0.01
10
9
0.01
0
–6
–0.01
–8
–0.02
–10
–0.03
–12
0
1
2
7
8
9
–0.04
10
–10
–0.05
–15
–0.06
–20
–0.07
6
7
8
9
10
–0.08
VOLTAGE NOISE DENSITY (nV/√Hz)
–0.04
OUTPUT VOLTAGE (V)
–5
5
6
13502-061
INPUT VOLTAGE (V)
–0.03
4
5
VSY = ±15V
–0.02
0
3
4
TIME (µs)
13502-064
VSY = ±15V
VIN = ±5V
2
3
Figure 66. Negative Setting Time, AV = −10, VSY = 5 V
–0.01
1
–0.07
TIME (µs)
10
0
10
–4
Figure 63. Positive Settling Time, AV = −10, VSY = 5 V
–25
9
0.02
TIME (µs)
5
8
VSY = 5V
VIN = –0.5V TO –4.5V
INPUT VOLTAGE (V)
–4
OUTPUT VOLTAGE (V)
VSY = 5V
VIN = –0.5V TO –4.5V
13502-060
INPUT VOLTAGE (V)
–2
1
7
Figure 65. Negative Setting Time, AV = −10, VSY = ±5 V
0
0
6
TIME (µs)
Figure 62. Positive Settling Time, AV = −10, VSY = ±5 V
–12
5
FREQUENCY (Hz)
Figure 64. Negative Setting Time, AV = −10, VSY = ±15 V
Figure 67. Voltage Noise Density, VSY = ±15 V
Rev. B | Page 21 of 34
OUTPUT VOLTAGE (V)
0
–0.01
13502-063
–20
VSY = ±5V
VIN = ±4V
OUTPUT VOLTAGE (V)
0.06
0
13502-062
–4
INPUT VOLTAGE (V)
VSY = ±5V
VIN = ±4V
0
OUTPUT VOLTAGE (V)
8
13502-059
INPUT VOLTAGE (V)
Data Sheet
ADA4622-1/ADA4622-2
Data Sheet
0
CH1 p-p = 776.0mV
VSY = ±15V
CHANNEL SEPARATION (dB)
–20
1
M1.00ms
A CH1
–40
–60
–80
–100
13502-068
–120
13502-065
CH1 200mV
VSY = ±15V
VIN = 20V p-p
–140
100
–3.80MV
1k
10k
100k
FREQUENCY (Hz)
Figure 71. Channel Separation vs. Frequency, VSY = ±15 V
Figure 68. 0.1 Hz to 10 Hz Noise, VSY = ±15 V
100
1.6
VSY = ±15V
10
1.2
–40°C
+25°C
+85°C
+125°C
1
1
THD + N (%)
SUPPLY CURRENT (mA)
1.4
0.8
0.6
0.1
0.01
BW = 500kHz
BW = 80kHz
0.4
13502-066
0
0
±2
±4
±6
±8
±10
±12
±14
±16
0.0001
0.001
±18
13502-069
0.001
0.2
0.01
10
100
1.6
VSY
VSY
VSY
VSY
1.5
VSY = ±5V
= +5V
= ±2.5V
= ±5V
= ±15V
10
1
1.3
0.1
1.2
0.01
1.1
0.001
–25
–10
5
20
35
50
65
80
95
110
0.0001
0.001
125
BW = 500kHz
BW = 80kHz
13502-070
THD + N (%)
1.4
13502-067
SUPPLY CURRENT (mA)
1
Figure 72. THD + N vs. Amplitude, VSY = ±15 V
Figure 69. Supply Current (ISY) vs. Supply Voltage (VSY) for Various
Temperatures
1.0
–40
0.1
AMPLITUDE (V rms)
SUPPLY VOLTAGE (V)
0.01
0.1
1
AMPLITUDE (V rms)
TEMPERATURE (°C)
Figure 70. Supply Current (ISY) vs. Temperature for Various Supply Voltages
Rev. B | Page 22 of 34
Figure 73. THD + N vs. Amplitude, VSY = ±5 V
10
Data Sheet
ADA4622-1/ADA4622-2
0.1
100
VSY = 5V
VSY = 5V
10
0.1
THD + N (%)
THD + N (%)
1
BW = 500kHz
0.01
0.01
BW = 80kHz
BW = 500kHz
BW = 80kHz
0.01
0.1
1
13502-074
0.0001
0.001
13502-071
0.001
0.001
10
10
100
1k
10k
100k
FREQUENCY (Hz)
AMPLITUDE (V rms)
Figure 74. THD + N vs. Amplitude, VSY = 5 V
Figure 77. THD + N vs. Frequency, VSY = 5 V
70
0.1
VSY = ±15V
THD + N (%)
0.01
0.001
BW = 500kHz
0.0001
13502-072
0.00001
BW = 80kHz
10
100
1k
10k
100k
FREQUENCY (Hz)
VSY = ±5V
0.001
BW = 500kHz
BW = 80kHz
13502-073
THD + N (%)
0.01
10
100
1k
30
20
10
0
–40
±15V
±5V
+5V
–25 –10
5
20
35
50
65
80
95
110
Figure 78. Shutdown Current vs. Temperature
0.1
0.00001
40
TEMPERATURE (°C)
Figure 75. THD + N vs. Frequency, VSY = ±15 V
0.0001
50
10k
100k
FREQUENCY (Hz)
Figure 76. THD + N vs. Frequency, VSY = ±5 V
Rev. B | Page 23 of 34
125
13502-277
SHUTDOWN CURRENT (µA)
60
ADA4622-1/ADA4622-2
Data Sheet
THEORY OF OPERATION
V–
R3
ED1
R4
R7
ED5
ED2
R1
+IN x
SLEW
ENHANCEMENT
CIRCUIT
R2
–IN x
Q2
Q1
Q3
C1
J1
J2
R5
Q5
Q4
ED3
OUT x
RR
OUTPUT
STAGE
R6
VBIAS
ED4
ED6
IMAGIC
CURRENT
OUT1
OUT2
R8
R9
R10
13502-075
IN
CURRENT MIRROR
V+
Figure 79. Simplified Circuit Diagram
INPUT CHARACTERISTICS
The ADA4622-1/ADA4622-2 input stage consists of N-channel,
JFETs that provide low offset, low noise, and high impedance.
The minimum input common-mode voltage extends from
−0.2 mV below V− to 1 V less than V+. Driving the input
closer to the positive rail causes loss of amplifier bandwidth
and increased common-mode voltage error. Figure 80 shows
the rounding of the output due to the loss of bandwidth. The
input and output are superimposed.
13502-077
1
CH1 1.00V CH2 1.00V
M2.00µs
A CH1
3.84V
Figure 81. No Phase Reversal
Because the input stage uses N-channel JFETs, the input current
during normal operation is negative. However, the input bias
current changes direction as the input voltage approaches V+
due to internal junctions becoming forward-biased (see Figure 82).
1
13502-076
4
A CH1
3.00V
Figure 80. Bandwidth Limiting due to Headroom Requirements
The ADA4622-1/ADA4622-2 do not exhibit phase reversal for
input voltages up to V+. For input voltages greater than V+, a
10 kΩ resistor in series with the noninverting input prevents
phase reversal at the expense of higher noise (see Figure 81).
2
1
0
–1
–2
–3
–5
13502-078
M2.00µs
INPUT BIAS CURRENT (pA)
CH1 1.00V CH2 1.00V
3
–4
–3
–2
–1
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
Figure 82. Input Bias Current vs. Common-Mode Voltage with ±5 V Supply
Rev. B | Page 24 of 34
Data Sheet
ADA4622-1/ADA4622-2
100
The ADA4622-1/ADA4622-2 are designed for 12 nV/√Hz
wideband input voltage noise density and maintain low noise
performance at low frequencies (see Figure 83). This noise
performance, along with the low input current as well as low
current noise, means that the ADA4622-1/ADA4622-2
contribute negligible noise for applications with a source resistance
greater than 10 kΩ and at signal bandwidths greater than 1 kHz.
EMIRR (dB)
80
100k
ADA4622-1/ADA4622-2 VOLTAGE AND CURRENT NOISE
RS NOISE
TOTAL NOISE
60
40
13502-080
20
0
FREQUENCY (Hz)
10k
Figure 84. EMIRR vs. Frequency
OUTPUT CHARACTERISTICS
13502-079
RESISTANCE (Ω)
COMPETITOR 1
COMPETITOR 2
ADA4622-1/ADA4622-2
1k
FREQUENCY (Hz)
Figure 83. Total Noise vs. Source Resistance
Input Overvoltage Protection
The ADA4622-1/ADA4622-2 have internal protective circuitry
that allows voltages as high as 0.3 V beyond the supplies applied
at the input of either terminal without causing damage. Use a
current-limiting resistor in series with the input of the ADA4622-1/
ADA4622-2 if the input voltage exceeds 0.3 V beyond the supply
rails of the amplifiers. If the overvoltage condition persists for
more than a few seconds, damage to the amplifiers can result.
The ADA4622-1/ADA4622-2 unique bipolar rail-to-rail output
stage swings within 10 mV of the supplies with no external
resistive load.
The ADA4622-1/ADA4622-2 approximate output saturation
resistance is 24 Ω, sourcing or sinking. Use the output impedance
to estimate the output saturation voltage when driving heavier
loads. As an example, when driving 5 mA, the saturation
voltage from either rail is roughly 120 mV.
If the ADA4622-1/ADA4622-2 output drives hard against the
output saturation voltage, it recovers within 1.2 μs of the input,
returning to the linear operating region of the amplifier (see
Figure 55 and Figure 58).
Capacitive Load Drive Capability
Direct capacitive loads interact with the effective output impedance
of the ADA4622-1/ADA4622-2 to form an additional pole in
the feedback loop of the amplifiers, which causes excessive
peaking on the pulse response or loss of stability. The worst case
condition is when the devices use a single 5 V supply in a unitygain configuration. Figure 85 shows the pulse response of the
ADA4622-1/ADA4622-2 driving 500 pF directly.
For higher input voltages, determine the resistor value by
VIN  VSY
 10 mA
RS
where:
VIN is the input voltage.
VSY is the voltage of either the V+ pin or the V− pin.
RS is the series resistor.
With a very low input bias current of ±1.5 nA maximum up to
125°C, higher resistor values can be used in series with the inputs
without introducing large offset errors. A 1 kΩ series resistor
allows the ADA4622-1/ADA4622-2 to withstand 10 V of
continuous overvoltage and increases the noise by a negligible
amount. A 5 kΩ resistor protects the inputs from voltages as
high as 25 V beyond the supplies and adds less than 10 μV to
the offset voltage of the amplifiers.
1
13502-081
EMI Rejection Ratio
Figure 84 shows the EMI rejection ratio (EMIRR) vs. the
frequency for the ADA4622-1/ADA4622-2.
CH1 50.0mV BW
M2.00µs
A CH1
108mV
Figure 85. Pulse Response with 500 pF Load Capacitance
Rev. B | Page 25 of 34
ADA4622-1/ADA4622-2
Data Sheet
SHUTDOWN OPERATION
Use the active low DISABLE input to put the ADA4622-1 into
shutdown mode. When the voltage on the DISABLE input is
less than 1.4 V above the negative supply voltage (V−), the
ADA4622-1 shuts down and consumes only 50 μA to 60 μA
typical. When the voltage on the DISABLE input is more than
1.4 V above the negative supply voltage (V−), or if the DISABLE
input is left floating, the ADA4622-1 powers up. For best
performance, it is recommended that the input voltage level on
the DISABLE input be V− or that the input be left floating. The
ADA4622-1 is still a drop-in replacement for devices with
standard single channel op-amp pinouts because the ADA4622-1
enables when the DISABLE input is left floating. Figure 86
shows a simplified circuit for the DISABLE input.
∆: 1.98µs
@: –60ns
∆: 2mV
@: 2mV
CH1 100mV
CH2 5V
M1.00µs
T 49.8%
A CH2
13502-287
1
1
–11.5V
Figure 88. Shutdown Response When Toggling the DISABLE Input
Figure 89 shows the DISABLE input current vs. the DISABLE
input voltage relative to the negative supply voltage (V−).
DISABLE
Figure 87 and Figure 88 show the start-up and shutdown
response when toggling the DISABLE input.
∆: 1.12µs
@: 1.10µs
∆: 5mV
@: –1mV
0
1
2
3
4
5
DISABLE INPUT VOLTAGE RELATIVE TO V– (V)
6
13502-288
Figure 86. Simplified Circuit for the DISABLE Input
DISABLE INPUT CURRENT (µA)
IOUT
13502-285
MIRROR
Figure 89. DISABLE Input Current vs. DISABLE Input Voltage Relative to V−
CH1 50mV
CH2 5V
M1.00µs
T 49.8%
A CH2
–11.5V
13502-286
1
1
Figure 87. Start-Up Response When Toggling the DISABLE Input
Rev. B | Page 26 of 34
Data Sheet
ADA4622-1/ADA4622-2
APPLICATIONS INFORMATION
RECOMMENDED POWER SOLUTION
–16V
ADP7182
–15V
Description
DC-to-DC switching regulator with independent
positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO regulator
−28 V, −200 mA, low noise, linear regulator
MAXIMUM POWER DISSIPATION
The maximum power the ADA4622-1/ADA4622-2 can safely
dissipate is limited by the associated rise in junction
temperature. For plastic packages, the maximum safe junction
temperature is 150°C. If this maximum temperature is exceeded,
reduce the die temperature to restore proper circuit operation.
Leaving the device in the overheated condition for an extended
period can result in device burnout. To ensure proper operation, it
is important to observe the Absolute Maximum Ratings and
Thermal Resistance specifications.
SECOND-ORDER LOW-PASS FILTER
Figure 91 shows the ADA4622-1/ADA4622-2 configured as a
second-order, Butterworth, low-pass filter. With the values as
shown, the corner frequency equals 200 kHz. The following
equations show the component selection:
R1 = R2 = User Selected (Typical Values: 10 kΩ to 100 kΩ)
C1 
1.414
2πfCUTOFF  R1
C2 
0.707
ADA4622-1/
ADA4622-2
VOUT
50pF
C4
0.1µF
–5V
Table 10. Recommended Power Management Devices
Figure 92 shows a plot of the filter; greater than 35 dB of high
frequency rejection is achieved.
50
40
30
20
10
0
–10
–20
–30
–40
–50
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 92. Frequency Response of the Filter
WIDEBAND PHOTODIODE PREAMPLIFIER
The ADA4622-1/ADA4622-2 are an excellent choice for
photodiode preamplifier applications. The low input bias current
minimizes the dc error at the output of the preamplifier. In
addition, the high gain bandwidth product and low input
capacitance maximizes the signal bandwidth of the photodiode
preamplifier. Figure 93 shows the ADA4622-1/ADA4622-2 as a
current to voltage (I to V) converter with an electrical model of a
photodiode.
CF
RF
2πf CUTOFF  R1
–
CM
IPHOTO
CS
RSH = 1011Ω
+
VB
VOUT
CD
CM
ADA4622-1/
ADA4622-2
Figure 93. Wideband Photodiode Preamplifier
Rev. B | Page 27 of 34
13502-085
ADP7118
ADP7182
C1
28pF
Figure 91. Second-Order, Butterworth, Low-Pass Filter
Figure 90. Power Solution Configuration for the ADA4622-1/ADA4622-2
Product
ADP5070
R2
20kΩ
13502-084
ADP5070
+15V
R1
20kΩ
VIN
AMPLITUDE (dB)
+12V
ADP7118
+5V
C3
0.1µF
13502-082
+16V
C2
56pF
13502-083
The ADA4622-1/ADA4622-2 can operate from a ±2.5 V to ±15 V
dual supply or a 5 V to 30 V single supply. The ADP7118 and the
ADP7182 are recommended to generate the clean positive and
negative rails for the ADA4622-1/ADA4622-2. Both low dropout
regulators (LDOs) are available in fixed output voltage or
adjustable output voltage versions. To generate the input
voltages for the LDOs, the ADP5070 dc-to-dc switching regulator
is recommended. Figure 90 shows the recommended power
solution configuration for the ADA4622-1/ADA4622-2.
ADA4622-1/ADA4622-2
Data Sheet
The following basic transfer function describes the transimpedance
gain of the photodiode preamplifier:
I PHOTO  RF
1  sC F RF
where
IPHOTO is the output current of the photodiode.
The parallel combination of RF and CF sets the signal bandwidth
(see the I to V gain curve in Figure 95).
s refers to the s-plane.
Note that RF must be set so the maximum attainable output
voltage corresponds to the maximum diode output current,
IPHOTO, which allows use of the full output swing. The attainable
signal bandwidth with this photodiode preamplifier is a function
of RF, the gain bandwidth product (fGBP) of the amplifier, and
the total capacitance at the amplifier summing junction, including
CS and the amplifier input capacitance, CD and CM. RF and the
total capacitance produce a pole with loop frequency (fP).
fX
I TO V GAIN
fZ
With the additional pole from the amplifier open-loop response,
the two-pole system results in peaking and instability due to an
insufficient phase margin (see Figure 94).
G = 1 + CS/CF
G = RFCS(s)
G=1
f
fp
fGBP
90°
45°
f
0°
1
2RF CS
fN
–45°
–90°
13502-087
fP 
|A (s)|
VOUT 
OPEN-LOOP GAIN
OPEN-LOOP GAIN
–135°
Figure 95. Gain and Phase Plot of the Transimpedance Amplifier Design with
Compensation
|A| (dB)
Adding CF creates a zero in the loop transmission that compensates
for the effect of the input pole, which stabilizes the photodiode
preamplifier design because of the increased phase margin. Adding
CF also sets the signal bandwidth (see Figure 95). The signal
bandwidth and the zero frequency are determined by
fX
G = R2C1s
G=1
fZ 
log f
fP
fGBP
1
2 π RF C F
where fZ is the zero frequency.
Setting the zero at the fX frequency maximizes the signal bandwidth
with a 45° phase margin. Because fX is the geometric mean of fP
and fGBP, it can be calculated by
0°
f X  f P  f GBP
–90°
Combining these equations, the CF value that produces fX is
log f
CF 
–135°
–180°
Figure 94. Gain and Phase Plot of the Transimpedance Amplifier Design,
Without Compensation
13502-086
PHASE (°)
–45°
CS
2  R F  f GBP
The frequency response in this case shows about 2 dB of peaking
and 15% overshoot. Doubling CF and halving the bandwidth results
in a flat frequency response with about 5% transient overshoot.
The dominant sources of output noise in the wideband photodiode
preamp design are the input voltage noise of the amplifier, VNOISE,
and the resistor noise due to RF. The gray curve in Figure 95 shows
the noise gain over frequencies for the photodiode preamp.
Rev. B | Page 28 of 34
Data Sheet
ADA4622-1/ADA4622-2
2pF
Calculate the noise bandwidth at the fN frequency by
49.9kΩ
f GBP
(C S  C F ) C F
+5V
Figure 96 shows the ADA4622-1/ADA4622-2 configured as
a transimpedance photodiode amplifier. The amplifiers are
used in conjunction with a photodiode detector with an input
capacitance of 5 pF. Figure 97 shows the transimpedance response
of the ADA4622-1/ADA4622-2 when IPHOTO is 1 μA p-p. The
amplifiers have a bandwidth of 2 MHz when they are maximized
for a 45° phase margin with CF = 2 pF. Note that with the PCB
parasitics added to CF, the peaking is only 0.5 dB, and the
bandwidth is reduced slightly.
0.1µF
–5V
VOUT
ADA4622-1/
ADA4622-2
100Ω
0.1µF
13502-088
fN 
–5V
Figure 96. Photodiode Preamplifier
3
Increasing CF to 3 pF completely eliminates the peaking;
however, increasing CF to 3 pF reduces the bandwidth to 1 MHz.
2
1
Table 11 shows the noise sources and total output noise for the
photodiode preamp, where the preamp is configured to have a
45° phase margin for maximum bandwidth and fZ = fX = fN in
this case.
2pF
AMPLITUDE (dB)
0
–1
3pF
–2
–3
–4
13502-089
–5
–6
–7
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 97. Photodiode Preamplifier Frequency Response
Table 11. RMS Noise Contributions of the Photodiode Preamplifier
Contributor
RF
VNOISE
Root Sum Square (RSS) Total
1
Expression
4kT  RF  f N 
VNOISE 
π
2
(C S  C M  C F  C D )


 fN
CF
2
RF 2  VNOISE2
RMS noise with RF = 50 kΩ, CS = 5 pF, CF = 2 pF, CM = 3.7 pF, and CD = 0.4 pF.
Rev. B | Page 29 of 34
RMS Noise (μV)1
50.8
131.6
141
100M
ADA4622-1/ADA4622-2
Data Sheet
PEAK DETECTOR
MULTIPLEXING INPUTS
A peak detector captures the peak value of a signal and
produces an output equal to it. By taking advantage of the dc
precision and super low input bias current of the JFET input
amplifiers, such as the ADA4622-1/ADA4622-2, a highly
accurate peak detector can be built, as shown in Figure 98.
By using the ADA4622-1 DISABLE input, it is possible to
multiplex two inputs to a single output by using the circuit shown
in Figure 99. If the gain configuration or filter configuration of
the two amplifiers is different, and a common single input to
both amplifiers is used, this configuration can control selectable
gain or selectable frequency response at the output.
+
2
U1
5
1
4
–
VIN
C4
VEE 50pF
D3
1N4148
D4
1N4148
R7
10kΩ
D2
1N448
+PEAK
VCC
ADA4622-1/
ADA4622-2
8
6
C3
1µF
V+
ADA4622-1/
ADA4622-2
8
U2
3
7
4
7
ADA4622-1
+
U1
2
–
V
V–
6
8
4
VEE
R6
1kΩ
VOUT
DISABLE
V
Figure 98. Positive Peak Detector
3
+
In this application, D3 and D4 act as unidirectional current
switches that open when the output is kept constant in hold mode.
–
V
6
4
8
V–
Figure 99. Multiplexed Input Circuit
Figure 100 shows the output response when multiplexing two
input signals. The input to the first amplifier is a 4 V p-p,
200 kHz sine wave; the input to the second amplifier is an
8 V p-p, 100 kHz sine wave.
The ADA4622-1/ADA4622-2, shown in Figure 98, are a perfect
fit for building a peak detector because U1 requires dc precision
and high output current during fast peaks, and U2 requires low
input bias current (IB) to minimize capacitance discharge between
peaks. A low leakage and low dielectric absorption capacitor, such
as polystyrene or polypropylene, is required for C3. Reversing the
diode directions causes the circuit to detect negative peaks.
OUTPUT
VOLTAGE
Feedback from the output of the U2B (positive peak) through
R6 limits the output voltage of U2A. After detecting the peak,
the output of U2A swings low but is clamped by D2. D3 reverses
bias and the common node of D3, D4, and R7 is held to a voltage
equal to positive peak by R7. The voltage across D4 is 0 V;
therefore, the leakage is small. The bias current of U2B is also
small. With almost no leakage, C3 has a long hold time.
ADA4622-1
13502-298
To detect a positive peak, U2A drives C3 through D3 and drives
D4 until C3 is charged to a voltage equal to the input peak value.
7
U2
2
VLOGIC
TIME
Figure 100. Multiplexed Output
Rev. B | Page 30 of 34
13502-299
3
13502-090
VCC
Data Sheet
ADA4622-1/ADA4622-2
FULL WAVE RECTIFIER
Figure 101 shows the circuit of a full-wave rectifier using two
ADA4622-1 op amps in single-supply operation. The circuit is
composed of a voltage follower (U1) and a second stage amplifier
(U2) that combine the output of the first stage amplifier and the
inverted version of the input signal. U1 follows the input during
the positive half cycle and clamps the negative going input
signal to ground giving a half wave signal at VHW. The following
equation defines the circuit transfer function:
During the input positive half cycle, U1 follows the input so that
VHW = VIN; therefore, VFW = VIN. During the negative half cycle,
U1 clamps the signal to ground so that VHW = 0 V; therefore,
VFW = −(R3/R2) × VIN = −VIN because R3/R2 = 1. Figure 102
shows the input and outputs waveforms from the circuit. The
input is 2 V p-p, 1 kHz sine wave while the circuit is running on
a 5 V single supply.
INPUT
VFW = (1+ R3/R2)VHW − (R3/R2) × VIN
VCC
U1
5V
VCC
U2
FULL
WAVE
5V
VFW
2V p-p
1kHz
0°
TIME
GND
R2
50kΩ
GND
R3
50kΩ
Figure 102. Full Wave and Half Wave Rectifier Input and Output Waveforms
13502-300
GND
HALF
WAVE
13502-301
R1
30kΩ
VOLTAGE
where:
VFW is the full wave output from U1.
R3 and R2 are the feedback resistors shown in Figure 101.
VHW is half wave output from U1.
VIN is the input voltage.
Figure 101. Full Wave Rectifier Circuit
Rev. B | Page 31 of 34
ADA4622-1/ADA4622-2
Data Sheet
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
5
4
1
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
10°
5°
0°
SEATING
PLANE
0.55
0.45
0.35
0.60
BSC
11-01-2010-A
1.30
1.15
0.90
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 103. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 104. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 32 of 34
012407-A
4.00 (0.1574)
3.80 (0.1497)
Data Sheet
ADA4622-1/ADA4622-2
1.84
1.74
1.64
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
1.55
1.45
1.35
EXPOSED
PAD
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SIDE VIEW
SEATING
PLANE
PIN 1
INDICATOR
(R 0.15)
BOTTOM VIEW
0.30
0.25
0.20
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
05-11-2016-A
0.80
0.75
0.70
1
4
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4
Figure 105. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 106. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. B | Page 33 of 34
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
ADA4622-1/ADA4622-2
Data Sheet
ORDERING GUIDE
Model1
ADA4622-1ARJZ-R2
ADA4622-1ARJZ-R7
ADA4622-1ARJZ-RL
ADA4622-1ARZ
ADA4622-1ARZ-R7
ADA4622-1ARZ-RL
ADA4622-1BRZ
ADA4622-1BRZ-R7
ADA4622-1BRZ-RL
ADA4622-2ACPZ-R7
ADA4622-2ACPZ-RL
ADA4622-2ARMZ
ADA4622-2ARMZ-R7
ADA4622-2ARMZ-RL
ADA4622-2ARZ
ADA4622-2ARZ-R7
ADA4622-2ARZ-RL
ADA4622-2BRZ
ADA4622-2BRZ-R7
ADA4622-2BRZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13502-0-2/17(B)
Rev. B | Page 34 of 34
Package Option
RJ-5
RJ-5
RJ-5
R-8
R-8
R-8
R-8
R-8
R-8
CP-8-13
CP-8-13
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
Branding
A3J
A3J
A3J
A3D
A3D
A3D
A3D
A3D

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