MTB30N06VL Preferred Device Power MOSFET 30 Amps, 60 Volts, Logic Level N−Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 30 AMPERES 60 VOLTS RDS(on) = 50 mΩ N−Channel D MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 20 Vdc Vpk ID ID 30 20 105 Adc Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1.) PD 90 0.6 3.0 Watts W/°C Watts Operating and Storage Temperature Range TJ, Tstg − 55 to 175 °C MARKING DIAGRAM & PIN ASSIGNMENT EAS 154 mJ 4 Drain RθJC RθJA RθJA 1.67 62.5 50 °C/W T30N06VL YWW TL 260 Rating Drain Current − Continuous Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 μs) Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 30 Apk, L = 0.342 mH, RG = 25 Ω) Thermal Resistance − Junction to Case − Junction to Ambient − Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds IDM G S 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 1 Gate °C 2 Drain 3 Source T30N06VL = Device Code Y = Year WW = Work Week 1. When surface mounted to an FR4 board using the minimum recommended pad size. ORDERING INFORMATION Device Package Shipping MTB30N06VL D2PAK 50 Units/Rail MTB30N06VLT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 6 1 Publication Order Number: MTB30N06VL/D MTB30N06VL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 − − 63 − − Vdc mV/°C − − − − 10 100 − − 100 nAdc 1.0 − 1.5 4.0 2.0 − Vdc mV/°C − 0.033 0.05 Ohms − − 1.1 − 1.8 1.73 gFS 13 21 − Mhos Ciss − 1130 1580 pF Coss − 360 500 Crss − 95 190 td(on) − 14 30 tr − 260 520 td(off) − 54 110 tf − 108 220 QT − 27 40 Q1 − 5 − Q2 − 17 − Q3 − 15 − − − 0.98 0.89 1.6 − trr − 86 − ta − 49 − tb − 37 − QRR − 0.228 − − 4.5 − − 7.5 − OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 μAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS μAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 5 Vdc, ID = 15 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 5 Vdc, ID = 30 Adc) (VGS = 5 Vdc, ID = 15 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 5 Vdc, RG = 9.1 Ω) Rise Time Turn−Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 5 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) Reverse Recovery Stored Charge VSD Vdc ns μC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 1. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTB30N06VL TYPICAL ELECTRICAL CHARACTERISTICS VGS = 10 V 8V I D , DRAIN CURRENT (AMPS) 50 60 TJ = 25°C 6V 5V 40 4V 30 20 50 3V 25°C 30 20 10 0.08 1 2 3 4 5 6 7 8 9 0 10 0 4 5 Figure 2. Transfer Characteristics 0.06 TJ = 100°C 0.05 0.04 25°C 0.03 0.02 −55°C 0.01 0 0 40 20 30 ID, DRAIN CURRENT (AMPS) 10 50 60 6 0.06 TJ = 25°C 0.05 VGS = 5 V 0.04 10 V 0.03 0.02 0.01 0 0 Figure 3. On−Resistance versus Drain Current and Temperature 10 40 20 30 ID, DRAIN CURRENT (AMPS) 50 60 Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 1000 VGS = 5 V ID = 15 A VGS = 0 V TJ = 125°C 1.4 I DSS , LEAKAGE (nA) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 3 Figure 1. On−Region Characteristics 0.07 1.6 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 1.8 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0 100°C 40 10 0 TJ = −55°C VDS ≥ 10 V I D , DRAIN CURRENT (AMPS) 60 1.2 1 0.8 0.6 100 100°C 10 0.4 0.2 0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 1 175 0 Figure 5. On−Resistance Variation with Temperature 10 20 40 50 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 60 MTB30N06VL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 5000 VDS = 0 V 4500 VGS = 0 V TJ = 25°C Ciss C, CAPACITANCE (pF) 4000 3500 3000 Crss 2500 2000 1500 Ciss 1000 500 0 Coss Crss 10 5 VGS 0 VDS 5 10 15 20 25 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 30 4.5 27 4 24 QT 3.5 VGS Q2 Q1 3 21 18 2.5 15 2 12 1.5 Q3 1 0.5 0 5 10 15 6 3 VDS 0 9 TJ = 25°C ID = 30 A 0 25 20 1000 TJ = 25°C ID = 30 A VDD = 30 V VGS = 5 V t, TIME (ns) 5 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MTB30N06VL 100 tr tf td(off) td(on) 10 1 1 10 QT, TOTAL CHARGE (nC) 100 RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge DRAIN−TO−SOURCE DIODE CHARACTERISTICS 30 I S , SOURCE CURRENT (AMPS) 25 TJ = 25°C VGS = 0 V 20 15 10 5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 μs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTB30N06VL SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 160 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 10 μs 10 100 μs 1 ms 10 ms dc 1 0.1 10 1 ID = 30 A 140 120 100 80 60 40 20 0 100 25 50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 75 100 125 175 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 P(pk) 0.05 0.10 0.02 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 0.01 1.0E−05 1.0E−04 1.0E−03 1.0E−02 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) 1.0E−01 1.0E+00 1.0E+01 t, TIME (s) Figure 13. Thermal Response 3 PD, POWER DISSIPATION (WATTS) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.00 di/dt IS trr ta tb TIME 0.25 IS tp 2.5 2.0 1.5 1 0.5 0 IS RθJA = 50°C/W Board material = 0.065 mil FR−4 Mounted on the minimum recommended footprint Collector/Drain Pad Size ≈ 450 mils x 350 mils 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) Figure 14. Diode Reverse Recovery Waveform 150 Figure 15. D2PAK Power Derating Curve http://onsemi.com 6 175 MTB30N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.33 8.38 0.08 2.032 0.42 10.66 0.24 6.096 0.04 1.016 0.12 3.05 0.63 17.02 inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175°C − 25°C = 3.0 Watts 50°C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50°C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RθJA versus drain pad area is shown in Figure 16. TJ(max) − TA RθJA RθJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (°C/W) The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. 70 Board Material = 0.0625″ G−10/FR−4, 2 oz Copper 60 TA = 25°C 2.5 Watts 50 3.5 Watts 40 5 Watts 30 20 0 2 4 6 8 10 A, AREA (SQUARE INCHES) 12 14 16 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 7 MTB30N06VL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143, SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The ÇÇ ÇÇ ÇÇ ÇÇ ÇÇÇÇÇÇ ÇÇ ÇÇÇÇÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇÇÇ SOLDER PASTE OPENINGS STENCIL Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 8 MTB30N06VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177−189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 9 MTB30N06VL PACKAGE DIMENSIONS D2PAK CASE 418B−03 ISSUE D C E −B− V 4 1 2 3 A S −T− SEATING PLANE K J G D 3 PL 0.13 (0.005) H M T B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E G H J K S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 STYLE 2: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40 GATE DRAIN SOURCE DRAIN Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MTB30N06VL/D