LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 LED Driver with Dynamic Headroom Control and Thermal Control Interfaces Check for Samples: LM3464, LM3464A FEATURES DESCRIPTION • The LM3464/64A is a 4-channel high voltage current regulator that provides a simple solution for LED lighting applications. The LM3464/64A provides four individual current regulator channels and works in conjunction with external N-channel MOSFETs and sense resistors to give accurate driving current for every LED string. Additionally, the Dynamic Headroom Control (DHC) output can be interfaced to the external power supply to adjust the LED supply voltage to the lowest level that is adequate to maintain all the string currents in regulation, yielding the optimal overall efficiency. 1 2 • • • • • • • • • • • Wide Input Voltage Range – 12V-80V (LM3464) – 12V-95V (LM3464A) Dynamic Headroom Control Ensures Maximum Efficiency 4 Output Channels With Individual Current Regulation High Channel to Channel Accuracy Digital PWM/Analog Dimming Control Interface Resistor Programmable Dimming Frequency and Minimum Duty Cycle (Analog Dimming Mode) Direct Interface to Thermal Sensor Fault Detection Over Temperature Protection Thermal Shutdown Under Voltage Lockout Thermal Enhanced TSSOP-28 Package Digital PWM or analog voltage signals can be used to control the duty cycle of the all the channels. When analog control is used, the dimming frequency can be programmed via an external capacitor. A minimum duty cycle control is provided in the conditions that the analog dimming is configured as thermal feedback. Protection features include VIN under-voltage lockout, LED open/short circuit and over-temperature fault signaling to the system controller. APPLICATIONS • • Streetlights Solid State Lighting Solutions Typical Application High Power LED Arrays VRAIL NTC thermistor couple to LED arrays RFB1 Voltage output B EN OutP VLedFB CDHC Voltage feedback pin RFB2 CDHC VIN DR1 DR2 DR3 DR4 FAULT_CAP CFLT PGND VDHC FAULTb Q2 GD2 SE2 AGND External voltage headroom control Q3 GD3 SE3 VDHC Fault acknowledgement output Faultb DIM Q4 GD4 SE4 RISNS1 RTHM1 PWM dimming input RISNS2 RISNS3 RISNS4 Thermal 5V 0V Q1 GD1 SE1 VCC DIM To thermal sensor terminals LM3464/64A RDHC Primary power supply A PGND RDMIN1 RTHM2 A To NTC thermal sensor RDMIN2 B PGND PGND PGND DMIN CVCC Thermal_Cap SYNC AGND PGND AGND PGND CTHM 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com Connection Diagram Figure 1. Top View 28-Lead TSSOP-28 Package Number PWP PIN DESCRIPTIONS 2 Pin Name Description Application Information 1 SYNC Synchronization signal output for cascade operation (Master-Slave configuration) Connect this pin to the DIM pin of other LM3464/64A to enable cascade operation (multiple device). This pin should leave open for single device operation. 2 DIM PWM dimming control Apply logic level PWM signal to this pin controls the average brightness of the LED string. (<1.25V disable output). 3 Thermal Thermal sensor input Connect thermal sensor to this pin with bias accordingly to facilitate thermal foldback and control the brightness of the LED array. 4 Thermal_Cap Thermal dimming ramp capacitor Connect a capacitor across this pin and GND to define the thermal dimming frequency. 5 VDHC Head room control Apply external voltage across this pin and ground to define the minimum drain voltage. This pin is internal biased at 0.9V. 6 DMIN Minimum thermal dimming duty control The voltage across this pin and GND defines the minimum thermal dimming duty cycle. 7 Faultb Fault signal output Open Drain output, pull-down when FAULT condition occurred. 8 AGND Signal ground Analog ground connection for internal circuitry. Must be connected to PGND external to the package. Fault delay capacitor Connect to an external capacitor to program the fault response time. DHC time constant capacitor An external capacitor to ground programs the Dynamic Headroom Control loop response time DHC Output Connect this pin to the voltage feedback input of primary power supply to facilitate dynamic headroom control. Output voltage sense input This pin senses the output voltage of the primary power supply. Internal regulator output This pin is the output terminal of the internal voltage regulator and should be bypassed by a high quality 1uF ceramic capacitor. 9 FAULT_CAP 10 CDHC 11 OutP 12 VLedFB 13 VCC 14 EN Enable input This pin serves as device enable input when logic level signal is applied. (Active high with internal pull-up) 15 VIN Supply voltage The input voltage should be in the range of 12V to 80V for LM3464, 12–95V for LM3464A 16 DR4 Channel 4 drain sense input This pin senses the drain voltage of the external MOSFET of channel 4 to facilitate DHC operation and fault detection. 17 DR3 Channel 3 drain sense input This pin senses the drain voltage of the external MOSFET of channel 3 to facilitate DHC operation and fault detection. 18 DR2 Channel 2 drain sense input This pin senses the drain voltage of the external MOSFET of channel 2 to facilitate DHC operation and fault detection. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 PIN DESCRIPTIONS (continued) Pin Name Description Application Information 19 DR1 Channel 1 drain sense input This pin senses the drain voltage of the external MOSFET of channel 1 to facilitate DHC operation and fault detection. 20 SE4 Channel 4 sense input Connect to an external sense resistor to define the Channel 4 LED current. 21 GD4 Channel 4 gate driver output Connect to the gate of external NMOS to control the channel 4 LED current. 22 PGND Power Ground Ground for power circuitry. Reference point for all stated voltages. Must be externally connected to EP and AGND 23 GD3 Channel 3 gate driver output Connect to the gate of external NMOS to control the channel 3 LED current. 24 SE3 Channel 3 sense input Connect to an external sense resistor to define the Channel 3 LED current. 25 GD2 Channel 2 gate driver output Connect to the gate of external NMOS to control the channel 2 LED current. 26 SE2 Channel 2 sense input Connect to an external sense resistor to define the Channel 2 LED current. 27 GD1 Channel 1 gate driver output Connect to the gate of external NMOS to control the channel 1 LED current. 28 SE1 Channel 1 sense input Connect to an external sense resistor to define the Channel 1 LED current. EP EP Thermal Pad (Power Ground) Used to dissipate heat from the package during operation. Must be electrically connected to PGND external to the package. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 3 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (LM3464/LM3464A) (1) (2) VIN to GND -0.3V to 100V DR1, DR2, DR3, DR4 to GND -0.3V to 100V EN to GND -0.3V to 5.5V All other inputs to GND ESD Rating -0.3V to 7V (3) , Human Body Model ±2 kV −65°C to + 150°C Storage Temperature Range Junction Temperature (TJ) (1) (2) (3) + 150°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Operating Ratings (LM3464) Supply Voltage Range (VIN) 12V to 80V −40°C to + 125°C Junction Temperature Range (TJ) Thermal Resistance (θJA) (1) 33.5°C/W Thermal Resistance (θJC) (1) 6°C/W (1) Measurements are performed on a 4 layer JEDEC board with 10 vias provided under the exposed pad. See JESD51-1 to JESD51-11. The value of θJA is specifically dependent on the PCB trace area, trace material and the number of layers and thermal vias. Operating Ratings (LM3464A) Supply Voltage Range (VIN) 12V to 95V −40°C to + 125°C Junction Temperature Range (TJ) Thermal Resistance (θJA) (1) 33.5°C/W Thermal Resistance (θJC) (1) 6°C/W (1) Measurements are performed on a 4 layer JEDEC board with 10 vias provided under the exposed pad. See JESD51-1 to JESD51-11. The value of θJA is specifically dependent on the PCB trace area, trace material and the number of layers and thermal vias. Electrical Characteristics (LM3464/LM3464A) Specification with standard type are for TA = TJ = +25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48V. Symbol Parameter Conditions VIN-UVLO Vin under voltage lockout VIN increasing 8.5 V VIN-UVLO-HYS Vin UVLO hysteresis VIN decreasing 95 mV VCC VCC output voltage CVCC = 0.68 µF No load 6.15 VCC-UVLO VCC under-voltage lockout threshold (UVLO) VCC increasing 4.98 VCC-UVLO-HYS VCC UVLO hysteresis VCC decreasing IIN Quiescent Current from VIN CVCC = 0.68 µF No load IVCC VCC Current limit VCC = 0V 18 Device disable voltage threshold VEN Decreasing 2.1 Vcc Regulator Min Typ Max Units (1) 6.3 6.51 5.28 250 1.65 2.3 V V mV 3 mA mA Device Enable VEN-DISABLE (1) 4 2.55 3 V VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 Electrical Characteristics (LM3464/LM3464A) (continued) Specification with standard type are for TA = TJ = +25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48V. Symbol Parameter Conditions Min Typ Max Units IEN-MAX EN pin internal pull current VEN = 0V 7.2 11 14.7 uA Analog Dimming Control Interface VCTHM-MAX Sawtooth max. voltage threshold at Thermal_Cap pin 100% output duty cycle 2.95 3.25 3.3 V VCTHM-MIN Sawtooth min. voltage threshold at Thermal_Cap pin 0% output duty cycle 0.325 0.4 0.493 V ICTHM Thermal_Cap pin output current 38.9 50 61 uA PWM Dimming Control Interface VDIM-LED-ON DIM pin voltage threshold at LED ON VDMIN = 0V VTHERMAL = VCC VDIM-LED-OFF DIM pin voltage threshold at LED OFF VDMIN = 0V VTHERMAL = VCC 1.19 V 1.3 V Dynamic Headroom Control Output VOutP-MAX OutP pin max. output voltage VOutP-MIN OutP pin min. output voltage VLEDFB-LED-ON VLedFB pin voltage threshold at LED ON VLEDFB-SYS-RST System restart VLedFB pin voltage threshold for system restart IoutP = 1 mA current sink 2.4 Measure at VLedFB pin VCC-0.5 V 0.3 V 2.5 2.58 1.2 V V LED Current Regulator VGDx-MAX GDx gate driver max. output voltage VGDx-MIN GDx gate driver min. output voltage 4.73 IGDx-MAX GDx gate driver short circuit current GDx short to GND IDRx DRx pin input current VDRx = 10V VDRx = 100V VCC–1 0.115 V 0.127 V 8 mA 25 29 μA 55 70 μA V Fault Detection and Handling VOVP-TH DRx Pin over-voltage protection threshold Measure at DRx pin VSHORTFAULT DRx short fault threshold Any VDRx < 2.5V 18 19 21 8.35 8.4 9.75 VOPENFAULT SEx open fault threshold Measure at SEx pin IFAULT-CAP FAULT_CAP pin output current All VDRx < VOVP-TH 25 uA IFAULT-CAP-OVP FAULT_CAP pin output current at DRx overvoltage Any VDRx ≥ VOVP-TH 105 uA VFAULT-CAP FAULT-CAP pin voltage threshold at fault timer expire VFAULT-CAP rising 3.6 V RFaultb Faultb pin to GND resistance LED fault = TRUE 110 Ω 125 °C 30 V mV Thermal Protection TOTM-TH Over Temperature Monitor Threshold TOTM-HYS Over Temperature Monitor Hysteresis 20 °C TSD Thermal shutdown temperature TJ rising 165 °C TSD-HYS Thermal shutdown temperature hysteresis TJ falling 20 °C 33.5 °C/W 6 °C/W Thermal Resistance θJA Junction to Ambient θJC (2) (2) Junction to Case (2) TSSOP-28 Package Measurements are performed on a 4 layer JEDEC board with 10 vias provided under the exposed pad. See JESD51-1 to JESD51-11. The value of θJA is specifically dependent on the PCB trace area, trace material and the number of layers and thermal vias. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 5 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with four output channels active and output current per channel = 350 mA. TA = 25°C, unless otherwise specified. 6 Channel 1 Current Sense Voltage (VSE1) Effifciency (%) Figure 2. Figure 3. Thermal_Cap Pin Output Current VCC Variation (%) Figure 4. Figure 5. Operating Current (EN pin floating) Shutdown Current (EN pin = 0V) Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 Typical Performance Characteristics (continued) All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with four output channels active and output current per channel = 350 mA. TA = 25°C, unless otherwise specified. Startup Waveforms PWM Dimming (DIM pin) Figure 8. Figure 9. PWM Dimming Delay Time (VDIM) rising) PWM Dimming Delay Time (VDIM) falling) Figure 10. Figure 11. Thermal Foldback Dimming (VTHERMAL) rising) Thermal Foldback Dimming (VTHERMAL) falling) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 7 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com BLOCK DIAGRAM 8 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 Figure 14. Typical Application Circuit with Fly-Back AC/DC Converter Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 9 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com OVERVIEW The LM3464/64A is a four channel linear current regulator designed for LED lighting systems with wide input voltage range, high speed PWM and thermal foldback dimming control interface. The LM3464/64A incorporates a Dynamic Headroom Control (DHC) technology which maximizes overall efficiency of the lighting system by adjusting the output voltage of the primary power source dynamically. Linear current regulation secures high accuracy output current, LED and system reliability. High speed PWM dimming provides the flexibility of brightness control while maintaining constant color temperature of the light. The thermal foldback feature enables the LM3464/64A to manage the temperature of the LED heat sink or system chassis with a simple NTC/PTC temperature sensor. The thermal foldback input can also be used as an analog dimming control input to adapt to other sensors easily, such as ambient light sensor. Dynamic Headroom Control (DHC) Operation Principles of DHC Dynamic Headroom Control is a technology that aims at maximizing the overall system efficiency by altering the supply voltage to the LED(s) dynamically in respect to the characteristics of the LED(s). In the LM3464/64A, DHC is facilitated by connecting a resistor in between the OutP pin of the LM3464/64A and the voltage feedback node of the primary power supply (AC/DC) as shown in Figure 15. Figure 15. Circuitry of the DHC Mechanism For example, in steady state, when all the output channels are in regulation and the forward voltage of any LED string decreases due to temperature raise, the drain voltage of the corresponding channel (DRx) increases to exceed the default 0.9V typical headroom voltage in order to maintain constant output current. As the drain voltage increases, the voltage of CDHC increases and the current sink into the OutP pin decreases. This will finally result in decrease of rail voltage (VRAIL) until the corresponding DRx voltage returns to minimum level. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 System Operation In order to provide failure protection to the LEDs, the rail voltage is pulled up by the LM3464/64A from a relatively low voltage level at system startup until the rail voltage reaches certain preset level. Figure 16 shows the change of the rail voltage of the LM3464/64A LED lighting system upon the primary power source is powered. The Lm3464/64A can be interfaced to an off-the-shelf converter to form a LED lighting system with simple connections. Figure 14 shows the typical application circuit of a lighting system using the LM3464/64A with a flyback AC/DC converter. In this application, the output voltage of the AC/DC converter is mainly governed by a voltage reference IC, LM431 and a voltage divider consists of R1 and R2. The LM3464/64A influences the output voltage of the AC/DC converter by sinking current from the junction of the voltage divider (R1 and R2) to realize dynamic headroom control. The operation of the LM3464/64A upon startup can be divided into several phases according to the changes of the rail voltage as shown in Figure 16. When the AC/DC converter is powered, the rail voltage increases and stays steady when its native nominal output voltage, VRAIL(nom) is reached. This voltage is defined by the output voltage feedback resistor divider of the AC/DC converter. At this voltage level, the LM3464/64A is powered already. After certain delay defined by CDHC, the LM3464/64A starts to push the rail voltage up by sinking current into the OutP pin from the voltage feedback node of the AC/DC converter until the rail voltage reaches VDHC_READY. VDHC_READY is the highest rail voltage in normal operation and should be enough to turn on all the LED strings with current regulation (defined by RSNSx). As VRAIL reaches VDHC_READY, the LM3464/64A turns on all the output channels. This discharges the output capacitor of the primary power supply and causes the rail voltage to decrease to certain level that system efficiency is maximized (VLED). Figure 16. Changes of Rail Voltage Upon Power Up Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 11 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION SETTING (VRAIL(nom)) The nominal rail voltage VRAIL(nom) is the nominal output voltage of the primary power supply (AC/DC) prior to DHC begins. The selection of VRAIL(nom) is primarily depend on the forward voltages of the LED arrays and should follow the equation shows below: VRAIL(nom) ≤ Vf(all_temp) + VVDHC (1) In the equation, Vf(all_temp) is the lowest forward voltage among all the LED strings under all possible temperature. And VVDHC is the voltage headroom which equals to the voltage at the VDHC pin. Normally, the forward voltage of an LED drops as the ambient temperature increases. This could create large variation of total forward voltage of a LED sting under different temperature. In order to ensure proper system startup, the variation of LED forward voltage against temperature must be considered in calculations. SETTING VDHC_READY AND VRAIL(peak) DHC begins when the voltage at VLedFB pin reaches 2.5V, which is defined by the values of RFB1 and RFB2: 2.5V = VDHC_READY x RFB2 RFB1 + RFB2 (2) Where VDHC_READY < VRAIL(peak) (3) At this stage, the current of the LED strings are regulated and the rail voltage decreases in order to maintain minimum voltage drop and power dissipation on the MOSFETs. In case the OutP pin is accidentally shorten to ground, the rail voltage will increase and end up exceeds VDHC_READY. To avoid damaging the AC/DC converter, the possible peak output voltage, VRAIL(peak) can be roughly defined by the forward voltage of the LED strings and must set below the rated voltage of the components at the output of the AC/DC converter. In order to limit the power dissipation on the external MOSFETs, VRAIL(peak) is set to to no more than 10VDC higher than the forward voltage of the LED string. The following equations define the maximum output voltage of the AC/DC converter that can be pushed up by the LM3464/64A: VRAIL(peak) = VR1 + VREF(AC/DC) = (R1 x IR1) + VREF(AC/DC) (4) for VREF(AC/DC) = 2.5V IR1 = VRAIL(peak) - 2.5V R1 (5) also since IR1 = = VREF(AC/DC) RD2 + VREF(AC/DC) - VD1 - VoutP(min) RDHC 2.5V - 0.5V - 0.3V 2.5V + RD2 RDHC RDHC = (6) 1.7V IR1 - 2.5V R2 (7) As the system enters steady state, the rail voltage VRAIL decreases and finally settles to an optimal level that maintains the maximum power efficiency of the system. The voltage level of VRAIL under steady state can be calculated following this equation: VRAIL = Vf(highest) + VVDHC (8) In the equation, VRAIL is the rail voltage in steady state and Vf(highest) is the total forward voltage of the LED string which carry the highest forward voltage among the LED stings. 12 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 VVDHC is the voltage at the VDHC pin. This voltage decides the headroom voltage for the LM3464/64A driver stage and equals to the minimum VDRx among the drain voltages of the MOSFETs under steady state. The VDHC pin is internally biased to 0.9V which also set the default voltage headroom to 0.9V. In applications that the output of the AC/DC converter contains more than 0.9V peak-to-peak ripple voltage, the voltage headroom can be increased by applying external bias to the VDHC pin. DEFINING VOLTAGE HEADROOM The voltage headroom is the rail voltage margin that reserve for precision linear current regulation under steady state. Under steady state, the voltage headroom is always minimized by the LM3464/64A to reduce power losses on the MOSFETs till one of the drain voltage (VDRx) of the MOSFETs equals the voltage on VDHC pin (0.9V typical). With external bias, the voltage of the VDHC pin can be adjusted up or down to adapt to different types of primary power supply. Figure 17 shows a simple resistor based biasing circuit that derives biasing voltage from the output of the internal voltage regulator, the VCC pin. Figure 17. Adjusting Voltage Headroom with Resistors With the additional resistors, the VDHC pin voltage is adjustable in between 0.8V and 2V. The values of RA and RB should be at least 10 times lower than the typical values of the internal resistor divider of the VDHC pin (see Figure 17). However, it is recommended not to set the voltage headroom too low because the ripple voltage of the primary power supply output may cause visible flicker due to insufficient voltage headroom. Thus the voltage headroom follows this equation: 160 k: // RB x VCC VDHC = 160 k: // RB + 1 M: //RA where • 0.8V < VVDHC < 2V (9) SETTING LED CURRENT The LED current regulating mechanism of the LM3464/64A driver stage contains four individual LED current regulators. Every LED current regulator is composed of an external MOSFET (Q1-Q4), a current sensing resistor (RISNS1-RISNS4) and an amplifier inside the LM3464/64A that monitors the feedback voltage from the current sensing resistor. The integrated amplifier compares the voltage across current sensing resistors (RISNS1-RISNS4) to a 200mV typical reference voltage and controls the gate voltage of the MOSFETs (Q1-Q4) to realize linear current regulations. Figure 18 shows the simplified circuit of the linear LED current regulators. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 13 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com Figure 18. Linear LED Current Regulator The driving currents of the LED strings are defined by the values of RISNS1 to RISNS4 individually. The LED current and the value of RISNSx are related by the following equation: 200 mA ILED = RISNSx (10) Since the accuracy of the LED currents are dependent on the tolerance of RISNSx, the RISNSx to recommended to be thick carbon file resistors with no more than 1% tolerance and adequate rated power to the desired LED current. Figure 19. LED Current vs RISNSx RESPONSE OF THE LM3464/64A DRIVER STAGE In order to ensure good operation stability of the entire system, the response of the LM3464/64A circuitry must be set slower than the primary power supply. The response of the LM3464/64A is decided by the value of the capacitor, CDHC. In general, a higher capacitance CDHC will result in slower response of the LM3464/64A driver stage. Generally, a first order integrator that consists of CDHC and a transconductance amplifier with gm = 76umho and +/– 15uA current limit as shown in Figure 20 defines the frequency response of the LM3464/64A driver stage. 14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 Figure 20. Simplified Circuit of the Frequency Response Setting Mechanism The transconductance amplifier serves as a voltage to current converter that charges CDHC with a current proportional to the difference in voltage between the DRx and VDHC pins. As the voltage of the OutP pin is equal to VCC – VCDHC, the capacitance of CDHCdecide the rate of change of the OutP pin voltage and eventually limits the frequency response of the whole system . The higher capacitance the CDHC has, the longer time the OutP pins takes for certain voltage change. Thus the value of CDHC decides the response of the LM3464/64A driver stage. If the response of the LM3464/64A driver stage is set faster than that of the primary power supply, the entire system will suffer from unstable operation. However, setting the response of the LM3464/64A driver stage unnecessarily slow will worsen transient performance of the system and false trigger the fault detection mechanism of the LM3464/64A. Practically, the minimum value of the CDHC can be found out by means of ‘try and error’. In most cases, a 1uF 16V ceramic capacitor is a good starting point that sets the response of the LM3464/64A driver stage slow enough for initial trial. The value of the CDHC capacitor can be reduced to speed up the response of the LM3464/64A driver stage. Otherwise, in case the system is unstable with 1uF CDHC, the capacitance of the CDHC capacitor should be increased until the entire system get into stable operation. This approach is effectively setting the cut-off frequency of the LM3464/64A driver stage lower than that of the primary power supply. Usually, setting the cut-off frequencies of the two stages apart can help avoiding unstable operation. The cut-off frequency of the LM3464/64A driver stage is governed by the follow equation: fLM3464(-3 dB) = 1 6 2S(1.2 x 10 ) x CDHC (11) THERMAL FOLDBACK INTERFACE The thermal foldback function of the LM3464/64A helps in reducing the average LED currents and prolonging the LED lifetime under high temperature. By applying a DC voltage to the Thermal pin, the average output current is adjustable from 100% down to a minimum value limited by the discharge time of the CTHM. The Thermal pin of the LM3464/64A is an analog input for thermal foldback control that accepts a DC voltage in the range of 0V to VCC. The thermal foldback control circuitry reduces the average LED currents by means of PWM dimming as shown in Figure 21: Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 15 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 VThermal www.ti.com VCC 3.25V ILED (AVG) 100% 0.4V 0V Approximately 0.5% (Limited by tTHM_MIN) Temperature Thermal foldback begin Figure 21. Average LED Current Reduces According to VThermal The dimming frequency is defined by a sawtooth waveform that generated by charging and discharging the capacitor CTHM which connects across the Thermal_Cap pin and GND. The LM3464/64A charges the CTHM up to 3.25V with 50uA constant current and discharge the CTHM by pulling the Thermal_Cap pin to ground through a 125Ω (typ.) resistor until the pin voltage reaches 0.4V (VCTHM-MIN). When the voltages of the Thermal and DMIN pins are both below 0.4V, the minimum dimming on time equals the discharge time of the CTHM following the equation: tTHM_MIN = 262 x CTHM in second (12) Thus the minimum dimming duty cycle for thermal foldback that being restricted by the discharge time of CTHM is approximately 0.5%: (13) By comparing the voltage at the Thermal pin to the sawtooth voltage being generated at the Thermal_Cap pin of the LM3464/64A, a PWM dimming signal for thermal foldback is generated as shown in Figure 22: Figure 22. Signals Facilitating Thermal Foldback Control 16 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 If the voltage at the Thermal pin is driven to exceed 3.25V, all output channels will be enabled with 100% thermal dimming duty cycle. If the Thermal pin voltage is set below 0.4V, all output channels will be disabled with 0% thermal dimming duty cycle. The dimming frequency and duty cycle with thermal foldback control are governed by the following equations: fThermal-foldback = 50 PA (3.25 - 0.4) x CTHM (14) (15) (16) (17) DThermal-foldback = (TLED_ON x fThermal-foldback) x 100% = [(VTHERMAL - 0.4) X 35]% for 0.4 ≤ VTHERMAL ≤ 3.25V SETTING MINIMUM THERMAL DIMMING DUTY CYCLE In applications that need to ensure minimum illumines under high temperature environments, the minimum dimming duty cycle for thermal foldback may need to be limited. Such limit is defined by the voltage at the DMIN pin. When the Thermal pin voltage falls below the voltage at the DMIN pin, the thermal foldback dimming duty cycle will maintain at the level which set by the voltage of the DMIN pin (VDMIN), as shown in Figure 23. VThermal VCC 3.25V VDMIN 100% ILED (AVG) 0.4V 0V Min. ILED (AVG) Approximately 0.5% (Limited by tTHM_MIN) Temperature Thermal foldback begin Min. thermal foldback dimming Figure 23. Thermal Foldback Control with Minimum Dimming Duty Cycle Limit To define the minimum thermal dimming duty cycle, VDMIN should be set in between 0.4V to 3.25V. The minimum duty cycle is governed by the following equation: DMINIMUM = [(VDMIN - 0.4) X 35]% for 0.4 ≤ VDMIN ≤ 3.25V (18) (19) When VDMIN is below 0.4V (e.g. connect to GND), the minimum thermal dimming duty cycle limit is disabled. In applications that thermal foldback control is not required, the DMIN pin can be tied to GND to reduce power consumption. PWM DIMMING The LM3464/64A provides a DIM pin that accepts TTL logic level signal for PWM dimming. When the DIM pin is pulled low, all LED current regulators will turn off while maintaining VCC regulator and part of the internal circuitries operating. External pull up resistor is required if the DIM pin is driven by an open collector / drain driver. PWM dimming ensures uniform color temperature of the light throughout the entire dimming range. The average current of every output channel is decided by the dimming duty cycle and follows the equation below: Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 17 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com ILED(AVG) = DPWM x ILED (20) PWM DIMMING CONTROL WITH THERMAL FOLDBACK The PWM dimming control can coexist with thermal foldback by applying PWM dimming control signal and thermal control signal to the DIM and Thermal pins concurrently. Normally, the dimming frequency for thermal foldback control should be much higher than the frequency of the PWM dimming control signal. Figure 24 presents the relationship among VThermal, VThermal_Cap, VDIM and ILED. As shown in the figure, when thermal foldback is functioning, the average output current can be further decreased linearly according to the duty cycle of the PWM dimming signal being applied to the DIM pin. In order to synchronize the dimming signals, the CTHM is discharged on every rising edge of the PWM dimming signal on DIM pin, notice as t1, t2 and t3 in Figure 24. Figure 24. Thermal Foldback + PWM Dimming Control LOW POWER STANDBY The LM3464/64A will enter low power standby mode when the EN pin is pulled to GND. The EN pin is internally biased thus no external pull-up resistor or bias is required. Under standby mode, all the output channels are cutoff and part of the internal circuitries are disabled to maintain low power consumption. Upon the EN pin is pulled low, the OutP pin stopa sinking current from the feedback node of the primary power stage. This causes the rail voltage fall back to VRAIL(nom) slowly as the output capacitors of the primary power supply are being discharged by the LEDs. Pulling the EN pin low will not disable the VCC regulator. When the EN pin is released (floating), the LM3464/64A exits low power standby mode and the startup sequence begins as described in Figure 16. FAULT HANDLING and INDICATION The LM3464/64A features a complete mechanism for fault handling and indication. The LM3464/64A detects LED failures and raises fault indication signal at the Faultb pin upon open or short circuits of LED strings, insufficient supply voltage and so on. In order to avoid false triggering the fault detection circuitry, the LM3464/64A features a timer for fault recognition. When a fault condition arises and sustains longer than the time constant preset by the capacitor , CFLT, a fault is confirmed. The Faultb pin is then pulled low as an indication. The time constant for fault detection is defined by the value of the capacitor connects across the FAULT_CAP pin and GND, CFLT. Normally, a 2.2 nF CFLT that set a 264 us delay time is suitable for most application. For those applications with slow response primary power supply, the value of CFLT may need to increase accordingly. The time delay for fault detection is governed by the following equation: TFAULT = 18 CFLT x 3.0V 25 PA (21) Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 OPEN CIRCUIT OF LED STRINGS Detection of LED open circuit is achieved by detecting the voltages of the SEx pin and the internal gate control signal being fed to the internal MOSFET gate driver. When a LED string is open circuit, the VSEx pin is pulled down to below 30mV by the current sensing resistor. As VSEx falls below its regulated level, the LM3464/64A increases the gate voltage of the corresponding MOSFET (VGDx) in order to maintain current regulation. Thus, the requirement for LED open circuit is VSEx below 30mV and internal gate voltage reaches its maximum (at VGDx about 5V). When the requirement of LED open fault is fulfilled, the LM3464/64A begins to charge up the CFLT. When the voltage of the FAULT_CAP reaches 3V, and the condition of open fault retains, an open fault is confirmed. After an open fault is confirmed, the failed channel(s) will be disabled and excluded from DHC loop. To reactivate the disabled channel(s), the EN pin can be pulled to GND for a soft reset or re-power the primary power supply for a system reset. Either reset methods results in a system restart with startup sequence shows in Figure 16. SHORT CIRCUIT OF LED STRINGS If any LED string experiences partially short circuit after normal system startup, the drain voltage (DRx) of the corresponding channel(s) will increase so as to maintain correct current regulation. When drain voltage increases up to 8.4V higher than the drain voltages of any other channels, the shortened channel will be latched off and excluded from the DHC loop to avoid further damages. Once a short fault is confirmed, the Faultb pin will be pulled low no matter it is due to failure of the power source or shortening of LED strings. When a short circuit of LED sting is confirmed, the failed channel(s) will be disabled and excluded from DHC loop. The disabled channels can be reactivated by either pulling the EN pin to GND or system re-powering. DRx PIN OVER-VOLTAGE PROTECTION The LM3464/64A features a over-voltage protection function that prevents damaging of the external MOSFETs due to short circuit of LED string(s). When the voltage of any DRx pin reaches 19V typical, the fault detection timer is triggered with the output current of the FAULT_CAP pin increases by 4 times (IFAULT-CAP-OVP) and results in fault detection time 4 times shorter. If a over-voltage of any DRx pin is confirmed, the particular channel will be latched off and excluded from DHC loop until the EN pin is pulled low (soft reset) or system re-powering is undertaken. DRIVING LESS THAN FOUR LED STRINGS The LM3464/64A allows users to disable the unused output channels. Any output channel without a LED string connected or with DRx and SEx pins floating will be disabled at system startup. A disabled channel will be excluded from the DHC loop and will not contribute headroom control signal to the LM3464/64A. This function is applicable to both single LM3464/64A and cascade operation modes. EXPANDING NUMBER OF OUTPUT CHANNEL The LM3464/64A can be cascaded to expand the number of output channel. Bases on the master-slave architecture, one of the LM3464/64A in the system must be set to master mode and the rest must be set to slave mode. Figure 27 shows an example application circuit that provides eight output channels. To enable cascade operation, the SYNC pin of the master LM3464/64A should connect to the DIM pin of the first slave device and similarly the SYNC pin of such slave device should connect to its down stream slave device for startup synchronization. In addition, the OutP pins of all the LM3464/64A have to tie up though a diode and resistor RDHC to the voltage feedback node of the primary power supply to accomplish dynamic headroom control, as shown in Figure 27. The slave devices can only be commanded by the master LM3464/64A. With the master and slave devices linked up, the information of startup synchronization, thermal foldback and PWM dimming controls are gathered by the master device and distribute stage by stage through the SYNC pin. To set a LM3464/64A in master mode, the voltage of the VLedFB pin must be set below 3.25V. When the VLedFB pin is connected to VCC, the device is in slave mode. In slave mode, local thermal foldback and PWM controls are overridden by the packaged synchronization signal delivered from the master. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 19 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com CONNECTION TO LED ARRAYS When LEDs are connected to the LM3464/64A driver stage through long cables, the parasitic components of the cable harness and external MOSFETs may resonant and eventually lead to unstable system operation. In applications that the cables between the LM3464/64A driver circuit and LED light engine are longer than 1 meter, a 4.7kΩ resistor should be added across the GDx pins to GND as shown in Figure 25. Figure 25. Additional Resistor Across GDx and SEx for Cable Harness Over 1m Long 20 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 Figure 26. Additional Voltage Clamping Circuits for VRAIL(peak) > 80V/95V (LM3464/64A) APPLICATIONS WITH HIGH RAIL VOLTAGE The normal operation voltage of the LM3464 and LM3464A are rated to 80V and 95V respectively, applying voltage over the operation voltage limit to the LM3464/64A can damage the device permanently. In applications that the rail voltage is higher than the operation voltage limited of the device (80V for LM3464, 95V for LM3464A), voltage clamping circuits must be added externally to ensure the voltage limits of all the pins of the LM3464/64A are not violated. Figure 26 shows a typical application circuit with 150V peak rail voltage. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 21 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com In Figure 26, Z1, Z2, Z3, Z4 and ZIN are zener diodes for clamping the DRx pin voltage and input voltage (VIN pin) of the LM3464/64A. The reverse voltage of the zener diodes must be below 80V for LM3464 and 95V for LM3464A. The resistors RDR1, RDR2, RDR3, RDR4 and RIN are resistors for absorbing the voltage difference between the clamping voltage of the zener diodes and the rail voltage. Calculating the Values of Zx and RDRx: The resistance of the RDRx must be properly selected according to the reverse current of the zener diode and input current of the DRx pins of the LM3464/64A to secure the allowable pin voltages are not violated. For instant, the DRx pins are required to clamp at 75V and a 500mW/75V zener diode CMHZ5267B from Central Semiconductor is used. The reverse current of the CMHZ5267B is specified 1.7mA at 75V zener voltage. The maximum allowable reverse current is 6.67mA as the power rating of the CMHZ5276B is 500mW. Given that the input current of the DRx pins of the LM3464/64A at 100V is 63uA maximum, if the DRx pin voltage is below 100V the current flows into the DRx pin (IDRx) is below 63uA. In order to reserve operation margin for component variations, IDRx is assumed equal to 63uA in the following calculations. Because VRAIL(peak) is the possible highest voltage at the DRx pins, the maximum resistance of RDRx can be obtained following this equation: (22) Where VZ and IZ are the reverse voltage and current of the zener diode Zx respectively. For VRAIL(peak) = 150V, the maximum value of RDRx is: (23) And the minimum value of RDRx is: (24) Thus, the value of RDRx must be selected in the range: (25) To minimize power dissipation on the zener diodes, a standard 42.2kΩ resistor can be used for the RDRx. Because the resistors, RDRx are used to absorb the power being introduced by the voltage difference between VRAIL and VZx, the maximum power dissipation on every RDRx equals to: (26) Thus, a standard 42.2kΩ resistor with 0.25W power rating (1206 package) and 1% tolerance can be used. Calculating the Values of ZIN and RIN: Similar to the requirements of selecting the Zx and RDRx, the voltage at the VIN pin of the LM3464/64A is clamped to 75V by a voltage clamping circuit consists of ZIN and RIN. Because the maximum operating and shutdown current (VEN < 2.1V) are 3mA and 700uA respectively, in order to ensure the voltage of the VIN pin is clamped close to 75V even when the LM3464/64A is disabled, a 1.5W/75V zener diode CMZ5946B from Central Semiconductor is used to ensure adequate conduction current for ZIN. The reverse current of the CMZ5946B is specified 5mA at 75V, so the allowable current flows through ZIN is in between 5mA to 20mA. 22 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 The value of RIN is governed by the following equations: (27) Maximum value of RIN: (28) Minimum value of RIN: (29) So the value of RIN must be in the range: (30) To minimize power dissipations on both the ZIN and RIN, a standard 9.31kΩ resistor can be selected for the RIN. Then the maximum power dissipation on RIN is: (31) Thus, a standard 9.38kΩ resistor with 2512 package (1W) and 1% tolerance can be used. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 23 LM3464, LM3464A SNVS652F – APRIL 2010 – REVISED MAY 2013 www.ti.com Additional Application Circuit Figure 27. Cascade Operation with Thermal Foldback Control 24 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A LM3464, LM3464A www.ti.com SNVS652F – APRIL 2010 – REVISED MAY 2013 REVISION HISTORY Changes from Revision E (May 2013) to Revision F • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 24 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3464 LM3464A 25 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM3464AMH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3464AMH LM3464AMHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3464AMH LM3464MH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3464MH LM3464MHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3464MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM3464AMHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 LM3464MHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.8 10.2 1.6 8.0 16.0 Q1 6.8 10.2 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3464AMHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM3464MHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PWP0028A PowerPAD TM - 1.1 mm max height SCALE 1.800 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 A SEATING PLANE PIN 1 ID AREA 28 1 9.8 9.6 NOTE 3 0.1 C 26X 0.65 2X 8.45 14 B 15 4.5 4.3 NOTE 4 0.30 0.19 0.1 C A 28X 1.1 MAX B 0.20 TYP 0.09 SEE DETAIL A 3.15 2.75 0.25 GAGE PLANE 5.65 5.25 THERMAL PAD 0 -8 0.10 0.02 0.7 0.5 (1) DETAIL A TYPICAL 4214870/A 10/2014 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MO-153, variation AET. www.ti.com EXAMPLE BOARD LAYOUT PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 (3) SOLDER MASK OPENING 28X (1.5) 28X (0.45) SOLDER MASK DEFINED PAD 1 28X (0.45) 28X (1.3) 28 26X (0.65) SYMM (5.5) (9.7) SOLDER MASK OPENING (1.3) TYP 14 15 ( 0.2) TYP VIA (1.3) SEE DETAILS SYMM (0.9) TYP METAL COVERED BY SOLDER MASK (0.65) TYP (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214870/A 10/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3) BASED ON 0.127 THICK STENCIL 28X (1.5) 28X (0.45) METAL COVERED BY SOLDER MASK 1 28X (1.3) 28 26X (0.65) 28X (0.45) (5.5) BASED ON 0.127 THICK STENCIL SYMM 14 15 SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SYMM (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE AREA SCALE:6X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.127 0.152 0.178 3.55 X 6.37 3.0 X 5.5 (SHOWN) 2.88 X 5.16 2.66 X 4.77 4214870/A 10/2014 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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