ETC2 EFM32GG942F512-QFP64 Efm32gg942 datasheet Datasheet

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EFM32GG942 DATASHEET
F1024/F512
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• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4µA @ 3 V Shutoff Mode with RTC
• 0.9 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 50 µA/MHz @ 3 V Sleep Mode
• 200 µA/MHz @ 3 V Run Mode, with code executed from Flash
• 1024/512 KB Flash
• Read-while-write support
• 128/128 KB RAM
• 50 General Purpose I/O pins
• Configurable Push-pull, Open-drain, pull resistor, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wakeup from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• 16-bit Low Energy Timer
• 1× 24-bit and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×16 segments
• Voltage boost, adjustable contrast and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
• Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
2
• 2× I C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host and OTG support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• 2× Analog Comparator
• Capacitive sensing with up to 4 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed Serial Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.85 to 3.8 V
• TQFP64 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4F microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
• www.energymicro.com/gecko
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32GG942 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (KB)
RAM
(KB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
Package
EFM32GG942F512-QFP64
512
128
48
1.85 - 3.8
-40 - 85 ºC
TQFP64
EFM32GG942F1024-QFP64
1024
128
48
1.85 - 3.8
-40 - 85 ºC
TQFP64
Visit www.energymicro.com for information on global distributors and representatives or contact
[email protected] for additional information.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32GG microcontroller is well suited for
any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
and shows a summary of the configuration for the EFM32GG942 devices. For a complete feature set
and in-depth information on the modules, the reader is referred to the EFM32GG Reference Manual.
A block diagram of the EFM32GG942 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
GG942F512/1024
Core and Mem ory
Clock Managem ent
Mem ory
Prot ect ion
Unit
ARM Cort ex™-M3 processor
Flash
Program
Mem ory
RAM
Mem ory
Debug
Int erface
w/ ETM
Energy Managem ent
High Freq.
Cryst al
Oscillat or
High Freq
RC
Oscillat or
Volt age
Regulat or
Volt age
Com parat or
Low Freq.
Cryst al
Oscillat or
Low Freq.
RC
Oscillat or
Brown-out
Det ect or
Power-on
Reset
DMA
Cont roller
Ult ra Low Freq.
RC
Oscillat or
Back-up
Power
Dom ain
32-bit bus
Peripheral Reflex Syst em
Serial Int erfaces
USART
Low
Energy
UART
USB
I/O Port s
Tim ers and Triggers
UART
2
I C
Ext ernal
Int errupt s
General
Purpose
I/O
Pin
Reset
Pin
Wakeup
Tim er/
Count er
LESENSE
Low Energy
Tim er
Real Tim e
Count er
Pulse
Count er
Wat chdog
Tim er
Back-up
RTC
Analog Int erfaces
ADC
LCD
Cont roller
DAC
Operat ional
Am plifier
Securit y
Hardware
AES
Pulse
Count er
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32 Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer
pin which can be used to output profiling information, data trace and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller.
The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is
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divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32GG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32GG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32GG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device,
On-the-go (OTG) Dual Role Device or Host-only configuration. In OTG mode the USB supports both
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both fullspeed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal dedicated
Descriptor-Based Scatter/Garther DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in
addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for
supplying 5V to VBUS when operating as host.
2.1.11 Inter-Integrated Circuit Interface (I2C)
2
2
The I C module provides an interface between the MCU and a serial I C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
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mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
2
The interface provided to software by the I C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, I2S devices and IrDA devices.
2.1.13 Pre-Programmed Serial Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.14 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
TM
The unique LEUART , the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.15 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/PulseWidth Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.16 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.17 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz
crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy
Modes and it can also run in backup mode, making it operational even if the main power should drain out.
2.1.18 Low Energy Timer (LETIMER)
TM
The unique LETIMER , the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
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2.1.19 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 – EM3.
2.1.20 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.21 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.22 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.23 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be
combined into one differential output. The DAC may be used for a number of different applications such
as sensor interfaces or sound output.
2.1.24 Operational Amplifier (OPAMP)
The EFM32GG942 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general
purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set
to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable
and the OPAMP has various internal configurations such as unity gain, programmable gain using internal
resistors etc.
2.1.25 Low Energy Sensor Interface (LESENSE)
TM
The Low Energy Sensor Interface (LESENSE ), is a highly configurable sensor interface with support
for up to 4 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE
is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable
FSM which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in
applications with a strict energy budget.
2.1.26 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,
and a set of retention registers, available in all energy modes. This power domain can be configured to
automatically change power source to a backup battery when the main power drains out. The backup
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power domain enables the EFM32GG942 to keep track of time and retain data, even if the main power
source should drain out.
2.1.27 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.28 General Purpose Input/Output (GPIO)
In the EFM32GG942, there are 50 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advances configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.1.29 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to segments. A voltage boost
function enables it to provide the LCD display with higher voltage than the supply voltage for the device.
In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter
interrupt that can wake-up the device on a regular basis for updating data.
2.2 Configuration Summary
The features of the EFM32GG942 is a subset of the feature set described in the EFM32GG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN,
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
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Module
Configuration
Pin Connections
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI.
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
PCNT0_S[1:0]
PCNT1
8-bit count register
PCNT1_S[1:0]
PCNT2
8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[3:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
AES
Full configuration
NA
GPIO
50 pins
Available pins are shown in
Table 4.3 (p. 54)
LCD
Full configuration
LCD_SEG[15:0], LCD_COM[7:0],
LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
OPAMP
2.3 Memory Map
The EFM32GG942 memory map is shown in Figure 2.2 (p. 9) , with RAM and Flash sizes for the
largest memory configuration.
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Figure 2.2. EFM32GG942 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 10) , by simulation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in Table 3.2 (p. 10) , by simulation and/or technology characterisation unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 10) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
10) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage temperature range
TS
Maximum soldering temperature
VDDMAX
External main supply voltage
VIOPIN
Voltage on any I/O pin
Condition
Min
Typ
Max
Unit
1
-40
150
Latest IPC/JEDEC J-STD-020
Standard
°C
260 °C
0
3.8 V
-0.3
VDD+0.3 V
1
Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed calibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data retention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
Parameter
TAMB
Ambient temperature range
VDDOP
Operating supply voltage
fAPB
Internal APB clock frequency
48 MHz
fAHB
Internal AHB clock frequency
48 MHz
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Min
Typ
-40
1.85
10
Max
Unit
85 °C
3.8 V
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3.3.2 Environmental
Table 3.3. Environmental
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VESDHBM
ESD (Human Body Model
HBM)
TAMB=25°C
2 kV
VESDCDM
ESD (Charged Device
Model, CDM)
TAMB=25°C
1 kV
Latch-up sensitivity test passed level A according to JEDEC JESD 78B method Class II, 85°C.
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3.4 Current Consumption
Table 3.4. Current Consumption
Symbol
IEM0
IEM1
IEM2
IEM3
IEM4
Parameter
EM0 current. No prescaling. Running prime number calculation code from
Flash.
EM1 current
Condition
Min
Typ
Max
Unit
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
200
µA/
MHz
28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
201
261 µA/
MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
203
263 µA/
MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
204
270 µA/
MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
207
273 µA/
MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
212
282 µA/
MHz
1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
244
µA/
MHz
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
50
µA/
MHz
28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
52
69 µA/
MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
53
71 µA/
MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
56
77 µA/
MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
57
80 µA/
MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
62
92 µA/
MHz
1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V
114
µA/
MHz
EM2 current with RTC at 1
Hz, RTC prescaled to 1kHz,
32.768 kHz LFRCO, VDD= 3.0
V, TAMB=25°C
1.1
µA
EM2 current with RTC at 1
Hz, RTC prescaled to 1kHz,
32.768 kHz LFRCO, VDD= 3.0
V, TAMB=85°C
4.0
8.0 µA
VDD= 3.0 V, TAMB=25°C
0.9
µA
VDD= 3.0 V, TAMB=85°C
3.8
7.8 µA
VDD= 3.0 V, TAMB=25°C
0.02
µA
VDD= 3.0 V, TAMB=85°C
0.25
0.7 µA
EM2 current
EM3 current
EM4 current
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3.5 Transition between Energy Modes
Table 3.5. Energy Modes Transitions
Symbol
Parameter
Min
tEM10
Transition time from EM1 to EM0
tEM20
Typ
Max
Unit
1
HF
core
CLK
cycles
Transition time from EM2 to EM0
2
µs
tEM30
Transition time from EM3 to EM0
2
µs
tEM40
Transition time from EM4 to EM0
163
µs
0
1
Core wakeup time only.
3.6 Power Management
Table 3.6. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
VBODextthr-
BOD threshold on falling
external supply voltage
1.82
1.85 V
VBODintthr-
BOD threshold on falling
internally regulated supply
voltage
1.62
1.68 V
VBODextthr+
BOD threshold on rising external supply voltage
VPORthr+
Power-on Reset (POR)
threshold on rising external
supply voltage
tRESET
Delay from reset is reApplies to Power-on Reset,
leased until program execu- Brown-out Reset and pin retion starts
set.
CDECOUPLE
Voltage regulator decoupling capacitor.
CUSB_VREGO
CUSB_VREGI
1.85
Unit
V
1.98 V
163
µs
X5R capacitor recommended.
Apply between DECOUPLE
pin and GROUND
1
µF
USB voltage regulator out
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGO
pin and GROUND
1
µF
USB voltage regulator in
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGI
pin and GROUND
4.7
µF
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
13
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Preliminary
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3.7 Flash
Table 3.7. Flash
Symbol
Parameter
ECFLASH
Flash erase cycles before
failure
Condition
Min
TAMB<150°C
RETFLASH
tW_PROG
tPERASE
tDERASE
Flash data retention
cycles
10000
h
10
years
TAMB<70°C
20
years
20
µs
< 512KB
20
20.4
20.8 ms
>= 512KB, LPERASE == 0
20
20.4
20.8 ms
>= 512KB, LPERASE == 1
40
40.4
40.8 ms
< 512KB
40
40.8
41.6 ms
Device erase time
161.6 ms
< 512KB
IWRITE
VFLASH
Unit
20000
>= 512KB
IERASE
Max
TAMB<85°C
Word (32-bit) programming
time
Page erase time
Typ
Erase current
Write current
1
mA
1
mA
1
mA
1
mA
1
mA
1
mA
7
>= 512KB, LPERASE == 0
14
>= 512KB, LPERASE == 1
7
< 512KB
7
>= 512KB, LPWRITE == 0
14
>= 512KB, LPWRITE == 1
7
Supply voltage during flash
erase and write
1.8
3.8 V
1
Measured at 25°C
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
14
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Preliminary
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3.8 General Purpose Input Output
Table 3.8. GPIO
Symbol
Parameter
VIOIL
Input low voltage
VIOIH
Input high voltage
VIOOH
VIOOL
Condition
Min
Typ
Max
Unit
0.3VDD V
0.7VDD
V
Sourcing 6 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.75VDD
V
Sourcing 6 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.95VDD
V
Sourcing 20 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVEMODE = HIGH
0.7VDD
V
Sourcing 20 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVEMODE = HIGH
0.9VDD
V
Output high voltage
Sinking 6 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.25VDD V
Sinking 6 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.05VDD V
Sinking 20 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVEMODE = HIGH
0.3VDD V
Sinking 20 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVEMODE = HIGH
0.1VDD V
Output low voltage
IIOLEAK
Input leakage current
RPU
I/O pin pull-up resistor
40
kOhm
RPD
I/O pin pull-down resistor
40
kOhm
RIOESD
Internal ESD series resistor
200
Ohm
tIOGLITCH
Pulse width of pulses to be
removed by the glitch suppression filter
tIOOF
VIOHYST
Output fall time
I/O pin hysteresis (VIOTHR+
- VIOTHR-)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
High Impedance IO connected to GROUND or Vdd
+/-25 nA
10
50 ns
0.5 mA drive strength
and load capacitance
CL=12.5-25pF.
20+0.1CL
250 ns
2mA drive strength and load
capacitance CL=350-600pF
20+0.1CL
250 ns
VDD = 1.8 - 3.8 V
15
0.1VDD
V
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Preliminary
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Figure 3.1. Typical Low-Level Output Current, 2V Supply Voltage
5
0.20
4
Low-Level Out put Current [ m A]
Low-Level Out put Current [ m A]
0.15
0.10
3
2
0.05
1
-40° C
25° C
85° C
0.00
0.0
0.5
1.5
1.0
Low-Level Out put Volt age [ V]
-40° C
25° C
85° C
0
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
1.5
1.0
Low-Level Out put Volt age [ V]
2.0
GPIO_Px_CTRL DRIVEMODE = LOW
45
20
40
35
Low-Level Out put Current [ m A]
Low-Level Out put Current [ m A]
15
10
30
25
20
15
5
10
5
-40° C
25° C
85° C
0
0.0
0.5
1.5
1.0
Low-Level Out put Volt age [ V]
0
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
-40° C
25° C
85° C
0.5
1.5
1.0
Low-Level Out put Volt age [ V]
2.0
GPIO_Px_CTRL DRIVEMODE = HIGH
16
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Preliminary
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Figure 3.2. Typical High-Level Output Current, 2V Supply Voltage
0.00
0.0
-40°C
25°C
85°C
-40°C
25°C
85°C
–0.5
High-Level Out put Current [ m A]
High-Level Out put Current [ m A]
–0.05
–0.10
–1.0
–1.5
–0.15
–2.0
–0.20
0.0
1.5
0.5
1.0
High-Level Out put Volt age [ V]
–2.5
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
1.5
0.5
1.0
High-Level Out put Volt age [ V]
2.0
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–10
High-Level Out put Current [ m A]
High-Level Out put Current [ m A]
–5
–10
–20
–30
–15
–40
–20
0.0
1.5
0.5
1.0
High-Level Out put Volt age [ V]
–50
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
1.5
0.5
1.0
High-Level Out put Volt age [ V]
2.0
GPIO_Px_CTRL DRIVEMODE = HIGH
17
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Preliminary
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0.5
10
0.4
8
Low-Level Out put Current [ m A]
Low-Level Out put Current [ m A]
Figure 3.3. Typical Low-Level Output Current, 3V Supply Voltage
0.3
0.2
0.1
6
4
2
-40° C
25° C
85° C
0.0
0.0
0.5
1.5
1.0
2.0
Low-Level Out put Volt age [ V]
2.5
-40° C
25° C
85° C
0
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
1.5
1.0
2.0
Low-Level Out put Volt age [ V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = LOW
40
50
35
40
Low-Level Out put Current [ m A]
Low-Level Out put Current [ m A]
30
25
20
15
30
20
10
10
5
0
0.0
-40° C
25° C
85° C
0.5
1.5
1.0
2.0
Low-Level Out put Volt age [ V]
2.5
-40° C
25° C
85° C
0
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
0.5
1.5
1.0
2.0
Low-Level Out put Volt age [ V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = HIGH
18
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Preliminary
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Figure 3.4. Typical High-Level Output Current, 3V Supply Voltage
0.0
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
High-Level Out put Current [ m A]
High-Level Out put Current [ m A]
–0.1
–0.2
–0.3
–2
–3
–4
–0.4
–5
–0.5
0.0
0.5
1.5
1.0
2.0
High-Level Out put Volt age [ V]
2.5
–6
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
2.5
3.0
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–10
High-Level Out put Current [ m A]
–10
High-Level Out put Current [ m A]
1.5
1.0
2.0
High-Level Out put Volt age [ V]
GPIO_Px_CTRL DRIVEMODE = LOW
0
–20
–30
–40
–50
0.0
0.5
–20
–30
–40
0.5
1.5
1.0
2.0
High-Level Out put Volt age [ V]
2.5
–50
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
0.5
1.5
1.0
2.0
High-Level Out put Volt age [ V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = HIGH
19
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Preliminary
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Figure 3.5. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
14
0.7
12
Low-Level Out put Current [ m A]
Low-Level Out put Current [ m A]
0.6
0.5
0.4
0.3
10
8
6
4
0.2
2
0.1
0.0
0.0
-40° C
25° C
85° C
0.5
1.5
1.0
2.0
2.5
Low-Level Out put Volt age [ V]
3.0
-40° C
25° C
85° C
0
0.0
3.5
1.5
1.0
2.0
2.5
Low-Level Out put Volt age [ V]
3.0
50
50
40
40
30
20
10
30
20
10
-40° C
25° C
85° C
0
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = LOW
Low-Level Out put Current [ m A]
Low-Level Out put Current [ m A]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
0.5
1.5
1.0
2.0
2.5
Low-Level Out put Volt age [ V]
3.0
-40° C
25° C
85° C
0
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = STANDARD
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
0.5
1.5
1.0
2.0
2.5
Low-Level Out put Volt age [ V]
3.0
3.5
GPIO_Px_CTRL DRIVEMODE = HIGH
20
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Figure 3.6. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
0
-40°C
25°C
85°C
–1
-40°C
25°C
85°C
–2
High-Level Out put Current [ m A]
High-Level Out put Current [ m A]
–0.2
–0.3
–0.4
–0.5
–3
–4
–5
–6
–0.6
–7
–0.7
–0.8
0.0
–8
0.5
1.5
1.0
2.0
2.5
High-Level Out put Volt age [ V]
3.0
–9
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = LOWEST
3.0
3.5
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–10
High-Level Out put Current [ m A]
–10
High-Level Out put Current [ m A]
1.5
1.0
2.0
2.5
High-Level Out put Volt age [ V]
GPIO_Px_CTRL DRIVEMODE = LOW
0
–20
–30
–40
–50
0.0
0.5
–20
–30
–40
0.5
1.5
1.0
2.0
2.5
High-Level Out put Volt age [ V]
3.0
–50
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = STANDARD
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
0.5
1.5
1.0
2.0
2.5
High-Level Out put Volt age [ V]
3.0
3.5
GPIO_Px_CTRL DRIVEMODE = HIGH
21
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3.9 Oscillators
3.9.1 LFXO
Table 3.9. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFXO
Supported nominal crystal
frequency
ESRLFXO
Supported crystal equivalent series resistance
(ESR)
CLFXOL
Supported crystal external
load range
DCLFXO
Duty cycle
ILFXO
Current consumption for
core and buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL
is 1
190
nA
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST
in CMU_CTRL is 1
400
ms
32.768
30
5
48
kHz
120 kOhm
25 pF
50
53.5 %
For safe startup of a given crystal, the load capacitance should be larger than the value indicated in
Figure 3.7 (p. 22) and in Table 3.10 (p. 23) for a given LFXOBOOST setting. The minimum
supported load capacitance depends on the crystal shunt capacitance, C0, which is specified in crystal
vendors’ datasheet.
Figure 3.7. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup
20
LFXOBOOST= 0,REDLFXOBOOST= 1
LFXOBOOST= 0,REDLFXOBOOST= 0
LFXOBOOST= 1,REDLFXOBOOST= 1
LFXOBOOST= 1,REDLFXOBOOST= 0
18
16
CL [ pF]
14
12
10
8
6
4
2
0.6
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
0.8
1.0
1.4
1.2
C0 [ pF]
22
1.6
1.8
2.0
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Preliminary
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Table 3.10. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup
Symbol
Capacitance [pF]
Shunt Capacitance C0
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
CLmin lfxoboost = 0
redlfxoboost = 1
3.7
4.0
4.3
4.5
4.8
5.0
5.3
5.5
5.7
5.9
6.0
6.2
6.4
6.5
6.7
6.9
CLmin lfxoboost = 1
redlfxoboost = 0
7.3
7.7
8.2
8.6
9.0
9.3
9.6
10.0 10.3 10.5 10.8 11.1 11.3 11.6 11.8 12.1
CLmin lfxoboost = 1
redlfxoboost = 1
10.0 10.6 11.1 11.6 12.1 12.6 13.0 13.4 13.8 14.1 14.5 14.8 15.1 15.4 15.7 16.0
CLmin lfxoboost = 1
redlfxoboost = 0
12.5 13.2 13.9 14.5 15.0 15.5 16.0 16.5 16.9 17.4 17.8 18.2 18.5 18.9 19.3 19.6
3.9.2 HFXO
Table 3.11. HFXO
Symbol
Parameter
fHFXO
Supported nominal crystal
Frequency
Condition
Min
Typ
Max
4
Unit
48 MHz
Supported crystal equivalent series resistance
(ESR)
Crystal frequency 32 MHz
30
60 Ohm
Crystal frequency 4 MHz
400
1500 Ohm
gmHFXO
The transconductance of
the HFXO input transistor
at crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
CHFXOL
Supported crystal external
load range
DCHFXO
Duty cycle
ESRHFXO
IHFXO
tHFXO
Current consumption for
HFXO after startup
Startup time
20
mS
5
25 pF
46
50
54 %
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
µA
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165
µA
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
400
µs
3.9.3 LFRCO
Table 3.12. LFRCO
Symbol
Parameter
fLFRCO
Oscillation frequency ,
VDD= 3.0 V, TAMB=25°C
tLFRCO
Startup time not including
software calibration
150
µs
ILFRCO
Current consumption
190
nA
TUNESTEPL-
Frequency step for LSB
change in TUNING value
1.5
%
FRCO
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Condition
Min
Typ
Max
32.768
23
Unit
kHz
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Figure 3.8. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
42
-40° C
25° C
85° C
40
38
Frequency [ kHz]
Frequency [ kHz]
40
36
38
34
34
32
32
30
1.8
2.2
2.6
3.0
3.4
30
–40
3.8
1.8 V
3V
3.8 V
36
–15
Vdd [ V]
5
45
25
Tem perat ure [ ° C]
65
85
3.9.4 HFRCO
Table 3.13. HFRCO
Symbol
fHFRCO
tHFRCO_settling
IHFRCO
Parameter
Oscillation frequency, VDD=
3.0 V, TAMB=25°C
Settling time after start-up
Min
Typ
Max
Unit
28 MHz frequency band
28
MHz
21 MHz frequency band
21
MHz
14 MHz frequency band
14
MHz
11 MHz frequency band
11
MHz
7 MHz frequency band
6.6
1
MHz
1 MHz frequency band
1.2
2
MHz
fHFRCO = 14 MHz
0.6
Cycles
fHFRCO = 28 MHz
106
µA
fHFRCO = 21 MHz
93
µA
fHFRCO = 14 MHz
77
µA
fHFRCO = 11 MHz
72
µA
fHFRCO = 6.6 MHz
63
µA
fHFRCO = 1.2 MHz
22
µA
Current consumption
DCHFRCO
Duty cycle
TUNESTEPH-
Frequency step for LSB
change in TUNING value
FRCO
Condition
fHFRCO = 14 MHz
48.5
50
51 %
0.3
%
1
7 MHz for devices with prod. rev. < 19.
1 MHz for devices with prod. rev. < 19.
2
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
24
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Preliminary
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Figure 3.9. Calibrated HFRCO 11 MHz Band Frequency vs Temperature and Supply Voltage
11.15
11.20
11.15
11.10
1.8 V
3V
3.8 V
11.10
11.00
10.95
Frequency [ MHz]
Frequency [ MHz]
11.05
-40°C
25°C
85°C
11.05
11.00
10.95
10.90
10.90
10.85
10.80
1.8
10.85
2.2
2.6
3.0
3.4
10.80
–40
3.8
–15
Vdd [ V]
5
45
25
Tem perat ure [ ° C]
65
85
Figure 3.10. Calibrated HFRCO 14 MHz Band Frequency vs Temperature and Supply Voltage
14.15
14.15
-40° C
25° C
85° C
14.10
14.05
Frequency [ MHz]
Frequency [ MHz]
14.10
14.00
14.05
14.00
13.95
13.95
13.90
13.90
13.85
1.8
2.2
2.6
3.0
3.4
13.85
–40
3.8
1.8 V
3V
3.8 V
–15
Vdd [ V]
5
45
25
Tem perat ure [ ° C]
65
85
Figure 3.11. Calibrated HFRCO 21 MHz Band Frequency vs Temperature and Supply Voltage
21.2
21.2
-40° C
25° C
85° C
21.1
21.0
Frequency [ MHz]
Frequency [ MHz]
21.1
20.9
21.0
20.9
20.8
20.8
20.7
20.7
20.6
1.8
2.2
2.6
3.0
3.4
20.6
–40
3.8
Vdd [ V]
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
25
1.8 V
3V
3.8 V
–15
5
45
25
Tem perat ure [ ° C]
65
85
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Preliminary
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Figure 3.12. Calibrated HFRCO 28 MHz Band Frequency vs Temperature and Supply Voltage
28.1
28.0
28.0
27.9
27.9
Frequency [ MHz]
Frequency [ MHz]
28.1
27.8
27.7
27.6
27.8
27.7
27.6
-40° C
25° C
85° C
27.5
27.4
1.8
1.8 V
3V
3.8 V
2.2
2.6
3.0
3.4
27.5
27.4
–40
3.8
–15
5
45
25
Tem perat ure [ ° C]
Vdd [ V]
65
85
3.9.5 ULFRCO
Table 3.14. ULFRCO
Symbol
Parameter
Condition
fULFRCO
Oscillation frequency
25°C, 3V
TCULFRCO
Temperature coefficient
VCULFRCO
Supply voltage coefficient
Min
Typ
Max
0.8
Unit
1.5 kHz
0.05
%/°C
-18.2
%/V
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol
Parameter
VADCIN
Input voltage range
Condition
Min
Single ended
Differential
VADCREFIN
Input range of external reference voltage, single ended and differential
Typ
Max
Unit
0
VREF V
-VREF/2
VREF/2 V
1.25
VDD V
VADCREFIN_CH7 Input range of external negative reference voltage on
channel 7
See VADCREFIN
0
VDD - 1.1 V
VADCREFIN_CH6 Input range of external positive reference voltage on
channel 6
See VADCREFIN
0.625
VDD V
0
VDD V
VADCCMIN
Common mode input range
IADCIN
Input current
CMRRADC
Analog input common
mode rejection ratio
2pF sampling capacitors
1 MSamples/s, 12 bit, external reference
IADC
<100
nA
65
dB
351
µA
67
µA
Average active current
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
MODE in ADCn_CTRL set to
0b00
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b01
63
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b10
64
µA
Internal voltage reference
65
µA
2
pF
IADCREF
Current consumption of internal voltage reference
CADCIN
Input capacitance
RADCIN
Input ON resistance
RADCFILT
Input RC filter resistance
10
CADCFILT
Input RC filter/decoupling
capacitance
250
fADCCLK
ADC Clock Frequency
tADCCONV
1
MOhm
Acquisition time
tADCACQVDD3
Required acquisition time
for VDD/3 reference
fF
13 MHz
6 bit
7
ADCCLK
Cycles
10 bit
11
ADCCLK
Cycles
12 bit
13
ADCCLK
Cycles
1
256 ADCCLK
Cycles
Conversion time
tADCACQ
kOhm
Programmable
2
µs
Startup time of reference
generator and ADC core in
NORMAL mode
5
µs
Startup time of reference
generator and ADC core in
KEEPADCWARM mode
1
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
59
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
65
dB
1 MSamples/s, 12 bit, differential, internal 1.25V reference
60
dB
1 MSamples/s, 12 bit, differential, internal 2.5V reference
65
dB
tADCSTART
SNRADC
Signal to Noise Ratio
(SNR)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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Symbol
SNDRADC
Parameter
Signal to Noise-puls-Distortion Ratio (SNDR)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, differential, 5V reference
54
dB
1 MSamples/s, 12 bit, differential, VDD reference
67
dB
1 MSamples/s, 12 bit, differential, 2xVDD reference
69
dB
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
62
dB
200 kSamples/s, 12 bit, single ended, internal 2.5V reference
63
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
67
dB
200 kSamples/s, 12 bit, differential, internal 1.25V reference
63
dB
200 kSamples/s, 12 bit, differential, internal 2.5V reference
66
dB
200 kSamples/s, 12 bit, differential, 5V reference
66
dB
200 kSamples/s, 12 bit, differential, VDD reference
69
dB
200 kSamples/s, 12 bit, differential, 2xVDD reference
70
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
58
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
64
dB
1 MSamples/s, 12 bit, differential, internal 1.25V reference
60
dB
1 MSamples/s, 12 bit, differential, internal 2.5V reference
64
dB
1 MSamples/s, 12 bit, differential, 5V reference
54
dB
1 MSamples/s, 12 bit, differential, VDD reference
66
dB
1 MSamples/s, 12 bit, differential, 2xVDD reference
68
dB
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
61
dB
200 kSamples/s, 12 bit, single ended, internal 2.5V reference
65
dB
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Symbol
SFDRADC
Parameter
Spurious-Free Dynamic
Range (SFDR)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, single
ended, VDD reference
66
dB
200 kSamples/s, 12 bit, differential, internal 1.25V reference
63
dB
200 kSamples/s, 12 bit, differential, internal 2.5V reference
66
dB
200 kSamples/s, 12 bit, differential, 5V reference
66
dB
200 kSamples/s, 12 bit, differential, VDD reference
68
dB
200 kSamples/s, 12 bit, differential, 2xVDD reference
69
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
64
dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
73
dBc
1 MSamples/s, 12 bit, differential, internal 1.25V reference
66
dBc
1 MSamples/s, 12 bit, differential, internal 2.5V reference
77
dBc
1 MSamples/s, 12 bit, differential, VDD reference
76
dBc
1 MSamples/s, 12 bit, differential, 2xVDD reference
75
dBc
1 MSamples/s, 12 bit, differential, 5V reference
69
dBc
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
75
dBc
200 kSamples/s, 12 bit, single ended, internal 2.5V reference
75
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
76
dBc
200 kSamples/s, 12 bit, differential, internal 1.25V reference
79
dBc
200 kSamples/s, 12 bit, differential, internal 2.5V reference
79
dBc
200 kSamples/s, 12 bit, differential, 5V reference
78
dBc
200 kSamples/s, 12 bit, differential, VDD reference
79
dBc
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Symbol
VADCOFFSET
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, differential, 2xVDD reference
79
dBc
After calibration, single ended
0.3
mV
After calibration, differential
0.3
mV
Offset voltage
-1.92
mV/°C
Thermometer output gradient
-6.3
ADC
Codes/
°C
DNLADC
Differential non-linearity
(DNL)
±0.7
LSB
INLADC
Integral non-linearity (INL),
End point method
±1.2
LSB
MCADC
No missing codes
TGRADADCTH
GAINED
OFFSETED
1
11.999
12
bits
1.25V reference
0.01
2
0.033
2.5V reference
0.01
2
0.03
1.25V reference
0.2
2
0.7
2.5V reference
0.2
2
0.62
Gain error drift
Offset error drift
3
%/°C
3
%/°C
3
LSB/°C
3
LSB/°C
1
On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2
Typical numbers given by abs(Mean) / (85 - 25).
3
Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.13 (p.
30) and Figure 3.14 (p. 31) , respectively.
Figure 3.13. Integral Non-Linearity (INL)
Digit al ouput code
INL= |[ (VD -VSS)/VLSBIDEAL] - D| where 0 < D < 2 N - 1
4095
4094
4093
4092
Act ual ADC
t ranfer funct ion
before offset and
gain correct ion
Act ual ADC
t ranfer funct ion
aft er offset and
gain correct ion
INL Error
(End Point INL)
3
Ideal t ransfer
curve
2
1
VOFFSET
0
Analog Input
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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Figure 3.14. Differential Non-Linearity (DNL)
Digit al
ouput
code
DNL= |[ (VD+ 1 - VD )/VLSBIDEAL] - 1| where 0 < D < 2 N - 2
Full Scale Range
4095
4094
Exa m p le : Adjacent
input value VD+ 1
corrresponds t o digit al
out put code D+ 1
4093
4092
Act ual t ransfer
funct ion wit h one
m issing code.
Exa m p le : Input value
VD corrresponds t o
digit al out put code D
Code widt h = 2 LSB
DNL= 1 LSB
Ideal t ransfer
curve
5
0.5
LSB
Ideal spacing
bet ween t wo
adjacent codes
VLSBIDEAL= 1 LSB
4
3
2
1
Ideal 50%
Transit ion Point
Ideal Code Cent er
0
Analog Input
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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3.10.1 Typical performance
Figure 3.15. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°
0
0
–20
–20
–40
–40
Am plit ude [ dB]
Am plit ude [ dB]
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
–160
–180
0
20
40
60
Frequency [ kHz]
–160
80
0
20
1.25V Reference
40
60
Frequency [ kHz]
80
2.5V Reference
0
0
–20
–20
–40
–40
Am plit ude [ dB]
Am plit ude [ dB]
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
–160
–180
0
20
40
60
Frequency [ kHz]
–160
80
2XVDDVSS Reference
0
20
40
60
Frequency [ kHz]
80
5VDIFF Reference
0
–20
–40
Am plit ude [ dB]
–60
–80
–100
–120
–140
–160
–180
0
20
40
60
Frequency [ kHz]
80
VDD Reference
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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1.5
1.5
1.0
1.0
0.5
0.5
INL (LSB)
INL (LSB)
Figure 3.16. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°
0.0
0.0
–0.5
–0.5
–1.0
0
512
1024
1536
2048
2560
Out put code
3072
3584
–1.0
4096
0
512
1.25V Reference
1024
1536
2048
2560
Out put code
3072
3584
4096
3072
3584
4096
2.5V Reference
0.8
1.0
0.6
0.4
INL (LSB)
INL (LSB)
0.5
0.2
0.0
0.0
–0.2
–0.4
–0.5
–0.6
0
512
1024
1536
2048
2560
Out put code
3072
3584
4096
0
2XVDDVSS Reference
512
1024
1536
2048
2560
Out put code
5VDIFF Reference
0.8
0.6
0.4
INL (LSB)
0.2
0.0
–0.2
–0.4
–0.6
–0.8
0
512
1024
1536
2048
2560
Out put code
3072
3584
4096
VDD Reference
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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1.0
1.0
0.5
0.5
DNL (LSB)
DNL (LSB)
Figure 3.17. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°
0.0
–0.5
–1.0
0.0
–0.5
0
512
1024
1536
2048
2560
Out put code
3072
3584
–1.0
4096
0
512
1.0
1.0
0.5
0.5
0.0
–0.5
–1.0
1536
2048
2560
Out put code
3072
3584
4096
3072
3584
4096
2.5V Reference
DNL (LSB)
DNL (LSB)
1.25V Reference
1024
0.0
–0.5
0
512
1024
1536
2048
2560
Out put code
3072
3584
–1.0
4096
2XVDDVSS Reference
0
512
1024
1536
2048
2560
Out put code
5VDIFF Reference
1.0
DNL (LSB)
0.5
0.0
–0.5
–1.0
0
512
1024
1536
2048
2560
Out put code
3072
3584
4096
VDD Reference
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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Figure 3.18. ADC Absolute Offset, Common Mode = Vdd /2
5
2.0
Vref= 1V25
Vref= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
4
1.5
2
Act ual Offset [ LSB]
Act ual Offset [ LSB]
3
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1
0
–1
1.0
0.5
0.0
–2
–0.5
–3
–4
2.0
2.2
2.4
2.6
2.8
3.0
Vdd (V)
3.2
3.4
3.6
–1.0
–40
3.8
Offset vs Supply Voltage, Temp = 25°
–15
5
25
Tem p (C)
45
65
85
Offset vs Temperature, Vdd = 3V
Figure 3.19. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
79.4
71
2XVDDVSS
70
1V25
79.2
Vdd
69
79.0
67
5VDIFF
2V5
66
SFDR [ dB]
SNR [ dB]
68
Vdd
2V5
78.8
78.6
2XVDDVSS
78.4
65
78.2
64
63
–40
–15
5
45
25
Tem perat ure [ ° C]
65
5VDIFF
1V25
85
78.0
–40
Signal to Noise Ratio (SNR)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
–15
5
45
25
Tem perat ure [ ° C]
65
85
Spurious-Free Dynamic Range (SFDR)
35
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Figure 3.20. ADC Temperature sensor readout
2600
Vdd= 1.8
Vdd= 3
Vdd= 3.8
Sensor readout
2500
2400
2300
2200
2100
–40
–25 –15
–5
5
15 25 35 45
Tem perat ure [ ° C]
55
65
75
85
3.11 Digital Analog Converter (DAC)
Table 3.16. DAC
Symbol
VDACOUT
VDACCM
IDAC
Parameter
Condition
Min
Typ
0
VDD V
VDD voltage reference, differential
-VDD
VDD V
0
VDD V
Output voltage range
Output common mode voltage range
Active current including references for 2 channels
500 kSamples/s, 12bit
400
µA
100 kSamples/s, 12 bit
200
µA
38
µA
Sample rate
500 ksamples/s
Continuous Mode
fDAC
DAC clock frequency
CYCDACCONV
Clock cyckles per conversion
tDACCONV
Conversion time
tDACSETTLE
Settling time
SNRDAC
Unit
VDD voltage reference, single
ended
1 kSamples/s 12 bit NORMAL
SRDAC
Max
Signal to Noise Ratio
(SNR)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
1000 kHz
Sample/Hold Mode
250 kHz
Sample/Off Mode
250 kHz
2
2
µs
5
µs
500 kSamples/s, 12 bit, single ended, internal 1.25V reference
58
dB
500 kSamples/s, 12 bit, single ended, internal 2.5V reference
59
dB
500 kSamples/s, 12 bit, differential, internal 1.25V reference
58
dB
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Symbol
SNDRDAC
SFDRDAC
VDACOFFSET
Parameter
Signal to Noise-pulse Distortion Ratio (SNDR)
Spurious-Free Dynamic
Range(SFDR)
Condition
Min
Typ
Max
Unit
500 kSamples/s, 12 bit, differential, internal 2.5V reference
58
dB
500 kSamples/s, 12 bit, differential, VDD reference
59
dB
500 kSamples/s, 12 bit, single ended, internal 1.25V reference
57
dB
500 kSamples/s, 12 bit, single ended, internal 2.5V reference
54
dB
500 kSamples/s, 12 bit, differential, internal 1.25V reference
56
dB
500 kSamples/s, 12 bit, differential, internal 2.5V reference
53
dB
500 kSamples/s, 12 bit, differential, VDD reference
55
dB
500 kSamples/s, 12 bit, single ended, internal 1.25V reference
62
dBc
500 kSamples/s, 12 bit, single ended, internal 2.5V reference
56
dBc
500 kSamples/s, 12 bit, differential, internal 1.25V reference
61
dBc
500 kSamples/s, 12 bit, differential, internal 2.5V reference
55
dBc
500 kSamples/s, 12 bit, differential, VDD reference
60
dBc
After calibration, single ended
2
mV
After calibration, differential
2
mV
Offset voltage
DNLDAC
Differential non-linearity
±1
LSB
INLDAC
Integral non-linearity
±5
LSB
MCDAC
No missing codes
12
bits
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.17. OPAMP
Symbol
IOPAMP
Parameter
Active Current
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, Unity
Gain
400
µA
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity
Gain
100
µA
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Symbol
Parameter
Condition
Min
Typ
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity
Gain
GOL
GBWOPAMP
PMOPAMP
Open Loop Gain
Gain Bandwidth Product
Phase Margin
RINPUT
Input Resistance
RLOAD
Load Resistance
ILOAD_DC
DC Load Current
VINPUT
Input Voltage
VOUTPUT
VOFFSET
Max
13
µA
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
101
dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
98
dB
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
91
dB
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
6.1
MHz
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
1.8
MHz
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
0.25
MHz
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0,
CL=75 pF
64
°
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1,
CL=75 pF
58
°
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1,
CL=75 pF
58
°
100
200
NOPAMP
Mohm
Ohm
11 mA
OPAxHCMDIS=0
VSS
VDD V
OPAxHCMDIS=1
VSS
VDD-1.2 V
VSS
VDD V
Output Voltage
Unity Gain, VSS<Vin<DD,
OPAxHCMDIS=0
6
mV
Unity Gain, VSS<Vin<DD-1.2,
OPAxHCMDIS=1
1
mV
Input Offset Voltage
VOFFSET_DRIFT Input Offset Voltage Drift
SROPAMP
Unit
Slew Rate
Voltage Noise
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
0.02 mV/°C
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
3.2
V/µs
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
0.8
V/µs
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
0.1
V/µs
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAxHCMDIS=0
101
µVRMS
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAxHCMDIS=1
141
µVRMS
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vout=1V, RESSEL=0,
0.1 Hz<f<1 MHz, OPAxHCMDIS=0
196
µVRMS
Vout=1V, RESSEL=0,
0.1 Hz<f<1 MHz, OPAxHCMDIS=1
229
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0
1230
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1
2130
µVRMS
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0
1630
µVRMS
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1
2590
µVRMS
Figure 3.21. OPAMP Common Mode Rejection Ratio
Figure 3.22. OPAMP Positive Power Supply Rejection Ratio
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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Figure 3.23. OPAMP Negative Power Supply Rejection Ratio
Figure 3.24. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
Figure 3.25. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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3.13 Analog Comparator (ACMP)
Table 3.18. ACMP
Symbol
Parameter
VACMPIN
Input voltage range
0
VDD V
VACMPCM
ACMP Common Mode voltage range
0
VDD V
IACMP
IACMPREF
VACMPOFFSET
VACMPHYST
RCSRES
Condition
Active current
Current consumption of internal voltage reference
Min
Typ
Max
Unit
BIASPROG=0b0000, FULLBIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
µA
BIASPROG=0b1111, FULLBIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
2.87
µA
BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
195
µA
Internal voltage reference off.
Using external voltage reference
0
µA
Internal voltage reference
5
µA
Single ended
10
mV
Differential
10
mV
Programmable
17
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
39
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
kOhm
CSRESSEL=0b10 in
ACMPn_INPUTSEL
104
kOhm
CSRESSEL=0b11 in
ACMPn_INPUTSEL
136
kOhm
Offset voltage
ACMP hysteresis
Capacitive Sense Internal
Resistance
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 41) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
41
(3.1)
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Figure 3.26. Typical ACMP Characteristics
4.5
2.5
HYSTSEL= 0.0
HYSTSEL= 2.0
HYSTSEL= 4.0
HYSTSEL= 6.0
4.0
3.5
Response Tim e [ us]
Current [ uA]
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0.0
4
8
ACMP_CTRL_BIASPROG
0
0.0
12
Current consumption
0
2
4
6
8
10
ACMP_CTRL_BIASPROG
12
14
Response time
100
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hyst eresis [ m V]
80
60
40
20
0
0
1
2
4
3
ACMP_CTRL_HYSTSEL
5
6
7
Hysteresis
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
42
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3.14 Voltage Comparator (VCMP)
Table 3.19. VCMP
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VVCMPIN
Input voltage range
VDD
V
VVCMPCM
VCMP Common Mode voltage range
VDD
V
BIASPROG=0b0000
and HALFBIAS=1 in
VCMPn_CTRL register
0.1
µA
14.7
µA
IVCMP
Active current
BIASPROG=0b1111
and HALFBIAS=0 in
VCMPn_CTRL register.
LPREF=0.
tVCMPREF
Startup time reference generator
NORMAL
10
µs
Single ended
10
mV
VVCMPOFFSET
Offset voltage
Differential
10
mV
17
mV
VVCMPHYST
VCMP hysteresis
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
43
(3.2)
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3.15 LCD
Table 3.20. LCD
Symbol
Parameter
Condition
fLCDFR
Frame rate
NUMSEG
Number of segments supported
VLCD
LCD supply voltage range
Min
Typ
30
ILCD
Steady state current consumption.
ILCDBOOST
Steady state Current contribution of internal boost.
Unit
200 Hz
16×8
Internal boost circuit enabled
seg
2.0
3.8 V
Display disconnected, static mode, framerate 32 Hz, all
segments on.
250
nA
Display disconnected,
quadruplex mode, framerate 32 Hz, all segments on,
bias mode to ONETHIRD in
LCD_DISPCTRL register.
550
nA
0
µA
Internal voltage boost on,
boosting from 2.2 V to 3.0 V.
8.4
µA
VBLEV of LCD_DISPCTRL
register to LEVEL0
3.0
V
VBLEV of LCD_DISPCTRL
register to LEVEL1
3.08
V
VBLEV of LCD_DISPCTRL
register to LEVEL2
3.17
V
VBLEV of LCD_DISPCTRL
register to LEVEL3
3.26
V
VBLEV of LCD_DISPCTRL
register to LEVEL4
3.34
V
VBLEV of LCD_DISPCTRL
register to LEVEL5
3.43
V
VBLEV of LCD_DISPCTRL
register to LEVEL6
3.52
V
VBLEV of LCD_DISPCTRL
register to LEVEL7
3.6
V
Internal voltage boost off
VBOOST
Max
Boost Voltage
The total LCD current is given by Equation 3.3 (p. 44) . ILCDBOOST is zero if internal boost is off.
Total LCD Current Based on Operational Mode and Internal Boost
ILCDTOTAL = ILCD + ILCDBOOST
(3.3)
3.16 Digital Peripherals
Table 3.21. Digital Peripherals
Symbol
Parameter
Condition
IUSART
USART current
USART idle current, clock enabled
IUART
UART current
UART idle current, clock enabled
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Min
44
Typ
Max
Unit
7.5
µA/
MHz
5.63
µA/
MHz
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Symbol
Parameter
Condition
ILEUART
LEUART current
LEUART idle current, clock
enabled
150
nA
II2C
I2C current
I2C idle current, clock enabled
6.25
µA/
MHz
ITIMER
TIMER current
TIMER_0 idle current, clock
enabled
8.75
µA/
MHz
ILETIMER
LETIMER current
LETIMER idle current, clock
enabled
150
nA
IPCNT
PCNT current
PCNT idle current, clock enabled
100
nA
IRTC
RTC current
RTC idle current, clock enabled
100
nA
ILCD
LCD current
LCD idle current, clock enabled
100
nA
IAES
AES current
AES idle current, clock enabled
2.5
µA/
MHz
IGPIO
GPIO current
GPIO idle current, clock enabled
5.31
µA/
MHz
IPRS
PRS current
PRS idle current
2,81
µA/
MHz
IDMA
DMA current
Clock enable
8.12
µA/
MHz
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Min
45
Typ
Max
Unit
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32GG942.
4.1 Pinout
The EFM32GG942 pinout is shown in Figure 4.1 (p. 46) and Table 4.1 (p. 46). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32GG942 Pinout (top view, not to scale)
Table 4.1. Device Pinout
Pin Alternate Functionality / Description
Pin #
QFP64 Pin#
and Name
Pin Name
Analog
Timers
Communication
Other
1
PA0
LCD_SEG13
TIM0_CC0 #0/1/4
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
2
PA1
LCD_SEG14
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
3
PA2
LCD_SEG15
TIM0_CC2 #0/1
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
46
CMU_CLK0 #0
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Pin #
QFP64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
ETM_TD0 #3
4
PA3
LCD_SEG16
TIM0_CDTI0 #0
LES_ALTEX2 #0
ETM_TD1 #3
5
PA4
LCD_SEG17
TIM0_CDTI1 #0
LES_ALTEX3 #0
ETM_TD2 #3
6
PA5
LCD_SEG18
TIM0_CDTI2 #0
LEU1_TX #1
7
IOVDD_0
8
VSS
9
PB3
LCD_SEG20/
LCD_COM4
PCNT1_S0IN #1
US2_TX #1
10
PB4
LCD_SEG21/
LCD_COM5
PCNT1_S1IN #1
US2_RX #1
11
PB5
LCD_SEG22/
LCD_COM6
US2_CLK #1
12
PB6
LCD_SEG23/
LCD_COM7
US2_CS #1
13
PC4
DAC0_P0 #0/
OPAMP_P0
ACMP0_CH4
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0
LES_CH4 #0
14
PC5
DAC0_N0 #0/
OPAMP_N0
ACMP0_CH5
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
LES_CH5 #0
15
PB7
LFXTAL_P
TIM1_CC0 #3
US0_TX #4
US1_CLK #0
16
PB8
LFXTAL_N
TIM1_CC1 #3
US0_RX #4
US1_CS #0
17
PA12
LCD_BCAP_P
TIM2_CC0 #1
18
PA13
LCD_BCAP_N
TIM2_CC1 #1
19
PA14
LCD_BEXT
TIM2_CC2 #1
20
RESETn
21
PB11
22
VSS
23
AVDD_1
24
PB13
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
25
PB14
HFXTAL_N
US0_CS #4/5
LEU0_RX #1
26
IOVDD_3
Digital IO power supply 3.
27
AVDD_0
Analog power supply 0.
LES_ALTEX4 #0
ETM_TD3 #3
Digital IO power supply 0.
Ground
Reset input.
Active low, with internal pull-up.
DAC0_OUT0 #0/
OPAMP_OUT0
TIM1_CC2 #3
LETIM0_OUT0 #1
I2C1_SDA #1
Ground
Analog power supply 1 .
28
PD0
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
DAC0_OUT2 #1/
OPAMP_OUT2
29
PD1
ADC0_CH1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
TIM0_CC0 #3
PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
30
PD2
ADC0_CH2
TIM0_CC1 #3
US1_CLK #1
USB_DMPU #0
DBG_SWO #3
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
PCNT2_S0IN #0
US1_TX #1
47
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Pin Alternate Functionality / Description
Pin #
QFP64 Pin#
and Name
Pin Name
Analog
Timers
Communication
Other
31
PD3
ADC0_CH3
DAC0_N2 #0/
OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
32
PD4
ADC0_CH4
DAC0_P2 #0/
OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
33
PD5
ADC0_CH5
DAC0_OUT2 #0/
OPAMP_OUT2
LEU0_RX #0
ETM_TD3 #0/2
34
PD6
ADC0_CH6
DAC0_P1 #0/
OPAMP_P1
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
US1_RX #2
I2C0_SDA #1
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
35
PD7
ADC0_CH7
DAC0_N1 #0/
OPAMP_N1
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ETM_TCLK #0
36
PD8
BU_VIN
37
PC6
ACMP0_CH6
LEU1_TX #0
I2C0_SDA #2
LES_CH6 #0
ETM_TCLK #2
38
PC7
ACMP0_CH7
LEU1_RX #0
I2C0_SCL #2
LES_CH7 #0
ETM_TD0 #2
39
VDD_DREG
Power supply for on-chip voltage regulator.
40
DECOUPLE
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
41
PE4
LCD_COM0
US0_CS #1
42
PE5
LCD_COM1
US0_CLK #1
43
PE6
LCD_COM2
US0_RX #1
44
PE7
LCD_COM3
US0_TX #1
45
USB_VREGI
USB Input to internal 3.3 V regulator.
46
USB_VREGO
USB Decoupling for internal 3.3 V USB regulator and regulator output.
47
PF10
USB_DM #0
48
PF11
USB_DP #0
49
PF0
TIM0_CC0 #5
LETIM0_OUT0 #2
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK #0/1/2/3
50
PF1
TIM0_CC1 #5
LETIM0_OUT1 #2
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
51
PF2
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
52
USB_VBUS
53
PF12
54
PF5
55
IOVDD_5
56
VSS
57
PE8
LCD_SEG4
PCNT2_S0IN #1
58
PE9
LCD_SEG5
PCNT2_S1IN #1
59
PE10
LCD_SEG6
TIM1_CC0 #1
US0_TX #0
BOOTLOADER_TX
60
PE11
LCD_SEG7
TIM1_CC1 #1
US0_RX #0
LES_ALTEX5 #0
LCD_SEG0
CMU_CLK1 #1
USB 5.0 V VBUS input.
USB_ID #0
LCD_SEG3
TIM0_CDTI2 #2/5
USB_VBUSEN #0
PRS_CH2 #1
Digital IO power supply 5.
Ground
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
48
PRS_CH3 #1
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Pin #
QFP64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
BOOTLOADER_RX
TIM1_CC2 #1
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
61
PE12
LCD_SEG8
62
PE13
LCD_SEG9
63
PE14
LCD_SEG10
TIM3_CC0 #0
LEU0_TX #2
64
PE15
LCD_SEG11
TIM3_CC1 #0
LEU0_RX #2
4.2 Alternate functionality pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 49) . The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 4.2. Alternate functionality overview
LOCATION
Alternate
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH4
PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5
PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6
PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7
PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
PD6
Analog comparator ACMP0, digital output.
ACMP1_O
PF2
PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOTLOADER_RX
PE11
Bootloader RX
BOOTLOADER_TX
PE10
Bootloader TX
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2
CMU_CLK1
PA1
DAC0_N0 /
PC5
PD8
PD7
Clock Management Unit, clock output number 0.
PE12
Clock Management Unit, clock output number 1.
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
Operational Amplifier 0 external negative input.
49
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
OPAMP_N0
DAC0_N1 /
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_N2 /
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
DAC0_OUT0 /
OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT
PD0
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
DAC0_OUT1ALT /
OPAMP_OUT1ALT
PD1
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
DAC0_OUT2 /
OPAMP_OUT2
PD5
Digital to Analog Converter DAC0_OUT2 /
OPAMP output channel number 2.
DAC0_P0 /
OPAMP_P0
PC4
Operational Amplifier 0 external positive input.
DAC0_P1 /
OPAMP_P1
PD6
Operational Amplifier 1 external positive input.
DAC0_P2 /
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
DBG_SWCLK
PF0
PF0
PF0
PF0
DBG_SWDIO
PF1
PF1
PF1
PF1
DBG_SWO
PF2
PD1
PD2
ETM_TCLK
PD7
PC6
ETM_TD0
PD6
PC7
PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3
PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4
PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5
PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0
PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU3
PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4
PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5
PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal (4 - 48 MHz) negative pin. Also
used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal (4 - 48 MHz) positive pin.
I2C0_SCL
PA1
PD7
PC7
PF1
PE13
I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0
PD6
PC6
PF0
PE12
I2C0 Serial Data input / output.
I2C1_SCL
PC5
I2C1_SDA
PC4
LCD_BCAP_N
PA13
LCD voltage booster (optional), boost capacitor, negative
pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P
PA12
LCD voltage booster (optional), boost capacitor, positive
pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
PD0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must
be enabled by software to be used.
Embedded Trace Module ETM clock .
I2C1 Serial Clock Line input / output.
PB11
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
I2C1 Serial Data input / output.
50
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD voltage booster (optional), boost output. If using the
LCD voltage booster, connect a 1 uF capacitor between
this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if
the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this
pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD_SEG20/
LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 4
LCD_SEG21/
LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 5
LCD_SEG22/
LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 6
LCD_SEG23/
LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 7
LES_ALTEX0
PD6
LESENSE alternate exite output 0.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_ALTEX1
PD7
LESENSE alternate exite output 1.
LES_ALTEX2
PA3
LESENSE alternate exite output 2.
LES_ALTEX3
PA4
LESENSE alternate exite output 3.
LES_ALTEX4
PA5
LESENSE alternate exite output 4.
LES_ALTEX5
PE11
LESENSE alternate exite output 5.
LES_ALTEX6
PE12
LESENSE alternate exite output 6.
LES_ALTEX7
PE13
LESENSE alternate exite output 7.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LETIM0_OUT0
PD6
LETIM0_OUT1
PD7
LEU0_RX
PD5
LEU0_TX
PD4
LEU1_RX
PC7
LEU1_TX
PC6
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
PB11
PF0
PC4
Low Energy Timer LETIM0, output channel 0.
PF1
PC5
Low Energy Timer LETIM0, output channel 1.
PB14
PE15
PF1
PA0
LEUART0 Receive input.
PB13
PE14
PF0
PF2
LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in
half duplex communication.
PA5
PCNT0_S0IN
PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN
PC4
PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN
PC5
PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN
PD0
PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN
PD1
PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PF5
Peripheral Reflex System PRS, channel 2.
PRS_CH3
PE8
Peripheral Reflex System PRS, channel 3.
TIM0_CC0
PA0
PA0
PD1
PF0
Timer 0 Capture Compare input / output channel 0.
TIM0_CC1
PA1
PA1
PD2
PF1
Timer 0 Capture Compare input / output channel 1.
TIM0_CC2
PA2
PA2
PD3
PF2
Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0
PA3
Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1
PA4
Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2
PA5
PF5
PA0
PC4
PF5
Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0
PE10
PB7
PD6
Timer 1 Capture Compare input / output channel 0.
TIM1_CC1
PE11
PB8
PD7
Timer 1 Capture Compare input / output channel 1.
TIM1_CC2
PE12
PB11
TIM2_CC0
PA12
Timer 2 Capture Compare input / output channel 0.
TIM2_CC1
PA13
Timer 2 Capture Compare input / output channel 1.
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Timer 1 Capture Compare input / output channel 2.
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Alternate
LOCATION
Functionality
0
TIM2_CC2
1
2
3
4
5
PA14
6
Description
Timer 2 Capture Compare input / output channel 2.
TIM3_CC0
PE14
Timer 3 Capture Compare input / output channel 0.
TIM3_CC1
PE15
Timer 3 Capture Compare input / output channel 1.
US0_CLK
PE12
PE5
PB13
PB13
USART0 clock input / output.
US0_CS
PE13
PE4
PB14
PB14
USART0 chip select input / output.
US0_RX
PE11
PE6
USART0 Asynchronous Receive.
PE12
PB8
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
US0_TX
PE10
PE7
PE13
PB7
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
PB7
PD2
PF0
USART1 clock input / output.
US1_CS
PB8
PD3
PF1
USART1 chip select input / output.
PD1
PD6
USART1 Asynchronous Receive.
US1_RX
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
US1_TX
PD0
PD7
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
PC4
PB5
USART2 clock input / output.
US2_CS
PC5
PB6
USART2 chip select input / output.
USART2 Asynchronous Receive.
US2_RX
PB4
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
US2_TX
PB3
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_VBUS
USB 5 V VBUS input.
USB_VBUSEN
PF5
USB 5 V VBUS enable.
USB_VREGI
USB_VREGI
USB Input to internal 3.3 V regulator
USB_VREGO
USV_VREGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
4.3 GPIO pinout overview
The specific GPIO pins available in EFM32GG942 is shown in Table 4.3 (p. 54) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
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Table 4.3. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin
9
Pin
8
Pin
7
Pin
6
Pin
5
Pin
4
Pin
3
Pin
2
Pin
1
Pin
0
Port A
-
PA14
PA13
PA12
-
-
-
-
-
-
PA5
PA4
PA3
PA2
PA1
PA0
Port B
-
PB14
PB13
-
PB11
-
-
PB8
PB7
PB6
PB5
PB4
PB3
-
-
-
Port C
-
-
-
-
-
-
-
-
PC7
PC6
PC5
PC4
-
-
-
-
Port D
-
-
-
-
-
-
-
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Port E
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
-
-
-
-
Port F
-
-
-
PF12
PF11
PF10
-
-
-
-
PF5
-
-
PF2
PF1
PF0
4.4 Opamp pinout overview
The specific opamp terminals available in EFM32GG942 is shown in Figure 4.2 (p. 54) .
Figure 4.2. Opamp Pinout
PB11
PC4
PC5
PD4
PD3
PD6
PD7
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OUT0ALT
+
OPA0
OUT0
+
OPA2
OUT2
OUT1ALT
+
OPA1
OUT1
-
54
PC12
PC13
PC14
PC15
PD0
PD1
PD5
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4.5 TQFP64 Package
Figure 4.3. LQFP64
Note:
1.
2.
3.
4.
5.
All dimensions & tolerancing confirm to ASME Y14.5M-1994.
The top package body size may be smaller than the bottom package body size.
Datum 'A,B', and 'B' to be determined at datum plane 'H'.
To be determined at seating place 'C'.
Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side.
'D1' and 'E1' are maximum plastic body size dimension including mold mismatch. Dimension 'D1' and
'E1' shall be determined at datum plane 'H'.
6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.
7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the
lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located
on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm
8. Exact shape of each corner is optional.
9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10.All dimensions are in millimeters.
Table 4.4. QFP64 (Dimensions in mm)
DIM
MIN
NOM
MAX
DIM
A
-
1.10
1.20
L1
A1
0.05
-
0.15
R1
0.08
-
-
A2
0.95
1.00
1.05
R2
0.08
-
0.20
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NOM
MAX
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DIM
MIN
NOM
MAX
DIM
MIN
NOM
MAX
b
0.17
0.22
0.27
S
0.20
-
-
b1
0.17
0.20
0.23
θ
0°
3.5°
7°
c
0.09
-
0.20
θ1
0°
-
-
C1
0.09
-
0.16
θ2
11°
12°
13°
θ3
11°
12°
13°
D
12.0 BSC
D1
10.0 BSC
e
0.50 BSC
E
12.0 BSC
E1
10.0 BSC
L
0.45
0.60
0.75
The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch.
The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. TQFP64 PCB Land Pattern
a
p8
p7
p6
p1
b
e
c
p2
p5
p3
p4
d
Table 5.1. QFP64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
Symbol
Pin number
Symbol
Pin number
a
1.60
P1
1
P6
48
b
0.30
P2
16
P7
49
c
0.50
P3
17
P8
64
d
11.50
P4
32
-
-
e
11.50
P5
33
-
-
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Figure 5.2. TQFP64 PCB Solder Mask
a
b
e
c
d
Table 5.2. QFP64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
1.72
b
0.42
c
0.50
d
11.50
e
11.50
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Figure 5.3. TQFP64 PCB Stencil Design
a
b
e
c
d
Table 5.3. QFP64 PCB Stencil Design Dimensions (Dimensions in mm)
1.
2.
3.
4.
5.
Symbol
Dim. (mm)
a
1.50
b
0.20
c
0.50
d
11.50
e
11.50
The drawings are not to scale.
All dimensions are in millimeters.
All drawings are subject to change without notice.
The PCB Land Pattern drawing is in compliance with IPC-7351B.
Stencil thickness 0.125 mm.
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 60) . If the revision
says "ES" (Engineering Sample), the revision must be read out electronically as specified in the reference
manual.
6.3 Errata
Please see the dxxxx_efm32gg942_errata.pdf for description and resolution of device erratas. This document is available in Simplicity Studio and online at http://www.energymicro.com/downloads/datasheets.
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7 Revision History
7.1 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.2 Revision 0.98
May 25th, 2012
Corrected EM3 current consumption in the Electrical Characteristics section.
7.3 Revision 0.96
February 28th, 2012
Added reference to errata document.
Corrected TQFP64 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.4 Revision 0.95
September 28th, 2011
Flash configuration for Giant Gecko is now 1024KB or 512KB. For flash sizes below 512KB, see the
Leopard Gecko Family.
Corrected operating voltage from 1.8 V to 1.85 V.
Added rising POR level to Electrical Characteristics section.
Updated Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup.
Added Gain error drift and Offset error drift to ADC table.
Added Opamp pinout overview.
Added reference to errata document.
Corrected TQFP64 package drawing.
Updated PCB land pattern, solder mask and stencil design.
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A Disclaimer and Trademarks
A.1 Disclaimer
Energy Micro AS intends to provide customers with the latest, accurate, and in-depth documentation of
all peripherals and modules available for system and software implementers using or intending to use
the Energy Micro products. Characterization data, available modules and peripherals, memory sizes and
memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in
different applications. Application examples described herein are for illustrative purposes only. Energy
Micro reserves the right to make changes without further notice and limitation to product information,
specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness
of the included information. Energy Micro shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder
to design or fabricate any integrated circuits. The products must not be used within any Life Support
System without the specific written consent of Energy Micro. A "Life Support System" is any product or
system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Energy Micro products are generally not intended for
military applications. Energy Micro products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable
of delivering such weapons.
A.2 Trademark Information
Energy Micro, EFM32, EFR, logo and combinations thereof, and others are the registered trademarks or
trademarks of Energy Micro AS. ARM, CORTEX, THUMB are the registered trademarks of ARM Limited.
Other terms and product names may be trademarks of others.
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B Contact Information
B.1 Energy Micro Corporate Headquarters
Postal Address
Visitor Address
Technical Support
Energy Micro AS
P.O. Box 4633 Nydalen
N-0405 Oslo
NORWAY
Energy Micro AS
Sandakerveien 118
N-0484 Oslo
NORWAY
support.energymicro.com
Phone: +47 40 10 03 01
www.energymicro.com
Phone: +47 23 00 98 00
Fax: + 47 23 00 98 01
B.2 Global Contacts
Visit www.energymicro.com for information on global distributors and representatives or contact
[email protected] for additional information.
Americas
Europe, Middle East and Africa Asia and Pacific
www.energymicro.com/americas www.energymicro.com/emea
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 7
2.3. Memory Map ................................................................................................................................. 8
3. Electrical Characteristics ........................................................................................................................... 10
3.1. Test Conditions ............................................................................................................................. 10
3.2. Absolute Maximum Ratings ............................................................................................................. 10
3.3. General Operating Conditions .......................................................................................................... 10
3.4. Current Consumption ..................................................................................................................... 12
3.5. Transition between Energy Modes .................................................................................................... 13
3.6. Power Management ....................................................................................................................... 13
3.7. Flash .......................................................................................................................................... 14
3.8. General Purpose Input Output ......................................................................................................... 15
3.9. Oscillators .................................................................................................................................... 22
3.10. Analog Digital Converter (ADC) ...................................................................................................... 26
3.11. Digital Analog Converter (DAC) ...................................................................................................... 36
3.12. Operational Amplifier (OPAMP) ...................................................................................................... 37
3.13. Analog Comparator (ACMP) .......................................................................................................... 41
3.14. Voltage Comparator (VCMP) ......................................................................................................... 43
3.15. LCD .......................................................................................................................................... 44
3.16. Digital Peripherals ....................................................................................................................... 44
4. Pinout and Package ................................................................................................................................. 46
4.1. Pinout ......................................................................................................................................... 46
4.2. Alternate functionality pinout ............................................................................................................ 49
4.3. GPIO pinout overview .................................................................................................................... 53
4.4. Opamp pinout overview .................................................................................................................. 54
4.5. TQFP64 Package .......................................................................................................................... 55
5. PCB Layout and Soldering ........................................................................................................................ 57
5.1. Recommended PCB Layout ............................................................................................................ 57
5.2. Soldering Information ..................................................................................................................... 59
6. Chip Marking, Revision and Errata ............................................................................................................ 60
6.1. Chip Marking ................................................................................................................................ 60
6.2. Revision ...................................................................................................................................... 60
6.3. Errata ......................................................................................................................................... 60
7. Revision History ...................................................................................................................................... 61
7.1. Revision 1.00 ............................................................................................................................... 61
7.2. Revision 0.98 ............................................................................................................................... 61
7.3. Revision 0.96 ............................................................................................................................... 61
7.4. Revision 0.95 ............................................................................................................................... 61
A. Disclaimer and Trademarks ....................................................................................................................... 62
A.1. Disclaimer ................................................................................................................................... 62
A.2. Trademark Information ................................................................................................................... 62
B. Contact Information ................................................................................................................................. 63
B.1. Energy Micro Corporate Headquarters .............................................................................................. 63
B.2. Global Contacts ............................................................................................................................ 63
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32GG942 Memory Map with largest RAM and Flash sizes ........................................................................ 9
3.1. Typical Low-Level Output Current, 2V Supply Voltage .................................................................................. 16
3.2. Typical High-Level Output Current, 2V Supply Voltage ................................................................................. 17
3.3. Typical Low-Level Output Current, 3V Supply Voltage .................................................................................. 18
3.4. Typical High-Level Output Current, 3V Supply Voltage ................................................................................. 19
3.5. Typical Low-Level Output Current, 3.8V Supply Voltage ............................................................................... 20
3.6. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................... 21
3.7. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup ..................................................... 22
3.8. Calibrated LFRCO Frequency vs Temperature and Supply Voltage ................................................................ 24
3.9. Calibrated HFRCO 11 MHz Band Frequency vs Temperature and Supply Voltage ............................................ 25
3.10. Calibrated HFRCO 14 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 25
3.11. Calibrated HFRCO 21 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 25
3.12. Calibrated HFRCO 28 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 26
3.13. Integral Non-Linearity (INL) ................................................................................................................... 30
3.14. Differential Non-Linearity (DNL) .............................................................................................................. 31
3.15. ADC Frequency Spectrum, Vdd = 3V, Temp = 25° ................................................................................... 32
3.16. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25° ..................................................................... 33
3.17. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25° ................................................................. 34
3.18. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 35
3.19. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 35
3.20. ADC Temperature sensor readout ......................................................................................................... 36
3.21. OPAMP Common Mode Rejection Ratio ................................................................................................. 39
3.22. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 39
3.23. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 40
3.24. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V ..................................................................... 40
3.25. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 40
3.26. Typical ACMP Characteristics ............................................................................................................... 42
4.1. EFM32GG942 Pinout (top view, not to scale) ............................................................................................. 46
4.2. Opamp Pinout ...................................................................................................................................... 54
4.3. LQFP64 .............................................................................................................................................. 55
5.1. TQFP64 PCB Land Pattern ..................................................................................................................... 57
5.2. TQFP64 PCB Solder Mask ..................................................................................................................... 58
5.3. TQFP64 PCB Stencil Design ................................................................................................................... 59
6.1. Example Chip Marking ........................................................................................................................... 60
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 7
3.1. Absolute Maximum Ratings ..................................................................................................................... 10
3.2. General Operating Conditions .................................................................................................................. 10
3.3. Environmental ....................................................................................................................................... 11
3.4. Current Consumption ............................................................................................................................. 12
3.5. Energy Modes Transitions ...................................................................................................................... 13
3.6. Power Management ............................................................................................................................... 13
3.7. Flash .................................................................................................................................................. 14
3.8. GPIO .................................................................................................................................................. 15
3.9. LFXO .................................................................................................................................................. 22
3.10. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup ................................................... 23
3.11. HFXO ................................................................................................................................................ 23
3.12. LFRCO .............................................................................................................................................. 23
3.13. HFRCO ............................................................................................................................................. 24
3.14. ULFRCO ............................................................................................................................................ 26
3.15. ADC .................................................................................................................................................. 26
3.16. DAC .................................................................................................................................................. 36
3.17. OPAMP ............................................................................................................................................. 37
3.18. ACMP ............................................................................................................................................... 41
3.19. VCMP ............................................................................................................................................... 43
3.20. LCD .................................................................................................................................................. 44
3.21. Digital Peripherals ............................................................................................................................... 44
4.1. Device Pinout ....................................................................................................................................... 46
4.2. Alternate functionality overview ................................................................................................................ 49
4.3. GPIO Pinout ........................................................................................................................................ 54
4.4. QFP64 (Dimensions in mm) .................................................................................................................... 55
5.1. QFP64 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 57
5.2. QFP64 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 58
5.3. QFP64 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 59
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 41
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 43
3.3. Total LCD Current Based on Operational Mode and Internal Boost ................................................................. 44
2012-09-11 - EFM32GG942FXX - d0128_Rev1.00
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