IDT IDT74FCT821ADB High-performance cmos bus interface register Datasheet


IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full temperature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FAST speed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT824
IDT54/74FCT821/823/825
D0
D0
DN
EN
EN
CLR
CLR
D
CL
Q
D
CP Q
CL
Q
D
CP Q
CP
OE
OE
Y0
YN
2608 cnv* 01
Q
D
CL
Q
CP Q
Y0
YN
2608 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1992 Integrated Device Technology, Inc.
CL
CP Q
CP
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
DN
7.19
MAY 1992
DSC-4618/2
1
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LOGIC SYMBOLS
IDT54/74FCT821 10-BIT REGISTER
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
CP
INDEX
D2
D3
D4
NC
D5
D6
D7
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
20
10
19
11
1213 14 15 16 17 18
10
Y2
Y3
Y4
NC
Y5
Y6
Y7
D
10
D
Q
Y
CP
CP
OE
D8
D9
GND
NC
CP
Y9
Y8
24
23
22
21
20
19
18
17
16
15
14
13
D1
D0
OE
NC
VCC
Y0
Y1
1
2
3
4 P24-1
5 D24-1
6 E24-1
&
7
SO24-2
8
9
10
11
12
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv* 03
1
2
3
4 P24-1
5 D24-1
6 SO24-2
&
7
E24-1
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CP
INDEX
D2
D3
D4
NC
D5
D6
D7
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
Y2
Y3
Y4
NC
Y5
Y6
Y7
D
9
D
9
Q
CP EN CLR
Y
CP
EN
CLR
OE
D8
CLR
GND
NC
CP
EN
Y8
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
D1
D0
OE
NC
VCC
Y0
Y1
IDT54/74FCT823/824 9-BIT REGISTERS
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv* 04
24
23
22
21
20
19
18
17
16
15
14
13
VCC
OE3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
EN
CP
INDEX
D
4 3 2
D1
D2
D3
NC
D4
D5
D6
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
7.19
Y1
Y2
Y3
NC
Y4
Y5
Y6
8
D
Q
CP EN CLR
8
Y
CP
EN
CLR
OE1
OE2
OE3
EN
Y7
CLR
GND
1
2
3
4 P24-1
5 D24-1
6 E24-1
&
7
8 SO24-2
9
10
11
12
D7
CLR
GND
NC
CP
OE1
OE2
D0
D1
D2
D3
D4
D5
D6
D7
D0
OE2
OE1
NC
VCC
OE3
Y0
IDT54/74FCT825 8-BIT REGISTER
2608 cnv* 05
2
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
IDT54/74FCT821/823/825
PRODUCT SELECTOR GUIDE
Device
10-Bit
Non-inverting
9-Bit
Inputs
8-Bit
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
Inverting
54/74FCT824A/B/C
2608 tbl 01
PIN DESCRIPTION
Name
DI
I/O
CLR
I
I
CP
I
YI , YI
O
EN
I
OE
I
Description
The D flip-flop data inputs.
For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the QI outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition.
The register three-state outputs.
Internal/
Outputs
QI
YI
OE
CLR
EN
DI
CP
H
H
H
H
L
L
L
H
↑
↑
L
H
Z
Z
H
L
H
L
H
H
L
L
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
↑
↑
↑
L
L
NC
NC
L
H
L
H
Z
L
Z
NC
Z
Z
L
H
Function
High Z
Clear
Hold
Load
NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-HIGH
Transition, Z = High Impedance
FUNCTION TABLE(1)
IDT54/74FCT824
Clock Enable. When the clock enable
is LOW, data on the D I input is
transferred to the QI output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the QI
outputs do not change state,
regardless of the data or clock input
transitions.
Output Control. When the OE input is
HIGH, the Y I outputs are in the high
impedance state. When the OE input is
LOW, the TRUE register data is
present at the Y I outputs.
Inputs
2608 tbl 10
Internal/
Outputs
QI
YI
OE
CLR
EN
DI
CP
H
H
H
H
L
L
L
H
↑
↑
H
L
Z
Z
H
L
H
L
H
H
L
L
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
↑
↑
↑
L
L
NC
NC
H
L
H
L
Z
L
Z
NC
Z
Z
H
L
Function
High Z
Clear
Hold
Load
NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-toHIGH Transition, Z = High Impedance
7.19
3
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
–0.5 to +7.0
VTERM (2) Terminal Voltage
with Respect to
GND
VTERM (3) Terminal Voltage
–0.5 to VCC
with Respect to
GND
TA
Operating
0 to +70
Temperature
TBIAS
Temperature
–55 to +125
Under Bias
TSTG
Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
IOUT
DC Output
Current
120
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
–0.5 to +7.0
Unit
V
–0.5 to VCC
V
–55 to +125
°C
–65 to +135
°C
–65 to +150
°C
0.5
W
120
mA
Symbol
CIN
COUT
Parameter(1)
Input
Capacitance
Output
Capacitance
Conditions
VIN = 0V
Typ.
6
Max.
10
Unit
VOUT = 0V
8
12
pF
pF
NOTE:
2608 tbl 05
1. This parameter is measured at characterization but not tested.
NOTES:
2608 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current
Symbol
VIH
II L
IOZH
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
5
µA
VI = VCC
Input LOW Current
Off State (High Impedance)
VCC = Max.
Output Current
IOZL
VI = 2.7V
—
—
5(4)
VI = 0.5V
—
—
–5(4)
VI = GND
—
—
–5
VO = VCC
—
—
10
VO = 2.7V
—
—
10(4)
VO = 0.5V
—
—
–10(4)
VO = GND
VIK
Clamp Diode Voltage
VCC = Min., IN = –18mA
Max.(3) ,
IOS
Short Circuit Current
VCC =
VOH
Output HIGH Voltage
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VOL
Output LOW Voltage
VO = GND
—
—
–10
—
–0.7
–1.2
V
–75
–120
—
mA
V
VHC
VCC
—
VCC = Min.
IOH = –300µA
VHC
VCC
—
VIN = VIH or VIL
IOH = –15mA MIL.
2.4
4.3
—
IOH = –24mA COM'L.
2.4
4.3
—
—
GND
VLC
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min.
IOL = 300µA
—
GND
VLC(4)
VIN = VIH or VIL
IOL = 32mA MIL.
—
0.3
0.5
IOL = 48mA COM'L.
—
0.3
0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.19
µA
V
2608 tbl 06
4
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
ICC
∆ICC
ICCD
IC
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current (6)
Test Conditions(1)
VCC = Max.
VIN ≥ VHC; V IN ≤ V LC
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
OE = EN = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = EN = GND
One Bit Toggling
at f i = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = EN = GND
Eight Bits Toggling
at f i = 2.5MHz
50% Duty Cycle
Min.
Typ.(2)
Max.
Unit
—
0.2
1.5
mA
—
0.5
2.0
mA
VIN ≥ VHC
VIN ≤ VLC
—
0.15
0.25
mA/
MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
1.7
4.0
mA
VIN = 3.4V
VIN = GND
—
2.2
6.0
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
4.0
7.8 (5)
VIN = 3.4V
VIN = GND
—
6.2
16.8 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.19
2608 tbl 07
5
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Test
Parameter
tPLH
tPHL
Description
Propagation Delay
CP to Y I (OE = LOW)
tSU
Set-up Time HIGH or LOW
D i to CP
tH
Hold Time HIGH or LOW
D I to CP
tSU
Set-up Time HIGH or LOW
EN
Conditions (1)
CL = 50pF
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 50pF
RL = 500Ω
to CP
IDT54/74FCT821A/
823A/824A/825A
IDT54/74FCT821B/
823B/824B/825B
IDT54/74FCT821C/
823C/824C/825C
Com'l.
Com'l.
Com'l.
(2)
Min.
Mil.
(2)
(2)
Mil.
(2)
(2)
Max. Min.
Max. Min.
Max. Min.
Max. Min.
—
10.0
—
11.5
—
7.5
—
8.5
—
6.0
—
20.0
—
20.0
—
15.0
—
16.0
—
4.0
—
4.0
—
3.0
—
3.0
—
2.0
—
2.0
—
1.5
—
1.5
4.0
—
4.0
—
3.0
—
Mil.
Max. Min.
(2)
Max.
Unit
—
7.0
ns
12.5
—
13.5
3.0
—
3.0
—
ns
—
1.5
—
1.5
—
ns
3.0
—
3.0
—
3.0
—
ns
tH
Hold Time HIGH or LOW
EN to CP
2.0
—
2.0
—
0
—
0
—
0
—
0
—
ns
tPHL
Propagation Delay, CLR to
YI
—
14.0
—
15.0
—
9.0
—
9.5
—
8.0
—
8.5
ns
tREM
Recovery Time CLR to CP
6.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
tW
CP Pulse Width
HIGH or LOW
7.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
Pulse Width
LOW
6.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
—
12.0
—
13.0
—
8.0
—
9.0
—
7.0
—
8.0
ns
—
23.0
—
25.0
—
15.0
—
16.0
—
12.5
—
13.5
—
7.0
—
8.0
—
6.5
—
7.0
—
6.2
—
6.2
—
8.0
—
9.0
—
7.5
—
8.0
—
6.5
—
6.5
tW
CLR
tPZH
tPZL
to YI
tPHZ
tPLZ
Output Enable Time OE
Output Disable Time OE
to YI
CL = 50pF
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 5pF(3)
RL = 500Ω
CL = 50pF
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
ns
2608 tbl* 08
7.19
6
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
SET-UP, HOLD AND RELEASE TIMES
Closed
All Other Tests
Open
3V
1.5V
0V
tH
TIMING
INPUT
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
tW
t REM
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
Open Drain
Disable Low
Enable Low
PULSE WIDTH
DATA
INPUT
ASYNCHRONOUS CONTROL
Switch
DEFINITIONS:
2608 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
t SU
Test
t SU
1.5V
3V
1.5V
0V
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
1.5V
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
CONTROL
INPUT
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
VOL
t PLH
t PHL
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
t PLZ
t PZL
0V
VOH
1.5V
OUTPUT
1.5V
3.5V
1.5V
3.5V
0.3V
V OL
t PHZ
0.3V
1.5V
0V
V OH
0V
0V
NOTES
2608 drw 01
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.19
7
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
2523IDTcnv*XX11
Temp. Range
FCT
XXXX
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
E
L
SO
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
821A
821B
821C
823A
823B
823C
824A
824B
824C
825A
825B
825C
10-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
Super Fast 10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
Super Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
Super Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
Super Fast 8-Bit Non-Inverting Register
54
74
–55°C to +125°C
0°C to +70°C
2608 cnv* 11
7.19
8
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