Cypress CY7C1386D-250BGC 18-mbit (512k x 36/1 mbit x 18) pipelined dcd sync sram Datasheet

PRELIMINARY
CY7C1386D
CY7C1387D
18-Mbit (512K x 36/1 Mbit x 18) Pipelined
DCD Sync SRAM
Functional Description[1]
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP,
119-ball BGA and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
The CY7C1386D/CY7C1387D SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BWX, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing system performance.
The CY7C1386D/CY7C1387D operates from a +3.3V core
power supply while all outputs operate with a +3.3V or a +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
• “ZZ” Sleep Mode Option
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.0
3.4
ns
Maximum Operating Current
350
300
275
mA
Maximum CMOS Standby Current
70
70
70
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE3 and CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.
Cypress Semiconductor Corporation
Document #: 38-05545 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 3, 2004
PRELIMINARY
CY7C1386D
CY7C1387D
1
Logic Block Diagram – CY7C1386D (512K x 36)
ADDRESS
REGISTER
A0,A1,A
2 A[1:0]
MODE
ADV
CLK
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWD
DQD,DQPD
BYTE
WRITE REGISTER
DQD,DQPD
BYTE
WRITE DRIVER
BWC
DQc,DQPC
BYTE
WRITE REGISTER
DQc,DQPC
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE REGISTER
DQB,DQPB
BYTE
WRITE DRIVER
BWB
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
E
DQA,DQPA
BYTE
WRITE DRIVER
DQA,DQPA
BYTE
WRITE REGISTER
BWA
BWE
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
ZZ
CONTROL
2
Logic Block Diagram – CY7C1387D (1M x 18)
A0, A1, A
ADDRESS
REGISTER
2
MODE
ADV
CLK
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
DQB , DQPB
BYTE
WRITE DRIVER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE DRIVER
DQA , DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs,
DQPA
DQPB
E
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05545 Rev. *A
Page 2 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Pin Configurations
NC
NC
NC
CY7C1387D
(1M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05545 Rev. *A
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC / 72M
NC / 36M
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1386D
(512K X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC / 72M
NC / 36M
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout (3 Chip Enables)
Page 3 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
1
CY7C1386D (512K x 36)
3
4
5
A
A
ADSP
A
VDDQ
2
A
B
C
NC
NC
A
A
A
ADSC
VDD
A
A
A
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
A
GW
VDD
CLK
NC
6
A
7
VDDQ
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
BWE
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
CY7C1387D (1M x 18)
1
2
3
4
5
6
7
A
VDDQ
A
ADSP
A
A
VDDQ
B
NC
A
A
A
A
NC
NC
A
A
ADSC
VDD
A
C
A
A
NC
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
OE
ADV
VSS
DQA
VDDQ
GW
VDD
NC
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
CLK
VSS
NC
DQA
NC
BWA
VSS
DQA
NC
NC
VDDQ
F
VDDQ
NC
VSS
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
K
NC
DQB
VSS
L
M
DQB
VDDQ
NC
DQB
NC
VSS
N
DQB
NC
VSS
BWE
A1
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05545 Rev. *A
Page 4 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1386D (512K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
R
NC
A
CE2
BWD
BWA
CLK
GW
A
NC / 144M
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
ADSP
DQPC
DQC
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
7
8
9
10
11
A
CY7C1387D (1M x 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
3
4
5
6
NC
CE3
A
CE1
CE2
BWB
NC
NC
BWA
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VDDQ
NC
DQB
VDDQ
NC
DQB
VDDQ
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
DQB
NC
DQB
DQB
DQPB
R
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC
NC
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
VDD
VDD
VDD
VSS
VSS
‘VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05545 Rev. *A
A
NC / 144M
DQPA
DQA
Page 5 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Pin Definitions
Name
I/O
Description
A0, A1, A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]
are sampled active. A1: A0 are fed to the two-bit counter..
BWA, BWB
BWC, BWD
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BWX and BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if
CE1 is HIGH. CE1 is sampled only when a new external address is loaded.
CE2[2]
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only
when a new external address is loaded.
CE3[2]
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.Not connected for BGA.
Where referenced, CE3[2] is assumed active throughout this document for BGA.
CE3 is sampled only when a new external address is loaded.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ
pins are tri-stated, and act as input data pins. OE is masked during the first clock of
a read cycle when emerging from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
InputAsynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPX
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are
placed in a tri-state condition.
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
Ground
VSSQ
I/O Ground
Document #: 38-05545 Rev. *A
Ground for the core of the device.
Ground for the I/O circuitry.
Page 6 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Pin Definitions (continued)
Name
I/O
Description
VDDQ
I/O Power Supply
MODE
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be disconnected. This pin is
not available on TQFP packages.
TDI
JTAG serial
input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TMS
JTAG serial
input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
JTAGClock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
–
Document #: 38-05545 Rev. *A
Power supply for the I/O circuitry.
No Connects. Not internally connected to the die
Page 7 of 30
PRELIMINARY
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1386D/CY7C1387D supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE1, CE2, CE3[2] and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
The CY7C1386D/CY7C1387D is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will tri-state
immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
Document #: 38-05545 Rev. *A
CY7C1386D
CY7C1387D
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BWX
signals. The CY7C1386D/CY7C1387D provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1386D/CY7C1387D is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BWX) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1386D/CY7C1387D is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQX inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1386D/CY7C1387DCY7C1387D provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Page 8 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Sleep Mode
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW..
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
2tCYC
ns
2tCYC
ns
0
ns
Truth Table [ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
ADV
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
L-H
Tri-State
None
X
X
X
H
X
X
X
X
X
X
Tri-State
External
L
H
L
L
L
X
X
X
L
L-H
Q
Sleep Mode, Power Down
Read Cycle, Begin Burst
WRITE OE CLK
DQ
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05545 Rev. *A
Page 9 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Truth Table (continued)[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
ADV
WRITE OE CLK
DQ
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Partial Truth Table for Read/Write[5, 9]
GW
BWE
BWD
BWC
BWB
BWA
Read
Function (CY7C1386D)
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
H
H
L
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write[5, 9]
GW
BWE
BWB
BWA
Read
Function (CY7C1387D)
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
L
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document #: 38-05545 Rev. *A
Page 10 of 30
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
CY7C1386D
CY7C1387D
Test Mode Select (TMS)
The CY7C1386D/CY7C1387D incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1386D/CY7C1387D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
2 1 0
1
TEST-LOGIC
RESET
TDI
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
31 30 29 . . . 2 1 0
1
Selection
Circuitry
TDO
Identification Register
x . . . . . 2 1 0
CAPTURE-IR
Boundary Scan Register
0
SHIFT-DR
0
SHIFT-IR
1
0
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
TMS
TAP CONTROLLER
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
Performing a TAP Reset
EXIT2-IR
1
1
UPDATE-DR
1
Instruction Register
0
0
0
Selection
Circuitry
0
UPDATE-IR
1
0
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05545 Rev. *A
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Page 11 of 30
PRELIMINARY
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Document #: 38-05545 Rev. *A
CY7C1386D
CY7C1387D
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Page 12 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
BYPASS
Reserved
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
25
ns
tTL
TCK Clock LOW time
25
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
5
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
tTMSH
TMS hold after TCK Clock Rise
5
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
ns
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05545 Rev. *A
Page 13 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... .VSS to 3.3V
Input pulse levels................................................ .VSS to 2.5V
Input rise and fall times .................................................. 1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels......................................... 1.25V
Output reference levels...................................................1.5V
Output reference levels ................................................ 1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –4.0 mA, VDDQ = 3.3V
2.4
V
IOH = –1.0 mA, VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
VOL1
Output LOW Voltage
IOL = 8.0 mA, VDDQ = 3.3V
IOL = 8.0 mA, VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
VIL
Input LOW Voltage
VDDQ = 2.5V
IX
Input Load Current
GND < VIN < VDDQ
V
0.4
VDDQ = 3.3V
VDDQ = 2.5V
V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.5
0.7
V
–0.3
0.7
V
–5
5
µA
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05545 Rev. *A
Page 14 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Identification Register Definitions
Instruction Field
Revision Number (31:29)
[13]
CY7C1386D
CY7C1387D
000
000
Description
Describes the version number
01011
01011
Reserved for internal use
Device Width (23:18)
000110
000110
Defines memory type and architecture
Cypress Device ID (17:12)
100101
010101
Defines width and density
00000110100
00000110100
1
1
Device Depth (28:24)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Instruction
Bit Size (x18)
Bit Size (x36)
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball fBGA package)
89
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
13. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05545 Rev. *A
Page 15 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
119-Ball BGA Boundary Scan Order [14, 15]
Bit#
1
2
CY7C1386D (256K x 36)
Ball ID
Bit#
44
H4
T4
45
Ball ID
E4
G4
Bit#
1
2
CY7C1387D (512K x 18)
Ball ID
Bit#
44
H4
T4
45
Ball ID
E4
G4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
G1
H2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
G1
H2
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M4
A5
K4
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
E2
G2
H1
J3
K2
L1
M2
N1
P1
K1
L2
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
Internal
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M4
A5
K4
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
E2
G2
H1
J3
K2
L1
M2
N1
P1
K1
L2
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
Internal
Notes:
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 85 is pre-set HIGH.
Document #: 38-05545 Rev. *A
Page 16 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
165-Ball BGA Boundary Scan Order [14, 16]
CY7C1386D (256K x36)
Bit#
Ball ID
Bit#
1
N6
37
2
N7
38
3
10N
39
4
P11
40
CY7C1386D (256K x36)
Ball ID
Bit#
Ball ID
A9
73
K2
B9
74
L2
C10
75
M2
A8
76
N1
5
P8
41
B8
77
N2
6
R8
42
A7
78
P1
7
R9
43
B7
79
R1
8
P9
44
B6
80
R2
9
P10
45
A6
81
P3
10
R10
46
B5
82
R3
11
R11
47
A5
83
P2
12
H11
48
A4
84
R4
13
N11
49
B4
85
P4
14
M11
50
B3
86
N5
15
L11
51
A3
87
P6
16
K11
52
A2
88
R6
17
J11
53
B2
89
Internal
18
M10
54
C2
19
L10
55
B1
20
K10
56
A1
21
J10
57
C1
22
H9
58
D1
23
H10
59
E1
24
G11
60
F1
25
F11
61
G1
26
E11
62
D2
27
D11
63
E2
28
G10
64
F2
29
F10
65
G2
30
E10
66
H1
31
D10
67
H3
32
C11
68
J1
33
A11
69
K1
34
B11
70
L1
35
A10
71
M1
36
B10
72
J2
Note:
16. Bit# 89 is pre-set HIGH.
Document #: 38-05545 Rev. *A
Page 17 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
165-Ball BGA Boundary Scan Order [14, 16]
CY7C1387D (512K x 18)
CY7C1387D (512K x 18)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
N6
37
A9
73
K2
2
N7
38
B9
74
L2
3
10N
39
C10
75
M2
4
P11
40
A8
76
N1
5
P8
41
B8
77
N2
6
R8
42
A7
78
P1
7
R9
43
B7
79
R1
8
P9
44
B6
80
R2
9
P10
45
A6
81
P3
10
R10
46
B5
82
R3
11
R11
47
A5
83
P2
12
H11
48
A4
84
R4
13
N11
49
B4
85
P4
14
M11
50
B3
86
N5
15
L11
51
A3
87
P6
16
K11
52
A2
88
R6
17
J11
53
B2
89
Internal
18
M10
54
C2
19
L10
55
B1
20
K10
56
A1
21
J10
57
C1
22
H9
58
D1
23
H10
59
E1
24
G11
60
F1
25
F11
61
G1
26
E11
62
D2
27
D11
63
E2
28
G10
64
F2
29
F10
65
G2
30
E10
66
H1
31
D10
67
H3
32
C11
68
J1
33
A11
69
K1
34
B11
70
L1
35
A10
71
M1
36
B10
72
J2
Document #: 38-05545 Rev. *A
Page 18 of 30
PRELIMINARY
Maximum Ratings
CY7C1386D
CY7C1387D
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.......................................... –55°C to +125Q°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Range
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [17, 18]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[17]
VIL
Input LOW Voltage[17]
IX
Input Load Current
except ZZ and MODE
Test Conditions
Min.
3.135
3.6
V
3.135
VDD
V
VDDQ = 2.5V
2.375
2.625
V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
V
V
0.4
V
0.4
V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
VDDQ = 3.3V
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
30
Input = VSS
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
µA
µA
–30
5
µA
5
µA
4.0-ns cycle, 250 MHz
350
mA
5-ns cycle, 200 MHz
300
mA
6-ns cycle, 167 MHz
275
mA
4.0-ns cycle, 250 MHz
160
mA
5.0-ns cycle, 200 MHz
150
mA
6.0-ns cycle, 167 MHz
140
mA
All speeds
70
mA
Input = VDD
IOZ
µA
–5
Input = VDD
ISB1
Unit
VDDQ = 3.3V
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
Input Current of ZZ
Max.
–5
ISB2
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
135
mA
130
mA
125
mA
Automatic CE
Power-down
Current—TTL Inputs
80
mA
ISB4
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All Speeds
Shaded areas contain advance information.
Notes:
17. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
18. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD\
Document #: 38-05545 Rev. *A
Page 19 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Thermal Resistance[19]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
TQFP
Package
BGA
Package
fBGA
Package
Unit
31
45
46
°C/W
6
7
3
°C/W
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
Capacitance[19]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP
Package
BGA
Package
fBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
OUTPUT
RL = 50Ω
Z0 = 50Ω
(c)
ALL INPUT PULSES
VDDQ
GND
5 pF
R = 1538Ω
VT = 1.25V
INCLUDING
JIG AND
SCOPE
(a)
≤ 1 ns
(b)
R = 1667Ω
2.5V
OUTPUT
90%
10%
90%
10%
≤ 1 ns
VT = 1.5V
(a)
ALL INPUT PULSES
VDDQ
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
(b)
Switching Characteristics Over the Operating Range[24, 25]
250 MHz
Parameter
tPOWER
Description
VDD(Typical) to the First Access[20]
Min.
Max.
200 MHz
Min.
Max.
167 MHz
Min.
Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
ns
tCH
Clock HIGH
1.7
2.0
2.2
ns
tCL
Clock LOW
1.7
2.0
2.2
ns
Output Times
tCO
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
1.0
1.3
1.3
ns
tCLZ
Clock to Low-Z[21, 22, 23]
1.0
1.3
1.3
ns
2.6
3.0
3.4
ns
Note:
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05545 Rev. *A
Page 20 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Switching Characteristics Over the Operating Range[24, 25]
250 MHz
Parameter
Description
Min.
Max.
tCHZ
[21, 22, 23]
Clock to High-Z
2.6
tOEV
OE LOW to Output Valid
2.6
Low-Z[21, 22, 23]
tOELZ
OE LOW to Output
tOEHZ
OE HIGH to Output High-Z[21, 22, 23]
0
200 MHz
Min.
Unit
3.0
3.4
ns
3.0
3.4
ns
0
2.6
167 MHz
Max.
Max.
Min.
0
3.0
ns
3.4
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.4
1.5
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Enable Set-Up Before CLK Rise
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.4
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
Shaded areas contain advance information.
Notes:
20. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
23. This parameter is sampled and not 100% tested.
24. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05545 Rev. *A
Page 21 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Switching Waveforms
Read Cycle Timing[26]
tCYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,BW
X
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
High-Z
CLZ
t OEHZ
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note:
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05545 Rev. *A
Page 22 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Switching Waveforms (continued)
Write Cycle Timing[26, 27]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
DS
Data in (D)
High-Z
t
OEHZ
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05545 Rev. *A
Page 23 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Switching Waveforms (continued)
Read/Write Cycle Timing[26, 28, 29]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE, BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
Data In (D)
tOELZ
High-Z
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Q(A4+2)
BURST READ
Single WRITE
DON’T CARE
Q(A4+1)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
Document #: 38-05545 Rev. *A
Page 24 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Switching Waveforms (continued)
ZZ Mode Timing [30, 31]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
250
200
Ordering Code
Package
Name
Part and Package Type
CY7C1386D-250AXC
CY7C1387D-250AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1386D-250BGC
CY7C1387D-250BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG
CY7C1386D-250BZC
CY7C1387D-250BZC
BB165D
CY7C1386D-250BGXC
CY7C1387D-250BGXC
BG119
CY7C1386D-250BZXC
CY7C1387D-250BZXC
BB165D
CY7C1386D-200AXC
A101
CY7C1387D-200AXC
Commercial
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables with JTAG
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables
with JTAG
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables with JTAG
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1386D-200AI
CY7C1387D-200AI
CY7C1386D-200BGC
Operating
Range
Commercial
Industrial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG
Commercial
CY7C1387D-200BGC
CY7C1386D-200BGI
Industrial
CY7C1387D-200BGI
CY7C1386D-200BZC
CY7C1387D-200BZC
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables with JTAG
CY7C1386D-200BZI
Commercial
Industrial
CY7C1387D-200BZI
Notes:
30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05545 Rev. *A
Page 25 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Ordering Information (continued)
Speed
(MHz)
Ordering Code
CY7C1386D-200BGXC
Package
Name
BG119
CY7C1387D-200BGXC
Part and Package Type
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables
with JTAG
CY7C1386D-200BGXI
Operating
Range
Commercial
Industrial
CY7C1387D-200BGXI
CY7C1386D-200BZXC
BB165D
CY7C1387D-200BZXC
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables with JTAG
CY7C1386D-200BZXI
Commercial
Industrial
CY7C1387D-200BZXI
167
CY7C1386D-167AXC
CY7C1387D-167AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1386D-167AXI
Commercial
Industrial
CY7C1387D-167AXI
CY7C1386D-167BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG
Commercial
CY7C1387D-167BGC
CY7C1386D-167BGI
Industrial
ICY7C1387D-167BGI
CY7C1386D-167BZC
BB165D
CY7C1387D-167BZC
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables with JTAG
CY7C1386D-167BZI
Commercial
Industrial
CY7C1387D-167BZI
CY7C1386D-167BGXC
BG119
CY7C1387D-167BGXC
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables
with JTAG
CY7C1386D-167BGXI
Commercial
Industrial
ICY7C1387D-167BGXI
CY7C1386D-167BZXC
CY7C1387D-167BZXC
CY7C1386D-167BZXI
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.2mm) 3 Chip Enables with JTAG
Commercial
Industrial
CY7C1387D-167BZXI
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG packages(Ordering Code:
BGX, BZX) will be available in 2005.
Document #: 38-05545 Rev. *A
Page 26 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
SEE DETAIL
50
0.20 MAX.
1.60 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
GAUGE PLANE
0.10
0° MIN.
0°-7°
A
51
31
R 0.08 MIN.
0.20 MAX.
12°±1°
(8X)
SEATING PLANE
R 0.08 MIN.
0.20 MAX.
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 38-05545 Rev. *A
A
51-85050-*A
Page 27 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05545 Rev. *A
Page 28 of 30
PRELIMINARY
CY7C1386D
CY7C1387D
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05545 Rev. *A
Page 29 of 30
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Similar pages