TI1 LP5912Q1.8DRVRQ1 Lp5912-q1 500-ma ultra-low-noise ldo for rf and analog circuits â requires no bypass capacitor Datasheet

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LP5912-Q1
SNVSAA8B – DECEMBER 2015 – REVISED JUNE 2016
LP5912-Q1 500-mA Ultra-Low-Noise LDO for RF and Analog Circuits –
Requires No Bypass Capacitor
1 Features
2 Applications
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Qualified for Automotive Applications
AEC Q100-Qualified With the Following Results
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM Classification Level 2
– Device CDM Classification Level C6
Input Voltage Range: 1.6 V to 6.5 V
Output Voltage Range: 0.8 V to 5.5 V
Output Current up to 500 mA
Low Output Voltage Noise: 12 µVRMS Typical
PSRR at 1 kHz: 75 dB Typical
Output Voltage Tolerance (VOUT ≥ 3.3 V): ±2%
Low IQ (Enabled, No Load): 30 µA Typical
Low Dropout (VOUT ≥ 3.3 V): 95 mV Typical at
500-mA Load
Stable With 1-µF Ceramic Input and Output
Capacitors
Thermal-Overload and Short-Circuit Protection
Reverse Current Protection
No Noise Bypass Capacitor Required
Output Automatic Discharge for Fast Turnoff
Power-Good Output With 140-µs Typical Delay
Internal Soft-Start to Limit the In-rush Current
–40°C to +125°C Operating Junction Temperature
Range
Camera Modules
Sensors
HiFi Audio Radio Transceivers
PLL/Synthesizer, Clocking
Medium-Current, Noise-Sensitive Applications
3 Description
The LP5912-Q1 is an LDO capable of supplying 500mA output current. Designed to meet the
requirements of RF and analog circuits, the LP5912Q1 device provides low noise, high PSRR, low
quiescent current, and low line and load transient
response. The LP5912-Q1 offers class-leading noise
performance without a noise bypass capacitor and
with the ability for remote output capacitance
placement.
The device is designed to work with a 1-µF input and
a 1-µF output ceramic capacitor (no separate noise
bypass capacitor required).
This device is available with fixed output voltages
from 0.8 V to 5.5 V in 25-mV steps. Contact Texas
Instruments Sales for specific voltage option needs.
Device Information(1)
PART NUMBER
LP5912-Q1
PACKAGE
WSON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the Package Option
Addendum (POA) at the end of this data sheet.
space
space
space
space
space
Simplified Schematic
VIN
IN
VOUT
OUT
LP5912-Q1
CIN
GND
COUT
NC
RPG
VEN
VPG
EN
PG
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5912-Q1
SNVSAA8B – DECEMBER 2015 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Voltage Options .....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Output and Input Capacitors .....................................
Typical Characteristics ..............................................
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 19
9
Applications and Implementation ...................... 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
Related Documentation .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2016) to Revision B
•
Page
Changed "linear regulator" to "LDO" on page 1 .................................................................................................................... 1
Changes from Original (December 2015) to Revision A
Page
•
Changed device from preview to production data ................................................................................................................. 1
•
Changed Block Diagram....................................................................................................................................................... 17
2
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SNVSAA8B – DECEMBER 2015 – REVISED JUNE 2016
5 Voltage Options
This device is capable of providing fixed output voltages from 0.8 V to 5.5 V in 25-mV steps. For all available
package and voltage options, see the POA at the end of this datasheet. Contact Texas Instruments Sales for
specific voltage option needs.
6 Pin Configuration and Functions
OUT
1
NC
2
PG
3
Thermal Pad
DRV Package
6-Pin WSON With Thermal Pad
Top View
6
IN
5
GND
4
EN
Pin Functions
PIN
NUMBER
NAME
I/O
DESCRIPTION
1
OUT
O
Regulated output voltage
2
NC
—
No internal connection. Leave open, or connect to ground.
3
PG
O
Power-good indicator. Requires external pullup.
4
EN
I
Enable input. Logic high = device is ON, logic low = device is OFF, with internal 3-MΩ
pulldown.
5
GND
G
Ground
6
IN
I
Unregulated input voltage
—
Exposed
thermal pad
—
Connect to copper area under the package to improve thermal performance. The use of
thermal vias to transfer heat to inner layers of the PCB is recommended. Connect the
thermal pad to ground, or leave floating. Do not connect the thermal pad to any potential
other than ground.
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SNVSAA8B – DECEMBER 2015 – REVISED JUNE 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN
Input voltage
–0.3
7
V
VOUT
Output voltage
–0.3
7
V
VEN
Enable input voltage
–0.3
7
V
VPG
Power Good (PG) pin OFF voltage
–0.3
7
V
TJ
Junction temperature
150
°C
PD
Continuous power dissipation (3)
Internally Limited
W
Tstg
Storage temperature
–65
°C
(1)
(2)
(3)
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the GND pin.
Internal thermal shutdown circuitry protects the device from permanent damage.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
Input supply voltage
1.6
6.5
V
VOUT
Output voltage
0.8
5.5
V
VEN
Enable input voltage
0
VIN
V
VPG
PG pin OFF voltage
0
6.5
V
IOUT
Output current
0
500
mA
TJ-MAX-OP
Operating junction temperature (2)
–40
125
°C
(1)
(2)
UNIT
All voltages are with respect to the GND pin.
TJ-MAX-OP = (TA(MAX) + (PD(MAX) × RθJA )).
7.4 Thermal Information
LP5912-Q1
THERMAL METRIC (1)
DRV (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance, High-K (2)
71.2 (3)
RθJC(top)
°C/W
Junction-to-case (top) thermal resistance
93.7
°C/W
RθJB
Junction-to-board thermal resistance
40.7
°C/W
ψJT
Junction-to-top characterization parameter
2.5
°C/W
ψJB
Junction-to-board characterization parameter
41.1
°C/W
ψJC(bot)
Junction-to-case (bottom) thermal resistance
11.2
°C/W
(1)
(2)
(3)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
The PCB for the WSON (DRV) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.
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7.5 Electrical Characteristics
VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise
stated). (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT VOLTAGE
For VOUT(NOM) ≥ 3.3 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA
For 1.1 V ≤ VOUT(NOM) < 3.3 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA
Output voltage tolerance
For VOUT(NOM) < 1.1 V:
1.6 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA
ΔVOUT
–2%
2%
–3%
3%
For VOUT(NOM) ≥ 1.1 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V
Line regulation
0.8
For VOUT(NOM) < 1.1 V:
1.6 V ≤ VIN ≤ 6.5 V
Load regulation
IOUT = 1 mA to 500 mA
%/V
0.0022
%/mA
CURRENT LEVELS
ISC
IRO
Reverse leakage current
IQ
Quiescent current (6)
IQ(SD)
Quiescent current,
shutdown mode (6)
IG
TJ = 25°C, see (4)
Short-circuit current limit
Ground current (7)
(5)
900
1100
mA
VIN < VOUT
700
10
150
µA
VEN = 1.3 V, IOUT = 0 mA
30
55
VEN = 1.3 V, IOUT = 500 mA
400
600
VEN = 0 V
–40°C ≤ TJ ≤ 85°C
0.2
1.5
VEN = 0 V
0.2
5
VEN = 1.3 V, IOUT = 0 mA
35
µA
µA
µA
VDO DROPOUT VOLTAGE
VDO
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Dropout voltage (8)
IOUT = 500 mA, 1.6 V ≤ VOUT(NOM) < 3.3 V
170
250
mV
IOUT = 500 mA, 3.3 V ≤ VOUT(NOM) ≤ 5.5 V
95
180
mV
All voltages are with respect to the device GND pin, unless otherwise stated.
Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of
–40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for
reference purposes only.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
Short-circuit current (ISC) is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with VOUT pulled to
100 mV below its nominal voltage.
Reverse current (IRO) is measured at the IN pin.
Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device (IQ + IEN).
Dropout voltage (VDO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its
nominal value when VIN = VOUT + 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with
the minimum operating voltage requirement cannot be assured.
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Electrical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise
stated).(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN to VOUT RIPPLE REJECTION
Power Supply Rejection
Ratio (9)
PSRR
ƒ = 100 Hz, VOUT ≥ 1.1 V, IOUT = 20 mA
80
ƒ = 1 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA
75
ƒ = 10 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA
65
ƒ = 100 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA
40
ƒ = 100 Hz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
65
ƒ = 1 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
65
ƒ = 10 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
65
ƒ = 100 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
40
IOUT = 1 mA, BW = 10 Hz to 100 kHz
12
IOUT = 500 mA, BW = 10 Hz to 100 kHz
12
dB
OUTPUT NOISE VOLTAGE
eN
Noise voltage
µVRMS
THERMAL SHUTDOWN
TSD
Thermal shutdown
temperature
160
°C
THYS
Thermal shutdown
hysteresis
15
°C
LOGIC INPUT THRESHOLDS
VEN(OFF)
OFF threshold
VIN = 1.6 V to 6.5 V
VEN falling until device is disabled
VEN(ON)
ON threshold
1.6 V ≤ VIN ≤ 6.5 V
VEN rising until device is enabled
IEN
Input current at EN pin (10)
PGHTH
PG high threshold (% of
nominal VOUT)
94%
PGLTH
PG low threshold (% of
nominal VOUT)
90%
VOL(PG)
PG pin low-level output
voltage
VOUT < PGLTH, sink current = 1 mA
IlKG(PG)
PG pin leakage current
VOUT < PGHTH, VPG = 6.5 V
tPGD
PG delay time
Time from VOUT > PG threshold to PG toggling
VEN = 6.5 V, VIN = 6.5 V
VEN = 0 V, VIN = 3.3 V
0.3
V
1.3
2.5
µA
0.001
140
100
mV
1
µA
µs
(9) This specification is ensured by design.
(10) There is a 3-MΩ pulldown resistor between the EN pin and GND pin on the device.
6
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Electrical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise
stated).(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSITION CHARACTERISTICS
For VIN ↑ and VOUT(NOM) ≥ 1.1 V:
VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1.1 V),
VIN trise = 30 µs
Line transients (9)
For VIN ↓ and VOUT(NOM) ≥ 1.1 V:
VIN = (VOUT(NOM) + 1.1 V) to (VOUT(NOM) + 0.5 V)
VIN tfall = 30 µs
ΔVOUT
For VIN ↓ and VOUT(NOM) < 1.1 V:
VIN = 2.2 V to 1.6 V
VIN tfall = 30 µs
IOUT = 5 mA to 500 mA
IOUT trise = 10 µs
Load transients (9)
tON
1
For VIN ↑ and VOUT(NOM) < 1.1 V:
VIN = 1.6 V to 2.2 V,
VIN trise = 30 µs
mV
–1
–45
mV
IOUT = 500 mA to 5 mA
IOUT tfall = 10 µs
45
Overshoot on start-up (9)
Stated as a percentage of VOUT(NOM)
Turnon time
From VEN > VEN(ON) to VOUT = 95% of VOUT(NOM)
200
µs
VEN = 0 V, VIN = 3.6 V
100
Ω
5%
OUTPUT AUTO DISCHARGE RATE
Output discharge pulldown
resistance
RAD
7.6 Output and Input Capacitors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(2)
CIN
Input capacitance
COUT
Output capacitance (2)
ESR
Output voltage (2)
(1)
(2)
TEST CONDITIONS
Capacitance for stability
MIN (1)
TYP
0.7
1
0.7
1
5
MAX
UNIT
µF
10
µF
500
mΩ
The minimum capacitance must be greater than 0.5 μF over full range of operating conditions. The capacitor tolerance must be 30% or
better over the full temperature range. The full range of operating conditions for the capacitor in the application must be considered
during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor
types X5R, Y5V, and Z5U may be used with consideration of the application conditions.
This specification is verified by design.
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7.7 Typical Characteristics
1.3
1.0
1.2
0.9
1.1
0.8
Output Voltage, VPG (V)
VEN Threshold (V)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
1.0
0.9
0.8
0.7
0.6
0.5
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VEN(ON)
VEN(OFF)
0.4
0.3
1.5
2.0
2.5
3.0
3.5 4.0 4.5 5.0
Input Voltage (V)
5.5
6.0
0.0
-0.1
0.0
6.5
Figure 1. VEN Thresholds vs Input Voltage
1.6
1.4
0.4
0.6
0.8 1.0 1.2 1.4
Input Voltage (V)
1.6
1.8
2.0
D002
Figure 2. LP5912-0.9 Output Voltage, VPG vs Input Voltage
3.5
VOUT at IOUT =1 mA
VPG at IOUT =1 mA
VOUT at IOUT = 500 mA
VPG at IOUT = 500 mA
VOUT at IOUT = 1mA
VPG at IOUT = 1mA
VOUT at IOUT = 500 mA
VPG at IOUT = 500mA
3.0
Output Voltage, VPG (V)
1.8
0.2
D001
2.0
Output Voltage, VPG (V)
VOUT at IOUT = 1mA
VPG at IOUT = 1mA
VOUT at IOUT = 500 mA
VPG at IOUT = 500 mA
1.2
1.0
0.8
0.6
0.4
2.5
2.0
1.5
1.0
0.5
0.2
0.0
-0.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Input Voltage (V)
D003
-0.5
0.0
Figure 3. LP5912-1.8 Output Voltage, VPG vs Input Voltage
Figure 4. LP5912-3.3 Output Voltage, VPG vs Input Voltage
2.0
2.0
1.8
1.8
1.6
1.6
1.4
1.4
Voltage (V)
Voltage (V)
0.0
1.2
1.0
0.8
0.6
0.5
1.5
2.0
2.5
Input Voltage (V)
3.0
3.5
4.0
D004
1.2
1.0
0.8
0.6
0.4
0.4
VIN
VOUT
VPG
0.2
VIN
VOUT
VPG
0.2
0.0
0.0
0
50
100
150
200 250 300
Time (Ps)
VIN = 0 V to 1.6 V
350
400
450
500
0
50
100
D005
IOUT = 1 mA
VIN = 0 V to 1.6 V
Figure 5. LP5912-0.9 Power Up
8
1.0
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150
200 250 300
Time (Ps)
350
400
450
500
D006
IOUT = 500 mA
Figure 6. LP5912-0.9 Power Up
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Typical Characteristics (continued)
3.0
3.0
2.5
2.5
2.0
2.0
Voltage (V)
Voltage (V)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
1.5
1.0
1.5
1.0
VIN
VOUT
VPG
0.5
VIN
VOUT
VPG
0.5
0.0
0.0
0
50
100
150
200 250 300
Time (Ps)
350
400
450
500
0
50
100
VIN = 0 V to 2.3 V
IOUT = 1 mA
350
400
450
500
D008
IOUT = 500 mA
Figure 8. LP5912-1.8 Power Up
4.5
4.5
4.0
4.0
3.5
3.5
3.0
3.0
Voltage (V)
Voltage (V)
200 250 300
Time (Ps)
VIN = 0 V to 2.3 V
Figure 7. LP5912-1.8 Power Up
2.5
2.0
1.5
2.5
2.0
1.5
1.0
1.0
VIN
VOUT
VPG
0.5
VIN
VOUT
VPG
0.5
0.0
0.0
0
50
100
150
200 250 300
Time (Ps)
350
400
450
500
0
50
100
150
D009
VIN = 0 V to 3.8 V
IOUT = 1 mA
200 250 300
Time (Ps)
350
Figure 9. LP5912-3.3 Power Up
400
450
500
D010
VIN = 0 V to 3.8 V
IOUT = 500 mA
Figure 10. LP5912-3.3 Power Up
50
50
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
45
40
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
45
40
35
35
30
30
IQ (µA)
IQ (µA)
150
D007
25
20
25
20
15
15
10
10
5
5
0
0
0
0.5
1
1.5
2
2.5
3 3.5
VIN (V)
4
4.5
5
5.5
6
6.5
0
0.5
1
1.5
D051
IOUT = 0 mA
2
2.5
3 3.5
VIN (V)
4
4.5
5
5.5
6
6.5
D052
IOUT = 0 mA
Figure 11. LP5912-0.9 IQ (No Load) vs VIN
Figure 12. LP5912-1.8 IQ (No Load) vs VIN
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
50
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
45
40
IQ (PA)
35
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3 3.5
VIN (V)
4
4.5
5
5.5
6
6.5
D053
IOUT = 0 mA
VEN = 0 V
Figure 13. LP5912-3.3 IQ (No Load) vs VIN
Figure 14. LP5912-0.9 IQ(SD) vs VIN
VEN = 0 V
VEN = 0 V
Figure 15. LP5912-1.8 IQ(SD) vs VIN
Figure 16. LP5912-3.3 IQ(SD) vs VIN
500
500
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
450
400
350
350
300
300
IQ (µA)
IQ (µA)
400
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
450
250
250
200
200
150
150
100
100
50
50
0
0
0
50
100
150
200 250 300
IOUT (mA)
350
400
450
500
0
50
D057
100
150
200 250 300
IOUT (mA)
350
400
450
500
D058
VIN = 1.6 V
Figure 17. LP5912-0.9 IGND vs IOUT
10
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Figure 18. LP5912-1.8 IGND vs IOUT
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
500
0
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
450
400
-10
-20
-30
PSRR (dB)
IQ (µA)
350
300
250
200
-40
-50
-60
150
-70
100
-80
50
-90
0
0
50
100
150
200 250 300
IOUT (mA)
350
400
450
-100
10 20
500
100
D059
VIN = 1.6 V
Figure 19. LP5912-3.3 IGND vs IOUT
1E+7
D011
IOUT = 20 mA
Figure 20. LP5912-0.9 PSRR vs Frequency
0
0
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
-20
-10
-20
-30
PSRR (db)
-40
PSRR (db)
1000
10000 100000 1000000
Frequency (Hz)
-60
-80
-40
-50
-60
-70
-80
-100
-90
-120
10 20
100
1000
10000 100000 1000000
Frequency (Hz)
-100
10 20
1E+7
VIN = 1.6 V
Figure 21. LP5912-0.9 PSRR vs Frequency
-20
D013
Figure 22. LP5912-1.8 PSRR vs Frequency
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
-10
-20
-30
PSRR (dB)
PSRR (dB)
1E+7
0
-30
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
10 20
1000
10000 100000 1000000
Frequency (Hz)
IOUT = 20 mA
0
-10
100
D012
100
1000
10000 100000 1000000
Frequency (Hz)
1E+7
-100
10 20
100
D014
1000
10000 100000 1000000
Frequency (Hz)
1E+7
D015
IOUT = 20 mA
Figure 23. LP5912-1.8 PSRR vs Frequency
Figure 24. LP5912-3.3 PSRR vs Frequency
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
1
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
' VOUT (mV)
PSRR (dB)
-30
-40
-50
0.6
2.2
0.4
2.1
0.2
2
0
1.9
-0.2
1.8
-70
-0.4
1.7
-80
-0.6
1.6
-90
-0.8
1.5
-60
-100
10 20
-1
100
1000
10000 100000 1000000
Frequency (Hz)
1E+7
0
50
100
150
D016
200 250 300
Time (µs)
350
400
0.8
'VOUT (mV)
2.3
VIN (V)
0.8
0.6
2.2
0.6
2.9
0.4
2.1
0.4
2.8
0.2
2
0.2
2.7
0
1.9
-0.2
1.8
-0.4
' VOUT (mV)
1
VIN (V)
'VOUT (mV)
Figure 26. LP5912-0.9 Line Transient
2.4
3.1
' VOUT (mV)
3
VIN (V)
0
2.6
-0.2
2.5
1.7
-0.4
2.4
-0.6
1.6
-0.6
2.3
-0.8
1.5
-0.8
2.2
-1
1.4
500
-1
50
100
150
200 250 300
Time (Ps)
350
400
450
0
50
100
150
D018
VIN = 2.2 V to 1.6 V
tfall = 30 µs
350
400
450
2.1
500
D019
trise = 30 µs
Figure 28. LP5912-1.8 Line Transient
3.1
1
' VOUT (mV)
3
VIN (V)
0.8
200 250 300
Time (µs)
VIN = 2.3 V to 2.9 V
Figure 27. LP5912-0.9 Line Transient
1
4.6
' VOUT (mV)
4.5
VIN (V)
0.8
2.9
0.6
4.4
0.4
2.8
0.4
4.3
0.2
2.7
0
2.6
-0.2
2.5
-0.2
4
-0.4
2.4
-0.4
3.9
-0.6
2.3
-0.6
3.8
-0.8
2.2
-0.8
3.7
2.1
500
-1
-1
0
50
100
150
200 250 300
Time (µs)
VIN = 2.9 V to 2.3 V
350
400
450
' VOUT (mV)
0.6
VIN (V)
' VOUT (mV)
trise = 30 µs
1
0
0.2
4.2
0
4.1
0
50
100
D020
tfall = 30 µs
VIN = 3.8 V to 4.4 V
Figure 29. LP5912-1.8 Line Transient
12
1.4
500
D017
VIN = 1.6 V to 2.2 V
Figure 25. LP5912-3.3 PSRR vs Frequency
450
VIN (V)
-20
2.4
' VOUT (mV)
2.3
VIN (V)
0.8
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150
200 250 300
Time (µs)
350
400
450
VIN (V)
-10
VIN (V)
0
3.6
500
D021
trise = 30 µs
Figure 30. LP5912-3.3 Line Transient
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
4.4
0.4
4.3
0.2
4.2
0
4.1
-0.2
4
-0.4
3.9
-0.6
3.8
-0.8
3.7
50
100
150
200 250 300
Time (µs)
350
400
450
3.6
500
20
400
0
300
-20
200
-40
100
-60
0
tfall = 30 µs
VIN = 1.6 V
Figure 31. LP5912-3.3 Line Transient
60
80
600
' VOUT (mV)
IOUT (mA)
140
160
180
0
200
D023
IOUT = 5 mA to 500 mA
trise = 10 µs
60
600
' VOUT (mV)
IOUT (mA)
40
20
400
20
400
0
300
0
300
-20
200
-20
200
-40
100
-40
100
-60
0
20
40
VIN = 1.6 V
60
80
100 120
Time (µs)
140
160
180
' VOUT (mV)
500
IOUT (mA)
40
100 120
Time (µs)
Figure 32. LP5912-0.9 Load Transient Response
60
' VOUT (mV)
40
D022
VIN = 4.4 V to 3.8 V
0
200
500
-60
0
20
40
60
80
D024
IOUT = 500 mA to 5 mA
tfall = 10 µs
160
180
0
200
D025
trise = 10 µs
60
600
' VOUT (mV)
IOUT (mA)
40
20
400
20
400
0
300
0
300
-20
200
-20
200
-40
100
-40
100
-60
0
20
40
60
80
100 120
Time (µs)
140
160
IOUT = 500 mA to 5 mA
180
0
200
' VOUT (mV)
500
IOUT (mA)
40
140
Figure 34. LP5912-1.8 Load Transient Response
600
' VOUT (mV)
IOUT (mA)
100 120
Time (µs)
IOUT = 5 mA to 500 mA
Figure 33. LP5912-0.9 Load Transient Response
60
' VOUT (mV)
20
Figure 35. LP5912-1.8 Load Transient Response
500
-60
0
20
40
60
D026
tfall = 10 µs
IOUT (mA)
0
500
IOUT = 5 mA to 500 mA
80
100 120
Time (µs)
140
160
180
IOUT (mA)
-1
600
' VOUT (mV)
IOUT (mA)
40
' VOUT (mV)
' VOUT (mV)
0.6
60
IOUT (mA)
4.6
' VOUT (mV)
4.5
VIN (V)
VIN (V)
1
0.8
0
200
D027
trise = 10 µs
Figure 36. LP5912-3.3 Load Transient Response
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
60
20
400
2
0
300
-20
200
1
-40
100
0.5
-60
0
20
40
60
80
100 120
Time (µs)
140
160
180
Voltage (V)
2.5
IOUT (mA)
500
40
' VOUT (mV)
3
600
' VOUT (mV)
IOUT (mA)
VEN (V)
VOUT (V)
VPG (V)
1.5
0
0
200
0
50
100
150
D028
IOUT = 500 mA to 5 mA
tfall = 10 µs
200 250 300
Time (µs)
350
450
500
D031
IOUT = 0 mA
Figure 37. LP5912-3.3 Load Transient Response
400
COUT = 1 µF
Figure 38. LP5912-1.8 VOUT vs VEN(ON)
3
2.5
VEN (V)
VOUT (V)
VPG (V)
2
VEN (V)
VOUT (V)
VPG (V)
2.5
Voltage (V)
Voltage (V)
2
1.5
1
1.5
1
0.5
0.5
0
0
0
50
100
150
200 250 300
Time (µs)
350
400
450
0
500
50
100
150
D032
IOUT = 0 mA
COUT = 1 µF
200 250 300
Time (µs)
350
450
500
D033
IOUT = 1 mA
Figure 39. LP5912-1.8 VOUT vs VEN(OFF)
400
COUT = 1 µF
Figure 40. LP5912-1.8 VOUT vs VEN(ON)
2.5
3
VEN (V)
VOUT (V)
VPG (V)
2
VEN (V)
VOUT (V)
VPG (V)
2.5
Voltage (V)
Voltage (V)
2
1.5
1
1.5
1
0.5
0.5
0
0
0
50
100
150
200 250 300
Time (µs)
IOUT = 1 mA
350
400
450
500
0
50
COUT = 1 µF
IOUT = 500 mA
Figure 41. LP5912-1.8 VOUT vs VEN(OFF)
14
100
D034
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150
200 250 300
Time (µs)
350
400
450
500
D035
COUT = 1 µF
Figure 42. LP5912-1.8 VOUT vs VEN(ON)
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
225
2.2
VEN (V)
VOUT (V)
VPG (V)
200
Dropout Voltage, VDO (mV)
2
1.8
Voltage (V)
1.6
1.4
1.2
1
0.8
0.6
0.4
175
150
125
100
75
25
0.2
0
0
0
5
10
15
20
25
30
Time (µs)
35
40
45
0
50
50
100
D036
IOUT = 500 mA
150
200 250 300
IOUT (mA)
350
400
450
500
D041
COUT = 1 µF
Figure 43. LP5912-1.8 VOUT vs VEN(OFF)
Figure 44. LP5912-1.8 Dropout Voltage (VDO) vs IOUT
225
1.2
-40°C
25°C
85°C
125°C
200
175
1 mA
500 mA
1
150
Noise (µV—Hz)
Dropout Voltage, VDO (mV)
-40°C
25°C
85°C
125°C
50
125
100
75
0.8
0.6
0.4
50
0.2
25
0
0
50
100
150
200 250 300
IOUT (mA)
350
400
450
0
10
500
100
D042
1000
10000
Frequency (Hz)
100000
1000000
D043
VIN = 1.6 V
Figure 45. LP5912-3.3 Dropout Voltage (VDO) vs IOUT
Figure 46. LP5912-0.9 Noise vs Frequency
1.2
1.2
1 mA
500 mA
0.8
0.6
0.4
0.2
0
10
1 mA
500 mA
1
Noise (µV—Hz)
Noise (µV—Hz)
1
0.8
0.6
0.4
0.2
100
1000
10000
Frequency (Hz)
100000
1000000
0
10
100
D044
Figure 47. LP5912-1.8 Noise vs Frequency
1000
10000
Frequency (Hz)
100000
1000000
D045
Figure 48. LP5912-3.3 Noise vs Frequency
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
5
500
VEN (V)
VOUT (V)
IIN (mA)
280
4
240
VEN and VOUT (V)
Turnon Time (Ps)
260
220
200
180
400
3
300
2
200
1
100
IIN (mA)
300
160
140
120
0
25
50
75
Junction Temperature (°C)
100
0
-50
125
D060
0
50
Figure 49. LP5912-3.3 Turnon Time vs Junction
Temperature
3
60
50
2
40
1.5
30
1
CIN = Open
300
350
0
450
400
0.9
0.75
2
0.5
150 200 250
Time (Ps)
1.2
1.05
0.6
1.5
20
100
1.35
3
10
50
0.45
0.3
0.15
0
-50
0
50
100
COUT = 1 µF
CIN = Open
Figure 51. LP5912-3.3 In-Rush Current
IOUT = 500 mA
VEN and VOUT (V)
4
400
0
450
D063
COUT = 10 µF
1.35
1.2
1.05
3
0.9
2.5
0.75
2
0.6
1.5
0.45
1
0.3
0.5
CIN = Open
350
1.5
VEN (V)
VOUT (V)
IIN (A)
3.5
0
-50
300
Figure 52. LP5912-3.3 In-Rush Current
5
4.5
150 200 250
Time (Ps)
D062
IOUT = 1 mA
COUT = 1 µF
2.5
1
0
D061
IOUT = 500 mA
3.5
0.5
0
-50
0
450
1.5
4
70
2.5
400
VEN (V)
VOUT (V)
IIN (A)
4.5
VEN and VOUT (V)
3.5
350
5
IIN (mA)
VEN and VOUT (V)
4
300
Figure 50. LP5912-3.3 In-Rush Current
100
VEN (V)
VOUT (V) 90
IIN (mA) 80
4.5
150 200 250
Time (Ps)
CIN = Open
IOUT = 0 mA (No Load)
5
100
IIN (A)
-25
IIN (A)
100
-50
0.15
0
50
100
150 200 250
Time (Ps)
300
350
IOUT = 1 mA
400
0
450
D064
COUT = 10 µF
Figure 53. LP5912-3.3 In-Rush Current
16
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8 Detailed Description
8.1 Overview
The LP5912-Q1 is a low-noise, high PSRR, LDO capable of sourcing a 500-mA load. The LP5912-Q1 can
operate down to 1.6-V input voltage and 0.8-V output voltage. This combination of low noise, high PSRR, and
low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from
noise-sensitive communication components to battery-powered system.
The LP5912-Q1 Functional Block Diagram contains several features, including:
• Internal output resistor divider feedback;
• Small size and low-noise internal protection circuit current limit;
• Reverse current protection;
• Current limit and in-rush current protection;
• Thermal shutdown;
• Output auto discharge for fast turnoff; and
• Power-good output, with fixed 140-µs typical delay.
8.2 Functional Block Diagram
Current
Limit
IN
OUT
RAD
100
45 k
VIN
EA
Output
Discharge
+
±
VBG
PG
EN
Control
EN
140-µs
DELAY
3M
GND
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8.3 Feature Description
8.3.1 Enable (EN)
The LP5912-Q1 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than
the VEN(ON) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage
must be lower than the VEN(OFF) threshold to ensure that the device is fully disabled and the automatic output
discharge is activated.
When the device is disabled the output stage is disabled, the PG output pin is low, and the output automatic
discharge is ON.
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Feature Description (continued)
8.3.2 Output Automatic Discharge (RAD)
The LP5912-Q1 output employs an internal 100-Ω (typical) pulldown resistance to discharge the output when the
EN pin is low. Note that if the LP5912-Q1 EN pin is low (the device is OFF) and the OUT pin is held high by a
secondary supply, current flows from the secondary supply through the automatic discharge pulldown resistor to
ground.
8.3.3 Reverse Current Protection (IRO)
The LP5912-Q1 input is protected against reverse current when output voltage is higher than the input. In the
event that extra output capacitance is used at the output, a power-down transient at the input would normally
cause a large reverse current through a conventional regulator. The LP5912-Q1 includes a reverse voltage
detector that trips when VIN drops below VOUT, shutting off the regulator and opening the PMOS body diode
connection, preventing any reverse current from the OUT pin from flowing to the IN pin.
If the LP5912 EN pin is low (the LP5912 is OFF) and the OUT pin is held high by a secondary supply, current
flows from the secondary supply through the automatic discharge pulldown resistor to ground. This is not reverse
current, this is automatic discharge pulldown current.
Note that reverse current (IRO) is measured at the IN pin.
8.3.4 Internal Current Limit (ISC)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate continuously at the ISC current limit. During a current-limit event, the LDO
sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a
current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO,
resulting in a thermal shutdown of the output.
8.3.5 Thermal Overload Protection (TSD)
Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which allows
the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
8.3.6 Power-Good Output (PG)
The LP5912-Q1 device has a power-good function that works by toggling the state of the PG output pin. When
the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages (low
impedance to GND). When the output voltage rises above the PG threshold voltage (PGVHTH), the PG pin
becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can
receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for
the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.
The input supply, VIN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin
output status is valid. The PG pin output status is undefined when VIN is less than 1.6 V.
In power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output voltage
rises above the PGHTH threshold voltage. If the output voltage rises above the PGHTH threshold and then falls
below the PGLTH threshold voltage the PG pin falls immediately with no delay time.
If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected to
ground or left floating.
18
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8.4 Device Functional Modes
8.4.1 Enable (EN)
The LP5912-Q1 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than
the VEN(ON) threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin
voltage is lower than the VEN(OFF) threshold, the output stage is disabled, the PG pin goes low, and the output
automatic discharge circuit is activated. Any charge on the OUT pin is discharged to ground through the internal
100-Ω (typical) output auto discharge pulldown resistance.
8.4.2 Minimum Operating Input Voltage (VIN)
The LP5912-Q1 device does not include any dedicated UVLO circuit. The device internal circuit is not fully
functional until VIN is at least 1.6 V. The output voltage is not regulated until VIN has reached at least the greater
of 1.6 V or (VOUT + VDO).
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP5912-Q1 is designed to meet the requirements of RF and analog circuits, by providing low noise, high
PSRR, low quiescent current, and low line or load transient response. The device offers excellent noise
performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a
value of 1 μF. The device delivers this performance in an industry standard WSON package, which for this
device is specified with an operating junction temperature (TJ) of –40°C to +125°C.
9.2 Typical Application
Figure 54 shows the typical application circuit for the LP5912-Q1. Input and output capacitances may need to be
increased above the 1-μF minimum for some applications.
VIN
IN
VOUT
OUT
LP5912-Q1
CIN
GND
COUT
NC
RPG
VEN
VPG
EN
PG
Copyright © 2016, Texas Instruments Incorporated
Figure 54. LP5912-Q1 Typical Application
9.2.1 Design Requirements
For typical RF linear regulator applications, use the parameters listed in Table 1.
Table 1. Design Parameters
20
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
1.6 to 6.5 V
Output voltage
0.8 to 5.5 V
Output current
500 mA
Output capacitor
1 to 10 µF
Input/output capacitor ESR range
5 mΩ to 500 mΩ
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9.2.2 Detailed Design Procedure
9.2.2.1 External Capacitors
Like most low-dropout regulators, the LP5912-Q1 requires external capacitors for regulator stability. The device
is specifically designed for portable applications requiring minimum board space and smallest components.
These capacitors must be correctly selected for good performance.
9.2.2.2 Input Capacitor
An input capacitor is required for stability. The input capacitor must be at least equal to, or greater than, the
output capacitor for good load-transient performance. A capacitor of at least 1 µF must be connected between
the LP5912-Q1 IN pin and ground for stable operation over full load-current range. It is acceptable to have more
output capacitance than input, as long as the input is at least 1 µF.
The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.
NOTE
To ensure stable operation it is essential that good PCB practices are employed to
minimize ground impedance and keep input inductance low. If these conditions cannot be
met, or if long leads are to be used to connect the battery or other power source to the
LP5912-Q1, increasing the value of the input capacitor to at least 10 µF is recommended.
Also, tantalum capacitors can suffer catastrophic failures due to surge current when
connected to a low-impedance source of power (such as a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must be verified by the
manufacturer to have a surge current rating sufficient for the application. There are no
requirements for the equivalent series resistance (ESR) on the input capacitor, but
tolerance and temperature coefficient must be considered when selecting the capacitor to
ensure the capacitance remains 1 μF ±30% over the entire operating temperature range.
9.2.2.3 Output Capacitor
The LP5912-Q1 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A
ceramic capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with an ESR from 5 mΩ to 500
mΩ, is suitable in the LP5912-Q1 application circuit. For this device the output capacitor must be connected
between the OUT pin with a good connection back to the GND pin.
Tantalum or film capacitors may also be used at the device output, VOUT, but these are not as attractive for
reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability.
9.2.2.4 Capacitor Characteristics
The LP5912-Q1 is designed to work with ceramic capacitors on the input and output to take advantage of the
benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,
least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP5912-Q1.
The preferred choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most
stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less
desirable than ceramic for use as output capacitors because they are more expensive when comparing
equivalent capacitance and voltage ratings in the 1-µF to 10-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. While it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C
down to –40°C, so some guard band must be allowed.
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9.2.2.5 Remote Capacitor Operation
To ensure stability the LP5912-Q1 requires at least a 1-μF capacitor at the OUT pin. There is no strict
requirement about the location of the output capacitor in regards to the LDO OUT pin; the output capacitor may
be located 5 to 10 cm away from the LDO. This means that there is no need to have a special capacitor close to
the OUT pin if there are already respective capacitors in the system. This placement flexibility requires that the
output capacitor be connected directly between the LP5912-Q1 OUT pin and GND pin with no vias. This remote
capacitor feature can help users to minimize the number of capacitors in the system.
As a good design practice, keep the wiring parasitic inductance at a minimum, which means using as wide as
possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground
layer as possible, avoiding vias on the path. If there is a need to use vias, implement as many as possible vias
between the connection layers. Keeping parasitic wiring inductance less than 35 nH is recommended. For
applications with fast load transients use an input capacitor equal to, or larger than, the sum of the capacitance
at the output node for the best load-transient performance.
9.2.2.6 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 1.
PD(MAX) = (VIN(MAX) – VOUT) × IOUT
(1)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that is greater than the dropout voltage (VDO). However, keep in mind that higher voltage
drops result in better dynamic (that is, PSRR and transient) performance.
On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad into the
PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal
ground plane with an appropriate amount of copper PCB area.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 2 or Equation 2:
TJ(MAX) = TA(MAX) + (RθJA × PD(MAX))
PD = TJ(MAX) – TA(MAX) / RθJA
(2)
(3)
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copperspreading area, and is to be used only as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance
(RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
22
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9.2.2.7 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 4 or Equation 5.
TJ(MAX) = TTOP + (ΨJT × PD(MAX))
where
•
•
PD(MAX) is explained in Equation 3
TTOP is the temperature measured at the center-top of the device package.
TJ(MAX) = TBOARD + (ΨJB × PD(MAX))
(4)
where
•
•
PD(MAX) is explained in Equation 3.
TBOARD is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
(5)
For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package
Thermal Metrics ; for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics ; and
for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are
available at www.ti.com.
9.2.3 Application Curves
2.5
2.5
2.0
Voltage (V)
Voltage (V)
2.0
VEN (V)
VOUT (V)
VPG (V)
1.5
1.0
0.5
1.5
1.0
0.5
VEN (V)
VOUT (V)
VPG (V)
0.0
0.0
0
50
VIN = 2.3 V
100
150
200 250 300
Time (µs)
350
IOUT = 500 mA
400
450
500
0
5
COUT = 1 µF
10
15
20
Time (µs)
D029
VIN = 2.3 V
Figure 55. LP5912-1.8 VOUT vs VEN (ON)
IOUT = 500 mA (3.6 Ω)
25
D030
COUT = 1 µF
Figure 56. LP5912-1.8 VOUT vs VEN (OFF)
10 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.6 V to 6.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the LP5912-Q1 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 0.5 V. A minimum capacitor value of
1 µF is required to be within 1 cm of the IN pin.
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11 Layout
11.1 Layout Guidelines
The dynamic performance of the LP5912-Q1 is dependant on the layout of the PCB. PCB layout practices that
are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5912-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5912-Q1, and as
close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5912-Q1
ground pin using as wide and as short of a copper trace as is practical.
Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such
connections add parasitic inductances and resistance that result in inferior performance especially during
transient conditions.
11.2 Layout Example
Thermal Vias (2)
OUT
1
6
IN
COUT
CIN
NC
2
5
GND
PG
3
4
EN
RPG
Figure 57. LP5912-Q1 Typical Layout
24
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12 Device and Documentation Support
12.1 Related Documentation
For additional information, see the following:
• AN1187 Leadless Leadframe Package (LLP)
• Semiconductor and IC Package Thermal Metrics
• Using New Thermal Metrics
• Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP5912Q0.9DRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QA
LP5912Q0.9DRVTQ1
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QA
LP5912Q1.5DRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QC
LP5912Q1.5DRVTQ1
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QC
LP5912Q1.8DRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QD
LP5912Q1.8DRVTQ1
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QD
LP5912Q2.8DRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QE
LP5912Q2.8DRVTQ1
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QE
LP5912Q3.3DRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QF
LP5912Q3.3DRVTQ1
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12QF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2016
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP5912-Q1 :
• Catalog: LP5912
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LP5912Q0.9DRVRQ1
WSON
DRV
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q0.9DRVTQ1
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q1.5DRVRQ1
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q1.5DRVTQ1
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q1.8DRVRQ1
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q1.8DRVTQ1
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q2.8DRVRQ1
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q2.8DRVTQ1
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q3.3DRVRQ1
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
LP5912Q3.3DRVTQ1
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP5912Q0.9DRVRQ1
WSON
DRV
6
3000
210.0
185.0
35.0
LP5912Q0.9DRVTQ1
WSON
DRV
6
250
210.0
185.0
35.0
LP5912Q1.5DRVRQ1
WSON
DRV
6
3000
210.0
185.0
35.0
LP5912Q1.5DRVTQ1
WSON
DRV
6
250
210.0
185.0
35.0
LP5912Q1.8DRVRQ1
WSON
DRV
6
3000
210.0
185.0
35.0
LP5912Q1.8DRVTQ1
WSON
DRV
6
250
210.0
185.0
35.0
LP5912Q2.8DRVRQ1
WSON
DRV
6
3000
210.0
185.0
35.0
LP5912Q2.8DRVTQ1
WSON
DRV
6
250
210.0
185.0
35.0
LP5912Q3.3DRVRQ1
WSON
DRV
6
3000
210.0
185.0
35.0
LP5912Q3.3DRVTQ1
WSON
DRV
6
250
210.0
185.0
35.0
Pack Materials-Page 2
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