LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 LMC6042 CMOS Dual Micropower Operational Amplifier Check for Samples: LMC6042 FEATURES DESCRIPTION 1 • • • • • 2 Low Supply Current: 10 μA/Amp (typ) Operates from 4.5V to 15V Single Supply Ultra Low Input Current: 2 fA (typ) Rail-to-Rail Output Swing Input Common-Mode Range Includes Ground APPLICATIONS • • • • • • • Battery Monitoring and Power Conditioning Photodiode and Infrared Detector Preamplifier Silicon Based Transducer Systems Hand-Held Analytic Instruments pH Probe Buffer Amplifier Fire and Smoke Detection Systems Charge Amplifier for Piezoelectric Transducers Ultra-low power consumption and low input-leakage current are the hallmarks of the LMC6042. Providing input currents of only 2 fA typical, the LMC6042 can operate from a single supply, has output swing extending to each supply rail, and an input voltage range that includes ground. The LMC6042 is ideal for use in systems requiring ultra-low power consumption. In addition, the insensitivity to latch-up, high output drive, and output swing to ground without requiring external pull-down resistors make it ideal for single-supply batterypowered systems. Other applications for the LMC6042 include bar code reader amplifiers, magnetic and electric field detectors, and hand-held electrometers. This device is built with TI's advanced Double-Poly Silicon-Gate CMOS process. See the LMC6041 for a single, and the LMC6044 for a quad amplifier with these features. Connection Diagram Figure 1. 8-Pin PDIP/SOIC Figure 2. Low-Power Two-Op-Amp Instrumental Amplifier 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Absolute Maximum Ratings (1) (2) Differential Input Voltage ±Supply Voltage Supply Voltage (V+ − V−) 16V + See (3) − Output Short Circuit to V See (4) Lead Temperature (Soldering, 10 seconds) 260°C Output Short Circuit to V Current at Input Pin ±5 mA Current at Output Pin ±18 mA Current at Power Supply Pin 35 mA Power Dissipation See −65°C to +150°C Storage Temperature Range Junction Temperature ESD Tolerance (5) 110°C (6) 500V (2) (3) (4) (5) (6) − + (V ) + 0.3V, (V ) − 0.3V Voltage at Input/Output Pin (1) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Do not connect output to V+when V+ is greater than 13V or reliability may be adversely affected. Applies to both single-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 110°C. Output currents in excess of ±30 mA over long term may adversely affect reliability. The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) − TA)/θJA. Human body model, 1.5 kΩ in series with 100 pF. Operating Ratings Temperature Range −40°C ≤ TJ ≤ +85°C LMC6042AI, LMC6042I 4.5V ≤ V+ ≤ 15.5V Supply Voltage Power Dissipation See Thermal Resistance (θJA), (1) (2) (2) (1) 8-Pin PDIP 101°C/W 8-Pin SOIC 165°C/W 8-Pin CDIP 115°C/W For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. All numbers apply for packages soldered directly into a PC board. Electrical Characteristics Unless otherwise specified, all limits ensured for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL > 1M unless otherwise specified. Symbol VOS Parameter Conditions Typical (1) Limit Input Offset Voltage TCVOS Input Offset Voltage LMC6042AI 1 (2) LMC6042I Limit (2) Units (Limit) 3 6 mV 3.3 6.3 Max μV/°C 1.3 Average Drift IB Input Bias Current 0.002 4 4 pA (Max) IOS Input Offset Current 0.001 2 2 pA (Max) RIN Input Resistance (1) (2) 2 >10 TeraΩ Typical values represent the most likely parametric norm. All limits are specified at room temperature (standard type face) or at operating temperature extremes (bold face type). Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL > 1M unless otherwise specified. Symbol CMRR +PSRR −PSRR CMR AV Parameter Common Mode 0V ≤ VCM ≤ 12.0V Rejection Ratio V+ = 15V Positive Power Supply 5V ≤ V+ ≤ 15V Rejection Ratio VO = 2.5V Negative Power Supply 0V ≤ V− ≤ −10V Rejection Ratio VO = 2.5V Input Common-Mode V+ = 5V and 15V Voltage Range For CMRR ≥ 50 dB Large Signal Typical (1) Conditions RL = 100 kΩ LMC6042AI LMC6042I Limit (2) Limit (2) 68 62 dB 66 60 Min 68 62 dB 66 60 Min 84 74 dB 83 73 Min −0.4 −0.1 −0.1 V 0 0 Max V+−1.9V V+− 2.3V V+− 2.3V V V+− 2.5V V+− 2.4V Min 400 300 V/mV 300 200 Min 180 90 V/mV 120 70 Min 200 100 V/mV 160 80 Min 250 100 50 V/mV 60 40 Min 4.987 4.970 4.940 V 4.950 4.910 Min 0.030 0.060 V 0.050 0.090 Max 4.920 4.870 V 4.870 4.820 Min 0.080 0.130 V 0.130 0.180 Max 14.920 14.880 V 14.880 14.820 Min 0.030 0.060 V 0.050 0.090 Max 14.900 14.850 V 14.850 14.800 Min 0.100 0.150 V 0.150 0.200 Max 16 13 mA 10 8 Min 13 mA Min 75 75 94 (3) Sourcing 1000 Voltage Gain Sinking RL = 25 kΩ (3) Sourcing Sinking VO Output Swing V+ = 5V 500 1000 RL = 100 kΩ to V+/2 0.004 V+ = 5V 4.980 RL = 25 kΩ to V+/2 0.010 V+ = 15V 14.970 + RL = 100 kΩ to V /2 0.007 V+ = 15V 14.950 RL = 25 kΩ to V+/2 0.022 ISC Output Current Sourcing, VO = 0V 22 V+ = 5V ISC Output Current Sinking, VO = 5V 21 16 8 8 Sourcing, VO = 0V 40 15 15 mA 10 10 Min 24 21 mA 8 8 Min V+ = 15V Sinking, VO = 13V (4) (3) (4) Units (Limit) 39 V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Do not connect output to V+when V+ is greater than 13V or reliability may be adversely affected. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 3 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL > 1M unless otherwise specified. Symbol IS Parameter Supply Current Conditions Both Amplifiers Typical (1) 20 VO = 1.5V Both Amplifiers 26 V+ = 15V LMC6042AI LMC6042I Limit (2) Limit (2) Units (Limit) 34 45 μA 39 50 Max 44 56 μA 51 65 Max AC Electrical Characteristics Unless otherwise specified, all limits ensured for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL > 1M unless otherwise specified. Symbol Parameter SR Slew Rate GBW Gain-Bandwidth Product φm Phase Margin en Conditions See (3) See Input-Referred Voltage Noise f = 1 kHz in Input-Referred Current Noise T.H.D. Total Harmonic Distortion 0.02 (4) Amp-to-Amp Isolation Typ (1) f = 1 kHz LMC6042AI LMC6042I Limit (2) Limit (2) 0.015 0.010 0.010 0.007 Units (Limit) V/μs Min 100 kHz 60 Deg 115 dB 83 nV/√Hz 0.0002 pA/√Hz 0.01 % f = 1 kHz, AV = −5 RL = 100 kΩ, VO = 2 VPP ±5V Supply (1) (2) (3) (4) 4 Typical values represent the most likely parametric norm. All limits are ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred V+ = 15V and RL = 100 kΩ connected to V+/2. Each amp excited in turn with 100 Hz to produce VO = 12 VPP. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 Typical Performance Characteristics VS = ±7.5V, TA = 25°C unless otherwise specified Supply Current vs Supply Voltage Offset Voltage vs Temperature of Five Representative Units Figure 3. Figure 4. Input Bias Current vs Temperature Input Bias Current vs Input Common-Mode Voltage Figure 5. Figure 6. Input Bias Current Voltage Range vs Temperature Output Characteristics Current Sinking Figure 7. Figure 8. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 5 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified 6 Output Characteristics Current Sourcing Input Voltage Noise vs Frequency Figure 9. Figure 10. Crosstalk Rejection vs Frequency CMRR vs Frequency Figure 11. Figure 12. CMRR vs Temperature Power Supply Rejection Ratio vs Frequency Figure 13. Figure 14. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified Open-Loop Voltage Gain vs Temperature Open-Loop Frequency Response Figure 15. Figure 16. Gain and Phase Responses vs Load Capacitance Gain and Phase Response vs Temperature Figure 17. Figure 18. Gain Error (VOS vs VOUT) Common-Mode Error vs Common-Mode Voltage of 3 Representative Units Figure 19. Figure 20. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 7 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified 8 Non-Inverting Slew Rate vs Temperature Inverting Slew Rate vs Temperature Figure 21. Figure 22. Non-Inverting Large Signal Pulse Response (AV = +1) Non-Inverting Small Signal Pulse Response Figure 23. Figure 24. Inverting Large-Signal Pulse Response Inverting Small Signal Pulse Response Figure 25. Figure 26. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified Stability vs Capacitive Load Stability vs Capacitive Load Figure 27. Figure 28. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 9 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6042 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6042 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance with amplifiers with ultra-low input curent, like the LMC6042. Although the LMC6042 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6042 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). Figure 29. Cancelling the Effect of Input Capacitance The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the feedback resistor (as in Figure 29 ) such that: (1) or R1 CIN ≤ R2 Cf (2) Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensating for input capacitance. CAPACITIVE LOAD TOLERANCE Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 30. 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 Figure 30. LMC6042 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 30, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 31). Typically a pull up resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure 31. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6042, typically less than 2 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6042's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's inputs, as in Figure 32. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6042's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 36 for typical connections of guard rings for standard op-amp configurations. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 11 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Figure 32. Example of Guard Ring in P.C. Board Layout Figure 33. Inverting Amplifier Figure 34. Non-Inverting Amplifier Figure 35. Follower Figure 36. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 37. 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) Figure 37. Air Wiring Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6042 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. The circuit in Figure 38 is recommended for applications where the common-mode input range is relatively low and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less than 20 μA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board layout an important part of the overall system design (see Printed-Circuit-Board Layout for High Impedance Work). Referring to Figure 38, the input voltages are represented as a common-mode input VCM plus a differential input VD. Rejection of the common-mode component of the input is accomplished by making the ratio of R1/R2 equal to R3/R4. So that where, (3) A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the gain equation can be simplified: (4) Due to the “zero-in, zero-out” performance of the LMC6042, and output swing rail-rail, the dynamic range is only limited to the input common-mode range of 0V to VS − 2.3V, worst case at room temperature. This feature of the LMC6042 makes it an ideal choice for low-power instrumentation systems. A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 39. Provisions have been made for low sensitivity trimming of CMRR and gain. Figure 38. Two Op-Amp Instrumentation Amplifier Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 13 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Figure 39. Low-Power Two-Op-Amp Instrumentation Amplifier Figure 40. Low-Leakage Sample and Hold Figure 41. Instrumentation Amplifier Figure 42. 1 Hz Square Wave Oscillator 14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 LMC6042 www.ti.com SNOS611E – AUGUST 1999 – REVISED MARCH 2013 Figure 43. AC Coupled Power Amplifier Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 15 LMC6042 SNOS611E – AUGUST 1999 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC6042 PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMC6042AIJ ACTIVE CDIP NAB 8 40 TBD Call TI Call TI LMC6042AIJ LMC6042AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 42AIM LMC6042AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 42AIM LMC6042AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 42AIM LMC6042AIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC60 42AIN LMC6042IM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 42IM LMC6042IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 42IM LMC6042IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 42IM LMC6042IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC60 42IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 17-Mar-2017 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6042AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6042IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6042AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6042IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NAB0008A J08A (Rev M) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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