Cypress CY7C192-15PC 64k x 4 static ram with separate i/o Datasheet

92
CY7C192
64K x 4 Static RAM
with Separate I/O
Features
pansion is provided by active LOW Chip Enable (CE) and
three-state drivers. It has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
• High speed
— 12 ns
• CMOS for optimum speed/power
• Low active power
— 880 mW
• Low standby power
— 220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Writing to the device is accomplished when the Chip Enable
(CE) and write enable (WE) inputs are both LOW.
Data on the four input pins (I0 through I3) is written into the
memory location specified on the address pins (A0 through
A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW while the Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the four data output pins.
Functional Description
The output pins stay in high-impedance state when Write Enable (WE) is LOW, or Chip Enable (CE) is HIGH.
The CY7C192 is a high-performance CMOS static RAM organized as 65,536 x 4 bits with separate I/O. Easy memory ex-
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
I0
I1
INPUT BUFFER
SENSE AMPS
ROW DECODER
O0
1024 x 64 x 4
ARRAY
O1
O2
O3
11
12
13
14
A8
A7
A6
VCC
A5
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
A5
A4
A3
A2
A1
A0
I3
I2
O3
O2
O1
O0
WE
15
A9
A10
A11
A12
A13
A14
A15
I0
I1
3 2 1 28 27
4
26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12
18
1314151617
A4
A3
A2
A1
A0
I3
I2
O3
O2
C191–3
C191–2
POWER
DOWN
CE
A15
COLUMN
DECODER
A10
A11
A12
A13
A14
1
2
3
4
5
6
7
8
9
10
CE
GND
WE
O0
O1
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
I0
I1
CE
GND
I3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
LCC
Top View
DIP/SOJ
Top View
I2
7C192 ONLY
WE
C191–1
Selection Guide
7C192-12
12
155
30
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05047 Rev. **
•
3901 North First Street
7C192-15
15
145
30
•
San Jose
7C192-20
20
135
30
•
7C192-25
25
115
30
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C192
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................... −0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature[2]
VCC
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C192-12
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
[1]
Min.
Max.
2.4
7C192-15
Min.
Max.
2.4
0.4
Unit
V
0.4
V
2.2
VCC +0.3V
2.2
VCC +0.3V
V
−0.5
0.8
−0.5
0.8
V
VIL
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
−5
+5
−5
+5
µA
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
−5
+5
−5
+5
µA
IOS
Output Short
Circuit Current[3]
VCC = Max., VOUT = GND
−300
−300
mA
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA, f = fMAX
= 1/tRC
155
145
mA
ISB1
Automatic CE PowerDown Current—
TTL Inputs
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
30
30
mA
ISB2
Automatic CE PowerDown Current—CMOS
Inputs
Max. VCC, CE > VCC − 0.3V,
VIN > VCC − 0.3V or VIN < 0.3V,
f=0
10
10
mA
Notes:
1. Minimum voltage is equal to − 2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05047 Rev. **
Page 2 of 10
CY7C192
Electrical Characteristics Over the Operating Range
7C192-20
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
IOZ
IOS
Min.
7C192-25
Max.
Min.
2.4
Max.
Unit
2.4
0.4
V
0.4
V
2.2
VCC
+0.3V
2.2
VCC
+0.3V
V
−0.5
0.8
−3.0
0.8
V
GND < VI < VCC
−5
+5
−5
+5
µA
Output Leakage Current
GND < VO < VCC, Output Disabled
−5
+5
−5
+5
µA
Output Short Circuit
Current[3]
VCC = Max., VOUT = GND
−300
−300
mA
ICC
VCC Operating Supply
Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
135
115
mA
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
30
30
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs
CE > VCC – 0.3V,
VIN ≤ VCC – 0.3V or VIN < 0.3V, f = 0
15
15
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
8
pF
10
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms[5]
R1 481Ω
5V
OUTPUT
R1 481Ω
5V
ALL INPUT PULSES
OUTPUT
R2
255Ω
30 pF
INCLUDING
JIG AND
SCOPE
(a)
3.0V
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
GND
10%
< tr
90%
90%
10%
< tr
C191–5
(b)
C191–4
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. tr = < 3 ns for the -12 and -15 speeds. T.r = < 5 ns for the -20 and slower speeds.
Document #: 38-05047 Rev. **
Page 3 of 10
CY7C192
Switching Characteristics Over the Operating Range[6]
7C192-12
Parameter
Description
Min.
Max.
7C192-15
Min.
Max.
7C192-20
Min.
Max.
7C192-25
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from
Address Change
tACE
CE LOW to
Data Valid
tLZCE
CE LOW to
Low Z[7]
tHZCE
CE HIGH to
High Z[7,8]
tPU
CE LOW to
Power-Up
tPD
CE HIGH to
Power-Down
12
15
12
3
20
15
3
12
3
3
15
3
5
0
3
3
0
3
0
ns
ns
11
0
20
ns
ns
25
9
15
ns
25
20
7
12
25
20
ns
ns
25
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
12
15
20
25
ns
tSCE
CE LOW to
Write End
9
10
15
18
ns
tAW
Address Set-Up to
Write End
9
10
15
20
ns
tHA
Address Hold from
Write End
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
8
9
15
18
ns
tSD
Data Set-Up to
Write End
8
9
10
10
ns
tHD
Data Hold from
Write End
0
0
0
0
ns
tLZWE
WE HIGH to
Low Z (7C192)[7]
3
3
3
3
ns
tHZWE
WE LOW to
High Z (7C192)[7,8]
7
7
10
11
ns
tDWE
WE LOW to Data Valid
(7C191)
12
15
20
25
ns
tADV
Data Valid to
Output Valid (7C191)
12
15
20
20
ns
tDCE
CE LOW to Data Valid
(7C191)
12
15
20
25
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 through -25 speeds, timing reference levels of
1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZWE is less than tLZWE for any given device. These parameters are guaranteed by
design and not 100% tested.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05047 Rev. **
Page 4 of 10
CY7C192
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
C191–6
Read Cycle No. 2[10, 12]
tRC
CE
tACE
DATA OUT
tHZCE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
C191–7
Write Cycle No. 1 (WE Controlled)[9]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
tHD
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
C191–8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05047 Rev. **
Page 5 of 10
CY7C192
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[9, 13]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tHD
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
(7C192)
HIGH IMPEDANCE
C191–9
Notes:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05047 Rev. **
Page 6 of 10
CY7C192
Typical DC and AC Characteristics
SB
1.4
1.2
ICC
0.8
VIN =5.0V
TA =25°C
0.4
0.2
1.0
0.8
0.6
VCC =5.0V
VIN =5.0V
0.4
0.2
ISB
0.0
4.0
1.2
4.5
5.0
5.5
ISB
0.0
-55
6.0
25
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
TA =25°C
1.0
1.2
1.0
VCC =5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
6.0
0.6
-55
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
VCC =5.0V
TA =25°C
60
40
20
0
0.0
1.0
25
3.0
30.0
2.5
25.0
2.0
1.5
1.0
0.5
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0
125
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
DELTA t AA (ns)
NORMALIZED IPO
80
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.0
0.0
100
AMBIENT TEMPERATURE(°C)
SUPPLY VOLTAGE (V)
1.1
120
125
OUTPUT SINK CURRENT (mA)
0.6
ICC
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED I CC vs. CYCLE TIME
1.25
20.0
15.0
VCC =4.5V
TA =25°C
10.0
NORMALIZED ICC
1.0
NORMALIZED I,CCI
NORMALIZED I,CCI
SB
1.4
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.00
VCC =5.0V
TA =25°C
VIN =0.5V
0.75
5.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-05047 Rev. **
5.0
0.0
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 7 of 10
CY7C192
Ordering Information
Speed (ns)
12
15
20
25
Ordering Code
Package Name
Package Type
CY7C192-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7C192-12VC
V21
28-Lead Molded SOJ
CY7C192-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C192-15VC
V21
28-Lead Molded SOJ
CY7C192-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C192-20VC
V21
28-Lead Molded SOJ
CY7C192-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C192-25VC
V21
28-Lead Molded SOJ
Document #: 38-05047 Rev. **
Operating Range
Commercial
Commercial
Commercial
Commercial
Page 8 of 10
CY7C192
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
51-85014-B
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
Document #: 38-05047 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C192
Document Title: CY7C192 64K x 4 Static RAM with Separate I/O
Document Number: 38-05047
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107149
09/10/01
SZV
Change Spec number from: 38-00076 to 38-05047
Document #: 38-05047 Rev. **
Page 10 of 10
Similar pages