MA-COM M02050-15 3.3/5v limiting amplifier for applications to 2.5 gbp Datasheet

M02050-15
3.3/5V Limiting Amplifier for Applications to 2.5 Gbps
The M02050-15 is an integrated high-gain limiting amplifier. The M02050-15 features PECL outputs and is intended
for use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02050-15
can operate with a 3.3V or 5V supply.
Rate select is supported for SFP applications and/or to achieve optimum sensitivity at data rates ≤ 1.25 Gbps.
When rate select is high, optimum sensitivity is achieved at 2.5 Gbps.
The M02050-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input signal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Other available solutions: M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
M02040-15 3.3/5V Limiting Amplifier for Applications to 2.125 Gbps (PECL outputs)
M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
1.25 Gbps and 4.25 Gbps SFP reference designs available on Mindspeed.com
Applications
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5 Gbps STM-16/OC-48 SDH/SONET
1.06, 2.12 and 4.24 Gbps Fibre Channel
1.25 Gbps Ethernet
1.25 Gbps SDH/SONET
2.67 Gbps SDH/SONET with FEC
Operates with a 3.3V or 5V supply
3.5 mV typical input sensitivity at 2.5 Gbps
PECL outputs
Rate Selection for ≤ 1.25 Gbps operation
Average Receive power monitor output (RSSIAVG)
Peak-to-peak Receive power monitor output (RSSIPP)
On-chip DC offset cancellation circuit
Low power (< 180 mW at 3.3V)
Output Jam Function
16 pin 3x3 QFN package
Typical Applications Diagram
12.1 k Ω
RATE SELControl
+3.3 V
Jam
IREF
RATE SEL
V TT
optional
Biasing
AC-Coupled
to TIA
DINP
Photodiode
MON
PECLP
Limiting
Amplifier
M02013
TIA
Output
Buffer
DINN
Clock Data
Recovery
Unit
PECLN
Offset cancel
Level
Detect
RxAVGIN
RSSIAVG
REXT
02050-DSH-002-F
Level
Shift
Comparator
Threshold
Setting
Circuit
STSET
Regulator
R
ST
RSSIPP
AC or DC Coupled
(as described in
Applications Information)
LOS
V CC3 V CC
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Ordering Information
Part Number
Package
Operating Temperature
M02050-15 *
M02050-15 in QFN16 package
–40 °C to 85 °C
M02050-15EVM
Evaluation board with M02050-15
–40 °C to 85 °C
* The letter “G” designator after the part number indicates that the device is RoHS-compliant. Refer to www.mindspeed.com for additional
information.
Revision History
Revision
Level
Date
ASIC
Revision
F
Final
August 2005
-15
Correct Jam connection in block diagram and typical applications figures.
Correct IREF figure (reference current generation).
E
Final
July 2005
-15
In the DC specifications, update ICC, RINDIFF and RSSIavg; added note 2;
moved RSSIavg from ac specifications. In the ac specifications update
VIN(MIN), VLOS, DJ, RJ and tr/tf; add specifications for LOS assert and
deassert. Updated RST values and the typical LOS curve (Figure 4-3 - Figure 45). Added typical hysteresis curve (Figure 4-6).
D
Preliminary
April 2005
-15
Separated the M02049 and M02050 data sheets. New document number for
the M02049 is 02049-15-DSH-002-D.
Update the following DC specifications: ICC, RINDIFF and VOH. Update the
following ac specifications: VIN(MIN), vn, VLOS, HYS, DJ, RJ, tr/tf, TLOS_ON, and
TLOS_OFF. Update RST and RSSI values for this revision of the part.
Description
16
1
12
VCC
10 mVPP differential input
2.5 Gbps
Connect to GND
02050-DSH-002-F
9
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DINP
8
VCC3
STSET
IREF
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DINN
4
5
160 mV/div
80 ps/div
RxAvgIN
GND
Center Pad
PECLN
PECLP
13
RATESEL
GND
JAM
LOS
RSSIAVG
M02050-15 Pin Configuration
RSSIPP
M02050 Typical Eye Diagram
ii
1.0 Product Specification
1.1
Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reliable operation at these extremes for any length of time is not implied.
NOTE:
The package bottom should be adequately grounded to ensure correct thermal performance,
and it is recommended that vias are inserted through to a lower ground plane.
Table 1-1.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
VCC
Power supply voltage (VCC-GND)
-0.5 to +5.75
V
TSTG
Storage temperature
-65 to +150
°C
VCC - 2 to VCC + 0.4
V
30
mA
0.80
V
Data input pins voltage meeting |DINP - DINN| requirement
GND to VCC3 + 0.4
V
STSET
Signal detect threshold setting pin voltage
GND to VCC3 + 0.4
V
JAM
Output enable pin voltage
GND to VCC + 0.4
V
LOS
Status Output pins voltage
GND to VCC + 0.4
V
Rate_Sel
Rate Select input pin voltage
GND to VCC + 0.4
V
IREF
Current into Reference input
+0 to -120
µA
I(RSSIAVG)
Current into RSSIavg input
+0 to -3
mA
GND to VCC3 + 0.4
V
+3000 to -100
µA
PECLP, PECLN
I(PECLP), I(PECLN)
|DINP - DINN|
DINP, DINN
PECL Output pins voltage
PECL Output pins maximum continuous current (delivered to load)
Data input pins differential voltage
RSSIPP
RSSIPP pin voltage
I(LOS)
Current into Loss of Signal pin
02050-DSH-002-F
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Product Specification
1.2
Recommended Operating Conditions
Table 1-2.
Recommended Operating Conditions
Parameter
Rating
Units
+5V ± 7.5% or
+3.3V ± 7.5%
V
Junction temperature
-40 to +110
°C
Operating ambient
-40 to +85
°C
Power supply: (VCC-GND) (apply no potential to VCC3) or
(VCC3-GND) (connect VCC to same potential as VCC3)
1.3
DC Characteristics
VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-3.
DC Characteristics
Symbol
ICC
Parameter
Conditions
Min
Typ
Max
Units
–
54 (1)
65
mA
VCC-1.81
VCC-1.71
VCC-1.62
V
VCC-1.025
VCC-0.952
VCC-0.88
V
90
110
130
Ω
Supply Current
Includes PECL load
PECL Output Low Voltage (2)
(PECLP, PECLN)
Single ended; 50 Ω load to VCC-2V
PECL Output High Voltage (2)
(PECLP, PECLN)
Single ended; 50Ω load to VCC-2V
Differential Input Resistance
Measured between DINP and DINN
VOH
LOS Output High Voltage
External 4.7-10 kΩ pull up to VCC
2.75
VCC
–
V
VOL
LOS Output Low Voltage
External 4.7-10 kΩ pull up to VCC
0
–
0.4
V
VIH
Logic Input High Voltage
JAM, RATESEL
2.7
–
VCC
V
VIL
Logic Input Low Voltage
JAM, RATESEL
–
–
0.8
V
RSSIavg
Average received signal
strength indicator range
5
–
2000
µA
VOUTLpecl
VOUTHpecl
RINDIFF
± 15% accuracy
Notes:
1. RATESEL high (high bandwidth operation). Typical supply current decreases by 1.5 mA in low rate mode.
2. Limits apply between 0°C to +85°C. Below 0 °C the minimum decreases by up to 40 mV.
02050-DSH-002-F
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Product Specification
1.4
AC Characteristics
VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, input bit rate = 2.5 Gbps 223-1 PRBS, high rate
mode (RATESEL = High) unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-4.
Symbol
VIN(MIN))
VI(MAX)
AC Characteristics
Parameter
Conditions
Differential Input Sensitivity
Min
Typ
Max
Units
1.25 Gbps, BER < 10-12, low rate mode
(RATESEL = low)
–
2
2.75
mV
2.125 Gbps, BER < 10-12, low rate mode
(RATESEL = low)
–
3
4.75
mV
2.5 Gbps, BER < 10-12
–
3.5
5
mV
1200
–
–
mV
600
–
–
mV
BER < 10-12, differential input 2.5 Gbps
Input Overload
BER < 10
-12
, single-ended input, 2.5 Gbps
RMS Input Referred Noise
RATESEL = high
–
280
–
µVRMS
Peak-to-peak received signal
strength indicator range
Differential input signal range
4
–
100
mV
BWLF
Small-Signal –3dB Low Frequency
Cutoff
Excluding AC coupling capacitors
–
25
–
kHz
DJ
Deterministic Jitter (includes DCD)
K28.5 pattern at 2.5 Gbps, 10 mVPP input
–
18
25
ps
RJ
Random Jitter
10 mVPP input
–
3.9
–
psRMS
vn
RSSIpp
110
145
125
180
Time from when rate select is asserted high or low
until amplifier is performing at selected bandwidth
–
–
10
µs
LOS Programmable Range
Differential inputs
5
–
55
mV
Signal Detect Hysteresis
electrical; across LOS programmable range
2
3.5
5.5
dB
Low Input LOS Assert threshold
RST = 7.50 kΩ, differential input
3.5
4.9
–
mVPP
–
7.8
11.3
mVPP
8.4
11.7
–
mVPP
RST = 6.81 kΩ, differential input
–
17.0
24.6
mVPP
RST = 6.19 kΩ, differential input
16.6
23.2
–
mVPP
–
33.4
48.4
mVPP
2.3
–
80
µs
Data Output Rise and Fall Times
TRATESEL
Rate select assert / deassert time
VLOS
HYS
DEASSERTLOW Low Input LOS De-Assert threshold RST = 7.50 kΩ, differential input
ASSERTMED
Medium Input LOS Assert threshold RST = 6.81 kΩ, differential input
DEASSERTMED Medium Input LOS De-Assert
threshold
ASSERTHI
DEASSERTHI
TLOS_ON
02050-DSH-002-F
ps
–
–
tr / tf
ASSERTLOW
20% to 80%; outputs terminated into 50 Ω;
10 mVPP input
RATESEL = High
RATESEL = Low
High Input LOS Assert threshold
High Input LOS De-Assert threshold RST = 6.19 kΩ, differential input
Time from LOS state until LOS
output is asserted (1)
LOS assert time after 1 VPP input signal is turned
off; signal detect level set to 10 mV
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Product Specification
Table 1-4.
Symbol
TLOS_OFF
AC Characteristics
Parameter
Conditions
Time from non-LOS state until LOS LOS deassert time after input crosses signal detect
is deasserted (2)
level; signal detect set to 10 mV with applied input
signal of 20 mVPP
Min
Typ
Max
Units
2.3
–
80
µs
Notes:
1. With VIN_DIFF = 1 VPP, typical times decrease as VIN_DIFF decreases.
2. With VIN_DIFF = 20 mVpp, typical times decrease as VIN_DIFF increases.
Figure 1-1.
Data Input Requirements
Differential Input
DINP
2 - 600 mV
DINN
4 - 1200 mV
Single-ended Input
DINP or DINN
Unused Input
NOTE:
02050-DSH-002-F
4 - 600 mV
For single-ended input connections.
When connecting to the used input with AC-coupling, the unused input should be AC-coupled
through 50 Ω to the supply voltage of the TIA;
When connecting to the used input with DC-coupling, the unused input should be DC-coupled
through 50 Ω to a voltage equal to the common mode level of the used input.
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Product Specification
1.5
Figure 1-2.
Typical Eye Diagrams
M02050 1.25 Gbps in Low Rate Mode
Figure 1-4.
10 mVPP differential input
1.25 Gbps
10 mVPP differential input
2.5 Gbps
160 mV/div
140 ps/div
Figure 1-3.
M02050 2.5 Gbps High Rate Mode
160 mV/div
80 ps/div
M02050 2.125 Gbps Low Rate Mode
10 mVPP differential input
2.125 Gbps
160 mV/div
80 ps/div
02050-DSH-002-F
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2.0 Pin Definitions
Table 2-1.
Pin Descriptions
QFN Pin#
Name
1
GND
Ground.
2
VCC
Power supply. Connect to either +5V or +3.3V.
3
PECLN
Inverting PECL data output.
4
PECLP
Non-inverting PECL data output.
5
IREF
6
STSET
Loss of signal threshold setting input. Connect a 1% resistor between this pin and VCC3 to set loss of signal
threshold.
7
VCC3
Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when VCC = 5V.
Connect directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power
supply if VCC = 5V.
8
RATESEL
Rate select. When low or floating, the device is in low-rate mode (data rates ≤ 1.25 Gbps) and has reduced
bandwidth. When high, the device is in full-rate mode with full bandwidth. Internal 80 kΩ resistor to ground.
Drive with a current limited source as described in Section 4.1.4.
9
DINP
Non-inverting data input. Internally terminated with 50 Ω to VTT (see Figure 3-2).
10
DINN
Inverting data input. Internally terminated with 50 Ω to VTT (see Figure 3-2).
11
GND
Ground.
12
RxAVGIN
13
JAM
Output disable. When high, data outputs are disabled (with non-inverting output held high and inverting
output held low). Connect to LOS output to disable outputs with loss of signal. Outputs are enabled when
JAM is low or floating. Internal 150 kΩ resistor to ground.
14
LOS
Loss of signal output. Goes high when input signal falls below threshold set by STSET. Open collector TTL with
internal 80 kΩ pull-up resistor to VCC.
15
RSSIAVG
Receiver average input power monitor. Provides a current source mirror of the current at RxAVGIN. Connect a
resistor to ground to set the full scale voltage to the desired level at maximum average input power.
16
RSSIPP
Receiver peak-to-peak input voltage monitor. Provides a DC voltage (ground referenced) proportional to the
peak-to-peak input voltage swing.
17
Center Pad
02050-DSH-002-F
Function
Internal LOS reference current. Must be connected to ground through a 12.1 kΩ 1% resistor.
Average power monitor input. Connect to monitor output of TIAs that produce a current (sink) mirror replica
of the photodiode current. Leave floating if not used.
Ground to PCB for thermal dissipation.
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Pin Definitions
16
1
12
VCC
PECLN
PECLP
13
Center Pad
GND
Connect to GND
DIN N
4
9
VCC3
STSET
IREF
DIN P
8
5
02050-DSH-002-F
RxAvgIN
RATESEL
GND
JAM
LOS
RSSIAVG
M02050-15 Pinout - 16 Pin (3 x 3 mm) QFN Top View
RSSIPP
Figure 2-1.
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3.0 Functional Description
3.1
Overview
The M02050-15 is an integrated high-gain limiting amplifier. The M2050 features PECL outputs and is intended for
use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02050-15
can operate with a 3.3V or 5V supply.
Rate select is supported for SFP applications and/or to achieve optimum sensitivity at data rates ≤ 1.25 Gbps.
When rate select is high, optimum sensitivity is achieved at 2.5 Gbps.
The M02050-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input signal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Figure 3-1.
Block Diagram Example
RATE SEL
REF
V
TT
DINP
DINN
Jam
I
Biasing
Limiting
Amplifier
Output
Buffer
PECLP
PECLN
Offset cancel
Level
Detect
RxAVGIN
RSSI
AVG
Level
Shift
RSSIPP
Threshold
Setting
Circuit
STSET
02050-DSH-002-F
LOS
Comparator
Regulator
V CC3
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V CC
8
Functional Description
3.2
•
•
•
•
•
•
•
•
•
•
Features
Operates with a 3.3V or 5V supply
3.5 mV typical input sensitivity at 2.5 Gbps
PECL outputs
Rate Selection for ≤ 1.25 Gbps operation
Average Receive power monitor output (RSSIAVG)
Peak-to-peak Receive power monitor output (RSSIPP)
On-chip DC offset cancellation circuit
Low power (< 180 mW at 3.3V)
Output Jam Function
16 pin 3x3 QFN package
3.3
General Description
The M02050-15 is a high-gain limiting amplifier for applications up to 2.5 Gbps, and incorporates a limiting amplifier, an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not
require any external components. The M02050-15 features PECL data outputs.
The M02050-15 provides the user with the flexibility to set the signal detect threshold. Optional output buffer disable (squelch/jam) can be implemented using the JAM input.
3.3.1
Inputs
The data inputs are internally connected to VTT via 50 Ω resistors, and generally need to be AC coupled. Referring
to Figure 3-2, the nominal VTT voltage is 2.85V because of the internal resistor divider to VCC3, which means this is
the DC potential on the data inputs. See the applications information section for further details on choosing the ACcoupling capacitor.
Figure 3-2.
CML Data Inputs
V
VCC3
CC
V CC
1.3 kΩ
VTT
50 Ω
50 Ω
8.3 kΩ
DINN
DINP
02050-DSH-002-F
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Functional Description
3.3.2
DC Offset Compensation
The M02050-15 contains an internal DC autozero circuit that can remove the effect of DC offsets without using
external components. This circuit is configured such that the feedback is effective only at frequencies well below
the lowest frequency of interest. The low frequency cut off is typically 25 kHz.
3.3.3
PECL Outputs
The M02050-15 features 100k/300k PECL compliant outputs as shown in Figure 3-3. The outputs may be terminated using any standard AC or DC-coupling PECL termination technique. AC-coupling is used in applications
where the average DC content of the data is zero e.g. SONET. The advantage of this approach is lower power consumption, no susceptibility to DC drive and compatibility with non-PECL interfaces.
Figure 3-3.
PECL Data Outputs
VCC
PECLP
PECLN
50 Ω
50 Ω
V CC - 2V
02050-DSH-002-F
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Functional Description
3.3.4
Loss of Signal (LOS)
The M02050-15 features input signal level detection over an extended range. Using an external resistor, RST,
between pin STSET and VCC3 (Figure 3-5) the user can program the input signal threshold. The signal detect status
is indicated on the LOS output pin shown in Figure 3-4. The LOS signal is active when the signal is below the
threshold value. The signal detection circuitry has the equivalent of 3.5 dB (typical) electrical hysteresis.
Figure 3-4.
LOS Output
VCC
LOS
80 kΩ
RST establishes a threshold voltage at the STSET pin as shown in Figure 3-5. Internally, the input signal level is
monitored by the Level Detector (which also outputs the RSSIPP voltage). As described in the RSSIPP section, this
voltage is proportional to the input signal peak to peak value. The voltage at STSET is internally compared to the
signal level from the Level Detector. When the Level Detect voltage is less than V(STSET), LOS is asserted and will
stay asserted until the input signal level increases by a predefined amount of hysteresis. When the input level
increases by more than this hysteresis above V(STSET), LOS is deasserted. See the applications information section for the selection of RST.
Note that STSET can be left open if the loss of signal detector function is not required. In this case LOS would be
low.
Figure 3-5.
STset Input
VCC3
VCC
RST
VSTSET
STSET
02050-DSH-002-F
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Functional Description
3.3.5
Peak to Peak Received Signal Strength Indicator (RSSIPP)
The RSSIPP output voltage is logarithmically proportional to the peak to peak level of the input signal. It is not necessary to connect an external capacitor to this output. Internally, the RSSI voltage is compared with a user selectable reference to determine loss of signal as described in the previous section.
Figure 3-6.
RSSIPP Output
VCC3
VCC
RSSIPP
4 kΩ
I(RSSIPP)
Figure 3-7.
Typical RSSIPP Transfer Function
275
250
225
V(RSSIPP) (mV)
200
175
150
125
100
75
50
25
0
0
25
50
75
100
125
150
175
200
Differential Input Level (mVPP)
02050-DSH-002-F
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Functional Description
Figure 3-8.
Typical RSSIPP Transfer Function (Low Input Level Range)
225
200
175
V(RSSIPP) (mV)
150
125
100
75
50
25
0
0
5
10
15
20
25
30
35
40
45
50
Differential Input Level (mVPP)
Figure 3-9.
Typical RSSIPP Transfer Function (Log Scale)
275
250
225
V(RSSIPP) (mV)
200
175
150
125
100
75
50
25
0
1
02050-DSH-002-F
10
Differential Input Level (mVPP)
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100
13
Functional Description
3.3.6
JAM Function
When asserted, the active high power down (JAM) pin forces the outputs to a logic “one” state. This ensures that
no data is propagated through the system. The loss of signal detection circuit can be used to automatically force
the data outputs to a high state when the input signal falls below the threshold. The function is normally used to
allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the
data outputs toggling due to noise when there is no signal present (“squelch”).
In order to implement this function, LOS should be connected to the JAM pin shown in Figure 3-10, thus forcing the
data outputs to a logic “one” state when the signal falls below the threshold.
3.3.7
Rate Select Function
When the RATESEL pin (shown in Figure 3-10) is driven high, the M02050-15 bandwidth is set to its maximum
which allows the M02050-15 to operate at data rates up to 2.5 Gbps. When operating at data rates ≤ 1.25 Gbps,
then RATESEL should be tied low or left floating. This enables low-rate mode which reduces the bandwidth (and
thus the noise level) of the part.
Figure 3-10. JAM and RATESEL Input
VCC
JAM or
R1
RATESEL
R2
R1 = 55 kΩ for JAM, 30 kΩ for RATESEL
R2 = 100 kΩ for JAM, 50 kΩ for RATESEL
02050-DSH-002-F
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Functional Description
3.3.8
Average Received Signal Strength Indicator (RSSIAVG)
The RSSIAVG output current is a mirrored version of the RxAVGIN current from compatible TIAs. It sources rather
than sinks the current making it compatible with DDMI type interfaces.
Figure 3-11. RSSIAVG Output
VCC
VCC3
RxAVGIN
RSSIAVG
(From TIA)
3.3.9
VCC
REXT
Voltage Regulation
The M02050-15 contains an on-chip voltage regulator to allow both 5V and 3.3V operation. When used at 5V, the
on-chip regulator is enabled and the digital inputs and outputs are compatible with TTL 5V logic levels.
02050-DSH-002-F
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4.0 Applications Information
4.1
•
•
•
•
•
Applications
2.5 Gbps STM-16/OC-48 SDH/SONET
1.06, 2.12 and 4.24 Gbps Fibre Channel
1.25 Gbps Ethernet
1.25 Gbps SDH/SONET
2.67 Gbps SDH/SONET with FEC
Figure 4-1.
Typical Applications Diagram
12.1 k Ω
RATE SELControl
+3.3 V
Jam
IREF
RATE SEL
V TT
optional
Biasing
AC-Coupled
to TIA
DINP
Photodiode
MON
PECLP
Limiting
Amplifier
M02013
TIA
Output
Buffer
DINN
Clock Data
Recovery
Unit
PECLN
Offset cancel
Level
Detect
RxAVGIN
RSSIAVG
REXT
02050-DSH-002-F
Level
Shift
Comparator
Threshold
Setting
Circuit
STSET
RST
Regulator
RSSIPP
AC or DC Coupled
(as described in
Applications Information)
LOS
V CC3 V CC
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Applications Information
4.1.1
Reference Current Generation
The M02050-15 contains an accurate on-chip bias circuit that requires an external 12.1 kΩ 1% resistor, RREF, from
pin IREF to ground to set the LOS threshold voltage at STSET precisely.
Figure 4-2.
Reference Current Generation
VCC3
RST
STSET
VSET
LOS
VLVL_Det
BG_Ref
IREF
RREF
4.1.2
Connecting VCC and VCC3
For 5V operation, the VCC pin is connected to an appropriate 5V ± 7.5% supply. No potential should be applied to
the VCC3 pin. The only connection to VCC3 should be RST as shown in Figure 3-5.
When VCC = 5V all logic outputs and the data outputs are 5V compatible while the CML data inputs are still referenced to 3.3V from the internal regulator (see Figure 3-2). For low power operation, VCC and VCC3 should be connected to an appropriate 3.3V ± 7.5% supply. In this case all I/Os are 3.3V compatible.
4.1.3
Choosing an Input AC-Coupling Capacitor
When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of
interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. For SONET
data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10,000) of the
input data rate. For example, for 2.5 Gbps data, the coupling capacitor should be chosen as:
fCUTOFF ≤ (2.5x109 / 10x103) = 250x103
The -3 dB cutoff frequency of the low pass filter at the 50 Ω input is found as:
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Applications Information
f3dB = 1/ (2 * π * 50 Ω * CAC)
so solving for C where f3dB = fCUTOFF
CAC = 1/ (2 * π * 50 Ω * fCUTOFF)
EQ.1
and in this case the minimum capacitor is 12 nF.
For Ethernet or Fibre Channel, there are less consecutive bits in the data, and the recommended cut-off frequency
is 1/(1,000) of the input data rate. This results in a minimum capacitor of 1.5 nF for 2.125 Gbps Fibre Channel.
Multirate applications down to 155 Mbps
In this case, the input coupling capacitor needs to be large enough to pass 15 kHz (155x106/10,000) which results
in a capacitor value of 0.2 µF. However, because this low pass frequency is close to the 25 kHz low pass frequency
of the internal DC servo loop, it is preferable to use a larger input coupling capacitor such as 1 µF which provides
an input cutoff frequency of 3.1 kHz. This separates the two poles sufficiently to allow them to be considered independent. This capacitor should also have a 10 nF capacitor in parallel to pass the higher frequency data (in the
multirate application) without distortion.
In all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input
data stream.
4.1.4
Using Rate Selection
Because of the performance of PECL outputs, the M02050-15 should not be used at data rates above 2.5 Gbps.
When the RATESEL pin (shown in Figure 3-10) is driven high, the M02050-15 bandwidth is set to its maximum
which allows the M02050-15 to operate at data rates up to 2.5 Gbps.
Because of the nature of the ESD structure on this pin, if it is driven by a device with IOL or IOH > 2 mA then a 1 kΩ
to 10 kΩ resistor should be used in series with the RATESEL pin. If rate selection is not used and the part is configured for high bandwidth only, the RATESEL pin should be connected to VCC using a 1 kΩ to 10 kΩ resistor. When
operating at data rates ≤ 1.25 Gbps, then RATESEL should be left floating (do not tie low). This enables low-rate
mode which reduces the bandwidth (and thus the noise level) of the part.
4.1.5
Using RSSIAVG
As shown in the typical applications circuit (Figure 4-1), when interfacing to a TIA that features a “MON” output
such as the M02013 or M02016, the M02050-15 can reference the current sunk into the TIA “MON” output and produce a proportional current at the M02050-15 RSSIAVG output. The current is sourced into resistor REXT to ground
creating a voltage suitable for DDMI applications. REXT should be chosen as:
REXT = 1/(maximum current into RSSIAVG)
EQ.2
This keeps the voltage at RSSIAVG between 0 and 1 V.
4.1.6
Setting the Signal Detect Level
Using Figure 4-3, the value for RST is chosen to set the LOS threshold at the desired value. The resulting hysteresis is also shown in Figure 4-3.
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Applications Information
From Figure 4-3, it is apparent that small variations in RST cause significant variation in the LOS threshold level,
particularly for low input signal levels. This is because of the logarithmic relationship between the RSSI voltage and
the input signal level. It is recommended that a 1% resistor be used for RST and that allowance is provided for LOS
variation, particularly when the LOS threshold is near the sensitivity limit of the M02050-15.
Example RST resistor values are given in Table 4-1.
Table 4-1.
Typical LOS Assert and De-assert Levels for Various 1% RST Resistor Values
VIN (mV pp) differential
RST (kΩ)
LOS Assert
LOS De-Assert
7.50
4.9
7.8
6.81
11.7
17.0
6.19
23.2
33.4
5.49
55.0
77.3
Figure 4-3.
Typical Loss of Signal Characteristic (Full Input Signal Range)
Threshold Level (mVPP)
80
70
Conditions:
60
2.5 Gbps, 231 - 1
50
Vcc = 3.3V, Temp = 25C
De-assert
40
Optical Hysteresis
30
= 10*log10(De-assert/Assert)
20
Assert
10
0
5.5
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5.7
5.9
6.1
6.3
6.5
6.7
RST (kΩ)
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7.1
7.3
7.5
19
Applications Information
Figure 4-4.
Typical Loss of Signal Characteristic (Low Input Signal Range)
30
Conditions:
Threshold Level (mVPP )
2.5 Gbps, 231 - 1
Vcc = 3.3V, Temp = 25C
20
De-assert
10
Assert
Optical Hysteresis = 10*log10(De-assert/Assert)
0
6.5
6.7
6.9
7.1
7.3
7.5
RST (kΩ)
Figure 4-5.
Typical Loss of Signal Characteristic (High Input Signal Range)
80
Conditions:
Threshold Level (mVPP)
70
2.5 Gbps, 231 - 1
60
Vcc = 3.3V, Temp = 25C
De-assert
50
40
30
Assert
Optical Hysteresis
20
= 10*log10(De-assert/Assert)
10
0
5.5
5.7
5.9
6.1
6.3
6.5
RST (kΩ)
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Applications Information
Figure 4-6.
Typical Loss of Signal Hysteresis Characteristic (Full Input Signal Range)
5.0
Electrical Hysteresis (dB)
4.5
Electrical Hysteresis = 20*log10(De-assert/Assert)
4.0
3.5
3.0
2.5
Conditions:
2.0
2.5 Gbps, 231 - 1
1.5
Vcc = 3.3V, Temp = 25C
1.0
0.5
0.0
5.5
4.1.7
5.7
5.9
6.1
6.3
6.5
6.7
RST (kΩ)
6.9
7.1
7.3
7.5
PECLP and PECLN Termination
The outputs of the M02050-15 are PECL compatible and any standard AC or DC-coupling termination technique
can be used. Figure 4-7 and Figure 4-8 illustrate typical AC and DC terminations.
AC-coupling is used in applications where the average DC content of the data is zero e.g. SONET. The advantage
of this approach is lower power consumption, no susceptibility to DC drift and compatibility with non-PECL interfaces. Figure 4-7 shows the circuit configuration and Table 4-2 lists the resistor values. If using transmission lines
other than 50 Ω, the shunt terminating resistance ZT should equal twice the impedance of the transmission line
(ZO).
DC-coupling can be used when driving PECL interfaces and has the advantage of a reduced component count. A
Thevenin termination is used at the receive end to give a 50 Ω load and the correct DC bias. Figure 4-8 shows the
circuit configuration and Table 4-2 the resistor values.
Alternatively, if available, terminating to VCC - 2V as shown in Figure 4-9 has the advantage that the resistance
value is the same for 3.3 V and 5 V operation and it also has performance advantages at high data rates.
Table 4-2.
PECL Termination Resistor Values
Supply
Output
Impedance
RPULL-DOWN
ZT
RTA / RTB
RT / RB
5V
50 Ω
270 Ω
100 Ω
2.7 kΩ / 7.8 kΩ
82 Ω / 130 Ω
3.3V
50 Ω
150 Ω
100 Ω
2.7 kΩ / 4.3 kΩ
130 Ω / 82 Ω
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Applications Information
Figure 4-7.
AC-Coupled PECL Termination
VCC
VCC
0.1µF
PECLP
RTA
Zo
R TA
ZT
PECLN
M02050
0.1µF
Zo
PECL
RTB
R TB
RPULL-DOWN
Figure 4-8.
DC-Coupled PECL Termination
VCC
VCC
10 nF
PECLP
Zo
RT
RT
PECL
M02050
Figure 4-9.
PECLN
Zo
RB
RB
Alternative PECL Termination
VCC
VCC
PECLP
Zo
PECL
M02050
PECLN
Zo
50 Ω
50 Ω
10 nF
VCC - 2V
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Applications Information
4.1.8
Using JAM
As shown in the typical applications circuit (Figure 4-1), the LOS output pin can optionally be connected to the Jam
input pin. When LOS asserts the Jam function sets the data outputs to a fixed “one” state (PECLP is held high and
PECLN is held low). This is normally used to allow data to propagate only when the signal is above the users' bit
error rate (BER) requirement. It prevents the outputs from toggling due to noise when no signal is present.
From the LOS assert and deassert figures above (Figure 4-3 - Figure 4-5), when an input signal is below the LOS
assert threshold, LOS asserts (LOS high) causing Jam to assert. When Jam asserts, the data outputs and the
internal servo loop of the M02050-15 are disabled. If the input signal reaches or exceeds the LOS deassert
threshold, LOS deasserts (LOS low) causing Jam to deassert, and hence enables the data outputs and the internal
servo loop. If, however, the input signal is slowly increasing to a level that does not exceed the LOS deassert
threshold (operating in the hysteresis region), the internal servo loop may not be fully established and this may
cause partial enabling of the data outputs. To avoid this the input signal needs to fully reach or exceed the LOS
deassert level to fully enable the data outputs.
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5.0 Package Specification
Figure 5-1.
Package Information
Note: View is for a 12 pin package. All dimensions in the
tables apply for the 16 pin package
16
4
4
1.35
1.35
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1.50
1.50
1.65
1.65
24
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