Lyontek LY62L20488AGL-70SLT 2048k x 8 bit low power cmos sram Datasheet

®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Description
Initial Issue
Add package “48-ball 8mm × 10mm TFBGA”
Revised ORDERING INFORMATION in page 11
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
Issue Date
Jan.09.2012
July.12.2013
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
FEATURES
GENERAL DESCRIPTION
„ Fast access time : 55/70ns
„ Low power consumption:
Operating current : 45/30mA (TYP.)
Standby current : 4μA (TYP.) SL-version
„ Single 2.7V ~ 3.6V power supply
„ All inputs and outputs TTL compatible
„ Fully static operation
„ Tri-state output
„ Data retention voltage : 1.2V (MIN.)
„ Green package available
„ Package : 44-pin 400 mil TSOP-II
48-ball 8mm x 10mm TFBGA
The LY62L20488A is a 16,777,216-bit low power
CMOS static random access memory organized as
2,097,152 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The LY62L20488A is well designed for very low
power system applications, and particularly well
suited for battery back-up nonvolatile memory
application.
The LY62L20488A operates from a single power
supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
LY62L20488A
LY62L20488A(I)
Operating
Temperature
0 ~ 70℃
-40 ~ 85℃
Vcc Range
Speed
2.7 ~ 3.6V
2.7 ~ 3.6V
55/70ns
55/70ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A20
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
4µA(SL)
45/30mA
4µA(SL)
45/30mA
2048Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 – A20
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#, CE2
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
PIN CONFIGURATION
44-pin TSOP(Type II)
48-ball 8mmx10mm TFBGA
A
NC
OE#
A0
A1
A2
CE2
B
NC
NC
A3
A4
CE#
NC
C
DQ0
NC
A5
A6
NC
DQ4
D
Vss DQ1 A17
A7
E
Vcc DQ2
F
DQ3
G
H
DQ5 Vcc
NC
A16 DQ6 Vss
NC
A14
A15
NC
A20
A12
A13 WE#
NC
A18
A8
A9
A10
A11
A19
1
2
3
4
TFBGA
5
6
NC
DQ7
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
SYMBOL
VT1
VT2
Operating Temperature
TA
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
RATING
-0.5 to 4.6
-0.5 to VCC+0.5
0 to 70(C grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
CE2
OE#
WE#
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
X
X
H
H
L
I/O OPERATION
High-Z
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
SUPPLY CURRENT
ISB,ISB1
ISB,ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
VCC
*1
Input High Voltage
VIH
*2
Input Low Voltage
VIL
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
Output Leakage
VCC ≧ VOUT ≧ VSS
ILO
Current
Output Disabled
Output High Voltage
VOH IOH = -1mA
Output Low Voltage
VOL
IOL = 2mA
Cycle time = Min.
- 55
CE# = VIL and CE2 = VIH
ICC
II/O = 0mA
- 70
Other pins at VIL or VIH
Average Operating
Power supply Current
Cycle time = 1µs
CE#≦0.2V and CE2≧VCC-0.2V
ICC1
II/O = 0mA
Other pins at 0.2V or VCC-0.2V
CE# = VIH or CE2 = VIL
ISB
Other pins at VIL or VIH
*5
25℃
SL
CE# ≧VCC-0.2V
Standby Power
*5
SLI
Supply Current
40℃
or CE2≦0.2V
ISB1
Other pins at 0.2V
SL
or VCC-0.2V
SLI
MIN.
2.7
2.2
- 0.2
-1
TYP.
3.0
-
*4
MAX.
3.6
VCC+0.3
0.6
1
UNIT
V
V
V
µA
-1
-
1
µA
2.2
-
2.7
-
0.4
V
V
-
45
60
mA
-
30
45
mA
-
8
16
mA
-
0.3
2
mA
-
4
4
4
4
10
10
30
40
µA
µA
µA
µA
Notes:
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
MAX
6
8
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
UNIT
pF
pF
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
LY62L20488A-55
MIN.
MAX.
55
55
55
30
10
5
20
20
10
-
LY62L20488A-70
MIN.
MAX.
70
70
70
35
10
5
25
25
10
-
UNIT
LY62L20488A-55
MIN.
MAX.
55
50
50
0
45
0
25
0
5
20
LY62L20488A-70
MIN.
MAX.
70
60
60
0
55
0
30
0
5
25
UNIT
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
CE2
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
VCC for Data Retention
VDR
1.2
CE# ≧ VCC - 0.2V or CE2≦0.2V
SL 25℃
VCC = 1.2V
SLI 40℃
Data Retention Current
IDR
CE# ≧VCC-0.2V or CE2≦0.2V
SL
Other pins at 0.2V or VCC-0.2V
SLI
See Data Retention
Chip Disable to Data
0
tCDR
Waveforms (below)
Retention Time
Recovery Time
tR
tRC*
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.2V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.2V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE2
tR
CE2 ≦ 0.2V
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
TYP.
2.5
2.5
2.5
2.5
MAX.
3.6
10
10
30
40
UNIT
V
µA
µA
µA
µA
-
-
ns
-
-
ns
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP-II Package Outline Dimension
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
ZD
y
Θ
DIMENSIONS IN MILLMETERS
MIN.
NOM.
MAX.
1.20
0.05
0.10
0.15
0.95
1.00
1.05
0.30
0.45
0.12
0.21
18.212
18.415
18.618
11.506
11.760
12.014
9.957
10.160
10.363
0.800
0.40
0.50
0.60
0.805
0.076
o
o
o
3
6
0
DIMENSIONS IN MILS
MIN.
NOM.
MAX.
47.2
2.0
3.9
5.9
37.4
39.4
41.3
11.8
17.7
4.7
8.3
717
725
733
453
463
473
392
400
408
31.5
15.7
19.7
23.6
31.7
3
o
o
o
0
3
6
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY62L20488A
Rev. 1.1
2048K X 8 BIT LOW POWER CMOS SRAM
48-ball 8mm × 10mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY62L20488A
2048K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
ORDERING INFORMATION
Package Type
44Pin(400mil)
TSOP-II
Access Time
(Speed)(ns)
55
Temperature
Range(℃)
0℃~70℃
-40℃~85℃
70
0℃~70℃
-40℃~85℃
48-ball(8mmx10mm)
TFBGA
55
0℃~70℃
-40℃~85℃
70
0℃~70℃
-40℃~85℃
Packing
Type
Tray
LY62L20488AML-55SL
Tape Reel
LY62L20488AML-55SLT
Tray
LY62L20488AML-55SLI
Tape Reel
LY62L20488AML-55SLIT
Tray
LY62L20488AML-70SL
Tape Reel
LY62L20488AML-70SLT
Tray
LY62L20488AML-70SLI
Tape Reel
LY62L20488AML-70SLIT
Tray
LY62L20488AGL-55SL
Tape Reel
LY62L20488AGL-55SLT
Tray
LY62L20488AGL-55SLI
Tape Reel
LY62L20488AGL-55SLIT
Tray
LY62L20488AGL-70SL
Tape Reel
LY62L20488AGL-70SLT
Tray
LY62L20488AGL-70SLI
Tape Reel
LY62L20488AGL-70SLIT
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
Lyontek Item No.
®
LY62L20488A
Rev. 1.1
2048K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
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