Cypress MB95F698KPMC1-G-UNE2 New 8fx 8-bit microcontroller Datasheet

MB95690K Series
New 8FX 8-bit Microcontrollers
The MB95690K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral functions.
Features
■
■
❐
F2MC-8FX CPU core
❐ Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
■
■
Clock
Selectable main clock source
• Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
• External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
• Main CR clock (4 MHz ±2%)
• Main CR PLL clock
- The main CR PLL clock frequency becomes 8 MHz
±2% when the PLL multiplication rate is 2.
- The main CR PLL clock frequency becomes 10 MHz
±2% when the PLL multiplication rate is 2.5.
- The main CR PLL clock frequency becomes 12 MHz
±2% when the PLL multiplication rate is 3.
- The main CR PLL clock frequency becomes 16 MHz
±2% when the PLL multiplication rate is 4.
❐ Selectable subclock source
• Suboscillation clock (32.768 kHz)
• External clock (32.768 kHz)
• Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
Timer
8/16-bit composite timer × 2 channels
❐ 8/16-bit PPG × 3 channels
❐ 16-bit PPG timer × 1 channel (can work independently or
together with the multi-pulse generator)
❐ 16-bit reload timer × 1 channel (can work independently or
together with the multi-pulse generator)
❐ Time-base timer × 1 channel
❐ Watch prescaler × 1 channel
UART/SIO × 1 channel
❐ Full duplex double buffer
❐ Capable of clock asynchronous (UART) serial data transfer
and clock synchronous (SIO) serial data transfer
■
8/10-bit A/D converter
LQF044: 8 channels
❐ LQA048, LQC052, WNR048: 12 channels
❐ 8-bit or 10-bit resolution can be selected.
❐
■
Low power consumption (standby) modes
There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
❐ In standby mode, two further options can be selected: normal
standby mode and deep standby mode.
❐
■
I/O port
LQF044 (number of I/O ports: 41)
• General-purpose I/O ports (CMOS I/O):37
• General-purpose I/O ports (N-ch open drain):4
❐ LQA048, LQC052, WNR048 (number of I/O ports: 45)
• General-purpose I/O ports (CMOS I/O):41
• General-purpose I/O ports (N-ch open drain):4
❐
■
On-chip debug
1-wire serial control
❐ Serial writing supported (asynchronous mode)
❐
■
Hardware/software watchdog timer
Built-in hardware watchdog timer
❐ Built-in software watchdog timer
❐
■
Power-on reset
A power-on reset is generated when the power is switched
on.
❐
■
I2C bus interface × 1 channel
❐ Built-in wake-up function
■
Multi-pulse generator (MPG) (for DC motor control) × 1 channel
❐ 16-bit reload timer × 1 channel
❐ 16-bit PPG timer × 1 channel
Cypress Semiconductor Corporation
Document Number: 002-04692 Rev. *E
External interrupt
LQF044: 7 channels
❐ LQA048, LQC052, WNR048: 8 channels
❐ Interrupt by edge detection (rising edge, falling edge, and
both edges can be selected)
❐ Can be used to wake up the device from different low power
consumption (standby) modes
❐
❐
■
LIN-UART
Full duplex double buffer
❐ Capable of clock asynchronous serial data transfer and clock
synchronous serial data transfer
❐
❐
■
Waveform sequencer (including a 16-bit timer equipped with
a buffer and a compare clear function)
•
■
198 Champion Court
Low-voltage detection (LVD) reset circuit
The LVD function is enabled by default. For details, see “20.2
Recommended Operating Conditions” in
“Electrical Characteristics”.
❐ The LVD function can be controlled through software.
❐
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 27, 2017
MB95690K Series
The LVD reset circuit control register (LVDCC) enables or
disables the LVD reset.
❐ The LVD reset circuit has an internal low-voltage detector.
The combination of detection voltage and release voltage
can be selected from four options.
❐
■
Comparator × 2 channels
Built-in dedicated BGR
❐ The comparator reference voltage can be selected between
the BGR voltage and the comparator pin.
❐
Document Number: 002-04692 Rev. *E
■
Clock supervisor counter
Built-in clock supervisor counter
❐
■
Dual operation Flash memory
The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simultaneously.
❐
■
Flash memory security function
Protects the content of the Flash memory.
❐
Page 2 of 129
MB95690K Series
Contents
Features............................................................................. 1
1. Product Line-up ............................................................ 4
15. Areas For Specific Applications ............................. 34
16. I/O Map....................................................................... 35
6. Pin Functions (LQA048, LQC052, WNR048.............. 16
17. I/O Ports.....................................................................
17.1 Port 0.................................................................
17.2 Port 1.................................................................
17.3 Port 4.................................................................
17.4 Port 6.................................................................
17.5 Port 7.................................................................
17.6 Port F.................................................................
17.7 Port G ................................................................
7. I/O Circuit Type ........................................................... 21
18. Interrupt Source Table ............................................. 80
8. Handling Precautions.................................................
8.1 Precautions for Product Design...........................
8.2 Precautions for Package Mounting .....................
8.3 Precautions for Use Environment........................
19. Pin States In Each Mode .......................................... 81
2. Packages And Corresponding Products.................... 6
3. Differences Among Products And Notes On
Product Selection ............................................................. 7
4. Pin Assignment ............................................................ 8
5. Pin Functions (LQF044 .............................................. 12
23
23
24
26
9. Notes On Device Handling......................................... 26
10. Pin Connection ......................................................... 27
11. Block Diagram (LQF044 ........................................... 29
12. Block Diagram (LQA048, LQC052, WNR048 .......... 30
13. CPU Core................................................................... 31
14. Memory Space ..........................................................
14.1 I/O area (addresses: 0x0000 to 0x007F)...........
14.2 Extended I/O area
(addresses: 0x0F80 to 0x0FFF) ................................
14.3 Data area...........................................................
14.4 Program area ....................................................
14.5 Memory space map...........................................
Document Number: 002-04692 Rev. *E
32
32
32
32
32
33
42
43
50
55
62
67
74
77
20. Electrical Characteristics......................................... 84
20.1 Absolute Maximum Ratings............................... 84
20.2 Recommended Operating Conditions ............... 86
20.3 DC Characteristics ............................................ 87
20.4 AC Characteristics............................................. 90
20.5 A/D Converter................................................. 109
20.6 Flash Memory Program/Erase Characteristics 113
21. Sample Characteristics.......................................... 114
22. Ordering Information.............................................. 121
23. Package Dimension................................................ 122
24. Major Changes In This Edition .............................. 126
Document History Page ............................................... 127
Sales, Solutions, and Legal Information .................... 129
Page 3 of 129
MB95690K Series
1. Product Line-up
Part number
MB95F694K
MB95F696K
MB95F698K
Parameter
Type
Clock
supervisor
counter
Flash memory product
It supervises the main clock oscillation and the subclock oscillation.
Flash memory
capacity
20 Kbyte
36 Kbyte
60 Kbyte
RAM capacity
512 bytes
1 Kbyte
2 Kbyte
Power-on reset
Yes
Low-voltage
detection reset
Controlled through software
Reset input
Selected through software
•
•
•
CPU functions
•
•
•
Generalpurpose I/O
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
: 61.5 ns (machine clock frequency = 16.25 MHz)
: 0.6 µs (machine clock frequency = 16.25 MHz)
• LQF044
- I/O port
: 41
- CMOS I/O
: 37
- N-ch open drain
:4
• LQA048, LQC052, WNR048
- I/O port
: 45
- CMOS I/O
: 41
- N-ch open drain
:4
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
Hardware/
• Reset generation cycle
software
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the software watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
LIN-UART
•
•
•
•
8/10-bit
A/D converter
A wide range of communication speed can be selected by a dedicated reload timer.
It has a full duplex double buffer.
Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled.
The LIN function can be used as a LIN master or a LIN slave.
• LQF044: 8 channels
• LQA048, LQC052, WNR048: 12 channels
8-bit or 10-bit resolution can be selected.
Document Number: 002-04692 Rev. *E
Page 4 of 129
MB95690K Series
Part number
MB95F694K
MB95F696K
MB95F698K
Parameter
2 channels
• The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.
8/16-bit
• It has the following functions: interval timer function, PWC function, PWM function and input capture
composite timer function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
External
interrupt
On-chip debug
• LQF044: 7 channels
• LQA048, LQC052, WNR048: 8 channels
• Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.)
• It can be used to wake up the device from different standby modes.
• 1-wire serial control
• It supports serial writing (asynchronous mode).
1 channel
UART/SIO
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator
and an error detection function.
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer
are enabled.
1 channel
I2C bus
interface
• Master/slave transmission and reception
• It has the following functions: bus error function, arbitration function, transmission direction detection
function, wake-up function, and functions of generating and detecting repeated START conditions.
3 channels
8/16-bit PPG
• Each channel can be used as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.
• The counter operating clock can be selected from eight clock sources.
1 channel
16-bit PPG
timer
•
•
•
•
PWM mode and one-shot mode are available to use.
The counter operating clock can be selected from eight clock sources.
It supports external trigger start.
It can work independently or together with the multi-pulse generator.
1 channel
16-bit reload
timer
Multi-pulse
generator (for
DC motor
control)
•
•
•
•
•
Two clock modes and two counter operating modes are available to use.
It can output square wave.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
Two counter operating modes: reload mode and one-shot mode
It can work independently or together with the multi-pulse generator.
•
•
•
•
16-bit PPG timer: 1 channel
16-bit reload timer operations: toggle output, one-shot output
Event counter: 1 channel
Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function)
Document Number: 002-04692 Rev. *E
Page 5 of 129
MB95690K Series
Part number
MB95F694K
MB95F696K
MB95F698K
Parameter
Watch prescaler Eight different time intervals can be selected.
2 channels
Comparator
Flash memory
The reference voltage of each channel can be selected between the BGR voltage and the comparator
pin.
• It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
20 years
10000
10 years
100000
5 years
There are four standby modes as follows:
• Stop mode
• Sleep mode
Standby mode
• Watch mode
• Time-base timer mode
In standby mode, two further options can be selected: normal standby mode and deep standby mode.
LQF044
LQA048
LQC052
WNR048
Package
2. Packages And Corresponding Products
Part number
MB95F694K
MB95F696K
MB95F698K
LQF044
Ο
Ο
Ο
LQA048
Ο
Ο
Ο
LQC052
Ο
Ο
Ο
WNR048
Ο
Ο
Ο
Package
Ο: Available
Document Number: 002-04692 Rev. *E
Page 6 of 129
MB95690K Series
3. Differences Among Products And Notes On Product Selection
• Current consumption
When using the on-chip debug function, take account of the current consumption of Flash memory program/erase.
For details of current consumption, see “Electrical Characteristics”.
• Package
For details of information on each package, see “Packages And Corresponding Products” and “Package Dimension”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of operating voltage, see “Electrical Characteristics”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details
of the connection method, refer to “CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New
8FX MB95690K Series Hardware Manual”.
Document Number: 002-04692 Rev. *E
Page 7 of 129
MB95690K Series
Vss
PG2/X1A/SNI2
1
2
PG1/X0A/SNI1
Vcc
C
P40/AN08
3
4
5
6
7
8
P67*1/OPT5/PPG21*2/TRG1
P01/INT01/AN01/CMP0_N
P00/INT00/AN00/CMP0_P
P03/INT03/AN03/CMP1_P
38
37
36
35
34
39
PF1/X1
PF0/X0
PF2/RST
P06/INT06/AN06
P05/INT05/AN05/CMP1_O
P04/INT04/AN04/CMP1_N
44
43
42
41
40
28
27
FPT-44P-M25
26
25
24
23
9
10
21
P72/SCL
P73/SDA
P66*1/OPT4/PPG20*2/PPG1
P65*1/OPT3/PPG11*2
P64*1/OPT2/PPG10*2/EC1
P63*1/OPT1/PPG01*2/TO11
P62*1/OPT0/PPG00*2/TO10
P61*1/TI1
P60*1/DTTI
P77/UI0
P76/UO0
P75/UCK0
P74/EC0
22
20
P71/TO01
P70/TO00
17
18
19
P15/PPG20*2
P14/PPG01*2
P11/PPG11*2
P12/DBG
P16/PPG21*2
P17/SNI0
11
12
P46/SOT
P47/SIN
P10/PPG10*2
31
30
29
(TOP VIEW)
LQFP44
P13/PPG00*2
P45/SCK
33
32
13
14
15
16
P44/TO1
P02/INT02/AN02/CMP0_O
4. Pin Assignment
*1: High-current pin (8 mA/12 mA)
*2: The 8/16-bit PPG output pins are mapped to port 1 by default. To map the 8/16-bit PPG output pins to port 6, write
“1” to the PPGSEL bit in the SYSC register.
Document Number: 002-04692 Rev. *E
Page 8 of 129
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
1
2
3
C
P40/AN08
P41/AN09
P42/AN10
P43/AN11
4
5
6
7
8
Vss
PF1/X1
PF0/X0
PF2/RST
P07/INT07/AN07
P06/INT06/AN06
P05/INT05/AN05/CMP1_O
P04/INT04/AN04/CMP1_N
P03/INT03/AN03/CMP1_P
P02/INT02/AN02/CMP0_O
P01/INT01/AN01/CMP0_N
P00/INT00/AN00/CMP0_P
48
47
46
45
44
43
42
41
40
39
38
37
MB95690K Series
(TOP VIEW)
LQFP48
LQA048-02
36
35
34
33
P67*1/OPT5/PPG21*2/TRG1
P66*1/OPT4/PPG20*2/PPG1
32
31
30
29
P63*1/OPT1/PPG01*2/TO11
P62*1/OPT0/PPG00*2/TO10
P61*1/TI1
P60*1/DTTI
P65*1/OPT3/PPG11*2
P64*1/OPT2/PPG10*2/EC1
23
24
P73/SDA
P16/PPG21*2
P15/PPG20*2
P12/DBG
P13/PPG00*2
P11/PPG11*2
P72/SCL
P74/EC0
22
25
P71/TO01
12
20
P75/UCK0
P47/SIN
21
26
P17/SNI0
11
P70/TO00
P76/UO0
P46/SOT
17
18
19
P77/UI0
27
P14/PPG01*2
28
13
14
15
16
9
10
P10/PPG10*2
P44/TO1
P45/SCK
*1: High-current pin (8 mA/12 mA)
*2: The 8/16-bit PPG output pins are mapped to port 1 by default. To map the 8/16-bit PPG output pins to port 6, write
“1” to the PPGSEL bit in the SYSC register.
Document Number: 002-04692 Rev. *E
Page 9 of 129
PG2/X1A/SNI2
PG1/X0A/SNI1
1
2
Vcc
C
P40/AN08
P41/AN09
NC
P42/AN10
P43/AN11
3
4
5
6
7
8
9
P02/INT02/AN02/CMP0_O
P01/INT01/AN01/CMP0_N
42
41
40
P00/INT00/AN00/CMP0_P
P03/INT03/AN03/CMP1_P
43
44
Vss
PF1/X1
PF0/X0
PF2/RST
P07/INT07/AN07
P06/INT06/AN06
NC
P05/INT05/AN05/CMP1_O
P04/INT04/AN04/CMP1_N
52
51
50
49
48
47
46
45
MB95690K Series
(TOP VIEW)
LQFP52
LQC052
39
38
37
36
P67*1/OPT5/PPG21*2/TRG1
P66*1/OPT4/PPG20*2/PPG1
35
34
33
32
P63*1/OPT1/PPG01*2/TO11
P62*1/OPT0/PPG00*2/TO10
31
P60*1/DTTI
P65*1/OPT3/PPG11*2
P64*1/OPT2/PPG10*2/EC1
NC
P61*1/TI1
P76/UO0
P46/SOT
12
13
28
27
P75/UCK0
P74/EC0
P73/SDA
24
25
26
P71/TO01
P72/SCL
P70/TO00
P17/SNI0
P15/PPG20*2
NC
P16/PPG21*2
P14/PPG01*2
P12/DBG
P13/PPG00*2
P10/PPG10*2
P11/PPG11*2
14
15
16
P47/SIN
22
23
P77/UI0
29
21
30
20
10
11
17
18
19
P44/TO1
P45/SCK
*1: High-current pin (8 mA/12 mA)
*2: The 8/16-bit PPG output pins are mapped to port 1 by default. To map the 8/16-bit PPG output pins to port 6, write
“1” to the PPGSEL bit in the SYSC register.
Document Number: 002-04692 Rev. *E
Page 10 of 129
PG2/X1A/SNI2
PG1/X0A/SNI1
1
2
Vcc
C
3
4
P40/AN08
P41/AN09
5
6
P42/AN10
P43/AN11
Vss
PF1/X1
PF0/X0
PF2/RST
P07/INT07/AN07
P06/INT06/AN06
P05/INT05/AN05/CMP1_O
P04/INT04/AN04/CMP1_N
P03/INT03/AN03/CMP1_P
P02/INT02/AN02/CMP0_O
P01/INT01/AN01/CMP0_N
P00/INT00/AN00/CMP0_P
48
47
46
45
44
43
42
41
40
39
38
37
MB95690K Series
(TOP VIEW)
QFN48
36
35
34
33
P67*1/OPT5/PPG21*2/TRG1
P66*1/OPT4/PPG20*2/PPG1
P65*1/OPT3/PPG11*2
32
31
30
29
P63*1/OPT1/PPG01*2/TO11
P62*1/OPT0/PPG00*2/TO10
P64*1/OPT2/PPG10*2/EC1
P61*1/TI1
P60*1/DTTI
P44/TO1
7
8
9
28
P77/UI0
P45/SCK
10
27
P76/UO0
P46/SOT
11
26
P75/UCK0
P47/SIN
12
25
P74/EC0
22
23
24
P72/SCL
P73/SDA
21
P70/TO00
P71/TO01
20
P17/SNI0
P16/PPG21*2
P15/PPG20*2
17
18
19
P14/PPG01*2
P12/DBG
P13/PPG00*2
13
14
15
16
P11/PPG11*2
P10/PPG10*2
LCC-48P-M11
*1: High-current pin (8 mA/12 mA)
*2: The 8/16-bit PPG output pins are mapped to port 1 by default. To map the 8/16-bit PPG output pins to port 6, write
“1” to the PPGSEL bit in the SYSC register.
Document Number: 002-04692 Rev. *E
Page 11 of 129
MB95690K Series
5. Pin Functions (LQF044)
Pin no.
1
I/O
Pin name circuit
type*1
VSS
—
PG2
2
3
X1A
C
SNI2
PG1
General-purpose I/O port
X0A
VCC
5
C
8
9
10
11
12
13
14
15
16
17
Subclock I/O oscillation pin
Trigger input pin for the position detection
function of the MPG waveform sequencer
4
7
Power supply pin (GND)
P40
AN08
P44
TO1
P45
SCK
P46
SOT
P47
SIN
P10
PPG10
P11
PPG11
P12
DBG
P13
PPG00
P14
PPG01
P15
PPG20
P16
PPG21
Input
—
Output OD*2 PU*3
—
—
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
—
—
—
—
Hysteresis/
CMOS
analog
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
Ο
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
General-purpose I/O port
C
SNI1
6
I/O type
Function
—
—
E
F
F
F
I
F
F
G
F
F
F
F
Subclock input oscillation pin
Trigger input pin for the position detection
function of the MPG waveform sequencer
Power supply pin
Decoupling capacitor connection pin
General-purpose I/O port
8/10-bit A/D converter analog input pin
General-purpose I/O port
16-bit reload timer ch. 1 output pin
General-purpose I/O port
LIN-UART clock I/O pin
General-purpose I/O port
LIN-UART data output pin
General-purpose I/O port
LIN-UART data input pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
DBG input pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 2 output pin
General-purpose I/O port
8/16-bit PPG ch. 2 output pin
Document Number: 002-04692 Rev. *E
—
—
CMOS
—
—
Page 12 of 129
MB95690K Series
Pin no.
I/O
Pin name circuit
type*1
P17
18
19
20
21
22
23
24
25
26
27
28
29
SNI0
P70
TO00
P71
TO01
P72
SCL
P73
SDA
P74
EC0
P75
UCK0
P76
UO0
P77
UI0
P60
F
F
F
H
H
F
F
F
I
D
Trigger input pin for the position detection
function of the MPG waveform sequencer
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
I2C bus interface ch. 0 clock I/O pin
General-purpose I/O port
I2C bus interface ch. 0 data I/O pin
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
High-current pin
DTTI
MPG waveform sequencer input pin
P61
General-purpose I/O port
High-current pin
D
TI1
16-bit reload timer ch. 1 input pin
P62
General-purpose I/O port
High-current pin
OPT0
D
TO11
MPG waveform sequencer output pin
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
CMOS
CMOS
Ο
—
CMOS
CMOS
Ο
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
High-current pin
P63
PPG01
Output OD*2 PU*3
8/16-bit PPG ch. 0 output pin
TO10
OPT1
Input
General-purpose I/O port
PPG00
30
I/O type
Function
D
MPG waveform sequencer output pin
8/16-bit PPG ch. 0 output pin
8/16-bit composite timer ch. 1 output pin
Document Number: 002-04692 Rev. *E
Page 13 of 129
MB95690K Series
Pin no.
I/O
Pin name circuit
type*1
OPT2
D
PPG10
32
8/16-bit composite timer ch. 1 clock input pin
P65
General-purpose I/O port
High-current pin
D
35
D
PPG1
16-bit PPG timer ch. 1 output pin
D
8/16-bit PPG ch. 2 output pin
TRG1
16-bit PPG timer ch. 1 trigger input pin
P00
General-purpose I/O port
INT00
External interrupt input pin
E
8/10-bit A/D converter analog input pin
P01
General-purpose I/O port
INT01
External interrupt input pin
AN01
INT02
AN02
E
8/10-bit A/D converter analog input pin
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
General-purpose I/O port
E
External interrupt input pin
8/10-bit A/D converter analog input pin
Comparator ch. 0 digital output pin
P03
General-purpose I/O port
INT03
External interrupt input pin
CMP1_P
—
Comparator ch. 0 inverting analog input
(negative input) pin
CMP0_O
AN03
Hysteresis CMOS
Comparator ch. 0 non-inverting analog input
(positive input) pin
P02
38
MPG waveform sequencer output pin
PPG21
AN00
Ο
General-purpose I/O port
High-current pin
CMP0_N
37
MPG waveform sequencer output pin
8/16-bit PPG ch. 2 output pin
CMP0_P
36
MPG waveform sequencer output pin
PPG20
OPT5
—
General-purpose I/O port
High-current pin
P67
34
Hysteresis CMOS
8/16-bit PPG ch. 1 output pin
P66
OPT4
Output OD*2 PU*3
8/16-bit PPG ch. 1 output pin
PPG11
33
MPG waveform sequencer output pin
EC1
OPT3
Input
General-purpose I/O port
High-current pin
P64
31
I/O type
Function
E
8/10-bit A/D converter analog input pin
Comparator ch. 1 non-inverting analog input
(positive input) pin
Document Number: 002-04692 Rev. *E
Page 14 of 129
MB95690K Series
Pin no.
39
General-purpose I/O port
INT04
External interrupt input pin
AN04
E
INT05
AN05
E
43
44
RST
PF0
X0
PF1
X1
External interrupt input pin
8/10-bit A/D converter analog input pin
General-purpose I/O port
E
AN06
PF2
CMOS
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis CMOS
Ο
—
Hysteresis CMOS
—
—
Hysteresis CMOS
—
—
Comparator ch. 1 digital output pin
P06
42
CMOS/
analog
Output OD*2 PU*3
General-purpose I/O port
CMP1_O
INT06
8/10-bit A/D converter analog input pin
Input
Comparator ch. 1 inverting analog input
(negative input) pin
P05
41
Function
P04
CMP1_N
40
I/O type
I/O
Pin name circuit
type*1
External interrupt input pin
8/10-bit A/D converter analog input pin
A
B
B
General-purpose I/O port
Reset pin
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Ο: Available
*1: For the I/O circuit types, see “I/O Circuit Type”.
*2: N-ch open drain
*3: Pull-up
Document Number: 002-04692 Rev. *E
Page 15 of 129
MB95690K Series
6. Pin Functions (LQA048, LQC052, WNR048)
Pin no.
I/O
circuit
Pin
name
LQFP48* ,
LQFP52*3
type*4
QFN48*2
1
PG2
2
1
Output OD*5 PU*6
Subclock I/O oscillation pin
C
SNI2
Trigger input pin for the position
detection function of the MPG
waveform sequencer
PG1
General-purpose I/O port
X0A
Subclock input oscillation pin
2
Input
General-purpose I/O port
X1A
1
I/O type
Function
C
SNI1
Trigger input pin for the position
detection function of the MPG
waveform sequencer
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
3
3
VCC
—
Power supply pin
—
—
—
—
4
4
C
—
Decoupling capacitor connection
pin
—
—
—
—
5
5
Hysteresis/
CMOS
analog
—
Ο
6
6
Hysteresis/
CMOS
analog
—
Ο
—
7
—
—
7
8
Hysteresis/
CMOS
analog
—
Ο
8
9
Hysteresis/
CMOS
analog
—
Ο
9
10
Hysteresis CMOS
—
Ο
10
11
Hysteresis CMOS
—
Ο
11
12
Hysteresis CMOS
—
Ο
12
13
CMOS
—
Ο
13
14
Hysteresis CMOS
—
Ο
P40
AN08
General-purpose I/O port
E
P41
AN09
NC
General-purpose I/O port
E
—
P42
AN10
P45
SCK
P46
SOT
P47
SIN
P10
PPG10
Document Number: 002-04692 Rev. *E
It is an internally connected pin.
Always leave it unconnected.
8/10-bit A/D converter analog
input pin
General-purpose I/O port
E
P44
TO1
8/10-bit A/D converter analog
input pin
General-purpose I/O port
E
P43
AN11
8/10-bit A/D converter analog
input pin
8/10-bit A/D converter analog
input pin
—
—
General-purpose I/O port
F
F
F
I
F
16-bit reload timer ch. 1 output
pin
General-purpose I/O port
LIN-UART clock I/O pin
General-purpose I/O port
LIN-UART data output pin
General-purpose I/O port
LIN-UART data input pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
CMOS
Page 16 of 129
MB95690K Series
I/O type
Pin no.
I/O
circuit
Pin
name
LQFP48* ,
LQFP52*3
type*4
QFN48*2
1
14
15
15
16
16
17
17
18
18
19
—
20
19
21
P11
PPG11
P12
DBG
P13
PPG00
P14
PPG01
P15
PPG20
NC
P16
PPG21
F
G
F
F
F
—
F
P17
20
22
SNI0
23
TO00
F
24
TO01
F
25
SCL
F
26
SDA
H
27
26
28
27
29
EC0
P75
UCK0
P76
UO0
Document Number: 002-04692 Rev. *E
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 2 output pin
It is an internally connected pin.
Always leave it unconnected.
General-purpose I/O port
8/16-bit PPG ch. 2 output pin
Ο
Hysteresis CMOS
Ο
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
—
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
—
—
Trigger input pin for the position
detection function of the MPG
waveform sequencer
8/16-bit composite timer ch. 0
output pin
8/16-bit composite timer ch. 0
output pin
I2C bus interface ch. 0 clock I/O
pin
CMOS
CMOS
Ο
—
CMOS
CMOS
Ο
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
General-purpose I/O port
H
P74
25
DBG input pin
—
General-purpose I/O port
P73
24
General-purpose I/O port
Hysteresis CMOS
General-purpose I/O port
P72
23
8/16-bit PPG ch. 1 output pin
Output OD*5 PU*6
General-purpose I/O port
P71
22
General-purpose I/O port
Input
General-purpose I/O port
P70
21
Function
I2C bus interface ch. 0 data I/O
pin
General-purpose I/O port
F
F
F
8/16-bit composite timer ch. 0
clock input pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
Page 17 of 129
MB95690K Series
Pin no.
I/O
circuit
Pin
name
LQFP48* ,
LQFP52*3
type*4
QFN48*2
1
28
30
P77
UI0
I
P60
29
30
31
32
D
33
34
35
General-purpose I/O port
High-current pin
D
NC
OPT0
—
34
36
37
It is an internally connected pin.
Always leave it unconnected.
D
MPG waveform sequencer
output pin
8/16-bit PPG ch. 0 output pin
TO10
8/16-bit composite timer ch. 1
output pin
D
MPG waveform sequencer
output pin
8/16-bit PPG ch. 0 output pin
TO11
8/16-bit composite timer ch. 1
output pin
D
MPG waveform sequencer
output pin
8/16-bit PPG ch. 1 output pin
EC1
8/16-bit composite timer ch. 1
clock input pin
P65
General-purpose I/O port
High-current pin
PPG11
Document Number: 002-04692 Rev. *E
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
—
—
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
Hysteresis CMOS
—
Ο
—
—
General-purpose I/O port
High-current pin
PPG10
OPT3
Hysteresis CMOS
General-purpose I/O port
High-current pin
PPG01
OPT2
Output OD*5 PU*6
General-purpose I/O port
High-current pin
PPG00
OPT1
Input
16-bit reload timer ch. 1 input pin
P64
33
General-purpose I/O port
High-current pin
P61
P63
32
UART/SIO ch. 0 data input pin
DTTI
P62
31
General-purpose I/O port
MPG waveform sequencer input
pin
TI1
—
I/O type
Function
D
MPG waveform sequencer
output pin
8/16-bit PPG ch. 1 output pin
Page 18 of 129
MB95690K Series
Pin no.
I/O
circuit
Pin
name
LQFP48* ,
LQFP52*3
type*4
QFN48*2
1
38
OPT4
D
8/16-bit PPG ch. 2 output pin
PPG1
16-bit PPG timer ch. 1 output pin
37
39
40
D
8/16-bit PPG ch. 2 output pin
TRG1
16-bit PPG timer ch. 1 trigger
input pin
P00
General-purpose I/O port
INT00
External interrupt input pin
E
41
General-purpose I/O port
INT01
External interrupt input pin
E
42
General-purpose I/O port
INT02
External interrupt input pin
E
43
8/10-bit A/D converter analog
input pin
P03
General-purpose I/O port
INT03
External interrupt input pin
AN03
CMP1_P
Document Number: 002-04692 Rev. *E
Ο
Hysteresis CMOS
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Comparator ch. 0 digital output
pin
CMP0_O
40
8/10-bit A/D converter analog
input pin
P02
AN02
—
Comparator ch. 0 inverting
analog input (negative input) pin
CMP0_N
39
8/10-bit A/D converter analog
input pin
P01
AN01
Hysteresis CMOS
Comparator ch. 0 non-inverting
analog input (positive input) pin
CMP0_P
38
MPG waveform sequencer
output pin
PPG21
AN00
Output OD*5 PU*6
General-purpose I/O port
High-current pin
P67
36
MPG waveform sequencer
output pin
PPG20
OPT5
Input
General-purpose I/O port
High-current pin
P66
35
I/O type
Function
E
8/10-bit A/D converter analog
input pin
Comparator ch. 1 non-inverting
analog input (positive input) pin
Page 19 of 129
MB95690K Series
I/O type
Pin no.
I/O
circuit
Pin
name
LQFP48* ,
LQFP52*3
type*4
QFN48*2
Function
1
41
44
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
E
45
P05
General-purpose I/O port
INT05
External interrupt input pin
AN05
E
46
NC
—
P06
43
47
INT06
E
P07
48
INT07
49
46
50
47
51
48
52
PF2
RST
PF0
X0
PF1
X1
VSS
Ο
8/10-bit A/D converter analog
input pin
Hysteresis/
CMOS
analog
—
Ο
It is an internally connected pin.
Always leave it unconnected.
—
—
Hysteresis/
CMOS
analog
—
Ο
Hysteresis/
CMOS
analog
—
Ο
Hysteresis CMOS
Ο
—
Hysteresis CMOS
—
—
Hysteresis CMOS
—
—
—
—
—
—
External interrupt input pin
8/10-bit A/D converter analog
input pin
General-purpose I/O port
E
AN07
45
—
General-purpose I/O port
AN06
44
CMOS
Comparator ch. 1 digital output
pin
CMP1_O
—
CMOS/
analog
Output OD*5 PU*6
Comparator ch. 1 inverting
analog input (negative input) pin
CMP1_N
42
8/10-bit A/D converter analog
input pin
Input
A
B
B
—
External interrupt input pin
8/10-bit A/D converter analog
input pin
General-purpose I/O port
Reset pin
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
—
—
Ο: Available
*1: LQA048
*2: WNR048
*3: LQC052
*4: For the I/O circuit types, see “I/O Circuit Type”.
*5: N-ch open drain
*6: Pull-up
Document Number: 002-04692 Rev. *E
Page 20 of 129
MB95690K Series
7. I/O Circuit Type
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
Clock input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
P-ch
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx. 5 MΩ
Digital output
N-ch
Digital output
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
• Pull-up control
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Document Number: 002-04692 Rev. *E
Page 21 of 129
MB95690K Series
Type
Circuit
Remarks
D
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Pull-up control
High current output
•
•
•
•
CMOS output
Hysteresis input
Pull-up control
Analog input
Digital output
N-ch
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
G
Standby control
• N-ch open drain output
• Hysteresis input
Hysteresis input
Digital output
N-ch
H
Digital output
• N-ch open drain output
• CMOS input
N-ch
Standby control
CMOS input
Document Number: 002-04692 Rev. *E
Page 22 of 129
MB95690K Series
Type
Circuit
Remarks
I
Pull-up control
R
P-ch
• CMOS output
• CMOS input
• Pull-up control
Digital output
P-ch
Digital output
N-ch
Standby control
CMOS input
8. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions
that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
8.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
• Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
• Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges
may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their sales representative beforehand.
• Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply
and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage
or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large
current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Document Number: 002-04692 Rev. *E
Page 23 of 129
MB95690K Series
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins
should be connected through an appropriate resistance to a power supply pin or ground pin.
• Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected
to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing
large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is
called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause
injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
• Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of
products.
• Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
• Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability
are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls,
medical devices for life support, etc.) are requested to consult with sales representatives before such use. The
company will not be responsible for damages arising from such use without prior approval.
8.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress’s recommended conditions. For detailed information about mount
conditions, contact your sales representative.
• Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering
on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and
using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually
causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting
processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to
contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts
and IC leads be verified before mounting.
Document Number: 002-04692 Rev. *E
Page 24 of 129
MB95690K Series
• Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more
easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased
susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established
a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
• Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
• Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,
with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
• Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking.
Condition: 125°C/24 h
• Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on
the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock
loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-04692 Rev. *E
Page 25 of 129
MB95690K Series
8.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity
levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In
such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect
the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances.
If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
9. Notes On Device Handling
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither
a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “20.1 Absolute Maximum Ratings” of “Electrical Characteristics” is applied to the VCC pin or
the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally
destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the
commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation
rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode.
Document Number: 002-04692 Rev. *E
Page 26 of 129
MB95690K Series
10. Pin Connection
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latchups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused input/output
pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input
pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the
ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the
power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the
VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC
pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin to an external pull-up resistor of 2 kΩ or above.
After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.
The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool
used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
• RST pin
Connect the RST pin to an external pull-up resistor of 2 kΩ or above.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length
between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the
layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST
pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O
function can be selected by the RSTEN bit in the SYSC register.
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the
VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling
capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device
is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and
the VSS pin when designing the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
Document Number: 002-04692 Rev. *E
Page 27 of 129
MB95690K Series
• Note on serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed
circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as
adding a checksum to the end of data in order to detect errors. If an error is detected, retransmit the data.
Document Number: 002-04692 Rev. *E
Page 28 of 129
MB95690K Series
11. Block Diagram (LQF044)
F2MC-8FX CPU
PF2*1/RST*2
PF0/X0
Reset with LVD
Dual operation Flash with
security function
(60/36/20 Kbyte)
*2
PF1/X1*2
PG1/X0A*2
Oscillator
circuit
CR oscillator
RAM (2048/1024/512 bytes)
PG2/X1A*2
Interrupt controller
Clock control
P70/TO00
Watch prescaler
C
8/16-bit composite timer ch. 0
P71/TO01
P74/EC0
P12*1/DBG
On-chip debug
(P62*3/TO10)
Wild register
8/16-bit composite timer ch. 1
(P63*3/TO11)
(P64*3/EC1)
(P00/INT00 to P06/INT06)
External interrupt
P45/SCK
P75/UCK0
P76/UO0
UART/SIO ch. 0
P77/UI0
P13/PPG00*4, (P62*3/PPG00*4)
P14/PPG01*4, (P63*3/PPG01*4)
P10/PPG10*4, (P64*3/PPG10*4)
P11/PPG11*4, (P65*3/PPG11*4)
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
Internal bus
LIN-UART
P46/SOT
P47/SIN
(P00/CMP0_P)
Comparator ch. 0
(P01/CMP0_N)
(P02/CMP0_O)
(P03/CMP1_P)
Comparator ch. 1
(P04/CMP1_N)
(P05/CMP1_O)
P15/PPG20*4, (P66*3/PPG20*4)
P16/PPG21*4, (P67*3/PPG21*4)
8/16-bit PPG ch. 2
MPG
16-bit reload timer ch. 1
(P00/AN00 to P06/AN06)
P40/AN08
P44/TO1
P61*3/TI1
8/10-bit A/D converter
P17/SNI0, PG1/SNI1, PG2/SNI2
P72*1/SCL
*1/SDA
P73
I2C bus interface ch. 0
Waveform sequencer
P60*3/DTTI
P61*3/TI1
(P62*3/OPT0 to P67*3/OPT5)
16-bit PPG timer ch. 1
Port
(P66*3/PPG1)
(P67*3/TRG1)
Port
Vcc
Vss
*1: P12, P72, P73 and PF2 are N-ch open drain pins.
*2: Software select
*3: P60 to P67 are high-current pins.
*4: The 8/16-bit PPG output pins are mapped to port 1 by default. To map the 8/16-bit PPG output pins to port 6,
write “1” to the PPGSEL bit in the SYSC register.
Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.
Document Number: 002-04692 Rev. *E
Page 29 of 129
MB95690K Series
12. Block Diagram (LQA048, LQC052, WNR048)
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Dual operation Flash with
security function
(60/36/20 Kbyte)
PF0/X0*2
PF1/X1*2
PG1/X0A*2
Oscillator
circuit
CR oscillator
RAM (2048/1024/512 bytes)
PG2/X1A*2
Interrupt controller
Clock control
P70/TO00
C
Watch prescaler
8/16-bit composite timer ch. 0
P71/TO01
P74/EC0
P12*1/DBG
On-chip debug
(P62*3/TO10)
Wild register
8/16-bit composite timer ch. 1
(P63*3/TO11)
(P64*3/EC1)
(P00/INT00 to P07/INT07)
External interrupt
P45/SCK
P75/UCK0
UART/SIO ch. 0
P77/UI0
P13/PPG00*4, (P62*3/PPG00*4)
P14/PPG01*4, (P63*3/PPG01*4)
P10/PPG10*4, (P64*3/PPG10*4)
P11/PPG11*4, (P65*3/PPG11*4)
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
Internal bus
P76/UO0
LIN-UART
P46/SOT
P47/SIN
(P00/CMP0_P)
Comparator ch. 0
(P01/CMP0_N)
(P02/CMP0_O)
(P03/CMP1_P)
Comparator ch. 1
(P04/CMP1_N)
(P05/CMP1_O)
P15/PPG20*4, (P66*3/PPG20*4)
P16/PPG21*4, (P67*3/PPG21*4)
8/16-bit PPG ch. 2
MPG
16-bit reload timer ch. 1
(P00/AN00 to P07/AN07)
P40/AN08 to P43/AN11
P44/TO1
P61*3/TI1
8/10-bit A/D converter
P17/SNI0, PG1/SNI1, PG2/SNI2
P72*1/SCL
P73*1/SDA
I2C
bus interface ch. 0
Waveform sequencer
P60*3/DTTI
P61*3/TI1
(P62*3/OPT0 to P67*3/OPT5)
16-bit PPG timer ch. 1
Port
(P66*3/PPG1)
(P67*3/TRG1)
Port
Vcc
Vss
*1: P12, P72, P73 and PF2 are N-ch open drain pins.
*2: Software select
*3: P60 to P67 are high-current pins.
*4: The 8/16-bit PPG output pins are mapped to port 1 by default. To map the 8/16-bit PPG output pins to port 6,
write “1” to the PPGSEL bit in the SYSC register.
Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.
Document Number: 002-04692 Rev. *E
Page 30 of 129
MB95690K Series
13. CPU Core
• Memory space
The memory space of the MB95690K Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area,
a data area, and a program area. The memory space includes areas intended for specific purposes such as generalpurpose registers and a vector table. The memory maps of the MB95690K Series are shown below.
• Memory maps
MB95F694K
0x0000
0x0080
0x0090
0x0100
0x0200
0x0290
I/O area
Access prohibited
RAM 512 bytes
Registers
MB95F696K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 1 Kbyte
Registers
MB95F698K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 2 Kbyte
Registers
0x0490
Access prohibited
Access prohibited
0x0890
Access prohibited
0x0F80
0x0F80
0x0F80
Extended I/O area
Extended I/O area
Extended I/O area
0x1000
0x1000
0x1000
Flash memory 4 Kbyte
Flash memory 4 Kbyte
0x2000
0x2000
Access prohibited
Access prohibited
0x8000
Flash memory 60 Kbyte
Flash memory 32 Kbyte
0xC000
Flash memory 16 Kbyte
0xFFFF
Document Number: 002-04692 Rev. *E
0xFFFF
0xFFFF
Page 31 of 129
MB95690K Series
14. Memory Space
The memory space of the MB95690K Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area,
a data area, and a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table.
14.1 I/O area (addresses: 0x0000 to 0x007F)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also
be accessed at high-speed by using direct addressing instructions.
14.2 Extended I/O area (addresses: 0x0F80 to 0x0FFF)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory.
14.3
•
•
•
•
Data area
Static RAM is incorporated in the data area as the internal data area.
The internal RAM size varies according to product.
The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions.
In MB95F698K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at highspeed by direct addressing instructions with a direct bank pointer set.
• In MB95F696K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at highspeed by direct addressing instructions with a direct bank pointer set.
• In MB95F694K, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at highspeed by direct addressing instructions with a direct bank pointer set.
• In MB95F694K/F696K/F698K, the area from 0x0100 to 0x01FF can be used as a general-purpose register area.
14.4
•
•
•
•
Program area
The Flash memory is incorporated in the program area as the internal program area.
The Flash memory size varies according to product.
The area from 0xFFC0 to 0xFFFF is used as the vector table.
The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.
Document Number: 002-04692 Rev. *E
Page 32 of 129
MB95690K Series
14.5 Memory space map
0x0000
0x0080
0x0090
0x0100
I/O area
Direct addressing area
Access prohibited
Registers
(General-purpose register area)
Extended direct addressing area
0x0200
0x047F
Data area
0x088F
0x0890
Access prohibited
0x0F80
0x0FFF
0x1000
Extended I/O area
Program area
0xFFC0
0xFFFF
Document Number: 002-04692 Rev. *E
Vector table area
Page 33 of 129
MB95690K Series
15. Areas For Specific Applications
The general-purpose register area and vector table area are used for the specific applications.
• General-purpose register area (Addresses: 0x0100 to 0x01FF)
• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
• As this area forms part of the RAM area, it can also be used as conventional RAM.
• When the area is used as general-purpose registers, general-purpose register addressing enables high-speed access with short instructions.
• Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “CHAPTER
27 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX MB95690K Series Hardware Manual”.
• Vector table area (Addresses: 0xFFC0 to 0xFFFF)
• This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.
• The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set
to an address in the vector table in the form of data.
“Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets.
For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS” and “A.2 Special Instruction ■ Special Instruction ● CALLV #vct” in “APPENDIX” in “New 8FX MB95690K Series Hardware Manual”.
• Direct bank pointer and access area
Direct bank pointer (DP[2:0])
Operand-specified dir
Access area
0bXXX (It does not affect mapping.)
0x0000 to 0x007F
0x0000 to 0x007F
0b000 (initial value)
0x0090 to 0x00FF
0x0090 to 0x00FF
0b001
0x0100 to 0x017F
0b010
0x0180 to 0x01FF
0b011
0x0200 to 0x027F
0b100
0x0080 to 0x00FF
0x0280 to 0x02FF*1
0b101
0x0300 to 0x037F
0b110
0x0380 to 0x03FF
0b111
0x0400 to 0x047F*2
*1: Due to the memory size limit, the available access area is up to “0x028F” in MB95F694K.
*2: Due to the memory size limit, the available access area is up to “0x047F” in MB95F696K/F698K.
Document Number: 002-04692 Rev. *E
Page 34 of 129
MB95690K Series
16. I/O Map
Address
Register
abbreviation
0x0000
PDR0
0x0001
Register name
R/W
Initial value
Port 0 data register
R/W
0b00000000
DDR0
Port 0 direction register
R/W
0b00000000
0x0002
PDR1
Port 1 data register
R/W
0b00000000
0x0003
DDR1
Port 1 direction register
R/W
0b00000000
0x0004
—
—
—
0x0005
WATR
Oscillation stabilization wait time setting register
R/W
0b11111111
0x0006
PLLC
PLL control register
R/W
0b000X0000
0x0007
SYCC
System clock control register
R/W
0bXXX11011
0x0008
STBC
Standby control register
R/W
0b00000000
0x0009
RSRR
Reset source register
R/W
0b000XXXXX
0x000A
TBTC
Time-base timer control register
R/W
0b00000000
0x000B
WPCR
Watch prescaler control register
R/W
0b00000000
0x000C
WDTC
Watchdog timer control register
R/W
0b00XX0000
0x000D
SYCC2
System clock control register 2
R/W
0bXXXX0011
0x000E
STBC2
Standby control register 2
R/W
0b00000000
0x000F
to
0x0011
—
—
—
0x0012
PDR4
Port 4 data register
R/W
0b00000000
0x0013
DDR4
Port 4 direction register
R/W
0b00000000
0x0014,
0x0015
—
—
—
0x0016
PDR6
Port 6 data register
R/W
0b00000000
0x0017
DDR6
Port 6 direction register
R/W
0b00000000
0x0018
PDR7
Port 7 data register
R/W
0b00000000
0x0019
DDR7
Port 7 direction register
R/W
0b00000000
0x001A
to
0x0027
—
—
—
0x0028
PDRF
Port F data register
R/W
0b00000000
0x0029
DDRF
Port F direction register
R/W
0b00000000
0x002A
PDRG
Port G data register
R/W
0b00000000
0x002B
DDRG
Port G direction register
R/W
0b00000000
0x002C
PUL0
Port 0 pull-up register
R/W
0b00000000
0x002D
PUL1
Port 1 pull-up register
R/W
0b00000000
0x002E,
0x002F
—
—
—
(Disabled)
(Disabled)
(Disabled)
(Disabled)
Document Number: 002-04692 Rev. *E
(Disabled)
Page 35 of 129
MB95690K Series
Address
Register
abbreviation
0x0030
PUL4
0x0031
R/W
Initial value
Port 4 pull-up register
R/W
0b00000000
PUL6
Port 6 pull-up register
R/W
0b00000000
0x0032
PUL7
Port 7 pull-up register
R/W
0b00000000
0x0033,
0x0034
—
—
—
0x0035
PULG
Port G pull-up register
R/W
0b00000000
0x0036
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
0b00000000
0x0037
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
0b00000000
0x0038
T11CR1
8/16-bit composite timer 11 status control register 1
R/W
0b00000000
0x0039
T10CR1
8/16-bit composite timer 10 status control register 1
R/W
0b00000000
0x003A
PC01
8/16-bit PPG timer 01 control register
R/W
0b00000000
0x003B
PC00
8/16-bit PPG timer 00 control register
R/W
0b00000000
0x003C
PC11
8/16-bit PPG timer 11 control register
R/W
0b00000000
0x003D
PC10
8/16-bit PPG timer 10 control register
R/W
0b00000000
0x003E
PC21
8/16-bit PPG timer 21 control register
R/W
0b00000000
0x003F
PC20
8/16-bit PPG timer 20 control register
R/W
0b00000000
0x0040
TMCSRH1
16-bit reload timer control status register (upper) ch. 1
R/W
0b00000000
0x0041
TMCSRL1
16-bit reload timer control status register (lower) ch. 1
R/W
0b00000000
0x0042
CMR0
Comparator control register ch. 0
R/W
0b11000101
0x0043
CMR1
Comparator control register ch. 1
R/W
0b11000101
0x0044
PCNTH1
16-bit PPG status control register (upper)
R/W
0b00000000
0x0045
PCNTL1
16-bit PPG status control register (lower)
R/W
0b00000000
0x0046,
0x0047
—
—
—
0x0048
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
0b00000000
0x0049
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
0b00000000
0x004A
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
0b00000000
0x004B
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
0b00000000
0x004C,
0x004D
—
—
—
0x004E
LVDR
LVD reset voltage selection ID register
R/W
0b00000000
0x004F
LVDCC
LVD reset circuit control register
R/W
0b00000001
0x0050
SCR
LIN-UART serial control register
R/W
0b00000000
0x0051
SMR
LIN-UART serial mode register
R/W
0b00000000
0x0052
SSR
LIN-UART serial status register
R/W
0b00001000
RDR
LIN-UART receive data register
TDR
LIN-UART transmit data register
R/W
0b00000000
R/W
0b00000100
0x0053
0x0054
ESCR
Register name
(Disabled)
(Disabled)
(Disabled)
LIN-UART extended status control register
Document Number: 002-04692 Rev. *E
Page 36 of 129
MB95690K Series
Address
Register
abbreviation
0x0055
ECCR
0x0056
Register name
R/W
Initial value
LIN-UART extended communication control register
R/W
0b000000XX
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
0b00000000
0x0057
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
0b00100000
0x0058
SSR0
UART/SIO serial status and data register ch. 0
R/W
0b00000001
0x0059
TDR0
UART/SIO serial output data register ch. 0
R/W
0b00000000
0x005A
RDR0
UART/SIO serial input data register ch. 0
R
0b00000000
0x005B
to
0x005F
—
—
—
0x0060
IBCR00
I2C bus control register 0 ch. 0
R/W
0b00000000
0x0061
IBCR10
I2C bus control register 1 ch. 0
R/W
0b00000000
0x0062
IBSR0
I2C bus status register ch. 0
R/W
0b00000000
0x0063
IDDR0
I2C data register ch. 0
R/W
0b00000000
0x0064
IAAR0
I2C address register ch. 0
R/W
0b00000000
0x0065
ICCR0
I2C clock control register ch. 0
R/W
0b00000000
0x0066
OPCUR
16-bit MPG output control register (upper)
R/W
0b00000000
0x0067
OPCLR
16-bit MPG output control register (lower)
R/W
0b00000000
0x0068
IPCUR
16-bit MPG input control register (upper)
R/W
0b00000000
0x0069
IPCLR
16-bit MPG input control register (lower)
R/W
0b00000000
0x006A
NCCR
16-bit MPG noise cancellation control register
R/W
0b00000000
0x006B
TCSR
16-bit MPG timer control status register
R/W
0b00000000
0x006C
ADC1
8/10-bit A/D converter control register 1
R/W
0b00000000
0x006D
ADC2
8/10-bit A/D converter control register 2
R/W
0b00000000
0x006E
ADDH
8/10-bit A/D converter data register (upper)
R/W
0b00000000
0x006F
ADDL
8/10-bit A/D converter data register (lower)
R/W
0b00000000
0x0070
—
—
—
0x0071
FSR2
Flash memory status register 2
R/W
0b00000000
0x0072
FSR
Flash memory status register
R/W
0b000X0000
0x0073
SWRE0
Flash memory sector write control register 0
R/W
0b00000000
0x0074
FSR3
Flash memory status register 3
R
0b000XXXXX
0x0075
FSR4
Flash memory status register 4
R/W
0b00000000
0x0076
WREN
Wild register address compare enable register
R/W
0b00000000
0x0077
WROR
Wild register data test setting register
R/W
0b00000000
0x0078
—
—
—
0x0079
ILR0
Interrupt level setting register 0
R/W
0b11111111
0x007A
ILR1
Interrupt level setting register 1
R/W
0b11111111
0x007B
ILR2
Interrupt level setting register 2
R/W
0b11111111
(Disabled)
(Disabled)
Mirror of register bank pointer (RP) and direct bank
pointer (DP)
Document Number: 002-04692 Rev. *E
Page 37 of 129
MB95690K Series
Address
Register
abbreviation
0x007C
ILR3
0x007D
Register name
R/W
Initial value
Interrupt level setting register 3
R/W
0b11111111
ILR4
Interrupt level setting register 4
R/W
0b11111111
0x007E
ILR5
Interrupt level setting register 5
R/W
0b11111111
0x007F
—
—
—
0x0F80
WRARH0
Wild register address setting register (upper) ch. 0
R/W
0b00000000
0x0F81
WRARL0
Wild register address setting register (lower) ch. 0
R/W
0b00000000
0x0F82
WRDR0
Wild register data setting register ch. 0
R/W
0b00000000
0x0F83
WRARH1
Wild register address setting register (upper) ch. 1
R/W
0b00000000
0x0F84
WRARL1
Wild register address setting register (lower) ch. 1
R/W
0b00000000
0x0F85
WRDR1
Wild register data setting register ch. 1
R/W
0b00000000
0x0F86
WRARH2
Wild register address setting register (upper) ch. 2
R/W
0b00000000
0x0F87
WRARL2
Wild register address setting register (lower) ch. 2
R/W
0b00000000
0x0F88
WRDR2
Wild register data setting register ch. 2
R/W
0b00000000
0x0F89
to
0x0F91
—
—
—
0x0F92
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
0b00000000
0x0F93
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
0b00000000
0x0F94
T01DR
8/16-bit composite timer 01 data register
R/W
0b00000000
0x0F95
T00DR
8/16-bit composite timer 00 data register
R/W
0b00000000
0x0F96
TMCR0
8/16-bit composite timer 00/01 timer mode control
register
R/W
0b00000000
0x0F97
T11CR0
8/16-bit composite timer 11 status control register 0
R/W
0b00000000
0x0F98
T10CR0
8/16-bit composite timer 10 status control register 0
R/W
0b00000000
0x0F99
T11DR
8/16-bit composite timer 11 data register
R/W
0b00000000
0x0F9A
T10DR
8/16-bit composite timer 10 data register
R/W
0b00000000
0x0F9B
TMCR1
8/16-bit composite timer 10/11 timer mode control
register
R/W
0b00000000
0x0F9C
PPS01
8/16-bit PPG01 cycle setting buffer register
R/W
0b11111111
0x0F9D
PPS00
8/16-bit PPG00 cycle setting buffer register
R/W
0b11111111
0x0F9E
PDS01
8/16-bit PPG01 duty setting buffer register
R/W
0b11111111
0x0F9F
PDS00
8/16-bit PPG00 duty setting buffer register
R/W
0b11111111
0x0FA0
PPS11
8/16-bit PPG11 cycle setting buffer register
R/W
0b11111111
0x0FA1
PPS10
8/16-bit PPG10 cycle setting buffer register
R/W
0b11111111
0x0FA2
PDS11
8/16-bit PPG11 duty setting buffer register
R/W
0b11111111
0x0FA3
PDS10
8/16-bit PPG10 duty setting buffer register
R/W
0b11111111
0x0FA4
PPGS
8/16-bit PPG start register
R/W
0b00000000
0x0FA5
REVC
8/16-bit PPG output inversion register
R/W
0b00000000
(Disabled)
(Disabled)
Document Number: 002-04692 Rev. *E
Page 38 of 129
MB95690K Series
Address
Register
abbreviation
0x0FA6
PPS21
0x0FA7
0x0FA8
0x0FA9
Register name
R/W
Initial value
8/16-bit PPG21 cycle setting buffer register
R/W
0b11111111
PPS20
8/16-bit PPG20 cycle setting buffer register
R/W
0b11111111
TMRH1
16-bit reload timer timer register (upper) ch. 1
TMRLRH1
16-bit reload timer reload register (upper) ch. 1
R/W
0b00000000
R/W
0b00000000
TMRL1
16-bit reload timer timer register (lower) ch. 1
TMRLRL1
16-bit reload timer reload register (lower) ch. 1
0x0FAA
PDS21
8/16-bit PPG21 duty setting buffer register
R/W
0b11111111
0x0FAB
PDS20
8/16-bit PPG20 duty setting buffer register
R/W
0b11111111
0x0FAC
to
0x0FAF
—
—
—
0x0FB0
PDCRH1
16-bit PPG downcounter register (upper) ch. 1
R
0b00000000
0x0FB1
PDCRL1
16-bit PPG downcounter register (lower) ch. 1
R
0b00000000
0x0FB2
PCSRH1
16-bit PPG cycle setting buffer register (upper) ch. 1
R/W
0b11111111
0x0FB3
PCSRL1
16-bit PPG cycle setting buffer register (lower) ch. 1
R/W
0b11111111
0x0FB4
PDUTH1
16-bit PPG duty setting buffer register (upper) ch. 1
R/W
0b11111111
0x0FB5
PDUTL1
16-bit PPG duty setting buffer register (lower) ch. 1
R/W
0b11111111
0x0FB6
to
0x0FBB
—
—
—
0x0FBC
BGR1
LIN-UART baud rate generator register 1
R/W
0b00000000
0x0FBD
BGR0
LIN-UART baud rate generator register 0
R/W
0b00000000
0x0FBE
PSSR0
UART/SIO dedicated baud rate generator prescaler
select register ch. 0
R/W
0b00000000
0x0FBF
BRSR0
UART/SIO dedicated baud rate generator baud rate
setting register ch. 0
R/W
0b00000000
0x0FC0,
0x0FC1
—
—
—
0x0FC2
AIDRH
A/D input disable register (upper)
R/W
0b00000000
0x0FC3
AIDRL
A/D input disable register (lower)
R/W
0b00000000
0x0FC4
OPDBRH0
16-bit MPG output data buffer register (upper) ch. 0
R/W
0b00000000
0x0FC5
OPDBRL0
16-bit MPG output data buffer register (lower) ch. 0
R/W
0b00000000
0x0FC6
OPDBRH1
16-bit MPG output data buffer register (upper) ch. 1
R/W
0b00000000
0x0FC7
OPDBRL1
16-bit MPG output data buffer register (lower) ch. 1
R/W
0b00000000
0x0FC8
OPDBRH2
16-bit MPG output data buffer register (upper) ch. 2
R/W
0b00000000
0x0FC9
OPDBRL2
16-bit MPG output data buffer register (lower) ch. 2
R/W
0b00000000
0x0FCA
OPDBRH3
16-bit MPG output data buffer register (upper) ch. 3
R/W
0b00000000
0x0FCB
OPDBRL3
16-bit MPG output data buffer register (lower) ch. 3
R/W
0b00000000
0x0FCC
OPDBRH4
16-bit MPG output data buffer register (upper) ch. 4
R/W
0b00000000
(Disabled)
(Disabled)
(Disabled)
Document Number: 002-04692 Rev. *E
Page 39 of 129
MB95690K Series
Address
Register
abbreviation
0x0FCD
OPDBRL4
0x0FCE
Register name
R/W
Initial value
16-bit MPG output data buffer register (lower) ch. 4
R/W
0b00000000
OPDBRH5
16-bit MPG output data buffer register (upper) ch. 5
R/W
0b00000000
0x0FCF
OPDBRL5
16-bit MPG output data buffer register (lower) ch. 5
R/W
0b00000000
0x0FD0
OPDBRH6
16-bit MPG output data buffer register (upper) ch. 6
R/W
0b00000000
0x0FD1
OPDBRL6
16-bit MPG output data buffer register (lower) ch. 6
R/W
0b00000000
0x0FD2
OPDBRH7
16-bit MPG output data buffer register (upper) ch. 7
R/W
0b00000000
0x0FD3
OPDBRL7
16-bit MPG output data buffer register (lower) ch. 7
R/W
0b00000000
0x0FD4
OPDBRH8
16-bit MPG output data buffer register (upper) ch. 8
R/W
0b00000000
0x0FD5
OPDBRL8
16-bit MPG output data buffer register (lower) ch. 8
R/W
0b00000000
0x0FD6
OPDBRH9
16-bit MPG output data buffer register (upper) ch. 9
R/W
0b00000000
0x0FD7
OPDBRL9
16-bit MPG output data buffer register (lower) ch. 9
R/W
0b00000000
0x0FD8
OPDBRHA
16-bit MPG output data buffer register (upper) ch. A
R/W
0b00000000
0x0FD9
OPDBRLA
16-bit MPG output data buffer register (lower) ch. A
R/W
0b00000000
0x0FDA
OPDBRHB
16-bit MPG output data buffer register (upper) ch. B
R/W
0b00000000
0x0FDB
OPDBRLB
16-bit MPG output data buffer register (lower) ch. B
R/W
0b00000000
0x0FDC
OPDUR
16-bit MPG output data register (upper)
R
0b0000XXXX
0x0FDD
OPDLR
16-bit MPG output data register (lower)
R
0bXXXXXXXX
0x0FDE
CPCUR
16-bit MPG compare clear register (upper)
R/W
0bXXXXXXXX
0x0FDF
CPCLR
16-bit MPG compare clear register (lower)
R/W
0bXXXXXXXX
0x0FE0
LVDPW
LVD reset circuit password register
R/W
0b00000000
0x0FE1
—
—
—
0x0FE2
TMBUR
16-bit MPG timer buffer register (upper)
R
0bXXXXXXXX
0x0FE3
TMBLR
16-bit MPG timer buffer register (lower)
R
0bXXXXXXXX
0x0FE4
CRTH
Main CR clock trimming register (upper)
R/W
0b000XXXXX
0x0FE5
CRTL
Main CR clock trimming register (lower)
R/W
0b000XXXXX
0x0FE6
—
—
—
0x0FE7
CRTDA
Main CR clock temperature dependent adjustment
register
R/W
0b000XXXXX
0x0FE8
SYSC
System configuration register
R/W
0b11000011
0x0FE9
CMCR
Clock monitoring control register
R/W
0b00000000
0x0FEA
CMDR
Clock monitoring data register
R
0b00000000
0x0FEB
WDTH
Watchdog timer selection ID register (upper)
R
0bXXXXXXXX
0x0FEC
WDTL
Watchdog timer selection ID register (lower)
R
0bXXXXXXXX
0x0FED,
0x0FEE
—
—
—
0x0FEF
WICR
R/W
0b01000000
(Disabled)
(Disabled)
(Disabled)
Interrupt pin selection circuit control register
Document Number: 002-04692 Rev. *E
Page 40 of 129
MB95690K Series
Address
Register
abbreviation
Register name
R/W
Initial value
0x0FF0
to
0x0FFF
—
(Disabled)
—
—
• R/W access symbols
R/W : Readable/Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
Document Number: 002-04692 Rev. *E
Page 41 of 129
MB95690K Series
17. I/O Ports
• List of port registers
Register name
Read/Write
Initial value
Port 0 data register
PDR0
R, RM/W
0b00000000
Port 0 direction register
DDR0
R/W
0b00000000
Port 1 data register
PDR1
R, RM/W
0b00000000
Port 1 direction register
DDR1
R/W
0b00000000
Port 4 data register
PDR4
R, RM/W
0b00000000
Port 4 direction register
DDR4
R/W
0b00000000
Port 6 data register
PDR6
R, RM/W
0b00000000
Port 6 direction register
DDR6
R/W
0b00000000
Port 7 data register
PDR7
R, RM/W
0b00000000
Port 7 direction register
DDR7
R/W
0b00000000
Port F data register
PDRF
R, RM/W
0b00000000
Port F direction register
DDRF
R/W
0b00000000
Port G data register
PDRG
R, RM/W
0b00000000
Port G direction register
DDRG
R/W
0b00000000
Port 0 pull-up register
PUL0
R/W
0b00000000
Port 1 pull-up register
PUL1
R/W
0b00000000
Port 4 pull-up register
PUL4
R/W
0b00000000
Port 6 pull-up register
PUL6
R/W
0b00000000
Port 7 pull-up register
PUL7
R/W
0b00000000
Port G pull-up register
PULG
R/W
0b00000000
A/D input disable register (upper)
AIDRH
R/W
0b00000000
A/D input disable register (lower)
AIDRL
R/W
0b00000000
R/W
: Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the readmodify-write (RMW) type of instruction.)
Document Number: 002-04692 Rev. *E
Page 42 of 129
MB95690K Series
17.1 Port 0
Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.1.1 Port 0 configuration
Port 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• Port 0 pull-up register (PUL0)
• A/D input disable register (lower) (AIDRL)
17.1.2 Block diagrams of port 0
• P00/INT00/AN00/CMP0_P pin
This pin has the following peripheral functions:
• External interrupt input pin (INT00)
• 8/10-bit A/D converter analog input pin (AN00)
• Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P)
• P01/INT01/AN01/CMP0_N pin
This pin has the following peripheral functions:
• External interrupt input pin (INT01)
• 8/10-bit A/D converter analog input pin (AN01)
• Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N)
• P03/INT03/AN03/CMP1_P pin
This pin has the following peripheral functions:
• External interrupt input pin (INT03)
• 8/10-bit A/D converter analog input pin (AN03)
• Comparator ch. 1 non-inverting analog input (positive input) pin (CMP1_P)
• P04/INT04/AN04/CMP1_N pin
This pin has the following peripheral functions:
• External interrupt input pin (INT04)
• 8/10-bit A/D converter analog input pin (AN04)
• Comparator ch. 1 inverting analog input (negative input) pin (CMP1_N)
Document Number: 002-04692 Rev. *E
Page 43 of 129
MB95690K Series
• Block diagram of P00/INT00/AN00/CMP0_P,
P04/INT04/AN04/CMP1_N
Comparator analog input
Comparator analog input disable
Peripheral function input
P01/INT01/AN01/CMP0_N,
P03/INT03/AN03/CMP1_P
and
A/D analog input
Peripheral function input enable
(INT00, INT01, INT03 and INT04)
Hysteresis
0
Pull-up
1
PDR0 read
PDR0
Pin
PDR0 write
Internal bus
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
Stop mode, watch mode (SPL = 1)
PUL0 read
PUL0
PUL0 write
AIDRL read
AIDRL
AIDRL write
Document Number: 002-04692 Rev. *E
Page 44 of 129
MB95690K Series
• P02/INT02/AN02/CMP0_O pin
This pin has the following peripheral functions:
• External interrupt input pin (INT02)
• 8/10-bit A/D converter analog input pin (AN02)
• Comparator ch. 0 digital output pin (CMP0_O)
• P05/INT05/AN05/CMP1_O pin
This pin has the following peripheral functions:
• External interrupt input pin (INT05)
• 8/10-bit A/D converter analog input pin (AN05)
• Comparator ch. 1 digital output pin (CMP1_O)
• Block diagram of P02/INT02/AN02/CMP0_O and P05/INT05/AN05/CMP1_O
Peripheral function input
A/D analog input
Peripheral function input enable
(INT02 and INT05)
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR0 read
1
PDR0
0
Pin
PDR0 write
Internal bus
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
Stop mode, watch mode (SPL = 1)
PUL0 read
PUL0
PUL0 write
AIDRL read
AIDRL
AIDRL write
Document Number: 002-04692 Rev. *E
Page 45 of 129
MB95690K Series
• P06/INT06/AN06 pin
This pin has the following peripheral functions:
• External interrupt input pin (INT06)
• 8/10-bit A/D converter analog input pin (AN06)
• P07/INT07/AN07 pin
This pin has the following peripheral functions:
• External interrupt input pin (INT07)
• 8/10-bit A/D converter analog input pin (AN07)
• Block diagram of P06/INT06/AN06 and P07/INT07/AN07
Peripheral function input
A/D analog input
Peripheral function input enable
(INT06 and INT07)
Hysteresis
0
Pull-up
1
PDR0 read
PDR0
Pin
PDR0 write
Internal bus
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
Stop mode, watch mode (SPL = 1)
PUL0 read
PUL0
PUL0 write
AIDRL read
AIDRL
AIDRL write
Document Number: 002-04692 Rev. *E
Page 46 of 129
MB95690K Series
17.1.3 Port 0 registers
• Port 0 register functions
Register
abbreviation
PDR0
DDR0
PUL0
AIDRL
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR0 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR0 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Analog input enabled
1
Port input enabled
• Correspondence between registers and pins for port 0
Correspondence between related register bits and pins
Pin name
P07
P06
P05
P04
P03
P02
P01
P00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PDR0
DDR0
PUL0
AIDRL
Document Number: 002-04692 Rev. *E
Page 47 of 129
MB95690K Series
17.1.4 Port 0 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.
• If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR0 register returns the PDR0 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input
disable register (lower) (AIDRL) to “1”.
• If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR0 register, the PDR0 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function
to “0”.
• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an
input port by setting the bit in the AIDRL register corresponding to that pin to “1”.
• Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with
the analog input function, its port input is disabled because the AIDRL register is initialized to “0”.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not
blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an analog input pin
• Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin
in the AIDRL register to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the
Document Number: 002-04692 Rev. *E
Page 48 of 129
MB95690K Series
corresponding bit in the PUL0 register to “0”.
• Operation as an external interrupt input pin
• Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt,
disable the external interrupt function corresponding to that pin.
• Operation of the pull-up register
Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register.
• Operation as a comparator input pin (only for P00 and P03)
• Set the bit in the AIDRL register corresponding to the comparator input pin to “0”.
• Regardless of the value of the PDR0 register and that of the DDR0 register, if the comparator analog input enable
bit in the comparator control register ch. 0/ch. 1 (CMR0/CMR1:VCID) is set to “0”, the comparator input function is
enabled.
• To disable the comparator input function, set the VCID bit to “1”.
• For details of the comparator, refer to “CHAPTER 28 COMPARATOR” in “New 8FX MB95690K Series Hardware
Manual”.
• Operation as a comparator input pin (only for P01 and P04)
• Set the bit in the AIDRL register corresponding to the comparator input pin to “0”.
• Regardless of the value of the PDR0 register and that of the DDR0 register, if the comparator analog input enable
bit (VCID) and the negative analog input voltage source select bit (BGRS) in the comparator control register ch.
0/ch. 1 (CMR0/CMR1) are both set to “0”, the comparator input function is enabled.
• To disable the comparator input function, set the VCID bit or the BGRS bit to “1”.
• For details of the comparator, refer to “CHAPTER 28 COMPARATOR” in “New 8FX MB95690K Series Hardware
Manual”.
Document Number: 002-04692 Rev. *E
Page 49 of 129
MB95690K Series
17.2 Port 1
Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.2.1 Port 1 configuration
Port 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up register (PUL1)
17.2.2 Block diagrams of port 1
• P10/PPG10* pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 1 output pin (PPG10)
• P11/PPG11* pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 1 output pin (PPG11)
• P13/PPG00* pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 0 output pin (PPG00)
• P14/PPG01* pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 0 output pin (PPG01)
• P15/PPG20* pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 2 output pin (PPG20)
• P16/PPG21* pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 2 output pin (PPG21)
*: The 8/16-bit PPG output pins are mapped to pins according to the setting of the PPGSEL bit in the SYSC register.
See the table below for details.
SYSC:PPGSEL = 0
SYSC:PPGSEL = 1
8/16-bit PPG output pin
Pin
PPG00
P13
P62
PPG01
P14
P63
PPG10
P10
P64
PPG11
P11
P65
PPG20
P15
P66
PPG21
P16
P67
Document Number: 002-04692 Rev. *E
Page 50 of 129
MB95690K Series
• Block diagram of P10/PPG10, P11/PPG11, P13/PPG00, P14/PPG01, P15/PPG20 and P16/PPG21
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR1 read
1
PDR1
Pin
0
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
• P12/DBG pin
This pin has the following peripheral function:
• DBG input pin (DBG)
• Block diagram of P12/DBG
Hysteresis
0
1
PDR1 read
Internal bus
PDR1
Pin
OD
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
Document Number: 002-04692 Rev. *E
Page 51 of 129
MB95690K Series
• P17/SNI0 pin
This pin has the following peripheral function:
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI0)
• Block diagram of P17/SNI0
Peripheral function input
Hysteresis
0
Pull-up
1
PDR1 read
PDR1
Pin
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
Document Number: 002-04692 Rev. *E
Page 52 of 129
MB95690K Series
17.2.3 Port 1 registers
• Port 1 register functions
Register
abbreviation
PDR1
DDR1
PUL1
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR1 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR1 value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 1
Correspondence between related register bits and pins
Pin name
P17
P16
P15
P14
P13
P12
P11
P10
bit7
bit6
bit5
bit4
bit3
bit2*
bit1
bit0
PDR1
DDR1
PUL1
*: Though P12 has no pull-up function, bit2 in the PUL1 register can still be accessed. The operation of P12 is not affected by the setting of bit2 in the PUL1 register.
Document Number: 002-04692 Rev. *E
Page 53 of 129
MB95690K Series
17.2.4 Port 1 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.
• If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR1 register returns the PDR1 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR1 register, the PDR1 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register.
Document Number: 002-04692 Rev. *E
Page 54 of 129
MB95690K Series
17.3 Port 4
Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.3.1 Port 4 configuration
Port 4 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
• Port 4 pull-up register (PUL4)
• A/D input disable register (upper) (AIDRH)
17.3.2 Block diagrams of port 4
• P40/AN08 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN08)
• P41/AN09 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN09)
• P42/AN10 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN10)
• P43/AN11 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN11)
Document Number: 002-04692 Rev. *E
Page 55 of 129
MB95690K Series
• Block diagram of P40/AN08, P41/AN09, P42/AN10 and P43/AN11
A/D analog input
Hysteresis
0
Pull-up
1
PDR4 read
PDR4
Pin
PDR4 write
Internal bus
Executing bit manipulation instruction
DDR4 read
DDR4
DDR4 write
Stop mode, watch mode (SPL = 1)
PUL4 read
PUL4
PUL4 write
AIDRH read
AIDRH
AIDRH write
Document Number: 002-04692 Rev. *E
Page 56 of 129
MB95690K Series
• P44/TO1 pin
This pin has the following peripheral function:
• 16-bit reload timer ch. 1 output pin (TO1)
• P46/SOT pin
This pin has the following peripheral function:
• LIN-UART data output pin (SOT)
• Block diagram of P44/TO1 and P46/SOT
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR4 read
1
PDR4
0
Pin
PDR4 write
Internal bus
Executing bit manipulation instruction
DDR4 read
DDR4
DDR4 write
Stop mode, watch mode (SPL = 1)
PUL4 read
PUL4
PUL4 write
Document Number: 002-04692 Rev. *E
Page 57 of 129
MB95690K Series
• P45/SCK pin
This pin has the following peripheral functions:
• LIN-UART clock I/O pin (SCK)
• Block diagram of P45/SCK
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR4 read
1
PDR4
0
Pin
PDR4 write
Internal bus
Executing bit manipulation instruction
DDR4 read
DDR4
DDR4 write
Stop mode, watch mode (SPL = 1)
PUL4 read
PUL4
PUL4 write
• P47/SIN pin
This pin has the following peripheral function:
• LIN-UART data input pin (SIN)
Document Number: 002-04692 Rev. *E
Page 58 of 129
MB95690K Series
• Block diagram of P47/SIN
Peripheral function input
Peripheral function input enable
CMOS
0
Pull-up
1
PDR4 read
PDR4
Pin
PDR4 write
Internal bus
Executing bit manipulation instruction
DDR4 read
DDR4
DDR4 write
Stop mode, watch mode (SPL = 1)
PUL4 read
PUL4
PUL4 write
Document Number: 002-04692 Rev. *E
Page 59 of 129
MB95690K Series
17.3.3 Port 4 registers
• Port 4 register functions
Register
abbreviation
PDR4
DDR4
PUL4
AIDRH
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR4 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR4 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Analog input enabled
1
Port input enabled
• Correspondence between registers and pins for port 4
Correspondence between related register bits and pins
Pin name
P47
P46
P45
P44
bit7
bit6
bit5
bit4
-
-
-
-
P43
P42
P41
P40
bit3
bit2
bit1
bit0
PDR4
DDR4
PUL4
AIDRH
Document Number: 002-04692 Rev. *E
Page 60 of 129
MB95690K Series
17.3.4 Port 4 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR4 register to external pins.
• If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR4 register returns the PDR4 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input
disable register (upper) (AIDRH) to “1”
• If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR4 register, the PDR4 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR4 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR4 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR4 register corresponding to the input pin of a peripheral function
to “0”.
• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an
input port by setting the bit in the AIDRH register corresponding to that pin to “1”.
• Reading the PDR4 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled. As for a pin shared with
the analog input function, its port input is disabled because the AIDRH register is initialized to “0”.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR4 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P45/SCK and P47/SIN is enabled by the external interrupt control register ch. 0 (EIC00)
of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an analog input pin
• Set the bit in the DDR4 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin
in the AIDRH register to “0”.
Document Number: 002-04692 Rev. *E
Page 61 of 129
MB95690K Series
• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the
corresponding bit in the PUL4 register to “0”.
• Operation of the pull-up register
Setting the bit in the PUL4 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL4 register.
17.4 Port 6
Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.4.1 Port 6 configuration
Port 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Port 6 pull-up register (PUL6)
17.4.2 Block diagrams of port 6
• P60/DTTI pin
This pin has the following peripheral function:
• MPG waveform sequencer input pin (DTTI)
• P61/TI1 pin
This pin has the following peripheral function:
• 16-bit reload timer ch. 1 input pin (TI1)
• Block diagram of P60/DTTI and P61/TI1
Peripheral function input
Hysteresis
0
Pull-up
1
PDR6 read
PDR6
Pin
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
Document Number: 002-04692 Rev. *E
Page 62 of 129
MB95690K Series
• P62/OPT0/PPG00/TO10 pin
This pin has the following peripheral functions:
• MPG waveform sequencer output pin (OPT0)
• 8/16-bit PPG ch. 0 output pin (PPG00)
• 8/16-bit composite timer ch. 1 output pin (TO10)
• P63/OPT1/PPG01/TO11 pin
This pin has the following peripheral functions:
• MPG waveform sequencer output pin (OPT1)
• 8/16-bit PPG ch. 0 output pin (PPG01)
• 8/16-bit composite timer ch. 1 output pin (TO11)
• P65/OPT3/PPG11 pin
This pin has the following peripheral functions:
• MPG waveform sequencer output pin (OPT3)
• 8/16-bit PPG ch. 1 output pin (PPG11)
• P66/OPT4/PPG20/PPG1 pin
This pin has the following peripheral functions:
• MPG waveform sequencer output pin (OPT4)
• 8/16-bit PPG ch. 2 output pin (PPG20)
• 16-bit PPG timer ch. 1 output pin (PPG1)
• Block diagram of P62/OPT0/PPG00/TO10, P63/OPT1/PPG01/TO11, P65/OPT3/PPG11 and
P66/OPT4/PPG20/PPG1
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR6 read
1
PDR6
0
Pin
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
Document Number: 002-04692 Rev. *E
Page 63 of 129
MB95690K Series
• P64/OPT2/PPG10/EC1 pin
This pin has the following peripheral functions:
• MPG waveform sequencer output pin (OPT2)
• 8/16-bit PPG ch. 1 output pin (PPG10)
• 8/16-bit composite timer ch. 1 clock input pin (EC1)
• P67/OPT5/PPG21/TRG1 pin
This pin has the following peripheral functions:
• MPG waveform sequencer output pin (OPT5)
• 8/16-bit PPG ch. 2 output pin (PPG21)
• 16-bit PPG timer ch. 1 trigger input pin (TRG1)
• Block diagram of P64/OPT2/PPG10/EC1 and P67/OPT5/PPG21/TRG1
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR6 read
1
PDR6
0
Pin
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
Document Number: 002-04692 Rev. *E
Page 64 of 129
MB95690K Series
17.4.3 Port 6 registers
• Port 6 register functions
Register
abbreviation
PDR6
DDR6
PUL6
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR6 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR6 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port 6
Correspondence between related register bits and pins
Pin name
P67
P66
P65
P64
P63
P62
P61
P60
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PDR6
DDR6
PUL6
Document Number: 002-04692 Rev. *E
Page 65 of 129
MB95690K Series
17.4.4 Port 6 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR6 register to external pins.
• If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR6 register returns the PDR6 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR6 register, the PDR6 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR6 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P64/EC1 and P67/TRG1 is enabled by the external interrupt control register ch. 0
(EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt
pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register.
Document Number: 002-04692 Rev. *E
Page 66 of 129
MB95690K Series
17.5 Port 7
Port 7 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.5.1 Port 7 configuration
Port 7 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 7 data register (PDR7)
• Port 7 direction register (DDR7)
• Port 7 pull-up register (PUL7)
17.5.2 Block diagrams of port 7
• P70/TO00 pin
This pin has the following peripheral function:
• 8/16-bit composite time ch. 0 output pin (TO00)
• P71/TO01 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 0 output pin (TO01)
• P76/UO0 pin
This pin has the following peripheral function:
• UART/SIO ch. 0 data output pin (UO0)
• Block diagram of P70/TO00, P71/TO01 and P76/UO0
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR7 read
1
PDR7
0
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
Document Number: 002-04692 Rev. *E
Page 67 of 129
MB95690K Series
• P72/SCL pin
This pin has the following peripheral function:
• I2C bus interface ch. 0 clock I/O pin (SCL)
• P73/SDA pin
This pin has the following peripheral function:
• I2C bus interface ch. 0 data I/O pin (SDA)
• Block diagram of P72/SCL and P73/SDA
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
CMOS
0
1
PDR7 read
PDR7
Internal bus
Pin
1
0
OD
PDR7 write
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
• P74/EC0 pin
This pin has the following peripheral functions:
• 8/16-bit composite timer ch. 0 clock input pin (EC0)
Document Number: 002-04692 Rev. *E
Page 68 of 129
MB95690K Series
• Block diagram of P74/EC0
Peripheral function input
Peripheral function input enable
Hysteresis
0
Pull-up
1
PDR7 read
PDR7
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
Document Number: 002-04692 Rev. *E
Page 69 of 129
MB95690K Series
• P75/UCK0 pin
This pin has the following peripheral function:
• UART/SIO ch. 0 clock I/O pin (UCK0)
• Block diagram of P75/UCK0
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR7 read
1
PDR7
0
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
Document Number: 002-04692 Rev. *E
Page 70 of 129
MB95690K Series
• P77/UI0 pin
This pin has the following peripheral function:
• UART/SIO ch. 0 data input pin (UI0)
• Block diagram of P77/UI0
Peripheral function input
Peripheral function input enable
CMOS
0
Pull-up
1
PDR7 read
PDR7
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
Document Number: 002-04692 Rev. *E
Page 71 of 129
MB95690K Series
17.5.3 Port 7 registers
• Port 7 register functions
Register
abbreviation
PDR7
DDR7
PUL7
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR7 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR7 value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 7
Correspondence between related register bits and pins
Pin name
P77
P76
P75
P74
bit7
bit6
bit5
bit4
PDR7
DDR7
PUL7
Document Number: 002-04692 Rev. *E
P73
P72
bit3
bit2
-
-
P71
P70
bit1
bit0
Page 72 of 129
MB95690K Series
17.5.4 Port 7 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR7 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR7 register to external pins.
• If data is written to the PDR7 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR7 register returns the PDR7 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR7 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR7 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR7 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR7 register, the PDR7 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR7 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR7 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR7 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR7 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR7 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR7 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P74/EC0, P75/UCK0 and P77/UI0 is enabled by the external interrupt control register
ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the
interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL7 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL7 register.
Document Number: 002-04692 Rev. *E
Page 73 of 129
MB95690K Series
17.6 Port F
Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.6.1 Port F configuration
Port F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
17.6.2 Block diagrams of port F
• PF0/X0 pin
This pin has the following peripheral function:
• Main clock input oscillation pin (X0)
• PF1/X1 pin
This pin has the following peripheral function:
• Main clock I/O oscillation pin (X1)
• Block diagram of PF0/X0 and PF1/X1
Hysteresis
0
1
PDRF read
Internal bus
PDRF
Pin
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF
DDRF write
Stop mode, watch mode (SPL = 1)
• PF2/RST pin
This pin has the following peripheral function:
• Reset pin (RST)
Document Number: 002-04692 Rev. *E
Page 74 of 129
MB95690K Series
• Block diagram of PF2/RST
Reset input
Reset input enable
Reset output enable
Reset output
Hysteresis
0
1
PDRF read
Internal bus
Pin
1
PDRF
OD
0
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF
DDRF write
Stop mode, watch mode (SPL = 1)
17.6.3 Port F registers
• Port F register functions
Register
abbreviation
PDRF
DDRF
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRF value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRF value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port F
Correspondence between related register bits and pins
Pin name
PDRF
DDRF
-
-
-
-
-
PF2
PF1
PF0
-
-
-
-
-
bit2*
bit1
bit0
*: When the external reset is selected (SYSC:RSTEN = 1), the port function cannot be used.
Document Number: 002-04692 Rev. *E
Page 75 of 129
MB95690K Series
17.6.4 Port F operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRF register to external pins.
• If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDRF register returns the PDRF register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDRF register, the PDRF register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
Document Number: 002-04692 Rev. *E
Page 76 of 129
MB95690K Series
17.7 Port G
Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95690K Series Hardware Manual”.
17.7.1 Port G configuration
Port G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)
17.7.2 Block diagram of port G
• PG1/X0A/SNI1 pin
This pin has the following peripheral functions:
• Subclock input oscillation pin (X0A)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI1)
• PG2/X1A/SNI2 pin
This pin has the following peripheral functions:
• Subclock I/O oscillation pin (X1A)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI2)
• Block diagram of PG1/X0A/SNI1 and PG2/X1A/SNI2
Peripheral function input
Hysteresis
0
Pull-up
1
PDRG read
PDRG
Pin
PDRG write
Internal bus
Executing bit manipulation instruction
DDRG read
DDRG
DDRG write
Stop mode, watch mode (SPL = 1)
PULG read
PULG
PULG write
Document Number: 002-04692 Rev. *E
Page 77 of 129
MB95690K Series
17.7.3 Port G registers
• Port G register functions
Register
abbreviation
PDRG
DDRG
PULG
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRG value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRG value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port G
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
PG2
PG1
-
-
-
-
-
-
bit2
bit1
-
PDRG
DDRG
PULG
Document Number: 002-04692 Rev. *E
Page 78 of 129
MB95690K Series
17.7.4 Port G operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
• If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDRG register returns the PDRG register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDRG register, the PDRG register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDRG register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDRG register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register.
Document Number: 002-04692 Rev. *E
Page 79 of 129
MB95690K Series
18. Interrupt Source Table
Interrupt source
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
UART/SIO ch. 0
MPG (DTTI)
8/16-bit composite timer ch. 0
(lower)
8/16-bit composite timer ch. 0
(upper)
LIN-UART (reception)
LIN-UART (transmission)
8/16-bit PPG ch. 1 (lower)
8/16-bit PPG ch. 1 (upper)
8/16-bit PPG ch. 2 (upper)
8/16-bit PPG ch. 0 (upper)
8/16-bit PPG ch. 0 (lower)
8/16-bit composite timer ch. 1
(upper)
8/16-bit PPG ch. 2 (lower)
16-bit reload timer ch. 1
MPG (write timing/compare clear)
I2C bus interface ch. 0
16-bit PPG timer ch. 1
MPG (position detection/compare
interrupt)
8/10-bit A/D converter
Time-base timer
Watch prescaler
Comparator ch. 0
Comparator ch. 1
8/16-bit composite timer ch. 1
(lower)
Flash memory
Document Number: 002-04692 Rev. *E
Interrupt
request
number
Vector table
address
Upper
Lower
Interrupt level
setting register
Register
Bit
IRQ00
0xFFFA 0xFFFB
ILR0
L00 [1:0]
IRQ01
0xFFF8 0xFFF9
ILR0
L01 [1:0]
IRQ02
0xFFF6 0xFFF7
ILR0
L02 [1:0]
IRQ03
0xFFF4 0xFFF5
ILR0
L03 [1:0]
IRQ04
0xFFF2 0xFFF3
ILR1
L04 [1:0]
IRQ05
0xFFF0 0xFFF1
ILR1
L05 [1:0]
IRQ06
0xFFEE 0xFFEF
ILR1
L06 [1:0]
IRQ07
IRQ08
IRQ09
IRQ10
IRQ11
IRQ12
IRQ13
0xFFEC
0xFFEA
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
0xFFED
0xFFEB
0xFFE9
0xFFE7
0xFFE5
0xFFE3
0xFFE1
ILR1
ILR2
ILR2
ILR2
ILR2
ILR3
ILR3
L07 [1:0]
L08 [1:0]
L09 [1:0]
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
IRQ14
0xFFDE 0xFFDF
ILR3
L14 [1:0]
IRQ15
0xFFDC 0xFFDD
ILR3
L15 [1:0]
IRQ16
0xFFDA 0xFFDB
ILR4
L16 [1:0]
IRQ17
0xFFD8 0xFFD9
ILR4
L17 [1:0]
IRQ18
IRQ19
0xFFD6 0xFFD7
0xFFD4 0xFFD5
ILR4
ILR4
L18 [1:0]
L19 [1:0]
IRQ20
0xFFD2 0xFFD3
ILR5
L20 [1:0]
IRQ21
0xFFD0 0xFFD1
ILR5
L21 [1:0]
IRQ22
0xFFCE 0xFFCF
ILR5
L22 [1:0]
IRQ23
0xFFCC 0xFFCD
ILR5
L23 [1:0]
Priority order of
interrupt sources
of the same level
(occurring
simultaneously)
High
Low
Page 80 of 129
MB95690K Series
19. Pin States In Each Mode
Pin name
Normal
operation
Sleep mode
Oscillation input Oscillation input
PF0/X0
I/O port*
1
I/O port*
1
Oscillation input Oscillation input
PF1/X1
PF2/RST
I/O port*1
I/O port*1
Reset input*4
Reset input*4
I/O port
I/O port
I/O port*1
I/O port*1
Oscillation input Oscillation input
PG2/X1A/
SNI2
P00/INT00/
AN00/
CMP0_P
P01/INT01/
AN01/
CMP0_N
P03/INT03/
AN03/
CMP1_P
P04/INT04/
AN04/
CMP1_N
P02/INT02/
AN02/
CMP0_O
P05/INT05/
AN05/
CMP1_O
P06/INT06/
AN06
P07/INT07/
AN07
I/O port*
1
I/O port*
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
blocked*1, *2
Reset input
Reset input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Oscillation input Oscillation input
PG1/X0A/
SNI1
Stop mode
SPL=0
SPL=1
1
Hi-Z
Hi-Z
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1, *2
blocked*1, *2
Hi-Z
Hi-Z
Watch mode
SPL=0
SPL=1
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
blocked*1, *2
Reset input
Reset input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1, *2
blocked*1, *2
Hi-Z
Hi-Z
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
On reset
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Reset input*4
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
blocked*2, *6
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
blocked*2, *6
- Hi-Z
- Input
blocked*2
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Hi-Z*5
kept*8
- Input
- Input
blocked*2, *7
2,
7
blocked* *
- Previous state
- Hi-Z*5
kept*8
- Input
- Input
blocked*2, *7
2,
7
blocked* *
- Hi-Z
- Input
blocked*2
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Hi-Z
- Input
blocked*2
Document Number: 002-04692 Rev. *E
Page 81 of 129
MB95690K Series
Pin name
P12/DBG
P10/PPG10
P11/PPG11
P13/PPG00
P14/PPG01
P15/PPG20
P16/PPG21
P17/SNI0
P40/AN08
P41/AN09
P42/AN10
P43/AN11
P44/TO1
P46/SOT
P45/SCK
P47/SIN
Normal
operation
Sleep mode
Stop mode
SPL=0
SPL=1
Watch mode
SPL=0
SPL=1
On reset
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Previous state
- Hi-Z
- Hi-Z
kept
kept
- Input blocked*2
- Input blocked*2
- Input blocked*2
- Input blocked*2
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
2
2
Input
blocked*
Input
blocked*
(However,
it
- Input blocked*2
- Input blocked*2
does not
function.)
I/O port/
analog input
I/O port/
analog input
- Previous state
- Previous state
- Hi-Z
- Hi-Z*5
- Hi-Z
kept
kept
- Input
- Input blocked*2
- Input blocked*2
- Input blocked*2
- Input blocked*2
blocked*2
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
- Input blocked*2
- Input blocked*2 (However, it
2
2
- Input blocked*
- Input blocked*
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Previous state
- Hi-Z*5
kept
kept
- Hi-Z*5
- Input
- Input
- Input blocked*7 - Input
blocked*2, *7
blocked*2, *7
blocked*2, *7
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
2
2
- Input blocked*
- Input blocked* (However, it
- Input blocked*2
- Input blocked*2
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
P60/DTTI
P61/TI1
P62/TO10/
PPG00/
OPT0
P63/TO11/
PPG01/
OPT1
I/O port/
peripheral
function I/O
P65/PPG11/
OPT3
P66/PPG1/
PPG20/
OPT4
P64/EC1/
PPG10/
OPT2
P67/TRG1/
PPG21/
OPT5
I/O port/
peripheral
function I/O
Document Number: 002-04692 Rev. *E
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Page 82 of 129
MB95690K Series
(Continued)
Pin name
P72/SCL
P73/SDA
Normal
operation
I/O port/
peripheral
function I/O
Sleep mode
I/O port/
peripheral
function I/O
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
- Input blocked*2
- Input blocked*2 (However, it
2
2
- Input blocked*
- Input blocked*
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
P74/EC0
I/O port/
peripheral
function I/O
On reset
I/O port/
peripheral
function I/O
P76/UO0
P75/UCK0
Watch mode
SPL=0
SPL=1
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *9
2,
9
blocked* *
P70/TO00
P71/TO01
Stop mode
SPL=0
SPL=1
P77/UI0
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *9
2,
9
blocked* *
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
SPL: Pin state setting bit in the standby control register (STBC:SPL)
Hi-Z: High impedance
*1: The pin stays at the state shown when configured as a general-purpose I/O port.
*2: “Input blocked” means direct input gate operation from the pin is disabled.
*3: “Input enabled” means that the input function is enabled. While the input function is enabled, execute a pull-up or
pull-down operation in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is
the same as that of other ports.
*4: The PF2/RST pin stays at the state shown when configured as a reset pin.
*5: The pull-up control setting is still effective.
*6: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled, and an
analog signal can also be input to generate a comparator interrupt when the comparator interrupt is enabled.
*7: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled.
*8: The output function of the comparator is still in operation in stop mode and watch mode.
*9: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “New 8FX MB95690K Series Hardware Manual”.
Document Number: 002-04692 Rev. *E
Page 83 of 129
MB95690K Series
20. Electrical Characteristics
20.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Power supply voltage*1
VCC
VSS − 0.3 VSS + 6
V
Input voltage*1
VI
VSS − 0.3 VSS + 6
V
*2
Output voltage*1
VO
VSS − 0.3 VSS + 6
V
*2
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Min
+2
mA Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA Applicable to specific pins*3
IOL
—
15
mA
4
—
IOLAV2
“H” level maximum
output current
mA
12
Other than P60 to P67
Average output current =
operating current × operating ratio (1 pin)
P60 to P67
Average output current =
operating current × operating ratio (1 pin)
ΣIOL
—
100
mA
ΣIOLAV
—
37
Total average output current =
mA operating current × operating ratio
(Total number of pins)
IOH
—
−15
mA
−4
IOHAV1
“H” level average
current
—
mA
−8
IOHAV2
“H” level total maximum
output current
Remarks
−2
“L” level average current
“L” level total average
output current
Unit
ICLAMP
IOLAV1
“L” level total maximum
output current
Max
Other than P60 to P67
Average output current =
operating current × operating ratio (1 pin)
P60 to P67
Average output current =
operating current × operating ratio (1 pin)
ΣIOH
—
−100
mA
ΣIOHAV
—
−47
Total average output current =
mA operating current × operating ratio
(Total number of pins)
Power consumption
Pd
—
320
mW
Operating temperature
TA
−40
+85
Storage temperature
Tstg
−55
+150
°C
°C
“H” level total average
output current
*1: These parameters are based on the condition that VSS is 0.0 V.
*2: V1 and V0 must not exceed VCC + 0.3 V. V1 must not exceed the rated voltage. However, if the maximum current
to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
*3: Specific pins: P00 to P07, P10, P11, P13 to P17, P40 to P47, P60 to P67, P70, P71, P74 to P77, PF0, PF1, PG1, PG2
Document Number: 002-04692 Rev. *E
Page 84 of 129
MB95690K Series
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between
the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin
when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient
current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage)
input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power
is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power
supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04692 Rev. *E
Page 85 of 129
MB95690K Series
20.2 Recommended Operating Conditions
Parameter
Symbol
(VSS = 0.0 V)
Value
Min
Max
Unit
Power supply voltage
VCC
2.88
5.5
V
Decoupling capacitor
CS
0.022
1
µF
Operating temperature
TA
−40
+85
+5
+35
°C
Remarks
*
Other than on-chip debug mode
On-chip debug mode
*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the
VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling
capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to
noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Connect the DBG pin to an external pull-up resistor of 2 kΩ or above. After power-on, ensure that the
DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the
interconnection length, refer to the tool document when selecting a pull-up resistor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
Document Number: 002-04692 Rev. *E
Page 86 of 129
MB95690K Series
20.3 DC Characteristics
Parameter Symbol
“H” level
input
voltage
“L” level
input
voltage
Open-drain
output
application
voltage
“H” level
output
voltage
“L” level
output
voltage
Input leak
current (Hi-Z
output leak
current)
Internal
pull-up
resistor
Input
capacitance
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Pin name
Condition
VIHI
P47, P72, P73,
P77
VIHS
Value
Unit
Remarks
VCC + 0.3
V
CMOS input level
—
VCC + 0.3
V
Hysteresis input
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
—
VSS − 0.3
—
0.3 VCC
V
CMOS input level
Other than P47,
P72, P73, P77,
PF2
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
PF2
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
P12, P72, P73,
PF2
—
VSS − 0.3
—
VSS + 5.5
V
VOH1
Output pins
other than P12,
IOH = −4 mA
P60 to P67,
PF2
VCC − 0.5
—
—
V
VOH2
P60 to P67
IOH = −8 mA
VCC − 0.5
—
—
V
VOL1
Output pins
other than P60 IOL = 4 mA
to P67
—
—
0.4
V
VOL2
P60 to P67
IOL = 12 mA
—
—
0.4
V
All input pins
0.0 V < VI < VCC
−5
—
+5
When the internal
µA pull-up resistor is
disabled
Other than P12,
P72, P73, PF0, VI = 0 V
PF1, PF2
25
50
100
When the internal
kΩ pull-up resistor is
enabled
Other than VCC
f = 1 MHz
and VSS
—
5
15
pF
Min
Typ
Max
—
0.7 VCC
—
Other than P47,
P72, P73, P77,
PF2
—
0.8 VCC
VIHM
PF2
—
VILI
P47, P72, P73,
P77
VILS
VILM
VD
ILI
RPULL
CIN
Document Number: 002-04692 Rev. *E
Page 87 of 129
MB95690K Series
Parameter
Power
supply
current*3
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Min Typ*1 Max*2
Except during
Flash memory
—
4.9
5.8
mA
programming and
FCH = 32 MHz
erasing
FMP = 16 MHz
During Flash
ICC
Main clock mode
memory
(divided by 2)
—
10.5 13.8 mA
programming and
erasing
—
6.5
9.1
mA At A/D conversion
FCH = 32 MHz
FMP = 16 MHz
ICCS
—
2
3
mA
Main sleep mode
(divided by 2)
VCC
(External clock FCL = 32 kHz
operation)
FMPL = 16 kHz
Subclock mode
ICCL
—
75.9 145
µA
(divided by 2)
TA = +25 °C
FCL = 32 kHz
FMPL = 16 kHz
In deep standby
Subsleep mode
—
12.7
16
µA
ICCLS
mode
(divided by 2)
TA = +25 °C
FCL = 32 kHz
Watch mode
In deep standby
—
11
13
µA
ICCT
Main stop mode
mode
TA = +25 °C
FMCRPLL = 16 MHz
FMP = 16 MHz
Main CR PLL clock
ICCMPLL
—
5.2
6.8
mA
mode
(multiplied by 4)
TA = +25 °C
VCC
FCRH = 4 MHz
FMP = 4 MHz
—
1.4
4.6
mA
ICCMCR
Main CR clock
mode
Sub-CR clock mode
(divided by 2)
—
76.9 230
µA
ICCSCR
TA = +25 °C
FCH = 32 MHz
Time-base timer
In deep standby
—
387
455
µA
ICCTS VCC
mode
mode
(External clock
TA = +25 °C
operation)
Substop mode
In deep standby
—
10.8
13
µA
ICCH
TA = +25 °C
mode
Document Number: 002-04692 Rev. *E
Page 88 of 129
MB95690K Series
Parameter
Symbol
Pin name
IV
ILVD
ICRH
Power
supply
current*3
VCC
ICRL
INSTBY
Condition
Current
consumption of the
comparator
Current
consumption of the
low-voltage
detection reset
circuit
Current
consumption of the
main CR oscillator
Current
consumption of the
sub-CR oscillator
oscillating at
100 kHz
Current
consumption
difference between
normal standby
mode and deep
standby mode
TA = +25 °C
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit
Remarks
Min Typ*1 Max*2
—
60
160
µA
—
4
7
µA
—
240
320
µA
—
7
20
µA
—
18
30
µA
With the LVD reset
already enabled by
the LVD reset
circuit control
register (LVDCC)
*1: VCC = 5.0 V, TA = +25 °C
*2: VCC = 5.5 V, TA = +85 °C (unless otherwise specified)
*3: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power supply current is the sum of adding the current consumption of the low-voltage detection reset
circuit (ILVD) to one of the values from ICC to ICCH. In addition, when both the low-voltage detection option and a CR
oscillator are selected, the power supply current is the sum of adding up the current consumption of the low-voltage
detection reset circuit (ILVD), the current consumption of the CR oscillators (ICRH or ICRL) and one of the values from
ICC to ICCH. In on-chip debug mode, the main CR oscillator (ICRH) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly.
• See “4. AC Characteristics Clock Timing” for FCH, FCL, FCRH and FMCRPLL.
• See “4. AC Characteristics Source Clock/Machine Clock” for FMP and FMPL.
• The power supply current value in standby mode is measured in deep standby mode. The current consumption in
normal standby mode is higher than that in deep standby mode. The power supply current value in normal standby
mode can be found by adding the current consumption difference between normal standby mode and deep standby
mode (INSTBY) to the power supply current value in deep standby mode. For details of normal standby mode and
deep standby mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in “New 8FX MB95690K Series Hardware
Manual”.
Document Number: 002-04692 Rev. *E
Page 89 of 129
MB95690K Series
20.4 AC Characteristics
20.4.1 Clock Timing
Parameter
Symbol Pin name Condition
X0, X1
FCH
X0
X0, X1
—
X1: open
*
Min
1
1
1
3.92
FCRH
—
—
3.8
7.84
7.6
9.8
Clock
frequency
9.5
FMCRPLL
—
—
11.76
11.4
15.68
15.2
—
FCL
X0A, X1A
—
—
FCRL
—
Document Number: 002-04692 Rev. *E
—
50
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit
Remarks
Typ
Max
When the main oscillation
—
16.25 MHz
circuit is used
—
12
MHz When the main external clock
—
32.5 MHz is used
Operating conditions
4
4.08 MHz • The main CR clock is used.
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• The main CR clock is used.
4
4.2 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
8
8.16 MHz • PLL multiplication rate: 2
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 2
8
8.4 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
10
10.2 MHz • PLL multiplication rate: 2.5
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 2.5
10
10.5 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
12
12.24 MHz • PLL multiplication rate: 3
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 3
12
12.6 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
16
16.32 MHz • PLL multiplication rate: 4
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 4
16
16.8 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
When the sub-oscillation
32.768
—
kHz
circuit is used
When the sub-external clock
32.768
—
kHz
is used
When the sub-CR clock is
100
150 kHz
used
Page 90 of 129
MB95690K Series
Parameter
Symbol Pin name Condition
⎯
X0, X1
Clock cycle
time
tHCYL
X0
X1: open
X0, X1
*
tLCYL X0A, X1A
⎯
X0
X1: open
tWH1, tWL1
Input clock
X0, X1
*
pulse width
tWH2, tWL2 X0A
⎯
Input clock
X0, X0A X1: open
rising time and tCR, tCF X0, X1,
*
falling time
X0A, X1A
Min
61.5
83.4
30.8
⎯
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit
Remarks
Typ
Max
When the main oscillation
1000 ns
⎯
circuit is used
1000 ns When an external clock is
⎯
1000 ns used
⎯
⎯
⎯
⎯
⎯
30.5
⎯
⎯
33.4
12.4
—
—
15.2
⎯
—
—
5
µs
ns
ns
µs
ns
5
ns
When the subclock is used
When an external clock is
used, the duty ratio should
range between 40% and 60%.
When an external clock is
used
When the main CR clock is
used
When the sub-CR clock is
tCRLWK
—
—
—
—
30
µs
used
PLL oscillation
When the main CR PLL clock
tMCRPLLWK
—
—
—
—
100
µs
start time
is used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
CR oscillation
start time
tCRHWK
—
—
—
—
50
µs
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tCR
tWL1
tCF
0.8 VCC 0.8 VCC
X0, X1
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When an external clock is used When an external clock
(X1 is open)
is used
X0
X1
FCH
X1
X1
Open
FCH
Document Number: 002-04692 Rev. *E
X0
FCH
Page 91 of 129
MB95690K Series
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
When an external clock
is used
X0A
X1A
Open
FCL
FCL
• Input waveform generated when an internal clock (main CR clock) is used
tCRHWK
1/FCRH
Main CR clock
Oscillation starts
Oscillation stabilizes
• Input waveform generated when an internal clock (sub-CR clock) is used
tCRLWK
1/FCRL
Sub-CR clock
Oscillation starts
Document Number: 002-04692 Rev. *E
Oscillation stabilizes
Page 92 of 129
MB95690K Series
• Input waveform generated when an internal clock (main CR PLL clock) is used
1/FMCRPLL
tMCRPLLWK
Main CR PLL clock
Oscillation starts
Oscillation stabilizes
20.4.2 Source Clock/Machine Clock
Parameter
Symbol
Pin
name
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Min
Value
Typ
Max
Unit
Remarks
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
When the main CR clock is used
62.5
—
1000
ns Min: FCRH = 4 MHz, multiplied by 4
Source clock
tSCLK
—
cycle time*1
Max: FCRH = 4 MHz, divided by 4
When the suboscillation clock is used
—
61
—
µs
FCL = 32.768 kHz, divided by 2
When the sub-CR clock is used
—
20
—
µs
FCL = 100 kHz, divided by 2
0.5
—
16.25 MHz When the main oscillation clock is used
FSP
—
4
12.5 MHz When the main CR clock is used
Source clock
—
—
16.384
—
kHz When the suboscillation clock is used
frequency
FSPL
When the sub-CR clock is used
—
50
—
kHz
FCRL = 100 kHz, divided by 2
When the main oscillation clock is used
61.5
—
32000 ns Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
When the main CR clock is used
Machine clock
250
—
4000
ns Min: FSP = 4 MHz, no division
2
cycle time*
Max: FSP = 4 MHz, divided by 16
(minimum
tMCLK
—
When the suboscillation clock is used
instruction
61
—
976.5
µs Min: FSPL = 16.384 kHz, no division
execution time)
Max: FSPL = 16.384 kHz, divided by 16
When the sub-CR clock is used
20
—
320
µs Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25 MHz When the main oscillation clock is used
FMP
0.25
—
16
MHz When the main CR clock is used
Machine clock
—
1.024
—
16.384 kHz When the suboscillation clock is used
frequency
FMPL
When the sub-CR clock is used
3.125
—
50
kHz
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits
(SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the
61.5
Document Number: 002-04692 Rev. *E
—
2000
ns
Page 93 of 129
MB95690K Series
machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following.
• Main clock divided by 2
• Main CR clock
• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Schematic diagram of the clock generation block
FCH
(Main oscillation clock)
Divided by 2
FMCRPLL
(Main CR PLL clock)
SCLK
(Source clock)
FCRH
(Main CR clock)
FCL
(Suboscillation clock)
Division circuit
×
1
× 1/4
× 1/8
× 1/16
MCLK
(Machine clock)
Divided by 2
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
FCRL
(Sub-CR clock)
Divided by 2
Clock mode select bits
(SYCC:SCS[2:0])
• Operating voltage - Operating Frequency (TA = −40 °C to +85 °C)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
Document Number: 002-04692 Rev. *E
Page 94 of 129
MB95690K Series
20.4.3 External Reset
Parameter
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
RST “L” level
pulse width
tRSTL
Min
Max
2 tMCLK*
—
Unit
Remarks
ns
*: See “Source Clock/Machine Clock” for tMCLK.
tRSTL
RST
0.2 VCC
0.2 VCC
20.4.4 Power-on Reset
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power
supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
Document Number: 002-04692 Rev. *E
Page 95 of 129
MB95690K Series
20.4.5 Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
Value
Pin name
INT00 to INT07, EC0, EC1, TI1,
TRG1
Min
Max
2 tMCLK*
⎯
⎯
2 tMCLK*
Unit
ns
ns
*: See “Source Clock/Machine Clock” for tMCLK.
tILIH
0.8 VCC
INT00 to INT07,
EC0, EC1, TI1,
TRG1
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
20.4.6 LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Serial clock cycle time
Symbol Pin name
Value
Condition
Max
5 tMCLK*3
—
ns
−50
tSCYC
SCK
SCK↓ → SOT delay time
tSLOVI
Valid SIN → SCK↑
tIVSHI
t
SCK↑ → valid SIN hold time
tSHIXI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
Serial clock “L” pulse width
tSLSH
SCK
3t
Serial clock “H” pulse width
tSHSL
SCK
t
SCK↓ → SOT delay time
tSLOVE
Valid SIN → SCK↑
tIVSHE
SCK↑ → valid SIN hold time
tSHIXE
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* −tR
—
ns
* + 10
—
ns
MCLK 3
MCLK 3
—
t
Unit
Min
2t
* + 60 ns
MCLK 3
30
—
ns
MCLK 3
* + 30
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
Document Number: 002-04692 Rev. *E
Page 96 of 129
MB95690K Series
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOVI
0.8 VCC
SOT
0.2 VCC
tIVSHI
tSHIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
0.8 VCC
SOT
0.2 VCC
tIVSHE
tSHIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
Document Number: 002-04692 Rev. *E
Page 97 of 129
MB95690K Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Serial clock cycle time
Symbol Pin name
Value
Condition
Max
5 tMCLK*3
—
ns
−50
tSCYC
SCK
SCK↑ → SOT delay time
tSHOVI
Valid SIN → SCK↓
tIVSLI
t
SCK↓→ valid SIN hold time
tSLIXI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
Serial clock “H” pulse width
tSHSL
SCK
3t
Serial clock “L” pulse width
tSLSH
SCK
t
SCK↑ → SOT delay time
tSHOVE
Valid SIN → SCK↓
tIVSLE
SCK↓→ valid SIN hold time
tSLIXE
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − tR
—
ns
* + 10
—
ns
MCLK 3
MCLK 3
—
t
Unit
Min
2t
* + 60 ns
MCLK 3
30
—
ns
MCLK 3
* + 30
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
Document Number: 002-04692 Rev. *E
Page 98 of 129
MB95690K Series
• Internal shift clock mode
tSCYC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tSHOVI
0.8 VCC
SOT
0.2 VCC
tIVSLI
tSLIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
0.8 VCC
SOT
0.2 VCC
tIVSLE
tSLIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
Document Number: 002-04692 Rev. *E
Page 99 of 129
MB95690K Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK↑ → SOT delay time
tSHOVI
Valid SIN → SCK↓
tIVSLI
t
SCK↓→ valid SIN hold time
tSLIXI
SCK, SOT Internal clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SOT → SCK↓delay time
tSOVLI
SCK, SOT
3t
Unit
Min
Max
5 tMCLK*3
—
ns
−50
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − 70
—
ns
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.2 VCC
SOT
0.2 VCC
tSHOVI
tSOVLI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIVSLI
SIN
tSLIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK↓ → SOT delay time
tSLOVI
Valid SIN → SCK↑
tIVSHI
t
SCK↑ → valid SIN hold time
tSHIXI
SCK, SOT Internal clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SOT → SCK↑delay time
tSOVHI
SCK, SOT
3t
Unit
Min
Max
5 tMCLK*3
—
ns
−50
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − 70
—
ns
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
Document Number: 002-04692 Rev. *E
Page 100 of 129
MB95690K Series
tSCYC
0.8 VCC
SCK
0.8 VCC
0.2 VCC
tSOVHI
SOT
tSLOVI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIVSHI
SIN
tSHIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
20.4.7 Low-voltage Detection
Parameter
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Release voltage*
VDL+
Detection voltage*
VDL−
Min
2.52
2.61
2.89
3.08
2.43
2.52
2.80
2.99
—
Value
Typ
2.7
2.8
3.1
3.3
2.6
2.7
3
3.2
—
Max
2.88
2.99
3.31
3.52
2.77
2.88
3.20
3.41
100
Unit
Remarks
V
At power supply rise
V
At power supply fall
Hysteresis width
VHYS
mV
Power supply start
Voff
—
—
2.3
V
voltage
Power supply end
Von
4.9
—
—
V
voltage
Power supply voltage
Slope of power supply that the reset
change time
tr
650
—
—
µs release signal generates within the
(at power supply rise)
rating (VDL+)
Power supply voltage
Slope of power supply that the reset
change time
tf
650
—
—
µs release signal generates within the
(at power supply fall)
rating (VDL-)
Reset release delay
td1
—
—
30
µs
time
Reset detection delay
td2
—
—
30
µs
time
LVD reset threshold
voltage transition
tstb
10
—
—
µs
stabilization time
*: After the LVD reset is enabled by the LVD reset circuit control register (LVDCC), the release voltage and the detection
voltage can be selected by using the LVD reset voltage selection ID register (LVDR) in the low-voltage detection reset
circuit. For details of the LVDCC register and the LVDR register, refer to “CHAPTER 16 LOW-VOLTAGE
DETECTION RESET CIRCUIT” in “New 8FX MB95690K Series Hardware Manual”.
Document Number: 002-04692 Rev. *E
Page 101 of 129
MB95690K Series
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
Document Number: 002-04692 Rev. *E
td1
Page 102 of 129
MB95690K Series
20.4.8 I2C Bus Interface Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Standardmode
Fast-mode
Min
Max
Min
Max
0
100
0
400
kHz
SCL, SDA
4.0
—
0.6
—
µs
Symbol Pin name Condition
SCL clock frequency
fSCL
(Repeated) START condition hold
time
SDA ↓ → SCL ↓
tHD;STA
SCL
Unit
SCL clock “L” width
tLOW
SCL
4.7
—
1.3
—
µs
SCL clock “H” width
tHIGH
SCL
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
(Repeated) START condition setup
time
SCL ↑ → SDA ↓
tSU;STA
SCL, SDA
Data hold time
SCL ↓ → SDA ↓↑
tHD;DAT
SCL, SDA
0
3.45*2
0
0.9*3
µs
Data setup time
SDA ↓↑ → SCL ↑
tSU;DAT
SCL, SDA
0.25
—
0.1
—
µs
STOP condition setup time
SCL ↑ → SDA ↑
tSU;STO
SCL, SDA
4
—
0.6
—
µs
tBUF
SCL, SDA
4.7
—
1.3
—
µs
Bus free time between STOP
condition and START condition
R = 1.7 kΩ,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the
SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT
≥ 250 ns is fulfilled.
tWAKEUP
SDA
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL
tHD;STA
Document Number: 002-04692 Rev. *E
tSU;DAT
fSCL
tSU;STA
tSU;STO
Page 103 of 129
MB95690K Series
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value*2
Pin
Unit
Remarks
Parameter Symbol
Condition
name
Min
Max
SCL clock
tLOW SCL
(2 + nm/2)tMCLK − 20
—
ns Master mode
“L” width
SCL clock
tHIGH SCL
(nm/2)tMCLK − 20
(nm/2)tMCLK + 20
ns Master mode
“H” width
Master mode
Maximum value
is applied when
START
SCL,
(-1 + nm/2)tMCLK − 20 (-1 + nm)tMCLK + 20 ns m, n = 1, 8.
condition
tHD;STA
SDA
Otherwise, the
hold time
minimum value is
applied.
STOP
SCL,
condition
tSU;STO
(1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode
SDA
setup time
START
SCL,
condition
tSU;STA
(1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode
SDA
setup time
Bus free time
between
STOP
SCL,
tBUF
(2 nm + 4) tMCLK − 20
—
ns
condition
SDA
and START
condition
R = 1.7 kΩ,
SCL,
Data hold
C = 50 pF*1
3 tMCLK − 20
—
ns Master mode
tHD;DAT
SDA
time
Master mode
It is assumed that
“L” of SCL is not
extended. The
minimum value is
Data setup
SCL,
tSU;DAT
(-2 + nm/2) tMCLK − 20 (-1 + nm/2) tMCLK + 20 ns
applied to the first
time
SDA
bit of continuous
data. Otherwise,
the maximum
value is applied.
The minimum
value is applied
Setup time
to the interrupt at
between
the ninth SCL↓.
clearing
tSU;INT SCL
(nm/2) tMCLK − 20 (1 + nm/2) tMCLK + 20 ns
The maximum
interrupt and
value is applied
SCL rising
to the interrupt at
the eighth SCL↓.
SCL clock
tLOW SCL
4 tMCLK − 20
—
ns At reception
“L” width
SCL clock
tHIGH SCL
4 tMCLK − 20
—
ns At reception
“H” width
Document Number: 002-04692 Rev. *E
Page 104 of 129
MB95690K Series
Parameter
Pin
Symbol
Condition
name
START condition
detection
tHD;STA
SCL,
SDA
STOP condition
detection
tSU;STO
SCL,
SDA
RESTART
condition detection
condition
tSU;STA
SCL,
SDA
Bus free time
tBUF
Data hold time
tHD;DAT
Data setup time
tSU;DAT
Data hold time
tHD;DAT
Data setup time
tSU;DAT
SDA↓ → SCL↑
(with wakeup
function in use)
tWAKEUP
SCL,
SDA
SCL,
SDA
SCL,
SDA
SCL,
SDA
SCL,
SDA
SCL,
SDA
R = 1.7 kΩ,
C = 50 pF*1
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value*2
Unit
Remarks
Min
Max
No START
condition is
2 tMCLK − 20
—
ns detected when 1
tMCLK is used at
reception.
No STOP condition
is detected when 1
2 tMCLK − 20
—
ns
tMCLK is used at
reception.
No RESTART
condition is
2 tMCLK − 20
—
ns detected when 1
tMCLK is used at
reception.
2 tMCLK − 20
—
ns At reception
2 tMCLK − 20
—
ns
tLOW − 3 tMCLK − 20
—
0
—
ns At reception
tMCLK − 20
—
ns At reception
Oscillation
stabilization wait time
+2 tMCLK − 20
—
ns
At slave
transmission mode
At slave
ns
transmission mode
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: • See “Source Clock/Machine Clock” for tMCLK.
• m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0).
• n represents the CS[2:0] bits in the I2C clock control register ch. 0 (ICCR0).
• The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK)
and the CS[4:0] bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
: 0.9 MHz < tMCLK ≤ 10 MHz
(m, n) = (8, 22)
: 0.9 MHz < tMCLK ≤ 16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
(m, n) = (5, 8)
: 3.3 MHz < tMCLK ≤ 16.25 MHz
Document Number: 002-04692 Rev. *E
Page 105 of 129
MB95690K Series
20.4.9 UART/SIO, Serial I/O Timing
Parameter
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin name
Value
Condition
Unit
Min
Max
4 tMCLK*
—
ns
−190
+190
ns
2 tMCLK*
—
ns
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
—
ns
Serial clock “H” pulse width
tSHSL
UCK0
4 tMCLK*
—
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
—
ns
UCK ↓ → UO time
tSLOV
UCK0, UO0
—
190
ns
Valid UI → UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
—
ns
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
—
ns
Internal clock operation
External clock operation
*: See “Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
0.8 VCC
UCK0
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
UO0
0.2 VCC
tIVSH
tSHIX
0.7 VCC 0.7 VCC
UI0
0.3 VCC 0.3 VCC
Document Number: 002-04692 Rev. *E
Page 106 of 129
MB95690K Series
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
UCK0
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
UO0
0.2 VCC
tIVSH
tSHIX
0.7 VCC 0.7 VCC
UI0
0.3 VCC 0.3 VCC
20.4.10 MPG Input Timing
Parameter
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin name
Condition
tTIWH,
tTIWL
SNI0 to SNI2,
DTTI
—
Input pulse width
Value
Min
Max
4 tMCLK
—
Unit
Remarks
ns
0.8 VCC
0.8 VCC
SNI0 to SNI2, DTTI
0.2 VCC
tTIWH
Document Number: 002-04692 Rev. *E
0.2 VCC
tTIWL
Page 107 of 129
MB95690K Series
20.4.11 Comparator Timing
Parameter
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Pin name
Value
Unit
Remarks
Min
Typ
Max
Voltage range
CMP0_P,
CMP0_N,
CMP1_P,
CMP1_N
0
—
VCC − 1.3
V
Offset voltage
CMP0_P,
CMP0_N,
CMP1_P,
CMP1_N
−15
—
+15
mV
Delay time
CMP0_O,
CMP1_O
—
650
1200
ns
Overdrive 5 mV
—
140
420
ns
Overdrive 50 mV
Power down delay
CMP0_O,
CMP1_O
—
—
1200
ns
Power down recovery
PD: 1 → 0
Power up
CMP0_O,
stabilization wait time CMP1_O
—
—
1200
ns
Output stabilization wait time at
power up
20.4.12 BGR for Comparator
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Power up
stabilization wait time
Output voltage
Value
Unit
Min
Typ
Max
—
—
—
150
µs
VBGR
1.1495
1.21
1.2705
V
Document Number: 002-04692 Rev. *E
Remarks
Load: 10 pF
Page 108 of 129
MB95690K Series
20.5 A/D Converter
20.5.1 A/D Converter Electrical Characteristics
Parameter
(VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Unit
Min
Typ
Max
Resolution
—
—
10
bit
Total error
−3
—
+3
LSB
−2.5
—
+2.5
LSB
−1.9
—
+1.9
LSB
—
Linearity error
Differential linearity
error
Zero transition
voltage
V0T
VSS − 7.2 LSB VSS + 0.5 LSB VSS + 8.2 LSB
V
Full-scale transition
voltage
VFST
VCC − 6.2 LSB VCC − 1.5 LSB VCC + 9.2 LSB
V
Compare time
—
3
—
10
Remarks
µs
2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V,
with external
impedance < 3.3 kΩ
and external
capacitance = 10 pF
Sampling time
—
0.941
—
∞
µs
Analog input current
IAIN
−0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
20.5.2 Notes on Using A/D Converter
• External impedance of analog input and its sampling time
The A/D converter of the MB95690K Series has a sample and hold circuit. If the external impedance is too high to
keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the
register value and operating frequency or decrease the external impedance so that the sampling time is longer than
the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to
the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
1.45 kΩ (Max)
14.89 pF (Max)
2.7 V ≤ VCC < 4.5 V
2.7 kΩ (Max)
14.89 pF (Max)
Note: The values are reference values.
Document Number: 002-04692 Rev. *E
Page 109 of 129
MB95690K Series
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
100
External impedance [kΩ]
80
60
40
20
0
0
2
4
6
8
10
12
14
16
18
20
Minimum sampling time [μs]
[External impedance = 0 kΩ to 20 kΩ]
External impedance [kΩ]
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Minimum sampling time [μs]
Note: External capacitance = 10 pF
• A/D conversion error
As |VCC − VSS| decreases, the A/D conversion error increases proportionately.
Document Number: 002-04692 Rev. *E
Page 110 of 129
MB95690K Series
20.5.3 Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point
(“0000000000” ← → “0000000001”) of a device to the full-scale transition point (“1111111111” ← → “1111111110”) of
the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
0x3FF
0x3FF
2 LSB
0x3FD
Digital output
Digital output
0x3FD
0x004
0x003
Actual conversion
characteristic
0x3FE
0x3FE
V0T
{1 LSB × (N − 1) + 0.5 LSB}
0x004
VNT
0x003
1 LSB
0x002
0x002
0x001
Actual conversion
characteristic
Ideal characteristic
0x001
0.5 LSB
VSS
Analog input
1 LSB =
VCC
VCC − VSS
V
1024
N
VSS
Analog input
Total error of digital output N =
VCC
VNT − {1 LSB × (N − 1) + 0.5 LSB}
LSB
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN
Document Number: 002-04692 Rev. *E
Page 111 of 129
MB95690K Series
Zero transition error
Full-scale transition error
0x004
Ideal characteristic
Actual conversion
characteristic
0x3FF
Actual conversion
characteristic
0x002
Ideal
characteristic
Digital output
Digital output
0x003
Actual conversion
characteristic
0x3FE
VFST
(measurement
value)
0x3FD
Actual conversion
characteristic
0x001
0x3FC
V0T (measurement value)
VSS
Analog input
VCC
VSS
Linearity error
0x3FF
0x3FE
Ideal characteristic
0x(N+1)
Actual conversion
characteristic
{1 LSB × N + V0T}
VFST
Digital output
Digital output
0x3FD
(measurement
value)
VNT
0x004
0x002
VCC
Differential linearity error
Actual conversion
characteristic
V(N+1)T
0xN
VNT
0x(N−1)
Actual conversion
characteristic
0x003
Analog input
Ideal
characteristic
Actual conversion
characteristic
0x(N−2)
0x001
V0T (measurement value)
VSS
Analog input
VCC
Linearity error of digital output N =
VSS
VCC
VNT − {1 LSB × N + V0T}
1 LSB
Differential linearity error of digital output N =
N
Analog input
V(N+1)T − VNT
− 1
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN
V0T (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC − 2 LSB [V]
Document Number: 002-04692 Rev. *E
Page 112 of 129
MB95690K Series
20.6 Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
1.6*2
s
The time of writing “0x00” prior to erasure is excluded.
0.6*1
3.1*2
s
The time of writing “0x00” prior to erasure is excluded.
17
272
µs
System-level overhead is excluded.
Program/erase cycle 100000
—
—
cycle
Power supply voltage
at program/erase
2.4
—
5.5
V
20*3
—
—
Average TA = +85 °C
Number of program/erase cycles: 1000 or below
10*3
—
—
Average TA = +85 °C
year Number of program/erase cycles: 1001 to 10000
inclusive
5*3
—
—
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.3*1
Sector erase time
(32 Kbyte sector)
—
Byte writing time
—
Flash memory data
retention time
Average TA = +85 °C
Number of program/erase cycles: 10001 or above
*1: VCC = 5.5 V, TA = +25 °C, 0 cycle
*2: VCC = 2.4 V, TA = +85 °C, 100000 cycles
*3: These values were converted from the result of a technology reliability assessment. (These values were converted
from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85 °C.)
Document Number: 002-04692 Rev. *E
Page 113 of 129
MB95690K Series
21. Sample Characteristics
• Power supply current temperature characteristics
ICC − VCC
TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC − TA
VCC = 5.5 V, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
15
ICC[mA]
ICC[mA]
15
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
10
10
5
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
ICCS − VCC
TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
+150
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
6
ICCS[mA]
6
ICCS[mA]
+100
ICCS − TA
VCC = 5.5 V, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
10
4
4
2
2
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICCL − VCC
TA = +25 °C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
75
75
ICCL[μA]
ICCL[μA]
+50
TA[°C]
50
25
50
25
0
0
2
3
4
5
VCC[V]
Document Number: 002-04692 Rev. *E
6
7
−50
0
+50
+100
+150
TA[°C]
Page 114 of 129
MB95690K Series
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
80
80
70
70
60
60
50
50
ICCLS[μA]
ICCLS[μA]
ICCLS − VCC
TA = +25 °C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
40
30
40
30
20
20
10
10
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+100
+150
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
80
80
70
70
60
60
50
50
ICCT[μA]
ICCT[μA]
ICCT − VCC
TA = +25 °C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
40
40
30
30
20
20
10
10
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICCTS − VCC
TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICCTS − TA
VCC = 5.5 V, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
1.4
1.4
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.0
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.2
1.0
ICCTS[mA]
1.2
ICCTS[mA]
+50
TA[°C]
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
2
3
4
5
VCC[V]
Document Number: 002-04692 Rev. *E
6
7
−50
0
+50
+100
+150
TA[°C]
Page 115 of 129
MB95690K Series
ICCH − TA
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[μA]
ICCH[μA]
ICCH − VCC
TA = +25 °C, FMPL = (stop)
Substop mode with the external clock stopping
10
10
5
5
0
0
1
2
3
4
5
6
−50
7
0
ICCMCR − VCC
TA = +25 °C, FMP = 4 MHz (no division)
Main CR clock mode
+100
+150
ICCMCR − TA
VCC = 5.5 V, FMP = 4 MHz (no division)
Main CR clock mode
20
20
15
15
ICCMCR[mA]
ICCMCR[mA]
+50
TA[°C]
VCC[V]
10
5
10
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
10
10
8
8
6
6
ICCMPLL[mA]
ICCMPLL[mA]
ICCMPLL − VCC
ICCMPLL − TA
TA = +25 °C, FMP = 16 MHz (PLL multiplication rate: 4) VCC = 5.5 V, FMP = 16 MHz (PLL multiplication rate: 4)
Main CR PLL clock mode
Main CR PLL clock mode
4
2
4
2
0
0
1
2
3
4
5
VCC[V]
Document Number: 002-04692 Rev. *E
6
7
−50
0
+50
+100
+150
TA[°C]
Page 116 of 129
MB95690K Series
ICCSCR − TA
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Sub-CR clock mode
200
200
150
150
ICCSCR[μA]
ICCSCR[μA]
ICCSCR − VCC
TA = +25 °C, FMPL = 50 kHz (divided by 2)
Sub-CR clock mode
100
100
50
50
0
0
2
3
4
5
VCC[V]
Document Number: 002-04692 Rev. *E
6
7
−50
0
+50
+100
+150
TA[°C]
Page 117 of 129
MB95690K Series
• Input voltage characteristics
VIHI − VCC and VILI − VCC
TA = +25 °C
VIHS − VCC and VILS − VCC
TA = +25 °C
5
5
VIHI
VILI
VIHS
VILS
4
3
3
VIHI/VILI[V]
VIHS/VILS[V]
4
2
1
2
1
0
0
2
3
4
5
6
7
2
3
4
VCC[V]
5
6
7
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25 °C
5
VIHM
VILM
VIHM/VILM[V]
4
3
2
1
0
2
3
4
5
6
7
VCC[V]
Document Number: 002-04692 Rev. *E
Page 118 of 129
MB95690K Series
• Output voltage characteristics
(VCC − VOH2) − IOH
TA = +25 °C
2.0
2.0
1.8
1.8
1.6
1.6
1.4
1.4
VCC − VOH2[V]
VCC − VOH1[V]
(VCC − VOH1) − IOH
TA = +25 °C
1.2
1.0
0.8
1.2
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15
0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15
IOH[mA]
IOH[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL1 − IOL
TA = +25 °C
VOL2 − IOL
TA = +25 °C
1.0
2.0
1.8
1.6
0.8
1.4
0.6
VOL2[V]
VOL1[V]
1.2
1.0
0.8
0.4
0.6
0.4
0.2
0.2
0.0
0.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOL[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
Document Number: 002-04692 Rev. *E
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOL[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
Page 119 of 129
MB95690K Series
• Pull-up characteristics
RPULL − VCC
TA = +25 °C
200
RPULL[kΩ]
150
100
50
0
2
3
4
5
6
VCC[V]
Document Number: 002-04692 Rev. *E
Page 120 of 129
MB95690K Series
22. Ordering Information
Part number
Package
Packing
MB95F694KPMC2-G-SNE2
MB95F696KPMC2-G-SNE2
MB95F698KPMC2-G-UNE2
44-pin plastic LQFP
(LQF044)
Tray
MB95F694KPMC-G-UNE2
MB95F696KPMC-G-SNE2
MB95F698KPMC-G-UNE2
48-pin plastic LQFP
(LQA048)
Tray
MB95F694KPMC1-G-SNE2
MB95F696KPMC1-G-SNE2
MB95F698KPMC1-G-UNE2
52-pin plastic LQFP
(LQC052)
Tray
MB95F694KWQN-G-SNE1
MB95F696KWQN-G-SNE1
MB95F698KWQN-G-SNE1
MB95F694KWQN-G-SNERE1
MB95F696KWQN-G-SNERE1
MB95F698KWQN-G-SNERE1
Document Number: 002-04692 Rev. *E
Tray
48-pin plastic QFN
(WNR048)
Reel
Page 121 of 129
MB95690K Series
23. Package Dimension
Package Type
Package Code
LQFP 44
LQF044
㻰
㻰㻝
㻟㻟
㻠
㻡 㻣
㻞㻟
㻟㻠
㻞㻟
㻞㻞
㻟㻟
㻞㻞
㻟㻠
㻝㻞
㻠㻠
㻱㻝 㻱
㻠
㻡
㻣
㻟
㻢
㻝㻞
㻠㻠
㻝
㻝㻝
㼑
㻝㻝
㻞 㻡 㻣
㻝
㻜㻚㻝㻜 㻯 㻭㻙㻮 㻰
㻟
㼎
㻜㻚㻞㻜 㻯 㻭㻙㻮 㻰
㻮㻻㼀㼀㻻㻹 㼂㻵㻱㼃
㻜㻚㻝㻟
㻯 㻭㻙㻮
㻰
㻤
㼀㻻㻼 㼂㻵㻱㼃
㻞
㻭
㻭㻓
㻥
䃗
㻭
㻿㻱㻭㼀㻵㻺㻳
㻼㻸㻭㻺㻱
㻜㻚㻝㻜 㻯
㻸
㻭㻝
㻝㻜
㻜㻚㻞㻡
㼏
㼎
㻿㻱㻯㼀㻵㻻㻺 㻭㻙㻭㻓
㻿㻵㻰 㻱 㼂㻵㻱㼃
㻿㼅㻹 㻮㻻㻸
㻰㻵㻹 㻱㻺㻿㻵㻻㻺㻿
㻹 㻵㻺㻚
㻺㻻㻹 㻚 㻹 㻭㼄㻚
㻜㻚㻜㻡
㻜㻚㻞㻜
㻝㻚㻣㻜
㻭
㻭㻝
㼎
㻜㻚㻞㻡
㼏
㻜㻚㻝㻜㻣
㻜㻚㻟㻡
㻰
㻝㻟㻚㻢㻜 㻮㻿㻯
㻰㻝
㻝㻜㻚㻜㻜 㻮㻿㻯
㼑
㻜㻚㻤㻜 㻮㻿㻯
㻱
㻝㻟㻚㻢㻜 㻮㻿㻯
㻝㻜㻚㻜㻜 㻮㻿㻯
㻱㻝
㻸
䃗
㻜㻚㻠㻡
㻜㻚㻝㻣㻣
㻜㻚㻤㻜
㻜㼻
㻝㻚㻜㻜
㻝㻚㻞㻜
㻤㼻
002-16347 **
㻼㻭㻯㻷㻭㻳㻱㻌㻻㼁㼀㻸㻵㻺㻱㻘 㻠㻠㻌㻸㻱㻭㻰㻌㻸㻽㻲㻼
㻝㻟㻚㻢㼄㻝㻟㻚㻢㼄㻝㻚㻣 㻹 㻹 㻌㻸㻽㻲㻜㻠㻠 㻾㻱㼂㻖㻖
Document Number: 002-04692 Rev. *E
Page 122 of 129
MB95690K Series
Package Type
Package Code
LQFP 48
LQA048
㻠
㻰
㻡 㻣
㻰㻝
㻟㻢
㻞㻡
㻟㻣
㻞㻠
㻱㻝
㻞㻠
㻟㻣
㻝㻟
㻠㻤
㻱
㻡
㻣
㻟
㻟㻢
㻞㻡
㻠
㻢
㻝㻟
㻠㻤
㻝
㻝㻞
㼑
㻝
㻝㻞
㻞 㻡 㻣
㻜㻚㻝㻜 㻯 㻭㻙㻮 㻰
㻟
㻜㻚㻞㻜 㻯 㻭㻙㻮 㻰
㼎
㻜㻚㻤㻜
㻯 㻭㻙㻮
㻰
㻤
㻞
㻭
䃗
㻭
㻭㻓
㻜㻚㻤㻜 㻯
㻿㼅㻹 㻮㻻㻸
㻸㻝
㻜㻚㻞㻡
㻸
㻭㻝
㼏
㼎
㻝㻜
㻿㻱㻯㼀㻵㻻㻺 㻭㻙㻭㻓
㻰 㻵㻹 㻱㻺 㻿㻵㻻㻺㻿
㻹 㻵㻺 㻚
㻺 㻻㻹 㻚 㻹 㻭㼄㻚
㻜㻚㻜㻜
㻜㻚㻞㻜
㻝㻚㻣㻜
㻭
㻭㻝
㻥
㻿㻱㻭㼀㻵㻺㻳
㻼㻸㻭㻺㻱
㼎
㻜㻚㻝㻡
㻜㻚㻞㻣
㼏
㻜㻚㻜㻥
㻜㻚㻞㻜
㻰
㻥㻚㻜㻜 㻮㻿㻯
㻰㻝
㻣㻚㻜㻜 㻮㻿㻯
㼑
㻜㻚㻡㻜 㻮㻿㻯
㻱
㻥㻚㻜㻜 㻮㻿㻯
㻱㻝
㻣㻚㻜㻜 㻮㻿㻯
㻸
㻜㻚㻠㻡
㻜㻚㻢㻜
㻜㻚㻣㻡
㻸㻝
㻜㻚㻟㻜
㻜㻚㻡㻜
㻜㻚㻣㻜
䃗
㻜㼻
㻤㼻
002-13731 **
㻼㻭㻯㻷㻭㻳㻱㻌㻻㼁㼀㻸㻵㻺㻱㻘 㻠㻤 㻸㻱㻭㻰㻌㻸㻽㻲㻼
㻣㻚㻜㼄㻣㻚㻜㼄㻝㻚㻣㻌㻹 㻹 㻌㻸㻽㻭㻜㻠㻤 㻾㻱㼂㻖㻖
Document Number: 002-04692 Rev. *E
Page 123 of 129
MB95690K Series
Package Type
Package Code
LQFP 52
LQC052
㻠
㻰
㻡 㻣
㻰㻝
㻟㻥
㻞㻣
㻞㻢
㻠㻜
㻟㻥
㻞㻣
㻞㻢
㻠㻜
㻝㻠
㻡㻞
㻱㻝 㻱
㻠
㻡
㻣
㻟
㻢
㻝㻠
㻡㻞
㻝
㻞 㻡 㻣
㻝㻟
㼑
㼎
㻜㻚㻞㻜 㻯 㻭㻙㻮 㻰
㻜㻚㻝㻟
㻯 㻭㻙㻮
㻝
㻝㻟
㻜㻚㻝㻜 㻯 㻭㻙㻮 㻰
㻟
㻮㻻㼀㼀㻻㻹 㼂㻵㻱㼃
㻰
㻤
㼀㻻㻼 㼂㻵㻱㼃
㻞
㻭
䃗
㻭
㻭㻓
㻜㻚㻝㻜 㻯
㻿㻱㻭㼀㻵㻺 㻳
㻼㻸㻭 㻺㻱
㻜㻚㻞㻡
㻸㻝
㻸
㻭㻝
㻝㻜
㻥
㼏
㼎
㻿㻱㻯㼀㻵㻻 㻺 㻭㻙㻭㻓
㻿㻵㻰㻱 㼂㻵㻱㼃
㻿㼅㻹 㻮㻻㻸
㻰㻵㻹 㻱㻺㻿㻵㻻㻺
㻹 㻵㻺㻚
㻺㻻㻹 㻚 㻹 㻭㼄㻚
㻭㻝
㻜㻚㻜㻜
㻜㻚㻞㻜
㼎
㻜㻚㻞㻢㻡
㼏
㻜㻚㻜㻥
㻝㻚㻣㻜
㻭
㻜㻚㻟㻜
㻜㻚㻟㻢㻡
㻜㻚㻞㻜
㻰
㻝㻞㻚㻜㻜 㻮㻿㻯
㻰㻝
㻝㻜㻚㻜㻜 㻮㻿㻯
㼑
㻜㻚㻢㻡 㻮㻿㻯
㻱
㻝㻞㻚㻜㻜 㻮㻿㻯
㻝㻜㻚㻜㻜 㻮㻿㻯
㻱㻝
㻸
㻜㻚㻠㻡
㻜㻚㻢㻜
㻜㻚㻣㻡
㻸㻝
㻜㻚㻟㻜
㻜㻚㻡㻜
㻜㻚㻣㻜
䃗
㻜㼻
㻤㼻
002-13880 **
㻼㻭㻯㻷㻭㻳㻱㻌㻻㼁㼀㻸㻵㻺㻱㻘 㻡㻞 㻸㻱㻭㻰㻌㻸㻽㻲㻼
㻝㻜㻚㻜㼄㻝㻜㻚㻜㼄㻝㻚㻣㻌㻹 㻹 㻸㻽㻯㻜㻡㻞 㻾㻱㼂㻖㻖
Document Number: 002-04692 Rev. *E
Page 124 of 129
MB95690K Series
Package Type
Package Code
QFN 48
WNR048
㻜㻚㻝㻡
㻰
㻯 㻭 㻮
㻰㻞
㻭
㻞㻡
㻟㻢
㻜㻚㻝㻜 㻯
㻟㻣
㻞㻠
㻞㼄
㻜㻚㻝㻡
㻔㻺㻰㻙㻝㻕㽢 㼑
㻱
㻯 㻭 㻮
㻱㻞
㻡
㻠㻤
㻝㻟
㻵㻺㻰㻱㼄 㻹㻭㻾㻷
㻤
㻥
㻝㻞
㼎
㻠
㻜㻚㻝㻜 㻯
㼏
㻸
㼑
㻮
㼀㻻㻼 㼂㻵㻱㼃
㻝
㻜㻚㻝㻜
㻜㻚㻜㻡
㻯 㻭 㻮
㻯
㻮㻻㼀㼀㻻㻹 㼂㻵㻱㼃
㻞㼄
㻜㻚㻝㻜 㻯
㻭
㻜㻚㻜㻡 㻯 㻿㻱㻭㼀㻵㻺㻳 㻼㻸㻭㻺㻱
㻭㻝
㻥
㻯
㻿㻵㻰㻱 㼂㻵㻱㼃
㻺㻻㼀㻱
㻰㻵㻹 㻱㻺㻿㻵㻻 㻺㻿
㻝㻚 㻭㻸㻸 㻰㻵㻹 㻱㻺㻿㻵㻻㻺㻿 㻭㻾㻱 㻵㻺 㻹 㻵㻸㻸㻵㻹 㻱㼀㻱㻾㻿㻚
㻿㼅㻹 㻮㻻㻸
㻹 㻵㻺㻚
㻺㻻㻹 㻚
㻹 㻭㼄㻚
㻞㻚 㻰㻵㻹 㻱㻺㻿㻵㻻㻺㻵㻺㻳 㻭㻺㻰 㼀㻻㻸㻱㻾㻭㻺㻯㻵㻺
㻟㻚 㻺 㻵㻿 㼀㻴㻱 㼀㻻㼀㻭㻸 㻺㼁
㻭
㻭㻝
㻜㻚㻤㻜
㻜㻚㻜㻜
㻣㻚㻜㻜 㻮㻿㻯
㻰
㻱
㼎
㻜㻚㻜㻡
㻜㻚㻞㻡
㻠㻚 㻰㻵㻹 㻱㻺㻿㻵㻻㻺 㻎㼎 㻎 㻭㻼㻼㻸㻵㻱㻿 㼀㻻 㻹 㻱㼀㻭㻸㻸㻵㼆㻱㻰 㼀㻱㻾㻹 㻵㻺㻭㻸 㻭㻺㻰 㻵㻿 㻹 㻱㻭㻿㼁㻾㻱㻰
㻮㻱㼀㼃 㻱㻱㻺 㻜㻚㻝㻡 㻭㻺㻰 㻜㻚㻟㻜㼙 㼙 㻲㻾㻻㻹 㼀㻱㻾㻹 㻵㻺㻭㻸 㼀㻵㻼㻚㻵㻲 㼀㻴㻱 㼀㻱㻾㻹 㻵㻺㻭㻸 㻴㻭㻿
㼀㻴㻱 㻻㻼㼀㻵㻻㻺㻭㻸 㻾㻭㻰㻵㼁㻿 㻻㻺 㼀㻴㻱 㻻㼀㻴㻱㻾 㻱㻺㻰 㻻㻲 㼀㻴㻱 㼀㻱㻾㻹 㻵㻺㻭㻸㻚 㼀㻴㻱
㻰㻵㻹 㻱㻺㻿㻵㻻㻺 㻎㼎 㻎㻿㻴㻻 㼁㻸㻰 㻺㻻㼀 㻮㻱 㻹 㻱㻭㻿㼁㻾㻱㻰 㻵㻺 㼀㻴㻭㼀 㻾㻭㻰㻵㼁㻿 㻭㻾㻱㻭㻚
㻡㻚 㻺㻰 㻾㻱㻲㻱㻾 㼀㻻 㼀㻴㻱 㻺㼁㻹 㻮㻱㻾 㻻㻲
㻣㻚㻜㻜 㻮㻿㻯
㻜㻚㻝㻤
㻜㻚㻟㻜
㻯 㻯㻻㻺㻲㻻㻾㻹 㻿 㼀㻻 㻭㻿㻹 㻱 㼅㻝㻠㻚㻡㻙㻝㻥㻥㻠㻚
㻹 㻮㻱㻾 㻻㻲 㼀㻱㻾㻹 㻵㻺㻭㻸㻿㻚
㼀㻱㻾㻹 㻵㻺㻭㻸㻿 㻻㻺 㻰 㻻㻾 㻱 㻿㻵㻰㻱㻚
㻢㻚 㻹 㻭㼄㻚 㻼㻭㻯㻷㻭㻳㻱 㼃 㻭㻾㻼㻭㻳㻱 㻵㻿 㻜㻚㻜㻡㼙 㼙 㻚
㻣㻚 㻹 㻭㼄㻵㻹 㼁㻹 㻭㻸㻸㻻㼃 㻭㻮㻸㻱 㻮㼁㻾㻾㻿 㻵㻿 㻜㻚㻜㻣㻢㼙 㼙 㻵㻺 㻭㻸㻸 㻰㻵㻾㻱㻯㼀㻵㻻㻺㻿㻚
㻰㻞
㻠㻚㻠㻜 㻮㻿㻯
㻱㻞
㻠㻚㻠㻜 㻮㻿㻯
㻤㻚 㻼㻵㻺 㻏㻝 㻵㻰 㻻㻺 㼀㻻㻼 㼃 㻵㻸㻸 㻮㻱 㻸㻻㻯㻭㼀㻱㻰 㼃 㻵㼀㻴㻵㻺 㻵㻺㻰㻵㻯㻭㼀㻱㻰 㼆㻻㻺㻱㻚
㼑
㻜㻚㻡㻜 㻮㻿㻯
㻥㻚 㻮㻵㻸㻭㼀㻱㻾㻭㻸 㻯㻻㻼㻸㻭㻺㻭㻾㻵㼀㼅 㼆㻻㻺㻱 㻭㻼㻼㻸㻵㻱㻿 㼀㻻 㼀㻴㻱 㻱㼄㻼㻻㻿㻱㻰 㻴㻱㻭㼀
㻿㻵㻺㻷 㻿㻸㼁㻳 㻭㻿 㼃 㻱㻸㻸 㻭㻿 㼀㻴㻱 㼀㻱㻾㻹 㻵㻺㻭㻸㻿㻚
㼏
㻜㻚㻟㻜 㻾㻱㻲
㻸
㻜㻚㻠㻡
㻜㻚㻡㻜
㻝㻜㻚 㻶㻱㻰㻱㻯 㻿㻼㻱㻯㻵㻲㻵㻯㻭㼀㻵㻻㻺 㻺㻻㻚 㻾㻱㻲㻌㻦 㻺㻛㻭
㻜㻚㻡㻡
002-15162 **
㻼㻭㻯㻷㻭㻳㻱 㻻㼁㼀㻸㻵㻺㻱㻘 㻠㻤 㻸㻱㻭㻰 㻽㻲㻺
㻣㻚㻜㼄㻣㻚㻜㼄㻜㻚㻤 㻹 㻹㻌㼃㻺㻾㻜㻠㻤㻌㻠㻚㻠㼄㻠㻚㻠 㻹 㻹 㻱㻼㻭㻰㻌㻔㻿㻭㼃㻺㻕 㻾㻱㼂㻖㻖
Document Number: 002-04692 Rev. *E
Page 125 of 129
MB95690K Series
24. Major Changes In This Edition
Spansion Publication Number: DS702-00014-2v0-E
Page
Section
Details
2
■ FEATURES
Added information on FPT-44P-M25.
4
■ PRODUCT LINE-UP
Added information on FPT-44P-M25 to the
parameters “General-purpose I/O” and “8/10-bit A/D
converter”.
5
Added information on FPT-44P-M25 to the parameter
“External interrupt”.
6
Added FPT-44P-M25 to the parameter “Package”.
7
■ PACKAGES AND
CORRESPONDING PRODUCTS
Added information on FPT-44P-M25.
9
■ PIN ASSIGNMENT
Added the pin assignment diagram of FPT-44P-M25.
13 to 16
■ PIN FUNCTIONS (FPT-44P-M25)
New section
17
■ PIN FUNCTIONS (FPT-48P-M49,
FPT-52P-M02, LCC-48P-M11)
Renamed the section “■ PIN FUNCTIONS” to “■ PIN
FUNCTIONS (FPT-48P-M49, FPT-52P-M02, LCC48P-M11).
29
■ PIN CONNECTION
• DBG pin
Revised details of “• DBG pin”.
• RST pin
Revised details of “• RST pin”.
30
• C pin
Corrected the following statement.
The bypass capacitor for the VCC pin must have a
capacitance larger than CS.
→
The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of
CS.
31
■ BLOCK DIAGRAM (FPT-44P-M25)
New section
32
■ BLOCK DIAGRAM (FPT-48P-M49,
FPT-52P-M02, LCC-48P-M11)
Renamed the section “■ BLOCK DIAGRAM” to
“■ BLOCK DIAGRAM (FPT-48P-M49, FPT-52P-M02,
LCC-48P-M11).
75
■ I/O PORTS
6. Port F
(4) Port F operations
• Operation as an input port
Added the following statement.
For a pin shared with other peripheral functions,
disable the output of such peripheral functions.
78
7. Port G
(4) Port G operations
• Operation as an input port
Added the following statement.
For a pin shared with other peripheral functions,
disable the output of such peripheral functions.
Document Number: 002-04692 Rev. *E
Page 126 of 129
MB95690K Series
Page
85
Section
Details
■ ELECTRICAL CHARACTERISTICS Corrected the following statement in the remark of the
2. Recommended Operating Conditions parameter “Decoupling capacitor”.
The bypass capacitor for the VCC pin must have a
capacitance larger than CS.
→
The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of
CS.
Revised the remark in “• DBG/RST/C pins connection
diagram”.
86
3. DC Characteristics
Revised the remark of the parameter “Input leak
current (Hi-Z output leak current)”.
When pull-up resistance is disabled
→
When the internal pull-up resistor is disabled
Renamed the parameter “Pull-up resistance” to
“Internal pull-up resistor”.
Revised the remark of the parameter “Internal pull-up
resistor”.
When pull-up resistance is enabled
→
When the internal pull-up resistor is enabled
90
4. AC Characteristics
(1) Clock Timing
Corrected the pin names of the parameter “Input clock
rising time and falling time”.
X0 → X0, X0A
X0, X1 → X0, X1, X0A, X1A
125
■ ORDERING INFORMATION
Added the part numbers of FPT-44P-M25.
126
■ PACKAGE DIMENSION
Added the package diagram of FPT-44P-M25.
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04692 Rev. *E
Page 127 of 129
MB95690K Series
Document History Page
Document Title: MB95690K Series, New 8FX 8-bit Microcontrollers
Document Number: 002-04692
Revision
ECN
Orig. of
Change
Submission
Date
**
-
AKIH
06/17/2013
Migrated to Cypress and assigned document number 002-08453.
No change to document contents or format.
*A
5193921
AKIH
03/29/2016
Updated to Cypress template
Added MB95F698KPMC2-G-UNE2, MB95F698KPMC1-G-UNE2 in "Ordering Information".
*B
5421818
YUTT
09/01/2016
Changed package code as the following in 1.Product Line-up (Page4 to 6), 2.Packages And
Corresponding Products (Page 7), 4.Pin Assignment (Page 9 to 10), 6.Pin Functions (Page16,
20), 12.Block Diagram(Page30), 27.Ordering Information (Page 121) and 28.Package Dimensions (Page 77 to 83).
“FPT-48P-M49” to “LQA048-02” and “FPT-52P-M02” to “LQC052”
Added Part number “MB95F698KPMC-G-UNE2” in 22.Ordering Information (Page 121).
*C
5633433
HTER
02/17/2017
Changed the package codes as the following
from “FPT-44P-M25” to “LQF044”
from “LQA048-02” to “LQA048”
from “LCC-48P-M11” to “WNR048”
in chapter:
Features (Page 1)
1.Product Line-up (Page 4 to 6)
2.Packages And Corresponding Products (Page 6)
4.Pin Assignment (Page 8 to 11)
5.Pin Functions (Page 12)
6.Pin Functions (Page 16, 20)
11.Block Diagram (Page 29)
12.Block Diagram (Page 30)
22.Ordering Information (Page 121)
23.Package Dimensions (Page 122 to 125).
Description of Change
Deleted the Part numbers
- MB95F698KPMC2-G-SNE2
- MB95F698KPMC-G-SNE2
- MB95F698KPMC1-G-SNE2
in chapter 22.Ordering Information (Page 121).
*D
5725083
AESATMP8
05/16/2017
Updated logo and Copyright
*E
5896506
HUAL
09/27/2017
Added Packing information
Modified from “MB95F694KPMC-G-SNE2” to “MB95F694KPMC-G-UNE2” in 22.Ordering
Information (Page 121)
Document Number: 002-04692 Rev. *E
Page 128 of 129
MB95690K Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
.
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04692 Rev. *E
Revised September 27, 2017
Page 129 of 129