Maxim MAX5557ESA Low-cost stereo audio dac Datasheet

19-0550; Rev 0; 5/06
Low-Cost Stereo Audio DACs
The MAX5556–MAX5559 stereo audio sigma-delta
digital-to-analog converters (DACs) offer a simple and
complete stereo digital-to-analog solution for media
servers, set-top boxes, video-game hardware, automotive rear-seat entertainment and other general consumer
audio applications. These DACs feature built-in digital
interpolation/filtering, sigma-delta digital-to-analog conversion and analog output filtering. Control logic and
mute circuitry minimize audible pops and clicks during
power-up, power-down, clock changes, or when invalid
clock conditions occur.
The MAX5556–MAX5559 receive input data over a flexible 3-wire interface, supporting I2S-compatible, left-justified, right-justified 16-bit, and right-justified 18-bit
audio data. Data can be clocked by either an external
or internal serial clock. The internal serial clock frequency is programmable by selection of a master clock
(MCLK) and sample clock (LRCLK) ratio. Sampling
rates from 2kHz to 50kHz are supported.
The MAX5556–MAX5559 operate from a single +4.75V
to +5.5V analog supply with total harmonic distortion
plus noise below -87dB. These devices are available in
8-pin SO packages and are specified over the -40°C to
+85°C industrial temperature range.
Features
♦ Simple and Complete Stereo Audio DAC
Solutions, No Controls to Set
♦ Sigma-Delta Stereo DACs with Built-In
Interpolation and Analog Output Filters
♦ I2S-Compatible Digital Audio Interface (MAX5556)
♦ Clickless/Popless Operation
♦ Output Voltage Swing: 3.5VP-P
♦ -87dB THD+N
♦ +87dB Dynamic Range
♦ Sample Frequencies (fS) from 2kHz to 50kHz
♦ Master Clock (MCLK) up to 25MHz
♦ Automatic Detection of Clock Ratio (MCLK/
LRCLK)
Ordering Information
Applications
Digital Video Recorders and Media Servers
Set-Top Boxes
PINPKG
DATA FORMAT
PACKAGE CODE
MAX5556ESA 8 SO
S8-5 Left-justified I2S data
MAX5557ESA* 8 SO
S8-5 Left-justified data
MAX5558ESA* 8 SO
S8-5 Right-justified 16-Bit data
MAX5559ESA* 8 SO
S8-5 Right-justified 18-Bit data
PART
Video-Game Hardware
Automotive Rear-Seat Entertainment
Typical Operating Circuit
+5V
Note: All devices are specified over the -40°C to +85°C operating temperature range. Contact factory for +105°C operation.
*Future product—contact factory for availability.
Pin Configuration
TOP VIEW
VDD
LEFT
OUTPUT
SDATA
AUDIO
DECOMPRESSION
DAC
OUTL
SCLK
LRCLK
LINE-LEVEL
BUFFER
SERIAL
INTERFACE
SCLK 2
MAX5556–MAX5559
RIGHT
OUTPUT
CLOCK
DAC
MCLK
GND
SDATA 1
LRCLK
3
MAX5556–
MAX5559
8
OUTL
7
VDD
6
GND
5
OUTR
OUTR
LINE-LEVEL
BUFFER
MCLK 4
SO
________________________________________________________________ Maxim Integrated Products
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5556–MAX5559
General Description
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V
OUTL, OUTR, SDATA to GND................... -0.3V to (VDD + 0.3V)
Current Into Any Pin (excluding VDD and GND)...............±10mA
OUTL, OUTR Shorted to GND....................................Continuous
SCLK, LRCLK, MCLK to GND ...............................-0.3V to +6.0V
Continuous Power Dissipation (TA = +70°C)
8-Pin SO (derate 5.88mW above +70°C)....................471mW
Package Thermal Resistance (θJA) ...............................170°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK =
12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted.
Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.75
V
POWER SUPPLY
Supply Voltage
Supply Current
VDD
IDD
Power Dissipation
5.0
5.50
Up to 48ksps
13
15
Static digital
6
8.5
Up to 48ksps
65
82.5
Static digital
30
44
mA
mW
DYNAMIC PERFORMANCE (Note 2)
Dynamic Range, 16-Bit
Dynamic Range, 18-Bit to 24-Bit
Total Harmonic Distortion Plus
Noise, 16-Bit
Total Harmonic Distortion Plus
Noise, 18-Bit to 24-Bit
THD+N
THD+N
Interchannel Isolation
Unweighted
84
86
A-weighted
86
90
Unweighted
87
A-weighted
91
0dBFS
-86
-20dBFS
-67
-60dBFS
-26
0dBFS
-87
-20dBFS
-68
-60dBFS
-27
1kHz full-scale output (crosstalk)
94
dB
dB
-81
dB
-24
dB
dB
COMBINED DIGITAL AND INTEGRATED ANALOG FILTER FREQUENCY RESPONSE (Note 3)
-0.5dB corner
Passband
0.46
-3dB corner
0.49
-6dB corner
Frequency Response/Passband
Ripple
0.50
10Hz to 20kHz (fS = 48kHz)
-0.025
+0.08
10Hz to 20kHz (fS = 44.1kHz)
-0.025
+0.08
10Hz to 16kHz (fS = 32kHz)
-6.000
+0.073
Stopband
0.5465
Stopband Attenuation
Group Delay
Passband Group-Delay Variation
2
52
tgd
∆tgd
20Hz to 20kHz
fS
dB
fS
dB
20 / fS
s
±0.4 / fS
s
________________________________________________________________________________________
Low-Cost Stereo Audio DACs
(VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK =
12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted.
Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.1
0.4
dB
DC CHARACTERISTICS
Interchannel Gain Mismatch
Gain Error
-5
Gain Drift
+5
100
%
ppm/°C
ANALOG OUTPUTS
Full-Scale Output Voltage
VOUTR, VOUTL
DC Quiescent Output Voltage
VQ
Minimum Load Resistance
RL
Maximum Load Capacitance
CL
Power-Supply Rejection Ratio
PSRR
3.25
Input code = 0
3.5
3.75
VP-P
2.4
V
3
kΩ
100
pF
VRIPPLE = 100mVP-P, frequency = 1kHz
66
dB
100
dB
Power-Up Until Bias Established
Figure 14
360
ms
Valid Clock to Normal Operation
Soft-start ramp time, Figure 15 (Note 5)
20
ms
POP AND CLICK SUPPRESSION
Mute Attenuation
DIGITAL AUDIO INTERFACE (SCLK, SDATA, MCLK, LRCLK)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input Leakage Current
IIN
2.0
V
-10
Input Capacitance
0.8
V
+10
µA
8
pF
TIMING CHARACTERISTICS
Input Sample Rate
fS
MCLK Pulse-Width Low
MCLK Pulse-Width High
tMCLKL
tMCLKH
2
MCLK/LRCLK = 512
10
MCLK/LRCLK = 384
20
MCLK/LRCLK = 256
20
MCLK/LRCLK = 512
10
MCLK/LRCLK = 384
20
MCLK/LRCLK = 256
20
50
kHz
ns
ns
EXTERNAL SCLK MODE
LRCLK Duty Cycle
(Note 6)
25
75
%
SCLK Pulse-Width Low
tSCLKL
20
ns
SCLK Pulse-Width High
tSCLKH
20
ns
SCLK Period
tSCLK
1 / (128
x fS)
ns
LRCLK Edge to SCLK Rising
tSLRS
20
ns
LRCLK Edge to SCLK Rising
tSLRH
20
ns
SDATA Valid to SCLK Rising
tSDS
20
ns
SCLK Rising to SDATA Hold Time
tSDH
20
ns
_______________________________________________________________________________________
3
MAX5556–MAX5559
ELECTRICAL CHARACTERISTICS (continued)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK =
12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted.
Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL SCLK MODE
LRCLK Duty Cycle
(Note 7)
Internal SCLK Period
tISCLK
50
(Note 8)
%
1 / fSCLK
ns
LRCLK Edge to Internal SCLK
tISCLKR
SDATA Valid to Internal SCLK
tISDS
MCLK period = tMCLK
tMCLK + 10
ns
SDATA Valid to Internal SCLK
tISDH
MCLK period = tMCLK
tMCLK
ns
tISCLK / 2
ns
Note 1: 100% production tested at TA = +85°C. Limits to -40°C are guaranteed by design.
Note 2: 0.5 LSB of triangular PDF dither added to data.
Note 3: Guaranteed by design, not production tested.
Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR.
Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample
rate (fS). 20ms based on 48ksps operation.
Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figures
4–7.
Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode.
Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the device and the MCLK/LRCLK ratio selected. See
Figures 4–7.
VDD
DC POWER SUPPLY
(5VDC)
LOUT, ROUT
ZG
ACTIVE CLOCKS
AUDIO SIGNAL
GENERATOR
(100mVP-P AT 1kHz)
+
SCLK
LRCLK
MCLK
MAX5556–MAX5559
SPECTRUM
ANALYZER
SDATA
-
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
GND
Figure 1. PSRR Test Block Diagram
4
________________________________________________________________________________________
Low-Cost Stereo Audio DACs
(VDD = +5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.)
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-2
-40
-50
-60
-3
-4
-5
-6
-70
-70
-7
-80
-80
-8
-90
-90
-9
-100
-100
-10
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.40
0.44
FREQUENCY (NORMALIZED TO fS)
0.48
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.25
0.4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0
0.5
2
4
6
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
AMPLITUDE (dBr)
AMPLITUDE (dBr)
0
10 12 14 16 18 20
0.48
0.50
0.52
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
THD+N vs. AMPLITUDE
-60
MAX5556 toc08
MAX5556 toc07
4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.46
16,000-SAMPLE FFT USING 1kHz INPUT
TWIN-TONE IMD FFT
16,000-SAMPLE FFT WITH NO INPUT
2
8
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
FREQUENCY (kHz)
IDLE-CHANNEL NOISE FFT
0
0.44
-60dBFS FFT
16,000-SAMPLE FFT USING 1kHz INPUT
FREQUENCY (NORMALIZED TO fS)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.42
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dBr)
AMPLITUDE (dBr)
0.10
0.3
0.40
MAX5556 toc05
MAX5556 toc04
0.15
0.2
0.60
0dBFS FFT
0.20
0.1
0.56
MAX5556 toc06
PASSBAND RIPPLE
0.25
0
0.52
FREQUENCY (NORMALIZED TO fS)
16,000-SAMPLE FFT
WITH 13kHz AND
14kHz INPUT SIGNALS
-70
THD+N (dBr)
0
AMPLITUDE (dB)
-1
MAX5556 toc09
AMPLITUDE (dB)
-30
-10
AMPLITUDE (dB)
-20
0
MAX5556 toc02
MAX5556 toc01
-10
TRANSITION BAND DETAIL
TRANSITION BAND
0
MAX5556 toc03
STOPBAND REJECTION
0
UNWEIGHTED
-80
-90
INPUT = 1kHz 18-BIT SIGNAL
-100
A-WEIGHTED
INTEGRATION BANDWIDTH = 20Hz TO 20kHz
-110
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
-60
-50
-40
-30
-20
-10
0
AMPLITUDE (dBFS)
_______________________________________________________________________________________
5
MAX5556–MAX5559
Typical Operating Characteristics
Typical Operating Characteristics (continued)
(VDD = +5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.)
UNWEIGHTED THD+N
vs. FREQUENCY
-80
-90
50
40
30
20
14
13
-100
0
INPUT = 1kHz, 0dBFS SIGNAL
NORMAL OPERATION
11
10
9
STATIC DIGITAL INPUT
MUTE OPERATION
8
6
2
4
6
8
10 12 14 16 18 20
5
0
10
20
30
40
FREQUENCY (kHz)
SAMPLE FREQUENCY (kHz)
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE (VDIG)
CLOCK-LOSS MUTE RECOVERY
50
4.75
VDIG < VIH
MUTE
ENGAGED
5.05
5.20
5.50
POWER-UP RESPONSE
MAX5556 toc15
CLOCK
RESTORED
12
11
10
9
VIH
VOUT
1V/div
2.4V
VOUT
1V/div
8
7
6
VDD = +5.5V
DC OUTPUT
LOSS
OF CLOCK
0V
5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
5ms/div
100ms/div
DIGITAL INPUT VOLTAGE (VDIG) (V)
6
5.35
SUPPLY VOLTAGE (V)
MAX5556 toc14
VDIG < VIH
NORMAL OPERATION
4.90
MAX5556 toc13
13
VDD = +5V
INPUT = 1kHz, 0dBFS SIGNAL
0
-110
14
12
7
10
15
MAX5556 toc12
15
SUPPLY CURRENT (mA)
60
POWER DISSIPATION (mW)
THD+N (dBr)
-70
70
MAX5556 toc11
INPUT = 1kHz 18-BIT SIGNAL,
INTEGRATION BANDWIDTH = 20Hz TO 20kHz
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
POWER DISSIPATION
vs. SAMPLE FREQUENCY
MAX5556 toc10
-60
SUPPLY CURRENT (mA)
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
________________________________________________________________________________________
Low-Cost Stereo Audio DACs
PIN
NAME
FUNCTION
1
SDATA
2
SCLK
3
LRCLK
Left-/Right-Channel Select Clock. For the MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR. For the MAX5557/MAX5558/MAX5559, drive LRCLK high to
direct data to OUTL or LRCLK low to direct data to OUTR.
4
MCLK
Master Clock Input. The MCLK/LRCLK ratio must equal to 256, 384, or 512.
5
OUTR
Right-Channel Analog Output
6
GND
Ground
7
VDD
Power-Supply Input. Bypass VDD to GND with a 0.1µF capacitor in parallel with a 4.7µF capacitor as
close to VDD as possible. Place the 0.1µF capacitor closest to VDD.
8
OUTL
Serial Audio Data Input. Data is clocked into the MAX5556–MAX5559 on the rising edge of the
internal or external SCLK. Data is input in two’s complement format, MSB first. The state of LRCLK
determines whether data is directed to OUTL or OUTR.
External Serial Clock Input. Data is strobed on the rising edge of SCLK.
Left-Channel Analog Output
Detailed Description
The MAX5556–MAX5559 stereo audio sigma-delta DACs
offer a complete stereo digital-to-analog system for consumer audio applications. The MAX5556–MAX5559 feature built-in digital interpolation/filtering, sigma-delta
digital-to-analog conversion and analog output filters
(Figure 2). Control logic and mute circuitry minimize
audible pops and clicks during power-up, power-down,
and whenever invalid clock conditions occur.
These stereo audio DACs receive input data over a 3wire interface that supports up to 24 bits of left-justified,
right-justified, or I 2 S-compatible audio data. The
MAX5556 accepts left-justified I2S data, up to 24 bits.
The MAX5557 accepts left-justified data, up to 24 bits.
The MAX5558 accepts right-justified 16-bit data. The
MAX5559 accepts right-justified 18-bit data. These
DACs also support a wide range of sample rates from
2kHz to 48kHz. Direct analog output data is routed to
the right or left output by driving LRCLK high or low.
See the Clock and Data Interface section.
The MAX5556–MAX5559 support MCLK/LRCLK ratios
of 256, 384, or 512. These devices allow a change to
the clock speed ratio without causing glitches on the
analog outputs by internally muting the audio during
invalid clock conditions. The internal mute function
ramps down the audio amplitude and forces the analog
outputs to a 2.4V quiescent voltage immediately upon
clock loss or change of ratio. A soft-start routine is then
engaged when a valid clock ratio is re-established, producing clickless and popless continuous operation.
The MAX5556–MAX5559 operate from a +4.75V to
+5.5V analog supply and feature +87dB dynamic
range with total harmonic distortion typically below
-87dB.
Interpolator
The digital interpolation filter eliminates images of the
baseband audio signal that exist at multiples of the input
sample rate (fS). The resulting upsampled frequency
spectrum has images of the input signal at multiples of 8
x fS. An additional upsampling sinc filter further reduces
upsampling images up to 64 x fS. These images are ultimately removed through the internal analog lowpass filter
and the external analog output filter.
Sigma-Delta Modulator/DAC
The MAX5556–MAX5559 use a multibit sigma-delta DAC
with an oversampling ratio (OSR) of 64 to achieve a wide
dynamic range. The sigma-delta modulator accepts a 3bit data stream from the interpolation filter at a rate of 64
x fS (fS = LRCLK frequency) and provides an analog voltage representation of that data stream.
_______________________________________________________________________________________
7
MAX5556–MAX5559
Pin Description
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
VDD
SIGMA-DELTA
MODULATOR
INTERPOLATOR
ANALOG
LOWPASS
FILTER
DAC
SDATA
OUTL
BUFFER
SCLK
INTERNAL
REFERENCE
SERIAL
INTERFACE
LRCLK
MCLK
SIGMA-DELTA
MODULATOR
INTERPOLATOR
ANALOG
LOWPASS
FILTER
DAC
OUTR
BUFFER
MAX5556–MAX5559
GND
Figure 2. Functional Diagram
125
LOAD CAPACITANCE CL (pF)
100
75
50
SAFE OPERATING REGION
25
3
5
10
15
20
25
LOAD RESISTANCE RL (kΩ)
Figure 3. Load-Impedance Operating Region
Integrated Analog Lowpass Filter
Integrated Analog Output Buffer
The DAC output of the sigma-delta modulator is followed by an analog smoothing filter that attenuates
high-frequency quantization noise. The corner frequency of the filter is approximately 2 x fS.
Following the analog lowpass filter, the analog signal is
routed through internal buffers to OUTR and OUTL. The
buffer can directly drive load resistances larger than
3kΩ and load capacitances up to 100pF (Figure 3).
8
________________________________________________________________________________________
Low-Cost Stereo Audio DACs
SDATA Input
The serial interface strobes data (SDATA) in on the rising edge of SCLK, MSB first. The MAX5556–MAX5559
support four different data formats, as detailed in
Figures 4–7.
DATA DIRECTED TO OUTL
LRCLK
DATA DIRECTED TO OUTR
SCLK
SDATA
MSB -1
-2
-3
-4 -5
+5
+4
+3
+2
+1 LSB
INTERNAL SERIAL CLOCK MODE
• I2S, 16-BIT DATA AND INTERNAL SCLK =
32 x fS IF MCLK/ LRCLK = 256 OR 512
• I2S, UP TO 24 BITS OF DATA AND INTERNAL
SCLK = 48 X fS IF MCLK/ LRCLK = 384
MSB -1
-2
-3 -4
+5
+4
+3
+2
+1 LSB
EXTERNAL SERIAL CLOCK MODE
• I2S, UP TO 24 BITS OF DATA
• DATA VALID ON RISING EDGE OF SCLK
Figure 4. MAX5556 Data Format Timing
DATA DIRECTED TO OUTR
LRCLK
DATA DIRECTED TO OUTL
SCLK
SDATA
MSB -1
-2
-3
-4 -5
+5
+4
+3
+2
+1 LSB
MSB -1
-2
-3 -4
+5
INTERNAL SERIAL CLOCK MODE
EXTERNAL SERIAL CLOCK MODE
• LEFT-JUSTIFIED, UP TO 24 BITS OF DATA
• INTERNAL SCLK = 64 x fS IF MCLK / LRCLK = 256 OR 512
• INTERNAL SCLK = 48 x fS IF MCLK / LRCLK = 384
• LEFT-JUSTIFIED, UP TO 24 BITS OF DATA
• DATA VALID ON RISING EDGE OF SCLK
+4
+3
+2
+1 LSB
Figure 5. MAX5557 Data Format Timing
_______________________________________________________________________________________
9
MAX5556–MAX5559
Clock and Data Interface
The MAX5556–MAX5559 strobe serial data (SDATA) in
on the rising edge of SCLK. LRCLK routes data to the
left or right outputs and, along with SCLK, defines the
number of bits per sample transferred. The digital interpolators filter data at internal clock rates derived from
the MCLK frequency. Each device supports both internal and external serial clock (SCLK) modes.
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
LRCLK
DATA DIRECTED TO OUTR
DATA DIRECTED TO OUTL
SCLK
SDATA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MSB
0
15
LSB
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
INTERNAL SERIAL CLOCK MODE
EXTERNAL SERIAL CLOCK MODE
• RIGHT-JUSTIFIED, 16-BIT DATA
• INTERNAL SCLK = 32 x fS IF MCLK / LRCLK = 256 OR 512
• INTERNAL SCLK = 48 x fS IF MCLK / LRCLK = 384
• RIGHT-JUSTIFIED, 16-BIT DATA
• DATA VALID ON RISING EDGE OF SCLK
• SCLK MUST HAVE AT LEAST 32 CYCLES PER LRCLK PERIOD
Figure 6. MAX5558 Data Format Timing
DATA DIRECTED TO OUTR
DATA DIRECTED TO OUTL
LRCLK
SCLK
SDATA
17
16 15
14
13
12
11 10
9
8
7
6
5
4
3
2
MSB
1
0
17
LSB
MSB
16
15
14
13
12 11
10
INTERNAL SERIAL CLOCK MODE
EXTERNAL SERIAL CLOCK MODE
• RIGHT-JUSTIFIED, 18-BIT DATA
• INTERNAL SCLK = 64 x fS IF MCLK / LRCLK = 256 OR 512
• INTERNAL SCLK = 48 x fS IF MCLK / LRCLK = 384
• RIGHT-JUSTIFIED, 18-BIT DATA
• DATA VALID ON RISING EDGE OF SCLK
• SCLK MUST HAVE AT LEAST 36 CYCLES PER LRCLK PERIOD
9
8
7
6
5
4
3
2
1
0
LSB
Figure 7. MAX5559 Data Format Timing
Serial Clock (SCLK)
SCLK strobes the individual data bits at SDATA into the
DAC. The MAX5556–MAX5559 operate in one of two
modes: internal serial clock mode or external serial
clock mode.
External SCLK Mode
The MAX5556–MAX5559 operate in external serial clock
mode when SCLK activity is detected. All four devices
return to internal serial clock mode if no SCLK signal is
detected for one LRCLK period. Figure 8 details the
external serial clock mode timing parameters.
10
Internal SCLK Mode
The MAX5556–MAX5559 transition from external serial
clock mode to internal serial clock mode if no SCLK
signal is detected for one LRCLK period. In internal
clock mode, SCLK is derived from and is synchronous
with MCLK and LRCLK (operation in internal clock
mode is identical to an external clock mode when
LRCLK is synchronized with MCLK). Figure 9 details
the internal serial clock mode timing parameters. Figure
10 details the generation of the internal clock.
_______________________________________________________________________________________
Low-Cost Stereo Audio DACs
MAX5556–MAX5559
LRCLK
tSCLK
tSLRH
tSLRS
tSCLKL
tSCLKH
SCLK
tSDH
tSDS
SDATA
Figure 8. External SCLK Serial Timing Diagram
LRCLK
tISCLKR
SDATA
tISDS
tISDH
tISCLK
INTERNAL
SCLK
Figure 9. Internal SCLK Serial Timing Diagram
LRCLK
MCLK
1
N / 2*
N*
INTERNAL
SCLK
SDATA
*N = MCLK / SCLK.
Figure 10. Internal Serial Clock Generation
______________________________________________________________________________________
11
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
Left/Right Clock Input (LRCLK)
LRCLK is the left/right clock input signal for the 3-wire
interface and sets the sample frequency (fS). On the
MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR (Figure 4). On the
MAX5557/MAX5558/MAX5559, drive LRCLK high to
direct data to OUTL or LRCLK low to direct data to
OUTR (Figures 5, 6, 7). LRCLK is internally resampled
on each SCLK rising edge. The MAX5556–MAX5559
accept data at LRCLK audio sample rates from 2kHz to
50kHz.
Master Clock (MCLK)
MCLK accepts the master clock signal from an external
clocking device and is used to derive internal clock frequencies. Set the MCLK/LRCLK ratio to 256, 384, or
512 to achieve the internal serial clock frequencies listed in Table 1. Table 2 details the MCLK/LRCLK ratios
for three sample audio rates.
The MAX5556–MAX5559 detect the MCLK/LRCLK ratio
during the initialization sequence by counting the number of MCLK transitions during a single LRCLK period.
MCLK, SCLK, and LRCLK must be synchronous signals.
Table 1. Internal and External Clock
Frequencies
INTERNAL SERIAL
CLOCK FREQUENCY
PART
EXTERNAL
SERIAL
CLOCK
FREQUENCY
MCLK/LRCLK
= 256 OR 512
MCLK/LRCLK
= 384
MAX5556
32 x fS
48 x fS
User defined
(Figure 4)
MAX5557
64 x fS
48 x fS
User defined
(Figure 5)
MAX5558
32 x fS
48 x fS
User defined
(Figure 6)
MAX5559
64 x fS
48 x fS
User defined
(Figure 7)
Table 2. MCLK/LRCLK Ratios
MCLK (MHz)
LRCLK
(kHz)
MCLK/LRCLK
= 256
MCLK/LRCLK
= 384
MCLK/LRCLK
= 512
32
8.1920
12.2880
16.3840
44.1
11.2896
16.9344
22.5792
48
12.2880
18.4320
24.5760
12
Data Formats
MAX5556 I2S Left-Justified Data Format
The MAX5556 accepts data with an I2S left-justified
data format, accepting up to 24 bits of data. SDATA
accepts data in two’s complement format with the MSB
first. The MSB is valid on the second SCLK rising edge
after LRCLK transitions low to high or high to low
(Figure 4). Drive LRCLK low to direct data to OUTL.
Drive LRCLK high to direct data to OUTR. The number
of SCLK pulses with LRCLK high or low determines the
number of bits transferred per sample. If fewer than 24
bits of data are written, the remaining LSBs are set to 0.
If more than 24 bits are written, any bits after the LSB
are ignored.
The MAX5556 accepts up to 24 bits of data in external
serial clock mode or when the MCLK/LRCLK ratio is
384 (internal serial clock = 48 x fS) in internal serial
clock mode. The DAC also accepts 16 bits of data in
internal serial clock mode when the MCLK/LRCLK ratio
is 256 or 512 (internal serial clock = 32 x fS).
MAX5557 Left-Justified Data Format
The MAX5557 accepts data with a left-justified data format, allowing for up to 24 bits of data. SDATA accepts
data in two’s complement format with the MSB first. The
MSB is valid on the first SCLK rising edge after LRCLK
transitions low to high or high to low (Figure 5). Drive
LRCLK high to direct data to OUTL. Drive LRCLK low to
direct data to OUTR. The number of SCLK pulses with
LRCLK high or low determines the number of bits transferred per sample. If fewer than 24 bits of data are written, the remaining LSBs are set to 0. If more than 24
bits are written, the bits after the LSB are ignored.
The MAX5557 accepts up to 24 bits of data in external
serial clock mode and internal serial clock mode.
Program the MCLK/LRCLK ratio to 384 to operate the
internal serial clock at 48 x f S . Program the
MCLK/LRCLK ratio to 256 or 512 to operate the internal
serial clock at 64 x fS.
MAX5558 16-Bit Right-Justified Data Format
The MAX5558 operates from a 16-bit right-justified data
format. The LSB is valid on the final SCLK rising edge
prior to LRCLK transitioning low to high or high to low
(Figure 6). In external serial clock mode, the MAX5558
requires a minimum of 32 SCLK cycles per LRCLK period (16 SCLK cycles with LRCLK low and 16 SCLK
cycles with LRCLK high). Drive LRCLK high to direct
data to OUTL. Drive LRCLK low to direct data to OUTR.
Any additional SDATA bits prior to the MSB are ignored.
_______________________________________________________________________________________
Low-Cost Stereo Audio DACs
MAX5559 18-Bit Right-Justified Data Format
The MAX5559 accepts data with an 18-bit right-justified
data format. The LSB is valid on the final SCLK rising
edge prior to LRCLK transitioning low to high or high to
low (Figure 7). In external serial clock mode, the
MAX5559 requires a minimum of 36 SCLK cycles per
LRCLK period (18 SCLK cycles with LRCLK low and 18
SCLK cycles with LRCLK high). Drive LRCLK high to
direct data to OUTL. Drive LRCLK low to direct data to
OUTR. Any additional SDATA bits prior to the MSB
are ignored.
The MAX5559 accepts 18 bits of data in external serial
clock mode and internal serial clock mode. Program the
MCLK/LRCLK ratio to 384 to operate the internal serial
clock at 48 x fS. Program the MCLK/LRCLK ratio to 256
or 512 to operate the internal serial clock at 64 x fS.
External Analog Filter
Use an external lowpass analog filter to further reduce
harmonic images, noise, and spurs. The external analog filter can be either active or passive depending
upon performance and design requirements. For example filters, see Figures 11 and 12 and the Applications
Information section. Careful attention should be paid
when selecting capacitors for audio signal path applications. NPO and C0G types are recommended as are
aluminum electrolytics and some tantalum varieties.
Use of generic ceramic types is not recommended and
may result in degraded THD performance. Always consult manufacturers’ data sheets and applications information.
R = 560Ω
OUTL
100kΩ
C = 1.5nF
MAX5556–MAX5559
R = 560Ω
OUTR
100kΩ
C = 1.5nF
Figure 11. Passive Component Analog Output Filter
______________________________________________________________________________________
13
MAX5556–MAX5559
The MAX5558 accepts 16 bits of data in external serial
clock mode and internal serial clock mode. Program the
MCLK/LRCLK ratio to 384 to operate the internal serial
clock at 48 x fS. Program the MCLK/LRCLK ratio to 256
or 512 to operate the internal serial clock at 32 x fS.
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
56pF
+5V
5.23kΩ
24.3kΩ
OUTR
33pF
10kΩ
59kΩ
VBIAS
MAX5556–MAX5559
56pF
+5V
5.23kΩ
24.3kΩ
OUTL
33pF
10kΩ
59kΩ
VBIAS
Figure 12. Active Component Analog Output Filter
14
_______________________________________________________________________________________
Low-Cost Stereo Audio DACs
MAX5556–MAX5559
NO POWER APPLIED
POWER-UP
OUTPUTS HELD
AT GROUND
OUTPUTS HELD
AT CURRENT LEVELS
VALID CLOCK
RATIO ESTABLISHED
LofC
OUTPUTS LINEARLY
RAMPED TO DC
QUIESCENT LEVELS (< 1 SECOND)
VALID CLOCK
RATIO RE-ESTABLISHED
VALID CLOCK
RATIO RE-ESTABLISHED
INTERNAL REGISTERS
INITIALIZED (MUTE)
LofC
LOSSOFPOWER
EVENT
OUTPUTS IMMEDIATELY
RETURNED TO DC
QUIESCENT LEVELS
LofC
LofC
LofC = LOSS OF CLOCK EVENT
SOFT-START
VOLUME RAMPING
NORMAL OPERATION
(FULL VOLUME)
INVALID RATIO DETECTED
MCLK TIME OUT
SCLK INT/EXT MODE CHANGED
LRCLK LOSS
OUTPUTS IMMEDIATELY
RETURNED TO GROUND
Figure 13. Internal State Diagram
______________________________________________________________________________________
15
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
Pop and Click Suppression
Power-Down
The MAX5556–MAX5559 feature a pop and click
supression routine to reduce the unwanted audible
effects of system transients. This routine produces
glitch-free operation at the outputs during power-on,
loss of clock, or invalid clock conditions. See Figure 13
for a detailed state diagram during transient conditions.
When the positive supply is removed from the
MAX5556–MAX5559, the outputs discharge to ground.
When power is restored, the power-up ramp routine
engages once a valid clock ratio is established (see the
Power-Up section).
Avoid violating absolute maximum conditions by supplying digital inputs to the part or forcing voltages on
the analog outputs during a loss-of-power event.
Power-Up
Once the MAX5556–MAX5559 recognize a valid
MCLK/LRCLK ratio (256, 384, or 512), the analog outputs
(OUTR and OUTL) are enabled in stages using a glitchless ramping routine. First, the outputs ramp up to the
quiescent output voltage at a rate of 5V/s typ (see Figure
14). After the outputs reach the quiescent voltage, the
converted data stream begins soft-start ramping, achieving the full-scale operation over a 20ms period.
If invalid clock signals are detected while the outputs
are DC ramping to their quiescent state, the outputs
stop ramping and hold their preset values until valid
clock signals are restored (Figure 15).
Loss of Clock and Invalid Clock Conditions
The MAX5556–MAX5559 mute both outputs after
detecting one of four invalid clock conditions. All four
devices mute their outputs to prevent propagation of
pops, clicks, or corrupted data through the signal path.
The MAX5556–MAX5559 force the outputs to the quiescent DC voltage (2.4V) to prevent clicks in capacitivecoupled systems. Invalid clock conditions include:
1. MCLK/LRCLK ratio changes between 256, 384,
and 512
2. Transition between internal and external serialclock mode
3. Invalid MCLK/LRCLK ratio
4. MCLK falls below the minimum operating
frequency 2kHz
When the MCLK/LRCLK ratio returns to 256, 384, or
512 and MCLK is equal or greater than its minimum
operating frequency, the MAX5556–MAX5559 outputs
return to their full-scale setting over a soft-start mute
time of 20ms (Figure 15).
16
Applications Information
Low-Cost Line-Level Solution
Connect the MAX5556–MAX5559 outputs through a
passive output filter as detailed in Figure 11 for a
low-cost solution. This lowpass filter yields single-pole
(20dB/decade) roll-off at a corner frequency (f C )
determined by:
fC =
1
2πRC
In the case of Figure 11, fC is approximately 190kHz.
High-Performance Line-Level Solution
For enhanced performance, connect the MAX5556–
MAX5559 outputs to an active filter by using an operational amplifier as shown in Figure 12. The use of an
active filter allows for steeper roll-off, more efficient filtering, and also adds the capability of a programmable
output gain.
Power-Supply Sequencing
For correct power-up sequencing, apply VDD and then
connect the input digital signals. Do not apply digital signals before VDD is applied.
Do not violate any of the absolute maximum ratings by
removing power with the digital inputs still connected.
To correctly power down the device, first disconnect
the digital input signals, and then remove VDD.
_______________________________________________________________________________________
Low-Cost Stereo Audio DACs
MAX5556–MAX5559
VOUT_ SETTLES AT
QUIESCENT VOLTAGE (2.4V)
VOUT_ RAMPS UP
TO QUIESCENT
VOLTAGE AT 5V/s (TYP)
OUTPUT
VOLTAGE
(OUTR OR OUTL)
VALID MCLK/LRCLK RATIO
DETECTED
VOUT_ BEGINS TO
FOLLOW THE DATA. THE
AMPLITUDE IS RAMPED
TO FULL SCALE (20ms TYP)
TIME
Figure 14. Power-Up Sequence
INVALID CLOCK
CONDITION
MUTE: VOUT_ IMMEDIATELY
FORCED TO DC QUIESCENT
LEVEL (2.4V)
OUTPUT
VOLTAGE
(OUTR OR OUTL)
VALID MCLK/LRCLK
RE-ESTABLISHED AND MCLK
EQUAL OR GREATER THAN
MINIMUM OPERATING FREQUENCY
VOUT_ SOFT START
RAMPING (20ms TYP)
TIME
Figure 15. Invalid Clock Output Response
______________________________________________________________________________________
17
MAX5556–MAX5559
Low-Cost Stereo Audio DACs
Power-Supply Connections and Ground
Management
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and analog outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Route the analog
paths (GND, VDD, OUTL, and OUTR) away from the
digital signals. Connect a 0.1µF capacitor in parallel
with a 4.7µF capacitor as close to VDD as possible. Low
ESR-type capacitors are recommended for supply
decoupling applications. A small value C0G-type
bypass capacitor located as close to the device as
possible is recommended in parallel with larger values.
Chip Information
PROCESS: BiCMOS
18
_______________________________________________________________________________________
Low-Cost Stereo Audio DACs
N
E
H
INCHES
MILLIMETERS
MAX
MIN
0.069
0.053
0.010
0.004
0.014
0.019
0.007
0.010
0.050 BSC
0.150
0.157
0.228
0.244
0.016
0.050
MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
1.27 BSC
3.80
4.00
5.80
6.20
0.40
SOICN .EPS
DIM
A
A1
B
C
e
E
H
L
1.27
VARIATIONS:
1
INCHES
TOP VIEW
DIM
D
D
D
MIN
0.189
0.337
0.386
MAX
0.197
0.344
0.394
MILLIMETERS
MIN
4.80
8.55
9.80
MAX
5.00
8.75
10.00
N MS012
8
AA
14
AB
16
AC
D
C
A
B
e
0∞-8∞
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
21-0041
REV.
B
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2006 Maxim Integrated Products
Heslington
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX5556–MAX5559
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
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