CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 D D D D D D D D D D D Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels Two 8-Bit Parity Generators/Checkers Open-Drain Active-Low Parity-Error Output Expandable for Larger Word Widths ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) CY54FCT480T – 32-mA Output Sink Current – 12-mA Output Source Current CY74FCT480T – 64-mA Output Sink Current – 32-mA Output Source Current CY74FCT480T . . . P, Q, OR SO PACKAGE (TOP VIEW) A1 B1 C1 D1 E1 F1 G1 H1 PAR1 CHK/GEN ODD1 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC A2 B2 C2 D2 E2 F2 G2 H2 PAR2 ERROR ODD2 CY54FCT480T . . . L PACKAGE (TOP VIEW) C1 B1 A1 NC VCC A2 B2 D D1 E1 F1 NC G1 H1 PAR1 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 C2 D2 E2 NC F2 G2 H2 CHK/GEN ODD1 GND NC ODD2 ERROR PAR2 description 5 The ’FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and NC – No internal connection parity-error (ERROR) output. These devices can be used in odd-parity systems. ERROR is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several ’FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual ’FCT480T device. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 ORDERING INFORMATION SPEED (ns) PACKAGE† TA 40°C to 85°C –40°C ORDERABLE PART NUMBER TOP-SIDE MARKING DIP – P Tube 6.1 CY74FCT480BTPC CY74FCT480BTPC QSOP – Q Tape and reel 6.1 CY74FCT480BTQCT FCT480B Tube 6.1 CY74FCT480BTSOC Tape and reel 6.1 CY74FCT480BTSOCT DIP – P Tube 7.5 CY74FCT480ATPC CY74FCT480ATPC QSOP – Q Tape and reel 7.5 CY74FCT480ATQCT FCT480A SOIC – SO FCT480B –55°C to 125°C LCC – L Tube 7 CY54FCT480BTLMB † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS A1–H1 A2–H2 Number of A2–H2 inputs, high is even Number of A1–H inputs, H1 inputs high is even Number of inputs A2–H2, high is odd Number of A2–H2 inputs, high is even Number of A1–H in uts, H1 inputs high is odd Number of A2–H2 inputs, high is odd OUTPUTS CHK/GEN PAR1 PAR2 ODD1 ODD2 ERROR H H H L L H H L H H L L H H L L H L H L L H H L L X X H H L H H H L H L H L H H H L H H L L L H H L L H L L L X X H L L H H H H L L H L H L L H H H L H H L H L L L H L L X X L H L H H H H H L H L H L H L H H L H L L H L L L L H L X X L L H H = High logic level, L = Low logic level, X = Don’t care 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 logic diagram A1 B1 C1 D1 E1 F1 1 2 3 4 7 H1 8 CHK/GEN A2 B2 C2 D2 E2 F2 G2 H2 PAR2 ODD1 6 G1 PAR1 11 5 9 14 10 ERROR 23 22 21 20 19 13 18 ODD2 17 16 15 Pin numbers shown are for the P, Q, and SO packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W (see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 recommended operating conditions (see Note 3) CY54FCT480T CY74FCT480T MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –32 mA IOL TA Low-level output current 32 64 mA 85 °C High-level input voltage 2 Operating free-air temperature 2 –55 125 V V –40 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH CY54FCT480T TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.75 V, IIN = –18 mA IIN = –18 mA VCC = 4.5 V, IOH = –12 mA IOH = –15 mA VCC = 4 4.75 75 V MIN –0.7 –1.2 –0.7 2.4 2.4 IOH = –32 mA IOL = 32 mA Vhys All inputs II VCC = 5.5 V, VCC = 5.25 V, VIN = VCC VIN = VCC 5 IIH VCC = 5.5 V, VCC = 5.25 V, VIN = 2.7 V VIN = 2.7 V ±1 IIL VCC = 5.5 V, VCC = 5.25 V, VIN = 0.5 V VIN = 0.5 V ±1 VCC = 0 V, VCC = 5.5 V, VOUT = 4.5 V VOUT = 0 V VCC = 5.25 V, VCC = 5.5 V, VOUT = 0 V VOUT = 2.7 V VCC = 5.25 V, VCC = 5.5 V, VOUT = 2.7 V VOUT = 0.5 V VCC = 5.25 V, VCC = 5.5 V, VOUT = 0.5 V VIN ≤ 0.2 V, IOZH IOZL ICC ∆ICC V V 3.3 2 VCC = 4.5 V, VCC = 4.75 V, IOS‡ –1.2 UNIT 3.3 VOL Ioff CY74FCT480T TYP† MAX MIN 0.3 0.55 IOL = 64 mA 0.3 0.2 0.55 0.2 V 5 ±1 ±1 ±1 –60 –120 ±1 –225 –60 –120 –225 10 10 –10 –10 VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.5 V µA µA µA µA mA µA µA 0.2 0.1 0.2 0.5 2 2 mA mA † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER ICCD¶ CY54FCT480T TYP† MAX TEST CONDITIONS MIN VCC = 5.5 V, Outputs open, One bit switching at 50% duty cycle, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.25 V, Outputs open, One bit switching at 50% duty cycle, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.5 V, f0 = 0 MHz MHz, Outputs open IC# VCC = 5.25 V, f0 = 0 MHz MHz, Outputs open 0.06 CY74FCT480T TYP† MAX MIN UNIT 0.12 mA/ MHz 0.06 One bit switching at f1 = 2.5 MHz at 50% duty cycle VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 16 bits switching at f1 = 2.5 MHz at 50% duty cycle One bit switching at f1 = 2.5 MHz at 50% duty cycle VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 16 bits switching at f1 = 2.5 MHz at 50% duty cycle 0.7 1.4 1 2.4 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2.5 5|| VIN = 3.4 V or GND 6.5 21|| VIN = 3.4 V or GND 0.12 mA 0.7 1.4 1 2.4 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2.5 5|| VIN = 3.4 V or GND 6.5 21|| VIN = 3.4 V or GND Ci 5 10 5 10 pF Co 9 12 9 12 pF † Typical values are at VCC = 5 V, TA = 25°C. ¶ This parameter is derived for use in total power-supply calculations. # IC= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC= Total supply current ICC= Power-supply current with CMOS input levels ∆ICC= Power-supply current for a TTL high input (VIN = 3.4 V) DH= Duty cycle for TTL inputs high NT= Number of TTL inputs at DH ICCD= Dynamic current caused by an input transition pair (HLH or LHL) f0= Clock frequency for registered devices, otherwise zero f1= Input signal frequency N1= Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 switching characteristics over operating free-air temperature range (see Figure 1) CY74FCT480AT CY74FCT480BT FROM (INPUT) TO (OUTPUT) tPLH tPHL A ODD (see Figure 1) 7.5 7 6.1 7 6.6 6.1 tPLH tPHL CHK/GEN ODD (see Figure 1) 6.5 6.3 5.9 7.5 7.4 5.9 tPLH† tPHL A ERROR (see Figure 2) 7 7 6.1 8.5 8.1 6.5 tPLH tPHL CHK/GEN ERROR (see Figure 2) 7.5 7.1 5.7 7 6.9 5.5 MIN MAX † tPLH is measured up to VOUT = VOL + 0.3 V. 6 CY54FCT480BT PARAMETER POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX MIN MAX UNIT ns ns ns ns CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION FOR OPEN-DRAIN OUTPUTS 7V VCC 500 Ω 1.5 V Input 1.5 V 0V From Output Under Test CL (see Note A) Test Point 500 Ω tPHL tPLH ≈VCC 1.5 V Output LOAD CIRCUIT FOR OPEN-DRAIN OUTPUTS VOL + 0.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty CY54FCT480BTLMB ACTIVE LCCC FK 28 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) TBD POST-PLATE N / A for Pkg Type -55 to 125 (4/5) CY74FCT480BTPC OBSOLETE PDIP NT 24 TBD Call TI Call TI -40 to 85 CY74FCT480BTPCE4 OBSOLETE PDIP NT 24 TBD Call TI Call TI -40 to 85 CY74FCT480BTQCT OBSOLETE SSOP DBQ 24 TBD Call TI Call TI -40 to 85 CY74FCT480BTQCTE4 OBSOLETE SSOP DBQ 24 TBD Call TI Call TI -40 to 85 CY74FCT480BTQCTG4 OBSOLETE SSOP DBQ 24 TBD Call TI Call TI -40 to 85 CY74FCT480BTSOC ACTIVE SOIC DW 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 25 Device Marking CY54FCT 480BTLMB FCT480B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated