CY29430 High-Performance Clock Synthesizer High-Performance Clock Synthesizer Features Functional Description ■ Low-noise PLL for high-performance clock applications ■ Differential Clock Output: Four frequencies selectable, reconfigurable by I2C ■ Output frequency support from 15 MHz to 2.1 GHz ■ Fractional N PLL with fully integrated VCO ■ Works on third overtone (OT3) of a fixed frequency crystal, Low frequency fundamental (LFF), High frequency fundamental (HFF) mode crystal and Low Frequency Input ■ LVPECL, CML, HCSL, LVDS or LVCMOS output standards available ■ Compatible with 3.3 V, 2.5 V, and 1.8 V supply ■ 150 fs typical integrated jitter performance (12 kHz to 20 MHz frequency offsets) for output greater than 150 MHz The CY29430 is a Programmable PLL based crystal oscillator solution with flexible output frequency options. It is field and factory programmable for any output frequency between 15 MHz and 2.1 GHz. Four frequencies are independently programmable on the differential output with the frequency select (FS) pins. Additionally, other frequency options can be configured with the I2C interface. Using advanced design technology, it provides excellent jitter performance across the entire output frequency range working reliably at supply voltages from 1.8 V to 3.3 V for ambient temperatures from –40 °C to +105 °C. This makes it ideally suited for communications applications (for example, OTN, SONET/SDH, xDSL, GbE, Networking, Wireless Infrastructure), test and instrumentation applications, and high speed data converters. Additionally, the VCXO function enables the use of CY29430 in applications requiring a clock source with voltage control and in discrete clocking solutions for synchronous timing applications. ■ VCXO functionality provided with tunable Total Pull Range (TPR) from +/- 50 ppm to +/- 275 ppm The CY29430 device configuration can be created using ClockWizard 2.1. For programming support, contact Cypress technical support or send an email to [email protected]. ■ 16 pin QFN package: 3 × 3 × 0.6 mm For a complete list of related documentation, click here. Logic Block Diagram VDD GND VDDO CLK_P XOUT Crystal Oscillator Fractional - N Output Dividers LC VCO Based PLL Output Drivers CLK_N CLK_SE XIN Digital Configuration and Control I2C Interface NVM SCL FS[1:0] Cypress Semiconductor Corporation Document Number: 002-11000 Rev. *E • ADC + Digital Filtering Pathway (for VCXO Function) SDA 198 Champion Court VC • OE San Jose, CA 95134-1709 • 408-943-2600 Revised February 3, 2017 CY29430 Contents Pin Diagram ....................................................................... 3 Pin Description ................................................................. 3 Functional Overview ........................................................ 4 Programmable Features .............................................. 4 Architecture Overview ................................................. 4 Internal State Diagram ................................................ 5 Small/Large Changes .................................................. 5 Programming Support ................................................. 5 Frequency Configurations ........................................... 5 Programmable OE Polarity .......................................... 5 Programmable VCXO .................................................. 5 Power Supply Sequencing .......................................... 5 I2C Interface ................................................................ 5 Memory Map ............................................................... 6 Absolute Maximum Ratings ............................................ 7 Recommended Operating Conditions ............................ 7 DC Electrical Specifications ............................................ 7 DC Specifications ............................................................. 8 DC Specifications ............................................................. 8 DC Specifications ............................................................. 8 DC Specifications ............................................................. 8 DC Specifications ............................................................. 9 VCXO Specific Parameters .............................................. 9 AC Electrical Specifications .......................................... 10 AC Electrical Specifications .......................................... 11 Document Number: 002-11000 Rev. *E AC Electrical Specifications .......................................... 11 HFF Crystal Specifications ............................................ 12 OT3 Crystal Specifications ............................................ 12 LFF Crystal Specifications ............................................ 12 LF Low Frequency Reference ....................................... 13 Timing Parameters ......................................................... 13 Input Clock Measurement Point .................................... 13 Phase Jitter Characteristics .......................................... 14 I2C Bus Timing Specifications ...................................... 14 Voltage and Timing Definitions ..................................... 15 Phase Noise Plots .......................................................... 17 Ordering Information ...................................................... 20 Ordering Code Definitions ......................................... 20 Package Diagram ............................................................ 21 Acronyms ........................................................................ 22 Document Conventions ................................................. 22 Units of Measure ....................................................... 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC®Solutions ....................................................... 24 Cypress Developer Community ................................. 24 Technical Support ..................................................... 24 Page 2 of 24 CY29430 Pin Diagram OE 3 NC1 4 XIN GND VDD 14 13 E-PAD GND 12 GND 11 CLK_SE 10 CLK_P 9 CLK_N 5 6 7 8 VDDO 2 15 SCL SDA 16 FS1 1 FS0 VC XOUT CY29430 PINOUT Pin Description Name Pin Number Description [1] VC 1 Input Voltage for VCXO SDA 2 Serial Data input/output for I2C OE 3 Output Enable input NC1 4 No Connect FS0 5 Frequency Select-0 (100 k pull-down) FS1 6 Frequency Select-1 (100 k pull-down) SCL 7 Serial Clock input for I2C 8 Power supply for output Driver [2] 9 Complementary Clock Output [2] 10 True Clock Output CLK_SE 11 (Optional) LVCMOS clock output GND 12 Supply Ground for Output Driver VDD 13 Power supply for core GND 14 Supply ground VDDO CLK_N CLK_P [2] XIN 15 Crystal or Clock reference input XOUT 16 Crystal reference output, leave floating in case clock input for XIN E-PAD Exposed Pad. Must be connected to ground Note 1. If VC is unused, do not leave it floating; connect it to VDD or GND. 2. CLK_SE and (CLK_P, CLK_N) will not be available at the same time. VDD should be equal VDDO. Document Number: 002-11000 Rev. *E Page 3 of 24 CY29430 Functional Overview Programmable Features Figure 1. Conceptual Memory Structure Table 1. Programmable Features Feature Program eFuse Description Frequency Tuning Frequency for the PLL Function OE Polarity Power Supply VDD (1.8, 2.5 or 3.3 V) Reset Oscillator tuning (load capacitance values) Enable/Disable VCXO VCXO Function Reference “NVMCopy” Volatile M U X I2C FS[0‐1] Chip Settings Kv Polarity Total Pull Range Modulation Bandwidth Output “eFuse” Non‐Volatile Output Standard (LVPECL, LVDS, HCSL, CML or LVCMOS) I2C address 4-/ 2-/ 1- Default Frequency Figure 2. Memory structure for configurations Crystal (HFF, OT3, LFF) or Clock input FS0 Profile FS1 Profile FS2 Profile FS3 Profile VCXO Function VDD I2C Output Standard LOCK Input Reference Architecture Overview The CY29430 is a high-performance programmable PLL crystal oscillator supporting multiple functions and multiple output standards. The device has internal one-time programmable (OTP) nonvolatile memory (NVM) that can be partitioned into Common Device Configurations and Output frequency-related Information (see Figure 2). The Common Device Configurations do not change with output frequency and consist of chip power supply, OE polarity, I2C device address, input reference, output standards, and VCXO. The device also contains volatile memory that stores an exact copy of the NVM at the release of reset on Power ON. The Chip settings depend on the contents of the volatile memory and the output frequency depends on the configurations, as explained in Figure 1. The volatile memory can be accessed through the I2C bus and modified. Document Number: 002-11000 Rev. *E Frequency Information Common Device Configurations Description of Settings for the Memory Structure ■ Profile[FS0-3]: Frequency information ■ VCXO Function: VCXO enable/disable, TPR, modulation bandwidth and Kv (Slope for VC vs. Frequency) information ■ VDD: 1.8-/2.5-/3.3V range information ■ I2C: enable/disable, I2C address information ■ Output Standards: LVPECL, LVDS, CML, HCSL or LVCMOS ■ LOCK pattern: 2-bit pattern to indicate eFuse lock ■ Input Reference: Crystal (OT3, HFF, LFF) or Clock Page 4 of 24 CY29430 Internal State Diagram Programming Support The CY29430 contains a state machine which controls the device behavior. The state machine loads the “eFuse” contents to “NVMCopy” after reset as indicated in Figure 3. The state machine enters one of the following states: “Command Wait state” or “Active state” according to the value of LOCK. In the “Command Wait state” state, user may access all the registers and read/write the “NVMCopy” contents. The following commands can be used in the “Command Wait state”: The CY29430 is a software-configurable solution in which Cypress provides a Programming Specification that defines all necessary configuration bits. This information is used by the customer to develop programming software for use with their programmer hardware. ■ Program eFuse ❐ Selectively Program eFuse ■ Copy eFuse to NVMCopy ■ Copy NVMCopy to NVMRegister ■ Loop Lock User may test the device functionality by issuing “Loop Lock” command to enter the “Active state” without programming the LOCK. The device will function according to the settings. Figure 3. State Diagrams Release Reset on Power LOCK = "10" or "01" LOCK=“10” LOCK=“00” Loop Lock Active state Output Clock Small Change Large Change When the LOCK is programmed to "10" or "01" the device goes into the “Active state” and output clock is available after the completion of the power ON cycle. In the “Active state”, user may change the output frequency by applying “Small Change” or “Large Change” commands. Small/Large Changes Small change refers to the case where the frequency is changing within ±500 ppm. The frequency information will be loaded through I2C and the output frequency will change without any glitch from its original frequency to the new frequency. Note. the small change functionality is not supported in the Integer mode PLL. For more information, see AC Electrical Specifications for LVPECL, LVDS, CML Outputs. Large change refers to the case where the frequency is changing more than ±500 ppm and is done through an I2C or FS state change. The device will recalibrate and reconfigure the PLL and the output will be unstable until this process is completed. Document Number: 002-11000 Rev. *E The FS[0-3] setting is done based on the logic levels on the FS0 and FS1 pins as indicated in the Table 5 on page 6. The Frequency Configuration consists of the desired output frequency corresponding to each of the FS[0–3] setting. The Fractional-N PLL is loaded with values required to generate the frequency for each of these settings based on the input crystal frequency. The Frequency configuration for FS[0–3] is provided in Table 3. Programmable OE Polarity The CY29430 contains a bit for OE polarity setting (default is active-low). User can choose active-high or active-low polarity for the OE function. The output will be disabled when OE is deasserted Programmable VCXO Copy “eFuse” to “NVMCopy” Command Wait State Frequency Configurations The device incorporates a proprietary technique for modulating frequency by modifying VCO frequency according to the VC control voltage. The pull profile is linear and accurate comparing with pulling the OT3/HFF reference. Also, the VCXO characteristics are very stable and do not vary over temperature, supply voltage or process variations. Kv (Slope for frequency vs. VC), TPR VC bandwidth and VCXO on/off are all programmable.Note. the VCXO functionality is not supported in the Integer mode PLL. Power Supply Sequencing The CY29430 does not require any specific sequencing for startup. Startup requires a monotonic VDD ramp specified in the datasheet. After the ramp up, VDD has to be maintained within the limits specified for it in the Recommended Operating Conditions. Brownout detection and protection has to be implemented elsewhere in the system. Other input signals, VC, FS0 or FS1, can power up earlier or later than VDD, there are no timing requirement for those input signals with reference to VDD. The device will operate normally when all of the input signals are settled in the configured state. If a TCXO or external clock is fed into the XIN/XOUT inputs, a stable input has to be present before start of the VDD ramp up to the specified level. This is because the on-chip frequency calibration process starts at Power ON and requires a stable reference input to be available at the start of the process. I2C Interface The CY29430 supports two-wire serial interface and I2C in Fast Mode (400 kbits/s) and 7-bit addressing. The device address is programmable and is 55h by default. It supports single-byte access only. The first I2C access to the device has to be 5 ms (minimum) after VDD reaches its minimum specified voltage. Page 5 of 24 CY29430 Memory Map The user must write all the contents created by the Configuration tool. Partial updates to the device is not allowed. Table 2. Common Configurations Memory Address 50h–57h Description Device configurations Table 3. FS[0-3]: Frequency Configurations Memory Address Description 10h, 20h, 30h, 40h DIVO 11h, 21h, 31h, 41h DIVO, DIVN_INT 12h, 22h, 32h, 42h ICP,DIVN_INT, PLL_MODE 13h, 23h, 33h, 43h DIVN_FRAC_L 14h, 24h, 34h, 44h DIVN_FRAC_M 15h, 25h, 35h, 45h DIVN_FRAC_H 1xh = FS0, 2xh = FS1, 3xh = FS2, 4xh = FS3 Access to locations other than those described here may cause fatal error in device operation. Table 5. FS Setting FS1 FS0 FS Setting 0 0 FS0 0 1 FS1 1 0 FS2 1 1 FS3 – Table 4. Miscellaneous Information Memory Address Description 00h (Read only) Device ID (= 51h) D4h–D6h User configurable information Document Number: 002-11000 Rev. *E Page 6 of 24 CY29430 Absolute Maximum Ratings Exceeding maximum ratings [3] may shorten the useful life of the device. User guidelines are not tested. Supply voltage to ground potential .............–0.5 V to + 3.8 V Input voltage ...............................................–0.5 V to + 3.8 V Storage temperature (non-condensing) ... –55 C to +150 C Junction temperature ............................... –40 C to +125 C Programming temperature ....................... +25 C to +125 C Programming voltage .......................................2.5 V ± 0.1 V Supply Current for eFuse Programming ..................... 50 mA Data retention at TJ = 125 C ...............................> 10 years Maximum programming cycles ............................................1 ESD HBM (JEDEC JS-001-2012) ............................ 2000 V ESD MM (JEDEC JESD22-A115B) ............................. 200 V ESD CDM (JEDEC JESD22-C101E) ........................... 500V Latch up current ...................................................... ±140 mA Recommended Operating Conditions Parameter VDD, VDDO TA fRES TPLLHOLD Description Supply voltage, 1.8 V operating range, 1.8 V ± 5% Supply voltage, 2.5 V operating range, 2.5 V ± 10% Supply voltage, 3.3 V operating range, 3.3 V ± 10% Ambient temperature Frequency resolution PLL Hold Temperature Range Min 1.71 2.25 2.97 –40 – – Max 1.89 2.75 3.63 +105 2 125 Unit V Min – Typ 93 Max 106 Unit mA – 81 94 – 69 81 – 80 93 – 73 86 – 58 70 – 66 78 – – – 0.7 × VDD – –0.5 – – – 59 30 30 – – – 200 200 100 70 50 50 – 0.3 × VDD 3.8 – – – C ppb C DC Electrical Specifications Parameter IDD[4] Description Supply current, LVPECL Supply current, LVPECL Supply current, LVDS Supply current, HCSL Supply current, CML Supply current, CMOS Supply current, CMOS IIH IIL VIH[6] VIL[6] VIN RP RD Supply current, PLL only Input high current Input low current Input high voltage Input low voltage Input voltage level Internal pull-up resistance Internal pull-down resistance Test Conditions VDD = 3.3 V/2.5 V, 50 to VTT (VDDO – 2.0 V), with common mode current VDD = 3.3 V/2.5 V, 50 to VTT (VDDO – 2.0 V), without common mode current[5] VDD = 3.3 V/2.5 V/1.8 V, 100 between CLKP and CLKN VDD = 3.3 V/2.5 V/1.8 V, 33 and 49.9 to GND VDD = 3.3 V/2.5 V/1.8 V, 50 to VDDO VDD = 3.3 V/2.5 V/1.8 V, 0-pF load, 33.33 MHz VDD = 3.3 V/2.5 V/1.8 V, 10-pF load, 33.33 MHz VDD = 3.3 V/2.5 V/1.8 V Logic input, Input = VDD Logic input, Input = GND OE, FS, SCL, SDA logic level = 1 OE, FS, SCL, SDA logic level = 0 All input, relative to GND OE, configured active High OE, configured active Low FS0, FS1 pins µA µA V V V k k k Notes 3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or at any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to Absolute-Maximum-Rated conditions for extended periods may affect device reliability or cause permanent device damage. 4. IDD is the total supply current and is measured with VDD and VDDO shorted together. 5. In ClockWizard 2.1, setting the output standard to LVPECL2 configures the output to "LVPECL without common mode current". Refer to AN210253 for LVPECL terminations for different use case configurations. 6. I2C operation applicable for VDD of 1.8 V and 2.5 V only. Document Number: 002-11000 Rev. *E Page 7 of 24 CY29430 DC Specifications for LVDS Output (VDDO = 1.8-V, 2.5-V, or 3.3-V range) Parameter Description VOCM[7] Output common-mode voltage VOCM Change in VOCM between complementary output states IOZ Output leakage current Conditions Min Typ Max Units 1.125 1.200 1.375 V – – – 50 mV Output off, VOUT = 0.75 V to 1.75 V –20 – 20 A VDDO = 2.5-V or 3.3-V range DC Specifications for LVPECL Output (VDDO = 2.5-V or 3.3-V range, with common mode current) Parameter Description Conditions Min Typ Max Units VOH Output high voltage R-term = 50 to VTT (VDDO – 2.0 V) VDDO – 1.165 – VDDO – 0.800 V VOL Output low voltage R-term = 50 to VTT (VDDO – 2.0 V) VDDO – 2.0 – VDDO – 1.55 V Min Typ Max Units DC Specifications For CML Output (VDDO = 1.8-V, 2.5-V, or 3.3-V range) Parameter Description Conditions VOH Output high voltage R-term = 50 to VDDO VOL Output low voltage R-term = 50 to VDDO VDDO – 0.085 VDDO – 0.01 VDDO – 0.6 VDDO – 0.4 VDDO V VDDO – 0.32 V DC Specifications for HCSL Output (VDDO = 1.8-V, 2.5-V or 3.3-V range) Parameter Description Min Typ Max Units Measurement taken from single-ended waveform – – 1150 mV Min output low voltage Measurement taken from single-ended waveform –300 – – mV VOHDIFF Differential output high voltage Measurement taken from differential waveform 150 – – mV VOLDIFF Differential output low voltage Measurement taken from differential waveform – – –150 mV VCROSS[8] Absolute crossing point voltage Measurement taken from single-ended waveform 250 – 600 mV – – 140 mV VMAX[8] Max output high voltage VMIN[8] Conditions VCROSSDELTA[8] Variation of VCROSS over all rising Measurement taken from clock edges single-ended waveform Notes 7. Requires external AC coupling for VDDO = 1.8-V range, as indicated in Figure 9. The common-mode voltage of 1.2V has to be generated and applied externally. 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 002-11000 Rev. *E Page 8 of 24 CY29430 DC Specifications for LVCMOS Output Parameter Description Output high voltage VOH Output low voltage VOL Conditions Min Typ Max Units VDDO – 0.2 – – V 4 mA load, VDD = 3.3 V VDDO – 0.3 – – 4 mA load, VDD = 1.8 V and 2.5 V VDDO – 0.4 – – 100 A load – – 0.2 4 mA load – – 0.3 Min Typ Max Units 100 A load V VCXO Specific Parameters Parameter[9] Description Condition TPR Total Pull Range VC range 0.1 × VDD to 0.9 × VDD +50 – +275 ppm KBSL Best-fit Straight Line (BSL) linearity Deviation from BSL line –5 – 5 % KINC Incremental linearity Kv slope deviation –10 – 10 % KBW Bandwidth of Kv modulation Programmable 5 10 20 kHz KRANGE voltage range on the control port – permissible 0 – VDD V VCTYP Nominal center voltage – 0.5 × VDD – V RVCIN [10] VRANGE VC control voltage Input resistance for VC – Input voltage range range of input possible at control port 5 – – M 0.1 × VDD – 0.9 × VDD V Notes 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. 10. RVCIN is 100% tested. Document Number: 002-11000 Rev. *E Page 9 of 24 CY29430 AC Electrical Specifications for LVPECL, LVDS, CML Outputs (VDD = 3.3 V and 2.5 V for LVPECL, with common mode current, and VDD = 3.3 V, 2.5 V, and 1.8 V for LVDS and CML outputs) Parameter[10] Description Details/Conditions Min Typ Max Unit fOUT Clock Output Frequency LVPECL, CML, LVDS output standards 15 – 2100 MHz tRF LVPECL Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for PECL outputs. – – 350 ps CML Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for CML outputs. – – 350 ps LVDS Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for LVDS outputs. – – 350 ps tODC Output Duty Cycle Measured at differential 50% level, 156.25 MHz. 45 50 55 % VP LVDS output differential peak 15 MHz to 700 MHz 247 – 454 mV VP LVDS output differential peak 700 MHz to 2100 MHz 150 – 454 mV VP Change in VP between complementary output states – – 50 mV VP LVPECL output differential peak fOUT = 15 MHz to 325 MHz 450 – – mV – VP fOUT = 325 MHz to 700 MHz 350 – – mV VP fOUT = 700 MHz to 2100 MHz 250 – – mv VP CML output differential peak fOUT = 15 MHz to 700 MHz 250 – 600 mV VP CML output differential peak fOUT = 700 MHz to 2100 MHz 200 – 600 mV tCCJ Cycle to Cycle Jitter pk, measured at differential signal, 156.25 MHz, over 10k cycles, 100 MHz–130 MHz crystal – – 50 ps tPJ Period Jitter pk-pk, measured at differential signal, 156.25 MHz, over 10k cycles, 100 MHz–130 MHz crystal – – 50 ps JRMS RMS Phase Jitter fOUT = 156.25 MHz, 12 kHz–20 MHz offset, non-VCXO mode – 150 250 fs Non-VCXO Mode PN1k Phase Noise, 1 kHz Offset 100 MHz–130 MHz crystal reference, fOUT = 156.25 MHz – – -113 dBc/Hz PN10k Phase Noise, 10 kHz Offset 100 MHz–130 MHz crystal reference, fOUT = 156.25 MHz – – -127 dBc/Hz PN100k Phase Noise, 100 kHz Offset 100 MHz–130 MHz crystal reference, fOUT = 156.25 MHz – – -135 dBc/Hz PN1M Phase Noise, 1MHz Offset 100 MHz–130 MHz crystal reference, fOUT = 156.25 MHz – – -144 dBc/Hz PN10M Phase Noise, 10 MHz Offset 100 MHz–130 MHz crystal reference, fOUT = 156.25 MHz – – –152 dBc/Hz PN-SPUR Spur At frequency offsets equal to and greater than the update rate of the PLL – – –65 dBc/Hz Note 11. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 002-11000 Rev. *E Page 10 of 24 CY29430 AC Electrical Specifications for HCSL Output Parameter [12] fOUT Description Output frequency Test Conditions HCSL Min Typ Max Units 15 – 700 MHz [13] V/ns ER Rising edge rate Measured taken from differential waveform, –150 mV to +150 mV 0.6 – 5.7 EF Falling edge rate Measured taken from differential waveform, –150 mV to +150 mV 0.6 – 5.7 [13] V/ns tSTABLE Time before voltage ring back (VRB) is allowed Measured taken from differential waveform, –150 mV to +150 mV 500 – – ps R-F_MATCHING Rise-Fall matching Measured taken from single-ended waveform, rising edge rate to falling edge rate matching, 100 MHz –100 – 100 ps tDC Output duty cycle Measured taken from differential waveform, fOUT = 100 MHz 45 – 55 % tCCJ Cycle to cycle Jitter Measured taken from differential waveform, 100 MHz – – 50 ps JRMSPCIE Random jitter, PCIE Specification 100 MHz–130 MHz crystal 3.0 – – 1 ps (RMS) Min Typ Max Unit 15 – 250 MHz Measured at 1/2 VDDO, loaded, fOUT < 100 MHz 45 – 55 % Measured at 1/2 VDDO, loaded, fOUT > 100 MHz 40 – 60 % VDDO = 1.8 V, 20%–80% – – 2 ns VDDO = 2.5 V, 20%–80% – – 1.5 ns AC Electrical Specifications for LVCMOS Output (Load: 10 pF < 100 MHz, 7.5 pF < 150 MHz, 5 pF > 150 MHz) Parameter[12] Description fOUT Output frequency tDC Output duty cycle tRFCMOS Rise/Fall time Test Conditions VDDO = 3.3 V, 20%–80% – – 1.2 ns tCCJ Cycle to cycle Jitter pk, Measured at 1/2VDDO over 10k cycle, fOUT = 156.25 MHz – – 50 ps tPJ Period Jitter pk, Measured at 1/2VDDO over 10k cycle, fOUT = 156.25 MHz – – 100 ps Notes 12. Parameters are guaranteed by design and characterization. Not 100% tested in production. 13. Edge rates are higher than 4 V/ns due to jitter performance requirements. Document Number: 002-11000 Rev. *E Page 11 of 24 CY29430 HFF Crystal Specifications Parameter[14] fXTAL Description Crystal frequency range Test Conditions Min Typ Max Unit – 100 – 130 MHz C0 Crystal shunt capacitance – – – 2 pF CL Crystal load capacitance – – 5 – pF ESR Crystal equivalent series resistance – 20 – DL Drive level – – – 200 W Test Conditions Min Typ Max Units ESR = Rm (1 + C0/CL) ^ 2 Rm = Crystal motional resistance OT3 Crystal Specifications Parameter[14] Description fXTAL Crystal frequency range – 100 – 130 MHz C0 Crystal shunt capacitance – – – 2 pF – – 5 – pF – 60 90 – – – 200 W Test Conditions Min Typ Max Units CL Crystal load capacitance ESR Crystal equivalent series resistance DL Drive level ESR = Rm (1 + C0/CL) ^ 2 Rm = Crystal motional resistance LFF Crystal Specifications Parameter[14] Description fXTAL Crystal frequency range – 50 – 60 MHz C0 Crystal shunt capacitance – – – 2 pF – – – 8 pF – – 90 W – – 200 W CL Crystal load capacitance ESR Crystal equivalent series resistance DL Drive level ESR = Rm (1 + C0/CL) ^ 2 Rm = Crystal motional resistance – Note 14. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 002-11000 Rev. *E Page 12 of 24 CY29430 LF Low Frequency Reference (TCXO reference input) Parameter[15] Description Test Conditions Min Typ Max Units – 50 – 60 MHz fIN Input frequency tDC Input duty cycle Measured at 1/2 input swing 40 – 60 % VPP pk-pk input swing AC coupled input 0.8 – 1.2 V VIL Input low voltage DC coupled input – – 0.2 V VIH[16] Input high voltage DC coupled input 0.8 – 1.2 V tR Input rise time 20%–80% of input – – 1.5 ns tF Input fall time 20%–80% of input – – 1.5 ns PN10K Input phase noise 10 kHz offset – – –151 dBc/Hz PN100K Input phase noise 100 kHz offset – – –155 dBc/Hz PN1M Input phase noise 1 MHz offset – – –156 dBc/Hz Timing Parameters Parameter[15] Description Min Max Unit 0.01 3000 ms Time from minimum specified power supply to <+ 0.1 ppm accurate output frequency clock, programmable (Clock stable within 2.2 ms (max) from VDDX Level, refer to Input Clock Measurement Point) – 10 ms Time from minimum specified power supply to <+ 0.1 ppm accurate output frequency clock, programmable (Clock stable within 5.8 ms (max) from VDDX Level, refer to Input Clock Measurement Point) – 15 tOEEN Time from OE edge to output enable – 2.5 ms tOEDIS Time for OE edge to output disable – 10 s tFS Time form FS change to new frequency – 2.5 ms tFSAMLL Frequency change time for small trigger ( ±500ppm) – 400 s tFLARGE Frequency change time for large trigger (> ±500ppm) – 2.5 ms tCLOCK Clock stable time delay from VDD ramp (see Figure 5), normal configuration – 2.2 ms Clock stable time delay from VDD ramp (see Figure 5), delay programmed – 5.8 tPU Supply ramp time (0.5 V to VDD(min)). tWAKEUP[16] Input Clock Measurement Point Parameter VDDX[15, 17] Description tCLOCK Measurement Point Test Conditions Min Typ Max Unit Supply voltage 1.8 V 1.4 – – V Supply voltage 2.5 V 1.8 – – Supply voltage 3.3 V 2.3 – – Notes 15. Parameters are guaranteed by design and characterization. Not 100% tested in production. 16. VIH should not to exceed 0.5V when VDD = 0V. 17. Applies to TCXO/External Clock Input. Document Number: 002-11000 Rev. *E Page 13 of 24 CY29430 Phase Jitter Characteristics (12 kHz to 20 MHz Integration Bandwidth) Parameter[18] Description Condition Min Typ Max Units Non VCXO functionality JRMS RMS jitter fOUT = 644.53 MHz – 110 – fs JRMS RMS jitter fOUT = 622.08 MHz – 120 – fs JRMS RMS jitter fOUT = 156.25 MHz – 145 – fs JRMS RMS jitter fOUT = 2.105 GHz – 145 – fs Modulation bandwidth = 10 kHz, VDD = 3.3V, fOUT = 622.08 MHz JRMS RMS jitter TPR = 50 ppm, Kv = 37.9 ppm/V – 151 – fs JRMS RMS jitter TPR = 155 ppm, Kv = 117.4 ppm/V – 158 – fs JRMS RMS jitter TPR = 275 ppm, Kv = 208.3 ppm/V – 170 – fs Modulation bandwidth = 10 kHz, VDD = 2.5V, fOUT = 622.08 MHz JRMS RMS jitter TPR = 50 ppm, Kv = 50 ppm/V – 152 – fs JRMS RMS jitter TPR = 155 ppm, Kv = 155 ppm/V – 160 – fs JRMS RMS jitter TPR = 275 ppm, Kv = 275 ppm/V – 175 – fs Modulation bandwidth = 10 kHz, VDD = 1.8V, fOUT = 622.08 MHz JRMS RMS jitter TPR = 50 ppm, Kv = 69.4 ppm/V – 153 – fs JRMS RMS jitter TPR = 155 ppm, Kv = 215.3 ppm/V – 166 – fs JRMS RMS jitter TPR = 275 ppm, Kv = 381.9 ppm/V – 190 – fs Min Typ Max Units – – 400 kHz I2C Bus Timing Specifications Parameter [18, 19] Description fSCL SCL clock frequency tHD:STA Hold time START condition 0.6 – – s tLOW Low period of SCL 1.3 – – s tHIGH High period of SCL 0.6 – – s tSU:STA Setup time for a repeated START condition 0.6 – – s tHD:DAT Data hold time 0 – – s tSU:DAT Data setup time 100 – – ns tR Rise time – – 300 ns tF Fall time – – 300 ns tSU:STO Setup time for STOP condition 0.6 – – s tBUF Bus-free time between STOP and START conditions 1.3 – – s Notes 18. Parameters are guaranteed by design and characterization. Not 100% tested in production. 19. I2C operation applicable for VDD of 1.8 V and 2.5 V only. Document Number: 002-11000 Rev. *E Page 14 of 24 CY29430 Voltage and Timing Definitions Figure 4. Differential Output Definitions tDC = tPW / tPERIOD Figure 8. Output Termination Circuit VOCM = (VA + VB) / 2 50 tPW VPP OUT-N 80% 20% 20% tR 50 VA 80% VB BUF OUT-P VDDO – 2 V VDDO tPERIOD tF 50 TP 50 TP LVPECL Figure 5. Input Clock Stable time VDDO VDDO 50 BUF VDDX VDD 50 50 TP 50 TP 50 100 TP 50 TP Stable Clock CML tCLOCK VDDO BUF Clock Input Figure 6. Output Enable/Disable/Frequency Select Timing Original Clock New Clock LVDS Clock VDDO FSx OE 5” 33 BUF tOEDISt FS tOEEN New Clock TP 2 pF 33 49.9 Original Clock 50 50 49.9 P 2 pF HCSL Clock Figure 9. LVDS Termination for 1.8 V[20] FSx VDDO tFS VDD 0.1 µF 50 50 ? Figure 7. Power Ramp and PLL Lock Time 50 50 ? Supply Voltage tPU Transmitter VDD(min) VOCM Receiver 50 50 ? 0.5 V 50 50 ? twakeup Stable Output 0.1 µF Output Note 20. The termination circuit shown in this figure is specific to the LVDS output standard for VDD =1.8-V operation. This needs AC coupling (100-nF series capacitor). The 50-ohm termination resistors along with the bias voltage (VOCM) is required to be set at the destination circuit as shown in the figure. Document Number: 002-11000 Rev. *E Page 15 of 24 CY29430 Figure 10. HCSL: Single-ended Measurement Points for Absolute Crossing Point Figure 12. HCSL: Differential Measurement Points for Rise and Fall Time Rising Edge Rate VMAX = 1.15 V REFCLK ‐ VCROSS MAX = 550 mV Falling Edge Rate VIH = +150 mV 0.0 V VIL = ‐150 mV VCROSS MIN = 250 mV REFCLK + VMIN = ‐0.30 V REFCLK + minus Figure 11. HCSL: Single-ended Measurement Points for Delta Crossing Point Figure 13. HCSL: Differential Measurement Points for Ringback REFCLK ‐ TSTABLE VRB VCROSS DELTA = 140 mV VIH = +150 mV VRB = +100 mV REFCLK + VRB = ‐100 mV VIL = ‐150 mV REFCLK + minus VRB TSTABLE Figure 14. I2C Bus Timing Specifications SDAT tf tLOW tr tSU;DAT tf tHD;STA tr tBUF SCLK tHD;STA S tHD;DAT Document Number: 002-11000 Rev. *E tHIGH tSU;STA tSU;STO Sr P S Page 16 of 24 CY29430 Phase Noise Plots Figure 15. Typical Phase Noise at 156.25 MHz (12 kHz–20 MHz) Document Number: 002-11000 Rev. *E Page 17 of 24 CY29430 Figure 16. Typical Phase Noise at 622.08 MHz (12 kHz–20 MHz) Document Number: 002-11000 Rev. *E Page 18 of 24 CY29430 Figure 17. Typical Phase Noise at 644.53 MHz (12 kHz–20 MHz) Document Number: 002-11000 Rev. *E Page 19 of 24 CY29430 Ordering Information Ordering Code Configuration Package Description Product Flow CY29430FLQXIT Field-programmable 16-pin QFN – Tape and Reel Industrial, –40 C to +105 C CY29430LQXIxxxT Factory-configured[21] 16-pin QFN – Tape and Reel Industrial, –40 C to +105 C Ordering Code Definitions CY 29430 X - LQXI xxx T T = Tape and Reel, Blank = Bulk Customer Part Configuration Code: Package Type: LQ(QFN), Pb-free: X, Industrial: I Configuration: F = Field programmable, Blank = Factory Configured Part Identifier Company ID: CY = Cypress Note 21. These are factory-programmed customer-specific part numbers. Contact your local Cypress FAE or sales representative for more information. Document Number: 002-11000 Rev. *E Page 20 of 24 CY29430 Package Diagram Figure 18. 16-pin QFN (3 × 3 × 0.6 mm) LQ16A 1.7 × 1.7 E-Pad (Sawn) Package Outline, 001-87187 001-87187 *A Document Number: 002-11000 Rev. *E Page 21 of 24 CY29430 Acronyms Document Conventions Acronym Description Units of Measure AC alternating current ADC analog-to-digital converter °C Degrees Celsius BSL best-fit straight line fs femtoseconds CML current mode logic GHz gigahertz DC direct current k kilohms ESD electrostatic discharge kHz kilohertz MHz megahertz M megaohms µA microamperes FS frequency select HCSL high-speed current steering logic I2C inter-integrated circuit JEDEC Joint Electron Device Engineering Council LDO low dropout (regulator) LVCMOS low voltage complementary metal oxide semiconductor LVDS low-voltage differential signals LVPECL low-voltage positive emitter-coupled logic NV non-volatile OE Symbol Unit of Measure µm micrometers µs microseconds µW microwatts mA milliamperes mm millimeters m milliohms ms milliseconds mV millivolts output enable nH nanohenrys PLL phase-locked loop ns nanoseconds POR power-on reset ohms PSoC® Programmable Sytem-on-Chip ppm parts per million QFN quad flat no-lead ppb parts per billion RMS root mean square % percent SCL serial I2C clock pF picofarads SDA serial I2C ps picoseconds VRB voltage ring back V volts VCXO voltage controlled crystal oscillator XTAL crystal data Document Number: 002-11000 Rev. *E Page 22 of 24 CY29430 Document History Page Document Title: CY29430, High-Performance Clock Synthesizer Document Number: 002-11000 Rev. ECN No. Submission Date Orig. of Change *B 5320399 07/18/2016 MGPL Changed status from Preliminary to Final. *C 5429121 09/07/2016 MGPL Updated Absolute Maximum Ratings: Added “Supply Current for eFuse Programming”. Replaced “> 2000 V” with “2000 V” in value corresponding to “ESD HBM”. Replaced “> 200 V” with “200 V” in value corresponding to “ESD MM”. Added “ESD CDM (JEDEC JESD22-C101E)”. Updated to new template. *D 5518357 11/15/2016 MGPL/ PSR Added Table 5 and reference to Table 5 in Frequency Configurations. Added Figure 9. *E 5613574 02/03/2017 PSR Document Number: 002-11000 Rev. *E Description of Change Added links to ClockWizard 2.1 and technical support, and added reference to related documentation in Functional Description. Updated LVPECL specs in DC Electrical Specifications. Added note clarifying voltage range in AC Electrical Specifications for LVPECL, LVDS, CML Outputs. Added a note for factory-configured parts in Ordering Information. Page 23 of 24 CY29430 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2016-2017. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-11000 Rev. *E Revised February 3, 2017 Page 24 of 24