AS4C8M32S
Revision History AS4C8M32S- 90 Ball TFBGA PACKAGE
Revision
Rev 1.0
Rev 1.1
Rev 2.0
Details
Preliminary datasheet
Added 166MHz option -6 clock cycle time
Typing error page 1 – fast clock rate error
133MHz should be 143MHz
Typing error - Frequency in Table 2. Ordering information
7-BCN reflected as 133MHz – changed to 143MHz
Date
February 2013
February 2013
May 2014
May 2014
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
AS4C8M32S
8M x 32 bit Synchronous DRAM (SDRAM)
Advanced (Rev. 2.0 May /2014)
Confidential
Features
Overview
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143MHz
Fully synchronous operation
Internal pipelined architecture
2M word x 32-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & interleaved
- Burst stop function
Auto Refresh and Self Refresh
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
4096
refresh cycles/64ms
CKE power down mode
Single +3.3V power supply
Interface: LVTTL
90-ball, 8.0 x 13 x 1.4mm TFBGA package
- Pb and Halogen Free
Table 1. Key Specifications
AS4C8M32S
Clock
Cycle time(min.)
tCK3
tAC3
tRAS
tRC
The 256Mb AS4C8M32S SDRAM is a highspeed CMOS synchronous DRAM containing 256
Mbits. It is internally configured as 4 Banks of 2M
word x 32 DRAM with a synchronous interface (all
signals are registered on the positive edge of the
clock signal, CLK). Read and write accesses to the
SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed
number of locations in a programmed sequence.
Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications
-6/7
Access time from CLK (max.)
Row Active time(min.)
Row Cycle time(min.)
6/7.5 ns
5/5.4 ns
42/45 ns
60/67.5 ns
Table 2.Ordering Information
Part Number
AS4C8M32S-6BIN
AS4C8M32S-7BCN
Frequency
166MHz
143MHz
Package
90-ball TFBGA
90-ball TFBGA
Temperature
Industrial
Commercial
Temp Range
-40 ~ 85°C
0 ~ 70°C
B: indicates 90-ball (8.0 x 13 x 1.4mm) TFBGA package
N: indicates Pb and Halogen Free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.
AS4C8M32S
Figure 1. Ball Assignment (Top View)
1
2
3
A
DQ26
DQ24
B
DQ28.
C
…
7
8
9
VSS
VDD
DQ23
DQ21
VDDQ
VSSQ
VDDQ.
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
D
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
E
VDDQ
DQ31
NC
NC
DQ16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS#
RAS#
K
DQM1
NC
NC
CAS#
WE#
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
P
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ13
DQ15
VSS
VDD
DQ0
DQ2
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AS4C8M32S
Figure 2. Block Diagram
CLOCK
BUFFER
Row
Decoder
CLK
CKE
2M x 32
CELL ARRAY
(BANK #A)
Column Decoder
COMMAND
DECODER
DQ
Buffer
CONTROL
SIGNAL
GENERATOR
DQ0
~
CS#
RAS#
CAS#
WE#
DQ31
A10/AP
COLUMN
COUNTER
MODE
REGISTER
A9
A11
BA0
BA1
2M x 32
CELL ARRAY
(BANK #B)
Column Decoder
ADDRESS
BUFFER
Row
Decoder
~
A0
Row
Decoder
DQM0 ~ DQM3
REFRESH
COUNTER
2M x 32
CELL ARRAY
(BANK #C)
Row
Decoder
Column Decoder
2M x 32
CELL ARRAY
(BANK #D)
Column Decoder
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AS4C8M32S
Pin Descriptions
Table 1. Pin Details
Symbol Type Description
CLK
Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
CKE
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes
low synchronously with clock (set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
BA0,
BA1
Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. The bank address BA0 and BA1 is used latched
in mode register set.
A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge)
to select one location out of the 2M available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
The address inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
CS#
Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS#
Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BA is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command is
selected and the bank designated by BA is switched to the idle state after the precharge
operation.
CAS#
Input Column Address Strobe: The CAS# signal
conjunction with the RAS# and WE# signals and
When RAS# is held "HIGH" and CS# is asserted
asserting CAS# "LOW." Then, the Read or Write
"LOW" or "HIGH."
WE#
Input Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used
to select the BankActivate or Precharge command and Read or Write command.
defines the operation commands in
is latched at the positive edges of CLK.
"LOW," the column access is started by
command is selected by asserting WE#
DQM0 - Input Data Input/Output Mask: Data Input Mask: DQM0-DQM3 are byte specific. Input data is
DQM3
masked when DQM is sampled HIGH during a write cycle. DQM3 masks DQ31-DQ24,
DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of
DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
No Connect: These pins should be left unconnected.
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
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AS4C8M32S
VDD
Supply Power Supply: +3.3V0.3V
VSS
Supply Ground
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AS4C8M32S
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table
4 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2))
Command
BankActivate
State
CKEn-1 CKEn DQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE#
Idle(3)
H
X
X
V
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
V
V
L
L
H
L
L
V
V
H
Column
address
(A0 ~ A8)
Write and AutoPrecharge
Active(3)
H
X
L
H
L
L
Read
Active(3)
H
X
V
V
L
L
H
L
H
H
X
V
V
H
Column
address
(A0 ~ A8)
Read and Autoprecharge
Active(3)
L
H
L
H
Mode Register Set
Idle
H
X
X
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
L
H
X
X
X
X
H
X
X
X
L
H
H
H
H
L
X
X
X
X
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
Burst Stop
SelfRefresh Exit
Idle
(SelfRefresh)
Clock Suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Active
Any(5)
Row address
OP code
H
L
X
X
X
X
Active
L
H
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
X
X
(PowerDown)
Data Write/Output Enable
Active
H
X
L
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
Note: 1. V=Valid, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
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AS4C8M32S
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0, 1 signals. By
latching the row address on A0 to A11 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of t RCD (min.) from
the time of bank activation. A subsequent BankActivate command to a different row in the same bank
can only be issued after the previous active row has been precharged (refer to the following figure).
The minimum time interval between successive BankActivate commands to the same bank is
defined by tRC (min.). The SDRAM has four internal banks on the same chip and shares part of the
internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the two banks.
tRRD (min.) specifies the minimum time required between activating different banks. After this
command is used, the Write command and the Block Write command perform the no mask write
operation.
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Col Addr.
Bank A
Row Addr.
Bank B
Row Addr.
RAS# - RAS# delay time(tRRD)
RAS# - CAS# delay(tRCD)
COMMAND
Bank A
Activate
NOP
NOP
Bank A
Row Addr.
Bank B
Activate
R/W A with
AutoPrecharge
NOP
NOP
Bank A
Activate
RAS# - Cycle time(tRC)
AutoPrecharge
Begin
Don’t Care
Figure 3. BankActivate Command Cycle (Burst Length = n)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
The BankPrecharge command precharges the bank disignated by BA signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS (max.). Therefore, the precharge function must be performed
in any active bank within tRAS (max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9 and A11 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t RCD (min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS latency after the issue of the Read command. Each subsequent data-out
element will be valid by the next positive clock edge (refer to the following figure). The DQs go into
high-impedance at the end of the burst unless other command is initiated. The burst length, burst
sequence, and CAS latency are determined by the mode register, which is already programmed. A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
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AS4C8M32S
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS# latency=2
tCK2, DQ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2
DOUT A3
Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
CAS# latency=2
tCK2, DQ
CAS# latency=3
tCK3, DQ
READ B
NOP
DOUT A0
NOP
NOP
NOP
NOP
NOP
NOP
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0
DOUT B0 DOUT B1
DOUT B2 DOUT B3
Figure 5. Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
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AS4C8M32S
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
DQM
COMMAND
NOP
NOP
BANKA
ACTIVATE
NOP
NOP
READ A WRITE A
CAS# latency=2
tCK2, DQ
DIN A0
NOP
NOP
DIN A1
DIN A2
NOP
NOP
DIN A3
Must be Hi-Z before
the Write Command
Figure 6. Read to Write Interval (Burst Length 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
NOP
READ A
CAS# latency=2
tCK2, DQ
NOP
NOP
WRITE B
DIN B0
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
Figure 7. Read to Write Interval (Burst Length ≧ 4, CAS# Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
CAS# latency=3
tCK3, DQ
NOP
NOP
NOP
NOP
WRITE B
DOUT A0
DIN B0
NOP
DIN B1
NOP
DIN B2
Must be Hi-Z before
the Write Command
Don’t Care
Figure 8. Read to Write Interval (Burst Length 4, CAS# Latency = 2)
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AS4C8M32S
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
ADDRESS
Bank
Row
Bank(s)
tRP
COMMAND
READ A
NOP
CAS# latency=2
tCK2, DQ
NOP
NOP
Precharge
NOP
NOP
Activate
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Don’t Care
Figure 9. Read to Precharge (CAS# Latency = 2, 3)
5
6
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t RCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
DQ
DIN A0
NOP
NOP
DIN A1
DIN A2
NOP
DIN A3
NOP
NOP
NOP
NOP
don’t care
The first data element and the write
are registered on the same clock edge
Figure 10. Burst Write Operation (Burst Length = 4)
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A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
DQ
WRITE A
WRITE B
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
NOP
NOP
NOP
Figure 11. Write Interrupted by a Write (Burst Length = 4)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
READ B
CAS# latency=2
tCK2, DQ
DIN A0
don’t care
CAS# latency=3
tCK3, DQ
DIN A0
don’t care
COMMAND
NOP
NOP
NOP
NOP
DOUT B0 DOUT B1
don’t care
DOUT B0
NOP
NOP
DOUT B2
NOP
DOUT B3
DOUT B1
DOUT B2
DOUT B3
Input data must be removed from the DQ
at least one clock cycle before the Read
data appears on the outputs to avoid data
contention
Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge
function should be issued m cycles after the clock edge in which the last data-in element is registered,
where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used
to mask input data, starting with the clock edge following the last data-in element and ending with the
clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
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T0
T1
T2
T3
T4
T5
T6
T7
Activate
NOP
CLK
DQM
tRP
COMMAND
ADDRESS
WRITE
NOP
NOP
BANK
COL n
Precharge
NOP
NOP
BANK(S)
ROW
tWR
DIN
N
DQ
DIN
N+1
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7
Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",
A0-A8 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
COMMAND
Bank A
Activate
NOP
DQ
NOP
Write A
Auto Precharge
NOP
DIN A0
DIN A1
NOP
NOP
NOP
NOP
Bank A
Activate
tDAL
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
tDAL=tWR+tRP
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
8
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued at
the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the
mode register. Two clock cycles are required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as all banks are in the idle state.
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AS4C8M32S
Table 3. Mode Register Bitmap
BA0,1 A11,A10 A9
RFU* RFU*
WBL
A9
0
1
A8
A7
Test Mode
Write Burst Length
Burst
Single Bit
A8
0
1
0
A7
0
0
1
A6
A5
A4
CAS Latency
A3
BT
A2
Test Mode
Normal
Vendor Use Only
Vendor Use Only
A3
0
1
A1
A0
Burst Length
Burst Type
Sequential
Interleave
A6
0
0
0
0
1
A5
A4
CAS Latency
A2
A1
A0
Burst Length
0
0
Reserved
0
0
0
1
0
1
Reserved
0
0
1
2
1
0
2 clocks
0
1
0
4
1
1
3 clocks
0
1
1
8
0
0
Reserved
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
BA0, 1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
Hi-Z
PrechargeAll
Mode Register
Set Command
Any
Command
Don’t Care
Figure 15. Mode Register Set Cycle
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AS4C8M32S
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 2, 4, 8, or full page.
Table 4. Burst Length Field
A2
A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Full Page
Full Page Length: 512
Burst Type Field (A3)
The Burst Type can be one of two modes, Interleave Mode or Sequential Mode.
Table 5. Burst Type Field
A3
Burst Type
0
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 6. Burst Definition
Burst Length
2
4
8
Full page
Start Address
A2
A1
A0
X
X
0
X
X
1
X
0
0
X
0
1
X
1
0
X
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
location = 0-255
Alliance Memory Confidential
Sequential
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
n, n+1, n+2, n+3, …511, 0,
1, 2, … n-1, n, …
14
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Not Support
Rev. 2.0 May /2014
AS4C8M32S
CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field.
tCAC(min) CAS Latency X tCK
Table 7. CAS Latency Field
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2 clocks
0
1
1
3 clocks
1
X
X
Reserved
Test Mode Field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 8. Test Mode Field
A8
A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
X
Vendor Use Only
Write Burst Length (A9)
This bit is used to select the burst write length.
Table 9. Write Burst length
A9
9
Write Burst Length
0
Burst
1
Single Bit
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
10
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS latency (refer to the following figure). The termination
of a write burst is shown in the following figure.
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Rev. 2.0 May /2014
AS4C8M32S
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
The burst ends after a delay equal to the CAS# latency
CAS# latency=2
tCK2, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Figure 16. Termination of a Burst Read Operation (Burst Length ＞ 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
DQ
WRITE A
NOP
NOP
Burst Stop
DIN A0
DIN A1
DIN A2
don’t care
NOP
NOP
NOP
NOP
Figure 17. Termination of a Burst Write Operation (Burst Length = X)
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
12
AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto refresh
operation is specified by tRC (min.). To provide the AutoRefresh command, all banks need to be in the
idle state and the device must not be in power down mode (CKE is high in the previous cycle). This
command must be followed by NOPs until the auto refresh operation is completed. The precharge
time requirement, tRP (min), must be met before successive auto refresh operations are performed.
13
SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM
may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14
SelfRefresh Exit command
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC (min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
Alliance Memory Confidential
16 Rev.
2.0 May /2014
AS4C8M32S
15
Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command
performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are
turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown
state longer than the refresh period (64ms) since the command does not perform any refresh
operations.
16
Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from
the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. tPDE (min.) is required when the device exits from the PowerDown mode. Any subsequent
commands can be issued after one clock cycle from the end of this command.
17
Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the
input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also
used for device selection, byte selection and bus control in a memory system.
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AS4C8M32S
Table 10. Absolute Maximum Rating
Symbol
Item
Rating
VIN, VOUT
Input, Output Voltage
- 1.0 ~ 4.6
V
1
VDD, VDDQ
Power Supply Voltage
-1.0 ~ 4.6
V
1
Commercial
0 ~ 70
°C
1
Industrial
-40 ~ 85
°C
1
TA
Ambient Temperature
Unit Note
TSTG
Storage Temperature
- 55 ~ 125
°C
1
TSOLDER
Soldering Temperature (10 second)
260
°C
1
PD
Power Dissipation
1
W
1
IOS
Short Circuit Output Current
50
mA
1
Table 11. Recommended D.C. Operating Conditions (TA = -40~85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit Note
VDD
Power Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
Power Supply Voltage(for I/O Buffer)
3.0
3.3
3.6
V
2
VIH
LVTTL Input High Voltage
2.0
3.0
VDDQ +0.3
V
2
VIL
LVTTL Input Low Voltage
- 0.3
0
0.8
V
2
IIL
Input Leakage Current
( 0V VIN VDD, All other pins not under test = 0V )
- 10
－
10
A
IOL
Output Leakage Current
Output disable, 0V VOUT VDDQ)
- 10
－
10
A
VOH
LVTTL Output "H" Level Voltage
( IOUT = -2mA )
2.4
－
－
V
VOL
LVTTL Output "L" Level Voltage
( IOUT = 2mA )
－
－
0.4
V
Table 12. Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol
CI
CI/O
Parameter
Min.
Max.
Unit
Input Capacitance
4
10
pF
Input/Output Capacitance
4
6.5
pF
Note: These parameters are periodically sampled and are not 100% tested.
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AS4C8M32S
Table 13. D.C. Characteristics (VDD = 3.3V 0.3V, TA = -40~85°C)
Description/Test condition
Symbol
Operating Current
tRC tRC(min), Outputs Open
One bank active
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# VIH(min), CKE VIH
Input signals are changed every 2clks
Precharge Standby Current in non-power down mode
tCK = , CLK VIL(max), CKE VIH
Precharge Standby Current in power down mode
tCK = 15ns, CKE VIL(max)
Precharge Standby Current in power down mode
tCK = , CKE VIL(max)
Active Standby Current in non-power down mode
tCK = 15ns, CKE VIH(min), CS# VIH(min)
Input signals are changed every 2clks
Active Standby Current in non-power down mode
CKE VIH(min), CLK VIL(max), tCK =
Operating Current (Burst mode)
tCK =tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
tRC tRC(min)
Self Refresh Current
CKE 0.2V ; for other inputs VIH≧VDD - 0.2V, VIL 0.2V
Alliance Memory Confidential
19
-6
- 75
Max.
Unit Note
3
IDD1
240
220
IDD2N
40
40
IDD2NS
30
30
IDD2P
12
12
IDD2PS
12
12
IDD3N
60
60
IDD3NS
50
50
IDD4
280
260
3, 4
IDD5
400
400
3
IDD6
12
12
mA
Rev. 2.0 May /2014
AS4C8M32S
Table 14. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)
Symbol
tRC
tRCD
tRP
tRRD
tRAS
-6
A.C. Parameter
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
-75
Min.
Max.
Min.
Max.
60
-
67.5
-
18
-
22.5
-
18
-
22.5
-
12
-
15
-
42
100k
45
100k
Unit Note
ns
tWR
Write recovery time
2
-
2
-
tCCD
CAS# to CAS# Delay time
1
-
1
-
tCK
Clock cycle time
CL* = 2
9
-
10
-
CL* = 3
6
-
7.5
-
tCH
Clock high time
2.5
-
2.5
tCL
Clock low time
2.5
-
2.5
-
tAC
Access time from CLK
(positive edge)
CL* = 2
-
6
-
6
CL* = 3
-
5
-
5.4
tOH
Data output hold time
2
-
2
-
tLZ
Data output low impedance
1
-
1
-
tHZ
Data output high impedance
-
5
-
5.4
8
tIS
Data/Address/Control Input set-up time
2
-
2
-
10
tIH
Data/Address/Control Input hold time
1
-
1
-
10
tPDE
Power Down Exit set-up time
tIS+ tCK
-
tIS+ tCK
-
tREFI
Average Refresh Interval Time
-
15.6
-
15.6
s
tDAL
Last data in to active latency
5
-
5
-
tCK
tXSR
Exit Self Refresh to Read Command time
tIS+ tRC
-
tIS+ tRC
-
ns
tCK
9
10
10
10
ns
9
* CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.0V for pulse
width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
Alliance Memory Confidential
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Rev. 2.0 May /2014
AS4C8M32S
Table 15. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2KΩ
Output
Output
30pF
Z0=50Ω
870Ω
Figure 18.1 LVTTL D.C. Test Load (A)
30pF
Figure 18.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a
fixed slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR & tF) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 s, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command.
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AS4C8M32S
Timing Waveforms
Figure 19. AC Parameters for Write Timing (Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCL
tCH
CKE
tIS
tIH
tIS
Begin Auto
Precharge Bank A
Begin Auto
Precharge Bank B
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10
tI
A0-A9,
A11
RAx
RBx
RAy
S
CAx
RAx
RBx
CBx
CAy
RAy
DQM
tRCD
DQ
Hi-Z
tRC
Ax0 Ax1 Ax2
Activate
Command
Bank A
Ax3
Write with
Activate
Auto PrechargeCommand
Command
Bank B
Bank A
Alliance Memory Confidential
tDAL
Bx0 Bx1
tIS
Bx2
Bx3
Write with
Activate
Auto Precharge Command
Command
Bank A
Bank B
22
tIH
tWR
Ay0 Ay1 Ay2 Ay3
Write
Command
Bank A
Precharge
Command
Bank A
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 20. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
CLK
T1
T2
T3
T4
T5
T6
T8
T7
T9
T10
T11
T12
T13
T14
T15
T16
tCH tCL
tIS
CKE
tIS
Begin Auto
Precharge Bank B
tIH
tIH
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10
RAx
RBx
RAy
tIS
A0-A9,
A11
RAx
CAx
CBx
RBx
tRRD
tRAS
RAy
tRC
DQM
DQ
Hi-Z
tAC
tLZ
tRCD
Activate
Command
Bank A
Alliance Memory Confidential
Read
Command
Bank A
tRP
tHZ
Ax0
Ax1
tOH
Activate
Command
Bank B
23
Bx0
Bx1
tHZ
Read with
Precharge
Auto Precharge Command
Command
Bank A
Bank B
Activate
Command
Bank A
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
tRP
DQM
tRCD
tRC
tRC
CAx
DQ
Ax0
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Ax1
Read
Command
Bank A
Don’t Care
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AS4C8M32S
Figure 22. Power on Sequence and Auto Refresh
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
Is reguired
Minimum for 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
tMRD
Hi-Z
Precharge All
Command
Inputs must be
Stable for
200μs
Mode Register
Set Command
1st Auto Refresh(*)
Command
2nd Auto Refresh(*)
Command
Any
Command
Don’t Care
Note(*): The Auto Refresh command can be issue before or after Mode Register Set command
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AS4C8M32S
Figure 23. Self Refresh Entry & Exit Cycle
T0
T2
T1
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
*Note 1
*Note 2
CKE
CS#
tXSR
*Note 5
*Note 3, 4
tIS tIH
*Note 8
tPDE
*Note 6
*Note 7
tIS
RAS#
*Note 9
CAS#
BA0,1
A0-A9,
A11
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
Auto Refresh
Don’t Care
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
5.
6.
7.
8.
9.
To Exit SelfRefresh Mode
System clock restart and be stable before returning CKE high.
Enable CKE and CKE should be set high for valid setup time and hold time.
CS# starts from high.
Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
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Rev. 2.0 May /2014
AS4C8M32S
Figure 24.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
tHZ
DQ
Hi-Z
Ax0
Activate
Cammand
Bank A
Read
Command
Bank A
Ax1
Clock Suspend
1 Cycle
Alliance Memory Confidential
Ax2
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Don’t Care
27
Rev. 2.0 May /2014
AS4C8M32S
Figure 24.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
tHZ
DQ
Hi-Z
Ax0
Activate
Cammand
Bank A
Read
Command
Bank A
Alliance Memory Confidential
Ax1
Ax2
Clock Suspend Clock Suspend
2 Cycles
1 Cycle
28
Ax3
Clock Suspend
3 Cycles
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 25. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Activate
Cammand
Bank A
DAx1
DAx2
Clock Suspend Clock Suspend
2 Cycles
1 Cycle
DAx3
Clock Suspend
3 Cycles
Don’t Care
Write
Command
Bank A
Alliance Memory Confidential
29
Rev. 2.0 May /2014
AS4C8M32S
Figure 26. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tPDE
tIH tIS
CKE
Valid
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
tHZ
DQ
Hi-Z
Ax2
Ax0 Ax1
ACTIVE
STANDBY
Activate
Cammand
Bank A
Power Down
Mode Entry
Read
Command
Bank A
Power Down
Mode Exit
Ax3
Clock Suspension Clock Suspension Precharge
Command
End
Start
Bank A
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Commad
Power Down
Mode Entry
Don’t Care
Alliance Memory Confidential
30
Rev. 2.0 May /2014
AS4C8M32S
Figure 27.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAw
A0-A9,
A11
RAw
RAz
CAx
CAw
RAz
CAy
CAz
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1
Activate
Cammand
Bank A
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Az0
Ay0 Ay1 Ay2 Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
Alliance Memory Confidential
31
Rev. 2.0 May /2014
AS4C8M32S
Figure 27.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAw
A0-A9,
A11
RAw
RAz
CAw
CAx
RAz
CAy
CAz
DQM
DQ Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Cammand
Bank A
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
Alliance Memory Confidential
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Rev. 2.0 May /2014
AS4C8M32S
Figure 28. Random Column Write (Page within same Bank)
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBw
A0-A9,
A11
RBw
RBz
CBw
CBx
RBz
CBy
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Cammand
Bank B
Write
Command
Bank B
Write
Write
Command Command
Bank B
Bank B
DBz0 DBz1
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Don’t Care
Alliance Memory Confidential
33
Rev. 2.0 May /2014
AS4C8M32S
Figure 29.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
CLK
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
RBx
RBx
tRCD
RAx
CBx
RBy
RAx
CBy
RBy
CAx
tAC
tRP
DQM
DQ Hi-Z
Activate
Cammand
Bank B
Bx0 Bx1 Bx2
Read
Command
Bank B
Alliance Memory Confidential
Bx3
Bx4
Bx5 Bx6 Bx7
Ax0 Ax1 Ax2 Ax3
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank A
34
Ax4 Ax5
Ax6 Ax7
Activate
Command
Bank B
Read
Command
Bank B
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 29.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBx
A0-A9,
A11
RBx
RAx
CBx
RAx
RBy
CAx
tAC
tRCD
RBy
CBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Read
Command
Bank B
Activate
Command
Bank A
Precharge
Read
Command Command
Bank B
Bank A
Activate
Command
Bank B
Read
Precharge
Command Command
Bank B
Bank A
Don’t Care
Alliance Memory Confidential
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Rev. 2.0 May /2014
AS4C8M32S
Figure 30. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBx
RAy
CBx
tWR*
tRCD
RAy
tRP
CAy
tWR*
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Precharge
Command Command
Bank A
Bank B
Don’t Care
* tWR > tWR (min.)
Alliance Memory Confidential
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Rev. 2.0 May /2014
AS4C8M32S
Figure 31.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAy
CAx
CAz
DQM
DQ
Hi-Z
Ax0 Ax1
Activate
Cammand
Bank A
Read
Command
Bank A
Ax2 Ax3
DAy0 DAy1
DAy3
Write
The Write Data
Command is Masked with a
Bank A
Zero Clock
Latency
Az0
Read
Command
Bank A
Az3
Az1
The Read Data
is Masked with a
Two Clock
Latency
Don’t Care
Alliance Memory Confidential
37
Rev. 2.0 May /2014
AS4C8M32S
Figure 31.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAy
CAx
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Cammand
Bank A
Ax1 Ax2
Ax3
DAy0 DAy1
Az0
DAy3
Write
The Write Data
Command is Masked with a
Bank A
Zero Clock
Read
Command
Bank A
Latency
Read
Command
Bank A
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Don’t Care
Alliance Memory Confidential
38
Rev. 2.0 May /2014
AS4C8M32S
Figure 32.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12 T13 T14 T15 T16 T17 T18 T19T20 T21 T22
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
RAx
RAx
RBx
RAx
RBx
CAy
tRCD
DQ Hi-Z
CBw
CBy
CAy
CBz
tAC
Ax0 Ax1 Ax2 Ax3
Activate
Cammand
Bank A
CBx
Activate
Read
Command Command
Bank B
Bank A
Read
Command
Bank B
Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3
Read
Read
Read
Read
Command CommandCommand Command
Bank B Bank A Bank B
Bank B
Precharge
Precharge
Command
Bank B
Command
Bank A
Don’t Care
Alliance Memory Confidential
39
Rev. 2.0 May /2014
AS4C8M32S
Figure 32.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
RBx
CBx
Hi-Z
Activate
Cammand
Bank A
CBy
CBz
Ax0 Ax1 Ax2 Ax3
Bx0 Bx1
CAy
tAC
tRCD
DQM
DQ
RBx
Read
Command
Bank A
Activate
Command
Bank B
Alliance Memory Confidential
By0
Read
Read
Read
Command Command Command
Bank B
Bank B
Bank B
By1 Bz0
Bz1 Ay0
Read
Precharge
Command Command
Bank A
Bank B
Ay1 Ay2
Ay3
Precharge
Command
Bank A
Don’t Care
40
Rev. 2.0 May /2014
AS4C8M32S
Figure 33. Interleaved Column Write Cycle (Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBw
A0-A9,
A11
RAx
CAx RBw
CBw
CBx
tRCD
Hi-Z
CAy
CBz
tWR
tWR
DQM
DQ
CBy
tRRD>tRRD(min)
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Cammand
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write
Write
Write
Write
Write
Command Command Command CommandCommand
Bank B Bank B Bank B Bank A Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Don’t Care
Alliance Memory Confidential
41
Rev. 2.0 May /2014
AS4C8M32S
Figure 34.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBy
RBx
CBx
RAy
RBy
CBy
RAz
tRP
DQM
DQ
RAz
Hi-Z
Activate
Cammand
Bank A
Ax0 Ax1 Ax2
Activate
Read
Command Command
Bank B
Bank A
Ax3
Bx0
Bx1
Bx2 Bx3 Ay0
Ay1
Ay2 Ay3
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
By0
By1
By2
Activate
Command
Bank A
Read with
Auto Precharge
Command
Bank B
Don’t Care
Alliance Memory Confidential
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Rev. 2.0 May /2014
AS4C8M32S
Figure 34.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBy
RBx
CBx
CAy
RBy
CBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Read
Command
Bank A Activate
Command
Bank B
Alliance Memory Confidential
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
By0 By1 By2
Read with
Auto Precharge
Command
Bank B
Don’t Care
43
Rev. 2.0 May /2014
AS4C8M32S
Figure 35. Auto Precharge after Write Burst (Burst Length=4)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBx
RBy
CBx
CAy
RBy
CBy
tDAL
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank B
Write
Command
Bank A
Alliance Memory Confidential
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
DBy0 DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
Don’t Care
44
Rev. 2.0 May /2014
AS4C8M32S
Figure 36.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBy
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax
Read
Activate
Command Cammand
Bank A
Bank B
Ax+1
Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6
Read
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Alliance Memory Confidential
Precharge
Command
Bank B
45
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 36.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16 T17 T18 T19T20 T21 T22
CLK
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBy
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Read
Read
Activate
Command
Command Cammand
Bank B
Bank A Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is
satisfied; the burst counter increments
and continues bursting beginning with
the starting address
Alliance Memory Confidential
46
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 37. Full Page Write Cycle (Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBy
CBx
RBx
RBy
DQM
DQ Hi-Z
Activate
Cammand
Bank A
Data is ignored
DAx
DAx+1 DAx+2 DAx+3 DAx-1
Write
Activate
Command Cammand
Bank A Bank B
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Write
Command
Bank B
Precharge
Command
Bank B
Burst Stop
The burst counter wraps
Command
from the highest order
page address back to zero Full Page burst operation does not
during this time interval terminate when the burst length is
satisfied; the burst counter increments
and continues bursting beginning with
the starting address
Alliance Memory Confidential
47
Activate
Command
Bank B
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 38. Byte Read and Write Operation (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAy
CAx
CAz
DQM m
DQM n
DQ M
Ax0 Ax1 Ax2
DQ N
Ax1 Ax2 Ax3
Activate
Cammand
Bank A
Read
Command
Bank A
Upper Byte
is masked
DAy1 DAy2
DAy0 DAy1
Upper Byte
Lower Byte Write
is masked Command is masked
Bank A
Read
Command
Bank A
Az2
Az1
Az2
Lower Byte
is masked
Az3
Lower Byte
is masked
Don’t Care
Note : M represent DQ in the byte m; N represent DQ in the byte n.
Alliance Memory Confidential
Az0
DAy3
Az1
48
Rev. 2.0 May /2014
AS4C8M32S
Figure 39. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency=2)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE High
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
RBu
RBu
RAu
CBu
RAv
RBv
CAu
RAu
RBv
CBv
DQ
Bu0
Activate
Command
Bank B
Bu1
Activate
Command
Bank A
Read
Bank B
with Auto
Precharge
Alliance Memory Confidential
Bu2
Bu3
Read
Bank A
with Auto
Precharge
RAv
CAv
tRP
tRP
DQM
RBw
Au0
Au1
Au2
Activate
Command
Bank B
49
RBw
tRP
Au
3
Bv0
Activate
Command
Bank A
Read
Bank B
with Auto
Precharge
Bv1
Bv2
Bv3
Read
Bank A
with Auto
Precharge
Av
0
Av1
Av
2
Av3
Activate
Command
Bank B
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 40. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
RAx
RBx
RAx
RBx
RBw
CAx
CBx CAy
CBy
CAz
RBw
CBz
tRP
DQM
tRRD
DQ
Hi-Z
tRCD
Ax0 Ax1 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Activate
Cammand
Bank A
Read
Activate
Read
Read
Command
Command
Command Command
Bank B
Bank B
Bank B
Bank A
Read
Read
Command
Command
Bank A
Bank A
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50
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 41. Full Page Random Column Write (Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
A0-A9,
A11
RAx
RBx CAx
RBw
CBx CAy
CBy
CAz
RBw
CBz
tWR
tRP
DQM
DQ
Hi-Z
tRRD
tRCD
DAx0 DAx1 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate Activate
Write
Write
Write
Cammand Command
Command
Command Command
Bank A
Bank B
Bank B
Bank B Bank A
Write
Write
Command
Command
Bank A
Bank A
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Write
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Write Data
are masked
Activate
Command
Bank B
Don’t Care
Rev. 2.0 May /2014
AS4C8M32S
Figure 42. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0
CLK
CKE
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RAy
RAz
RAy
CAx
tWR
CAy
tRP
RAz
tRP
DQM
DQ
Ay0 Ay1 Ay2
DAx0 DAx1
Activate
Cammand
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Write Burst
Write Data are masked
Alliance Memory Confidential
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Read Burst
Don’t Care
52
Rev. 2.0 May /2014
AS4C8M32S
Figure 43. 90-Ball (8.0mm x13mmx1.4mm) TFBGA
Units in mm
PIN #1
Top View
Bottom View
Side View
DETAIL : "A"
Symbol
A
A1
A2
C
D
E
D1
E1
e
b
F
Dimension in inch
Dimension in mm
Min
Nom Max
Min
Nom Max
--0.055
--1.40
0.012 0.014 0.016 0.30 0.35 0.40
0.033 0.035 0.037 0.84 0.89 0.94
0.013 0.014 0.016 0.32 0.36
0.4
0.311 0.315 0.319 7.90 8.00 8.10
0.508 0.512 0.516 12.90 13.00 13.10
-0.252
--6.40
--0.441
--11.2
--0.031
--0.80
-0.016 0.018 0.020 0.40 0.45 0.50
-0.126
--3.2
--
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Rev. 2.0 May /2014