ON NVD3055-150T4G Power mosfet Datasheet

NTD3055-150,
NVD3055-150
Power MOSFET
9.0 A, 60 V, N−Channel DPAK/IPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
• NVD Prefix for Automotive and Other Applications Requiring
•
9.0 AMPERES, 60 VOLTS
RDS(on) = 122 mW (Typ)
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
D
N−Channel
Typical Applications
•
•
•
•
http://onsemi.com
G
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
S
4
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 10 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tpv10 ms)
VGS
VGS
"20
"30
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Vdc
IDM
9.0
3.0
27
Apk
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
PD
28.8
0.19
2.1
1.5
W
W/°C
W
W
Operating and Storage Temperature Range
TJ, Tstg
−55 to 175
°C
EAS
30
mJ
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
L = 1.0 mH, IL(pk) = 7.75 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
°C/W
RqJC
RqJA
RqJA
5.2
71.4
100
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using minimum recommended
pad size.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 6
3
DPAK
CASE 369C
(SURFACE MOUNT)
STYLE 2
1
2
3
IPAK
CASE 369D
(STRAIGHT LEAD)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Adc
ID
ID
1
1 2
4
Drain
4
Drain
2
1
3
Drain
Gate
Source
A
3150
Y
WW
G
3150G
Unit
AYWW
Value
3150G
Symbol
AYWW
Rating
1 2 3
Gate Drain Source
= Assembly Location*
= Device Code
= Year
= Work Week
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTD3055−150/D
NTD3055−150, NVD3055−150
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
60
−
−
70.2
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
3.0
6.4
4.0
−
−
122
150
−
−
1.4
1.1
1.9
−
gFS
−
5.4
−
mhos
Ciss
−
200
280
pF
Coss
−
70
100
Crss
−
26
40
td(on)
−
11.2
25
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 4.5 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 3)
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc)
Vdc
mV/°C
mW
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 48 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc,
RG = 9.1 W) (Note 3)
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc) (Note 3)
ns
tr
−
37.1
80
td(off)
−
12.2
25
tf
−
23
50
QT
−
7.1
15
Q1
−
1.7
−
Q2
−
3.5
−
VSD
−
−
0.98
0.86
1.20
−
Vdc
trr
−
28.9
−
ns
ta
−
21.6
−
tb
−
7.3
−
QRR
−
0.036
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 9.0 Adc, VGS = 0 Vdc) (Note 3)
(IS = 19 Adc, VGS = 0 Vdc, TJ =
150°C)
Reverse Recovery Time
(IS = 9.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge
mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
NTD3055−150, NVD3055−150
20
VGS = 10 V
16
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
20
VGS = 9 V
VGS = 7 V
VGS = 8 V
12
8
VGS = 6 V
4
VGS = 5 V
1
2
3
4
5
6
7
12
8
TJ = 25°C
4
TJ = 100°C
8
TJ = −55°C
3
6
7
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.5
VGS = 10 V
0.4
TJ = 100°C
0.3
0.2
TJ = 25°C
TJ = −55°C
0.1
0
0
4
8
12
20
16
24
9
0.5
VGS = 15 V
0.4
0.3
TJ = 100°C
0.2
TJ = 25°C
0.1
TJ = −55°C
0
0
4
8
12
16
20
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
24
1000
2.2
2
5
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
VGS = 0 V
ID = 4.5 A
VGS = 10 V
TJ = 150°C
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
16
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
VDS ≥ 10 V
1.6
1.4
1.2
1
100
TJ = 125°C
10
TJ = 100°C
0.8
0.6
−50 −25
1
0
25
50
75
100
125
150
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
http://onsemi.com
3
60
560
VDS = 0 V
C, CAPACITANCE (pF)
480
VGS = 0 V
VGS, GATE−TO−SOURCE VOLTAGE (V)
NTD3055−150, NVD3055−150
TJ = 25°C
Ciss
400
320
Crss
240
Ciss
160
Coss
80
Crss
0
5 VGS 0 VDS 5
10
15
10
20
12
QT
10
8
6
4
ID = 9 A
TJ = 25°C
2
0
0
25
2
1
3
4
5
7
6
8
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
100
10
IS, SOURCE CURRENT (AMPS)
VDS = 30 V
ID = 9 A
VGS = 10 V
t, TIME (ns)
tr
tf
td(off)
td(on)
VGS = 0 V
TJ = 25°C
8
6
4
2
0
10
1
10
0.6
100
0.68
0.76
0.84
0.92
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
10 ms
100 ms
1 ms
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
dc
10
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
RG, GATE RESISTANCE (W)
100
ID, DRAIN CURRENT (AMPS)
VGS
Q2
Q1
1
32
ID = 7.75 A
24
16
8
0
25
50
75
100
125
150
175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
http://onsemi.com
4
NTD3055−150, NVD3055−150
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
10
D = 0.5
0.2
1
0.1
P(pk)
0.05
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.1
0.0001
0.00001
0.001
0.01
t, TIME (s)
0.1
1
10
Figure 13. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD3055−150G
DPAK
(Pb−Free)
75 Units / Rail
NTD3055−150−1G
IPAK
(Pb−Free)
75 Units / Rail
NTD3055−150T4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD3055−150T4H
DPAK
(Halide−Free)
2500 / Tape & Reel
NVD3055−150T4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
http://onsemi.com
5
NTD3055−150, NVD3055−150
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE E
A
E
C
A
b3
B
c2
4
L3
D
1
2
Z
Z
H
DETAIL A
3
L4
NOTE 7
b2
e
b
TOP VIEW
c
SIDE VIEW
0.005 (0.13)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
BOTTOM VIEW
BOTTOM VIEW
ALTERNATE
CONSTRUCTION
C
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
SEATING
PLANE
A1
ROTATED 905 CW
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
NTD3055−150, NVD3055−150
PACKAGE DIMENSIONS
IPAK
CASE 369D
ISSUE C
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
3 PL
0.13 (0.005)
M
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTD3055−150/D
Similar pages