LM98640QML LM98640QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output Literature Number: SNAS461B LM98640QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output General Description Features The LM98640QML is a fully integrated, high performance 14Bit, 5 MSPS to 40 MSPS signal processing solution for image processing applications. The LM98640QML is Radiation tolerant up to a total ionizing dose of 100krads allowing it to be used in space imaging applications. Configuration Registers are Single Event Functional Interrupt Free up to 120 MeVcm2/mg. The Serial LVDS Output format performs well during ionizing doses, preventing data loss. The LM98640QML has an adaptive power scaling feature to optimize power consumption based on the operating frequency and amount of gain required. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for Contact Image Sensors and CMOS image sensors). The sampling edges are programmable to a resolution of 1/64th of a pixel period. Both the CDS and S/H have a programmable gain of either 0dB or 6dB. The signal paths utilize two ±8 bit offset correction DACs for coarse and fine offset correction, and 8 bit Programmable Gain Amplifiers (PGA) for each channel. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each input. The signals are then routed to two on chip 14-bit 40MHz high performance analog-to-digital converters (ADC). The fully differential processing channel provides exceptional noise immunity, having a very low noise floor of -79dB with a gain of 1x. The 14-bit ADCs have excellent dynamic performance making the LM98640QML transparent in the image reproduction chain. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ ■ Focal Plane Electronics Imaging Attitude Control Systems Assembly Line Vision Systems Factory Automation Vision Systems High-speed Document Scanner Multi- Function Peripherals Total Ionizing Dose 100 krad(Si) Single Event Latch-Up free up to 120 MeV-cm2/mg SEFI free up to 120 MeV-cm2/mg Seialized LVDS Outputs LVDS Input Clock CDS or S/H Processing for CCD or CIS sensors Programmable Analog Gain for Each Channel Programmable Analog Offset Correction Programmable Input Clamp Voltage Programmable Sampling Edge up to 1/64th pixel period Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Input Level 2.85 Volts ADC Resolution 14-Bit ADC Sampling Rate 5MSPS to 40 MSPS INL @ 15MHz ±3.5 LSB CDS or S/H Gain 0dB or 6dB PGA Gain Steps 256 Steps PGA Gain Range -3dB to 18dB Coarse DAC Resolution ±8 Bits Coarse DAC Range ±250mV Fine DAC Resolution ±8 Bits Fine DAC Range ±5mV Noise Floor -79dB Crosstalk -80dB Power Consumption PGA 1-4x Gain 125 mW per channel (15MSPS) 140 mW per channel (25MSPS) PGA 1-8x Gain 125 mW per channel (15MSPS) 178 mW per channel (40MSPS) Operating Temp -55 to 125°C Supply Voltages 3.3V Nominal (3.15V to 3.45V range) 1.8V Nominal (1.7V to 1.9V range) Ordering Information NS Part Number SMD Part Number NS Package Number Package Description LM98640W-MLS Flight Part TBD EL68D 68 Pin Ceramic QFP EL68D 68 Pin Ceramic QFP LM98640W-MPR Pre-flight Prototype LM98640CVAL Ceramic Evaluation Board © 2011 National Semiconductor Corporation 68 Pin Ceramic QFP on Evaluation Board 300647 www.national.com LM98640QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output January 13, 2011 FIGURE 1. Chip Block Diagram 30064701 LM98640QML LM98640QML Overall Chip Block Diagram www.national.com 2 LM98640QML LM98640QML Pin Out Diagram 30064702 FIGURE 2. LM98640QML Pin Out Diagram 3 www.national.com LM98640QML System Block Diagram 30064770 FIGURE 3. TYPICAL CCD SYSTEM www.national.com 4 5 FIGURE 4. Typical Sample/Hold Mode Application Diagram 30064773 LM98640QML Typical Application Diagram www.national.com LM98640QML Pin Descriptions Pin Name 1 VCOM1 2 I/O Typ Res Description A Common mode of ADC reference. Bypass with 0.1µF capacitor to VSS33. VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 3 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 4 VSS33 P Analog supply return. 5 VSS33 P Analog supply return. 6 OS1- I A Analog input signal. 7 OS1+ I A Sample/Hold Mode Reference Level. Bypassed with a 0.1µF to ground in CDS mode. 8 VSS33 P Analog supply return. 9 VCLP A Programmable Clamp Voltage output. Normally bypassed with a 0.1µF capacitor to VSS33. 10 VSS33 P Analog supply return. 11 OS2+ I A Sample/Hold Mode Reference Level. Bypassed with a 0.1µF to ground in CDS mode. 12 OS2- I A Analog input signal. 13 VSS33 P Analog supply return. 14 VSS33 P Analog supply return. 15 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 16 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 17 VCOM2 O A Common mode of ADC reference. Bypass with 0.1µF capacitor to ground. 18 VREFB2 O A Bottom of ADC reference. Bypass with a 0.1µF capacitor to ground. 19 VREFT2 O A Top of ADC reference. Bypass with a 0.1µF capacitor to ground. 20 VSS33 P Analog supply return. 21 VSS33 P Analog supply return. 22 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 23 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 24 VSS33 P Analog supply return. 25 SDO O D Serial Interface Data Output. (Tri-State when SEN is high) 26 SDI I D 27 SCLK I D PD Serial Interface shift register clock. (Tri-State when SEN is high) 28 SEN I D PU Active-low chip enable for the Serial Interface. 29 NC 30 CLPIN I D Input clamp signal. 31 VSS18 P Digital supply return. 32 VDD18 P Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane. 33 DTM1 O D Digital Timing Monitor. If not used, can be connected to VDD18 through a 10kΩ resistor. 34 DTM0 O D Digital Timing Monitor. If not used, can be connected to VDD18 through a 10kΩ resistor. 35 VDD18 P Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane. 36 VSS18 P Digital supply return. 37 TXFRM+ O D LVDS Frame+ 38 TXFRM- O D LVDS Frame- 39 TXOUT3+ O D LVDS Data Out3+ 40 TXOUT3- O D LVDS Data Out3- 41 TXOUT2+ O D LVDS Data Out2+ 42 TXOUT2- O D LVDS Data Out2- 43 TXOUT1+ O D LVDS Data Out1+ 44 TXOUT1- O D LVDS Data Out1- www.national.com O O Serial Interface Data Input. (Tri-State when SEN is high) No Connection. Can be connected to VSS18. 6 Name I/O Typ Res LM98640QML Pin Description 45 TXOUT0+ O D LVDS Data Out0+ 46 TXOUT0- O D LVDS Data Out0- 47 TXCLK+ O D LVDS Clock+ 48 TXCLK- O D LVDS Clock- 49 VSS18 P Digital supply return. 50 VDD18 P Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane. 51 ATB0 O A Analog Test Bus. If not used, can be connected to VSS18 through a 10kΩ resistor. 52 ATB1 O A Analog Test Bus. If not used, can be connected to VSS18 through a 10kΩ resistor. 53 VDD18 P Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane. 54 VDD18 P Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane. 55 VSS18 P Digital supply return. 56 VSS18 P Digital supply return. 57 INCLK- I D Clock Input. Inverting input for LVDS clocks. 58 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks. 59 VSS33 P Analog supply return. 60 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 61 VDD33 P Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane. 62 VSS33 P Analog supply return. 63 IBIAS0 I A Connect with external 10kΩ 1% resistor to IBIAS1 pin. 64 IBIAS1 I A Connect with external 10kΩ 1% resistor to IBIAS0 pin. 65 VREFBG O A Band gap reference output. Bypass with a 0.1µF capacitor to VSS33. Can be overdriven with external voltage source. 66 VSS33 P Analog supply return. 67 VREFT1 O A Top of ADC reference. Bypass with a 0.1µF capacitor to VSS33. 68 VREFB1 O A Bottom of ADC reference. Bypass with a 0.1µF capacitor to VSS33. P Exposed pad must be soldered to ground plane to ensure rated performance. Exp Pad (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.). 7 www.national.com LM98640QML Thermal Resistance (Note 4) Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage (VDD33) Supply Voltage (VDD18) Voltage on any VDD33 Input Pin (Not to exceed 4.2V) Voltage on any VDD33 Output Pin (Not to exceed 4.2V) Voltage on any VDD18 Input Pin (Not to exceed 2.35V) Voltage on any VDD18 Output Pin (Not to exceed 2.35V) Input Current at any pin other than Supply Pins (Note 3) Package Input Current (except Supply Pins) (Note 3) Maximum Junction Temperature (TA) (θJA) @ 225 LFPM 11.1°C/W (θJA) @ 0 LFPM 16.5°C/W 1.2°C/W (θJC) ESD Rating (Note 5) Human Body Model 2500V Machine Model 250V Storage Temperature -65°C to +150°C Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) 4.2V 2.35V -0.3V to (VDD33 + 0.3V) -0.3V to (VDD33 + 0.3V) -0.3V to (VDD18 + 0.3V) -0.3V to (VDD18 + 0.3V) ±25 mA Operating Ratings Operating Temperature Range ±50 mA VDD33 VDD18 | VSS33 - VSS18 | 150°C (Note 1, Note 2) -55°C ≤ TA ≤ +125°C +3.15V to +3.45V +1.7V to +1.9V ≤100mV Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A www.national.com Subgroup Description Temp (°C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Setting time at +25 13 Setting time at +125 14 Setting time at -55 8 (Note 9) The following specifications apply for VDD33 = 3.3V, VDD18 = 1.8V, CL = 10pF, and fINCLK = 40MHz unless otherwise specified. Symbol Parameter Conditions Notes Typical (Note 8) Min Max Units Subgroups V 1, 2, 3 V 1, 2, 3 CMOS Digital Input DC Specifications (SCLK, SEN, SDI, CLPIN) VIH Logical “1” Input Voltage VIL Logical “0” Input Voltage IIH Logical “1” Input Current VIH = VDD33 IIL Logical “0” Input Current VIL = VSS 2.0 0.8 CLPIN 38 44 μA SCLK, SDI 40 300 nA SEN 21 28 CLPIN -85 -300 nA SCLK, SDI -50 -300 nA SEN -60 -70 μA 1.8 V 1, 2, 3 1, 2, 3 μA 1, 2, 3 CMOS Digital Output DC Specifications (SDO) VOH Logical "1" Output Voltage IOUT = -0.5mA 1.93 VOL Logical "0" Output Voltage IOUT = 1.6mA 0.05 0.2 V 1, 2, 3 IOH Output Leakage Current VOUT = VDD 20 50 nA 1, 2, 3 IOL Output Leakage Current VOUT = VSS -20 nA 1, 2, 3 mV 1, 2, 3 mV 1, 2, 3 -50 LVDS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins) VIHL Differential LVDS Clock RL = 100Ω High Threshold Voltage VCM (LVDS Input Common Mode Voltage) = 1.25V Differential LVDS Clock VILL Low Threshold Voltage RL = 100Ω VCM (LVDS Input Common Mode Voltage) = 1.25V 100 250 -100 -250 275 210 410 mV 1, 2, 3 1.19 1.05 1.3 V 1, 2, 3 325 250 460 mV 1, 2, 3 1.19 1.05 1.3 V 1, 2, 3 LVDS Output Modes = 0000 x110 RL = 100Ω 377 300 535 mV 1, 2, 3 1.1 .95 1.2 V 1, 2, 3 LVDS Output Modes = 0000 x111 RL = 100Ω 425 350 590 mV 1, 2, 3 1.1 0.95 1.2 V 1, 2, 3 5 μA 1, 2, 3 μA 1, 2, 3 LVDS Output DC Specifications VOD Differential Output Voltage LVDS Output Modes = 0000 x100 RL = 100Ω VOS LVDS Output Offset Voltage VOD Differential Output Voltage VOS LVDS Output Offset Voltage VOD Differential Output Voltage VOS LVDS Output Offset Voltage VOD Differential Output Voltage VOS LVDS Output Offset Voltage IOH LVDS Output Leakage Current 4.25 IOL LVDS Output Leakage Current -4.29 LVDS Output Modes = 0000 x101 RL = 100Ω -5 IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω 40 50 mA 1, 2, 3 IIHL Diffferential LVDS Clock Input Current VIH = VDD33 23 36 μA 1, 2, 3 IILL Diffferential LVDS Clock Input Current VIL = VSS -34 μA 1, 2, 3 9 -49 www.national.com LM98640QML LM98640QML Electrical Characteristics LM98640QML Symbol Parameter Conditions Notes Typical (Note 8) Min Max Units Subgroups mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 Power Supply Specifications VDD33 Analog Supply Current Dual Channel Power optimized for PGA Gain = 1-4x VDD33 Analog Supply Current Dual Channel Power optimized for PGA Gain = 1-8x IA VDD33 Analog Supply Current Single Channel Power optimized for PGA Gain = 1-4x VDD33 Analog Supply Current Single Channel Power optimized for PGA Gain = 1-8x VDD33 Analog Supply Current Powerdown VDD18 Digital Supply Current LVDS Quad Lane Mode LVDS Output Mode Reg = 0x0E ID VDD18 Digital Supply Current VDD18 Digital Supply Current Powerdown www.national.com Powerdown Control Reg = 0x00 (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 51.5 58 15MHz 61.3 69 25MHz 69.6 79 40MHz 87.6 98 Powerdown Control Reg = 0x00 (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 51.5 58 15MHz 61.3 68 25MHz 72.9 82 40MHz 91.3 103 5MHz 29.5 35 15MHz 36.1 42 25MHz 42 47 40MHz 53.7 60 5MHz 29.5 35 15MHz 36.1 42 25MHz 43.8 50 40MHz 55.6 64 Powerdown Control Reg = 0x80 2.85 3.85 Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) (see Power Trimming section for PGA and ADC Power Trimming register settings) Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 36 15MHz 39 25MHz 42 mA 40MHz 45 5MHz 23.5 29 15MHz 25.5 31 25MHz 27.5 33 40MHz 30.5 37 Powerdown Control Reg = 0x80 1.2 3.0 10 mA 1, 2, 3 mA 1, 2, 3 PWR PSRR Parameter Average Power Dissipation Power optimized for PGA Gain = 1-4x Dual Channel LVDS Dual Lane Mode Average Power Dissipation Power optimized for PGA Gain = 1-8x Dual Channel LVDS Dual Lane Mode Dynamic Power Supply Rejection Ratio CDS Gain = 1x PGA Gain = 1x Conditions Notes Typical (Note 8) Min Max 5MHz 212 244 15MHz 250 284 25MHz 280 320 40MHz 345 390 5MHz 212 244 15MHz 250 284 25MHz 290 330 40MHz 356 407 200 mVpp, 200 KHz -72.3 200 mVpp, 500 KHz 200 mVpp, 1 MHz 200 mVpp, 1.5 MHz (Note 11) 200 mVpp, 2 MHz Units Subgroups mW 1, 2, 3 mW 1, 2, 3 -72 -71 dB -68 -66 Internal Reference Specifications Reference Voltage (Note 10) 1.218 V Reference Tolerance (chip to chip) (Note 10) ±2 % RREFBG Reference Impedance (Note 10) 20 kΩ VREFTC Temperature Coefficient 25°C to 125°C 80 -55°C to 25°C 50 ppm/° C VREFBG Input Sampling Circuit Specifications VIN Input Voltage Level VRESET Reset Feed Through IIN_SH Sample and Hold Mode Input Leakage Current CDS Gain=1x, PGA Gain=1x 2 CDS Gain=2x, PGA Gain=1x 1 CDS Gain=1x, PGA Gain=0.7x 2.85 1, 2, 3 Vp-p 500 mV CDS Gain = 1x OSX = VDD33 (OSX = VSS) (Note 10) 384 μA CDS Gain = 2x OSX = VDD33 (OSX = VSS) (Note 10) -475 µA CDS Gain = 1x (Note 10) 4 pF (see Figure 10) CDS Gain = 2x (Note 10) 8 pF IIN_CDS CDS Mode Input Leakage Current OSX = VDD33 (OSX = VSS) (Note 10) 300 nA RCLPIN CLPIN Switch Resistance (OSX to VCLP Node in Figure 7) (Note 10) 16 Ω Sample/Hold Mode CSH Equivalent Input Capacitance VCLP Reference Circuit Specification VCLP DAC Resolution 5 5 Bits 1, 2, 3 VCLP DAC Step Size 98 96 102 mV 1, 2, 3 VCLP DAC Voltage Min Output VCLP Control Register = 0110 0000 224 194 298 mV 1, 2, 3 VCLP DAC Voltage Max Output VCLP Control Register = 0111 1101 3.07 2.99 3.11 V 1, 2, 3 VCLP DAC Short Circuit Output Current VCLP Control Register = 011x xxxx 33 VVCLP ISC 11 mA www.national.com LM98640QML Symbol LM98640QML Symbol Parameter Conditions Notes Typical (Note 8) Min Max Units Subgroups Coarse Analog Offset DAC Specifications Resolution Offset Adjustment Range Referred to AFE Input CDS Gain = 1x ±8 Bits Minimum DAC Code = 0x000 -262 -264 -251 Maximum DAC Code = 0x1FF 263 251 266 Minimum DAC Code = 0x000 -131 -132 -126 Maximum DAC Code = 0x1FF 131 126 133 Minimum DAC Code = 0x000 -2146 -2162 -2058 Maximum DAC Code = 0x1FF 2154 2058 2176 DAC Step Size CDS Gain = 1x Input Referred 1 DAC Step Size CDS Gain = 1x Output Referred 8 DNL Differential Non-Linearity CDS Gain = 1x or 2x 40MHz ±0.97 -1.1 1.1 LSB 1, 2, 3 INL Integral Non-Linearity CDS Gain = 1x or 2x 40MHz ±1.5 -2.8 2.80 LSB 1, 2, 3 Minimum DAC Code = 0x000 -4.6 -5.9 -3.1 Maximum DAC Code = 0x1FF 5.3 4.3 6.8 Minimum DAC Code = 0x000 -2.3 -2.9 -1.5 Maximum DAC Code = 0x1FF 2.6 2.1 3.4 Offset Adjustment Range Referred to AFE Input CDS Gain = 2x Offset Adjustment Range Referred to AFE Output mV 1, 2, 3 mV 1, 2, 3 LSB 1, 2, 3 mV LSB Fine Analog Offset DAC Specifications Resolution Offset Adjustment Range Referred to AFE Input CDS Gain = 1x Offset Adjustment Range Referred to AFE Input CDS Gain = 2x ±8 Bits Minimum DAC Code = 0x000 -38 -48 -25 Maximum DAC Code = 0x1FF 43 35 56 DAC Step Size CDS Gain = 1x Input Referred 20 DAC Step Size CDS Gain = 1x Output Referred Offset Adjustment Range Referred to AFE Output mV 1, 2, 3 mV 1, 2, 3 LSB 1, 2, 3 uV 0.16 LSB DNL Differential Non-Linearity ±1 LSB INL Integral Non-Linearity ±2.2 LSB PGA Specifications Gain Resolution Minimum Gain 1, 2, 3 CDS Gain = 1x 8.3 7.92 8.78 V/V 1, 2, 3 CDS Gain = 1x 18.4 17.99 18.88 dB 1, 2, 3 CDS Gain = 1x 0.64 0.62 0.66 V/V 1, 2, 3 CDS Gain = 1x -3.8 -4.15 -3.54 dB 1, 2, 3 1, 2 Gain (V/V) = (180/(277-PGA Code)) Gain (dB) = 20LOG10(180/(277-PGA Code)) PGA Function Minimum PGA Gain Channel Matching Maximum PGA Gain www.national.com Bits (Note 10) Monotonicity Maximum Gain 8 12 99.0 95.2 % 99.0 94.0 % 3 99.0 95.2 % 1, 2 99.0 94.0 % 3 Parameter Conditions Notes Typical (Note 8) Min Max Units Subgroups ADC Specifications VREFT Top of Reference 2.0 V VREFB Bottom of Reference 1.0 V VREFT - VREFB Differential Reference Voltage 1.0 Overrange Output Code 16383 Underrange Output Code 0 V 16383 0 Code 1, 2, 3 Code 1, 2, 3 LSB 1, 2, 3 LSB 1, 2, 3 Full Channel Performance Specifications 5MHz DNL INL Differential Non-Linearity Integral Non-Linearity 0.78 -1.03 1.53 5MHz CDS 1.0 -1.20 2.24 15MHz 0.78 -1.02 1.58 25MHz 0.78 -1.01 1.36 40MHz 0.78 -1.03 1.45 5MHz 1.7 -5.38 4.38 5MHz CDS 1.7 -3.41 5.15 15MHz 1.9 -3.45 3.49 25MHz 2.4 -5.40 6.03 40MHz 6.0 -9.9 5MHz Noise Floor CDS Gain = 1x PGA Gain = FE 15MHz 25MHz 40MHz Noise Floor CDS Gain = 1x PGA Gain = FE Noise Floor CDS Gain = 1x PGA Gain = 61 Channel to Channel Crosstalk -65.0 -62.5 -66.0 -64.6 -66.0 -64.5 -66.0 -64.6 -65.0 -64.3 -66.0 -64.6 -66.5 -65.7 dB dB dB dB 1, 2 3 1, 2 3 1, 2 3 1, 2 3 9.6 9.15 11.9 8.20 9.6 8.20 9.4 8.20 9.45 9.15 10.0 8.20 9.45 7.70 8.5 5MHz -79 -78 dB 1, 2 15MHz -79 -78 dB 1, 2 25MHz -79 -78 dB 1, 2 40MHz -79 -78 dB 1, 2 5MHz 1.8 2.05 LSB 1, 2 15MHz 1.8 2.05 LSB 1, 2 25MHz 1.8 2.05 LSB 1, 2 40MHz 1.8 2.05 LSB 1, 2 dB 4, 5, 6 15MHz 25MHz 40MHz Noise Floor CDS Gain = 1x PGA Gain = 61 -64.6 8.20 5MHz Noise 7.34 -66.0 5MHz -79 -77 15MHz -86 -84 25MHz -79 -77 40MHz -76 -74 13 LSB LSB LSB LSB 1, 2 3 1, 2 3 1, 2 3 1, 2 3 www.national.com LM98640QML Symbol LM98640QML Symbol Parameter CDS Mode Bimodal Offset CDS Gain = 1x PGA Gain = 8x BMD CDS Mode Bimodal Offset CDS Gain = 1x PGA Gain = 1x Conditions 6.0 2.1 6.0 25MHz 2.2 6.0 40MHz 2.3 6.0 5MHz 0.35 1 15MHz 0.29 0.87 25MHz 0.33 0.89 Signal-to-Noise Ratio 25MHz 40MHz 5MHz 15MHz Total Harmonic Distortion 25MHz 40MHz 5MHz 15MHz Spurious-Free Dynamic Range 25MHz 40MHz 5MHz SINAD Signal-to-Noise Plus Distortion Ratio 15MHz 25MHz 40MHz 5MHz 15MHz ENOB Effective Number of Bits 25MHz 40MHz www.national.com Max 2.2 15MHz SFDR Min 5MHz 5MHz THD Typical (Note 8) 15MHz 40MHz SNR Notes 14 0.4 Units Subgroups mV 1, 2, 3 mV 1, 2, 3 1.05 67.4 66.0 64.2 63.0 68.0 66.6 64.2 63.0 68.5 66.7 64.2 63.0 68.5 66.5 64.0 62.0 dB dB dB dB -71.4 -69.0 -69.9 -67.8 -75.1 -73.1 -73.9 -71.8 -68.9 -66.8 -68.2 -66.2 -62.0 -60.0 -62.0 -60.0 71.5 69.4 70.4 68.4 76.0 74.0 76.0 74.0 69.0 67.0 69.0 67.0 62.0 60.0 62.0 60.0 67.0 65.0 64.5 62.0 68.0 66.0 64.5 62.5 66.0 64.0 64.5 62.5 61.0 59.0 60.5 59.0 10.8 10.5 10.4 10.0 11.0 10.7 10.4 10.1 10.7 10.3 10.4 10.1 9.8 9.5 9.8 9.5 dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 4, 5 6 The following specifications apply for VDD33 = 3.3V, VDD18 = 1.8V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Symbol Parameter Conditions Notes Typical (Note 8) Units Subgroups Min Max 5 40 40/60 60/40 % 10 TADC 6.44 7.50 ns 9, 10, 11 0.69 1.91 ns 9, 10, 11 0.89 4.0 ns 9, 10, 11 0.63 2.00 ns 9, 10, 11 0.53 1.60 ns 9, 10, 11 Input Clock Timing Specifications fINCLK Input Clock Frequency Tdc Input Clock Duty Cycle INCLK = ADCCLK (ADC Rate Clock) 50/50 MHz 9, 10, 11 9, 10, 11 Full Channel Latency Specifications tLAT (Note 10) Pipeline Latency LVDS Output Timing Specifications tDOD Data Output Delay tDSO Dual Lane Mode Odd Data Setup tDSE Dual Lane Mode Even Data Setup tQSR Quad Lane Mode Data to Rising Clock Setup tQHF Quad Lane Mode Falling Clock to Data Hold fINCLK = 40MHz INCLK = ADCCLK (ADC Rate Clock) LVDS Output Specifications not tested in production. Min/ Max guaranteed by design, characterization and statistical analysis. Serial Interface Timing Specifications fSCLK <= fINCLK fSCLK tIH Input Clock Frequency INCLK = ADCCLK (ADC Rate Clock) 1 20 60/40 MHz 9, 10, 11 SCLK Duty Cycle 50/50 40/60 ns 9, 10, 11 Input Hold Time 1 2.5 ns 9, 10, 11 tIS Input Setup Time 1 2.5 ns 9, 10, 11 tSENSC SCLK Start Time After SEN Low 1 1.5 ns 9, 10, 11 tSCSEN SEN High after last SCLK Rising Edge 2 2.5 ns 9, 10, 11 8 ns 9, 10, 11 ns 9, 10, 11 tSENW SEN Pulse Width 6 tOD Output Delay Time 10.54 11.6 tHZ Data Output to High Z 1.2 1.23 15 TSCLK 9, 10, 11 www.national.com LM98640QML AC Timing Specifications LM98640QML Operating Life Test Delta Parameters TA @ 25°C Symbol Parameter VDD33 Analog Supply Current Dual Channel Power optimized for PGA Gain = 1-4x (Note 12) Conditions Min Max Units ±2 mA ±2 mA ±2 mA ±2 mA ±1 mA ±1 mA ±1 mA Powerdown Control Reg = 0x00 (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 15MHz 25MHz 40MHz VDD33 Analog Supply Current Dual Channel Power optimized for PGA Gain = 1-8x Powerdown Control Reg = 0x00 (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 15MHz 25MHz 40MHz IA VDD33 Analog Supply Current Single Channel Power optimized for PGA Gain = 1-4x Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 15MHz 25MHz 40MHz VDD33 Analog Supply Current Single Channel Power optimized for PGA Gain = 1-8x Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) (see Power Trimming section for PGA and ADC Power Trimming register settings) 5MHz 15MHz 25MHz 40MHz VDD33 Analog Supply Current Powerdown Powerdown Control Reg = 0x80 5MHz 15MHz VDD18 Digital Supply Current 25MHz ID 40MHz VDD18 Digital Supply Current Powerdown www.national.com Powerdown Control Reg = 0x80 16 Note 2: All voltages are measured with respect to VSS = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < VSS or VIN > VDD33), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per note 3. However, input errors will be generated If the input goes above VDD33 and below VSS. 30064771 Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 9: Pre and post irradiation are idential to those listed in the “DC” and “AC” Parametric Electrical Characteristics, except that they are tested at room. Note 10: This Parameter is guaranteed by design and/or characterization and is not tested. Note 11: Dynamic Power Supply Rejection Ratio is performed by injecting a 200mVpp sine wave ac coupled to the analog supply pin. The LM98640's inputs are left floating in CDS mode and an FFT is captured. The spur guaranteed by the injected signal is recorded. Note 12: These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are required. 17 www.national.com LM98640QML Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. LM98640QML Typical Performance Characteristics TA = 25°C, FS = 15MHz, PGA Gain = 1x, CDS Gain = 1x, Dual Lane Output Mode, FIN = 7.48MHz unless otherwise stated. DNL vs Output Code INL vs Output Code 30064715 30064716 DNL vs Voltage INL vs Voltage 30064717 30064718 SNR, SFDR and SINAD vs FS SNR, SFDR and SINAD vs Temperature 30064720 30064719 www.national.com 18 LM98640QML SNR, SFDR and SINAD vs Voltage THD and Noise vs FS 30064721 30064722 THD and Noise vs Temperature THD and Noise vs Voltage 30064723 30064724 Power vs FS Dynamic PSRR vs Power Supply Frequency 30064726 30064725 19 www.national.com LM98640QML matched, these are described in the Input Bias and Clamping section. To place the LM98640QML in Sample & Hold Mode from power up, first write the baseline configuration to the registers as shown in the Configuration Registers section. This configuration has Sample & Hold mode enabled by default. Next, the SAMPLE pulse must be properly positioned over the input signal using the CLAMP/SAMPLE Adjust. System Overview Introduction The LM98640QML is a 14-bit, 5MSPS to 40MSPS, dual channel, complete Analog Front End (AFE) for digital imaging applications. The system block diagram of the LM98640QML, shown in Figure 4 highlights the main features of the device. Each input has its own Input Bias and Clamping Network and Correlated Double Sample (CDS) amplifier (which can also be configure to operate in Sample/Hold Mode). Two +/-8Bit Offset DACs apply independent coarse and fine offset correction for each channel. A -3 to 18dB Programmable Gain Amplifier (PGA) applies independent gain correction for each channel. The signals are digitized using two independent on chip high performance 14-bit, 40MHz analog-to-digital converters. The data is finally output using a unique Serial LVDS output format that prevents data loss during any ionizing doses. Sample & Hold Mode CLAMP/SAMPLE Adjust For accurate sampling of the input signals the LM98640QML allows for full adjustment of the internal SAMPLE pulse to align it to the proper positions over the input signal. In Sample & Hold mode the SAMPLE pulse should be placed over the pixel output period of the image sensor. Only the Sample Start and Sample End Registers (0x22,0x23) need to be configured, the Clamp Start and Clamp End Registers (0x20,0x21) are not valid in Sample & Hold Mode. Internally the input clock is divided into 64 edges per clock period, the Sample Start and Sample End Registers correspond to the internal edge number the SAMPLE pulse will start and end. To adjust the SAMPLE pulse, first send the CLAMP and SAMPLE signals to the DTM pins by writing 10 to bits[4:3] of the Clock Monitor Register (0x09). This will allow the user to observe the SAMPLE pulse on pin DTM1 along with the image sensor output using an oscilloscope. Then, using the Sample Start and End Registers, adjust the SAMPLE pulse to align it over the Video Level portion of the image sensor output. To allow for settling and to reduce noise, the SAMPLE pulse should be made as wide as possible and fill the entire Video Level portion of the input signal. Figure 5 shows some examples of an input waveform and where the SAMPLE pulse should be placed. Ideally the image sensor output would line up directly with the input clock at the AFE inputs, but due to trace delays in the system the image sensor output is delayed relative to the input clock. In the delayed image sensor waveform the Sample Start value is higher than the Sample End value. In this situation the SAMPLE pulse will start in one clock period and wraps around to the next. This allows the LM98640QML to adjust for the delay in the image sensor waveform. Notice that edge zero of the internal clock does not line up with the rising edge of the input clock. This is due to internal delays of the clock signals. The amount of delay can be calculated from operating frequency using the following formula: tDCLK = 6.0ns + 3/64 * TINCLK Input Sampling Modes The LM98640QML provides two input sampling modes, Sample & Hold mode and Correlated Double Sample (CDS) mode. The following sections describe these two input sampling modes. Sample & Hold Mode In Sample/Hold mode, a Video Level signal and a Reference Level signal need to be presented to the LM98640QML. The Reference Level signal must be connected to the OSX+ pin, and the Video Level signal connected to the OSX- pin. The output code will then be OSX+ minus OSX-, or the difference between the Reference Level and Video Level. A minimum code represents zero deviation between the Reference and Video Levels and a maximum code represents a 2V deviation between the Reference and Video Levels with CDS and PGA gains of 1x. The Reference Level signal can be either an external signal from the image sensor, or the VCLP pin can be externally connected to the OSX+ pin. In order to fully utilize the range of the input circuitry it is desirable to cause the Black Level signal voltage to be as close to the Reference Level voltage as possible, resulting in a near zero scale output for Black Level pixels. The LM98640QML provides several methods for ensuring the Black Level signal and Reference Level are www.national.com 20 LM98640QML 30064775 FIGURE 5. S/H Mode CLAMP/SAMPLE Adjust 21 www.national.com LM98640QML TXFRM signal is the same for every pixel in Sample and Hold mode (i.e. high for three TXCLK periods). CDS Mode In CDS mode, both the Reference Level and Video Level are presented to the LM98640QML on the OSX- pin. The OSX+ pin should be bypassed to ground with a 0.1uF capacitor. The CLAMP pulse is then used to sample the Reference Level and the SAMPLE pulse is used to sample the Video Level. The output code will then be the Reference Level minus the Video Level, or the difference between the Reference Level and Video Level. A minimum code represents zero deviation between the Reference and Video Levels and a maximum code represents a 2V deviation between the Reference and Video Levels with CDS and PGA gains of 1x. To place the LM98640QML in CDS Mode from power up, first write the baseline configuration to the registers as shown in the Configuration Registers Section. Then ensure S/H mode is disabled by clearing bit[7] of the Sample & Hold Register (0x06), then enable CDS mode by setting bit[0] of the Main Configuration Register (0x00). Next the CLAMP and SAMPLE pulses need to be positioned correctly over the reference and video levels respectively using the CLAMP/SAMPLE Adjust. CDS Mode CLAMP/SAMPLE Adjust In CDS mode, the LM98640QML utilizes two input networks, alternating between them every pixel, to increase throughput speeds. Because of this, there are two sets of CLAMP and SAMPLE pulses in the Register Definitions - Timing Configuration, one for even pixels and one for odd. Sample Start and Sample End Registers (0x22,0x23) along with the Clamp Start and Clamp End Registers (0x20,0x21) control both the even and odd CLAMP and SAMPLE pulses. To adjust the CLAMP and SAMPLE pulses, first send the CLAMPODD and SAMPLEODD signals to the DTM pins by writing 10 to bits[4:3] of the Clock Monitor Register (0x09). This will allow the user to observe the CLAMPODD and SAMPLEODD pulses on pins DTM0 and DTM1 along with the image sensor output using an oscilloscope. The CLAMP and SAMPLE pulses will only be shown for every other pixel because of the even odd architecture, but the positions of the even CLAMP and SAMPLE pulses will be identical to that of the odd CLAMP and SAMPLE. Then, using the Clamp Start/End and Sample Start/End registers, adjust the positions of the CLAMP and SAMPLE pulses to align them over the Reference and Video Levels of the input signal. To allow for settling and to reduce noise, the CLAMP and SAMPLE pulses should be made as wide as possible and placed near the far edge of their respective input levels. The following figure shows some examples of input CCD waveforms and placement of the CLAMP and SAMPLE positions for each. Ideally the CCD output would line up directly with the input clock at the AFE inputs, but due to trace delays in the system the CCD output is delayed relative to the input clock. In the Delayed CCD waveform the Sample Start/End Register values are lower than the Clamp Start/End Register Values. In this situation the sample pulse is not generated until the next clock period, which allows it to be correctly placed in the Video Level of the input signal. Notice that edge zero of the internal clock does not line up with the rising edge of the input clock. This is due to internal delays of the clock signals. The amount of delay can be calculated from operating frequency using the following formula: tDCLK = 6.0ns + 3/64 * TINCLK CDS Mode Bimodal Offset In CDS mode, the input sampling amplifier has two physical paths through which a particular pixel will be sampled. These two sampling paths are a requirement in the Correlated Double Sampling architecture. The sampling of the one pixel will travel the first path (arbritrarily called an even pixel), and the sampling of the next pixel will travel the second path (called an odd pixel). The sampling will continue in an even/odd/ even/odd fashion for all pixels processed in a particular channel. Due to slight variances in the sampling paths (most commonly a difference in switched capacitor matching), the processing of identical pixels through the two different paths may result in a small offset in ADC output data between the two paths. To correct this, a simple digital offset can be applied in post processing to either the even pixel data or the odd pixel data. To simplify this action, the LM98640QML will indicate (with the TXFRM signal) whether the pixel traveled the even path or the odd path. For all "Odd" pixels, the TXFRM signal is high for three TXCLK periods. For "Even" pixels, the TXFRM signal is high for two TXCLK periods. In Sample and Hold Mode there is only one sampling path, therefore there is no need to indicate an even or odd pixel. As a result, the www.national.com 22 LM98640QML 30064774 FIGURE 6. CDS Mode CLAMP/SAMPLE Adjust 23 www.national.com LM98640QML of the AC coupling capacitor can to be set using an external DC bias resistor network, by using the CLPIN configuration, or by using the BITCLP configuration. A typical CCD waveform is shown in Figure 8. Also shown in Figure 8 is an internal signal “CLAMP” which can be used to “gate” the CLPIN signal so that it only occurs during the “pedestal” portion of the CCD pixel waveform. Input Bias and Clamping The inputs to the LM98640QML are typically AC coupled and can be sampled in either Sample and Hold Mode (S/H Mode) or Correlated Double Sampling Mode (CDS Mode). The circuit of Figure 7 shows the input structure of the LM98640QML. The DC bias point for the LM98640QML side 30064708 FIGURE 7. Input Structure Diagram www.national.com 24 LM98640QML 30064709 FIGURE 8. Typical CCD Waveform and LM98640QML Input Clamp Signal (CLPIN) Sample and Hold Mode Biasing Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating conditions. In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch (see Figure 7) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal controlling this switch is CLPIN. CLPIN is an external signal connected on the CLPIN pin. Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that is close to the Black Level signal voltage. To provide a more precise DC bias point (i.e. a voltage closer to the Black Level voltage), the CLPIN pulse can be “gated” by the internally generated CLAMP clock. This resulting CLPINGATED signal is the logical “AND” of the CLAMP and CLPIN signals as shown in Figure 8. By using the CLPINGATED signal, the higher Reset Noise peak will not be included in the clamping period and only the Pedestal Level components of the CCD waveform will be centered around VCLP. 30064710 FIGURE 9. Sample and Hold Mode Simplified Input Diagram In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of the CDS/ Sample and Hold amplifier. The amplifier switched capacitance, shown as CS in Figure 9, and internal parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, CSH, is charged to the OSX+ minus OSX- voltage then discharged. The average input current at the OSX- pin can be calculated knowing the input signal amplitude and the frequency of the pixel. 25 www.national.com LM98640QML The CDS mode biasing can be performed in the same way as described in the Sample and Hold Mode Biasing section, or, an external resistor divider can be placed across the OSXinput to provide the DC bias voltage. In CDS Mode the OSX+ pins should each be decoupled with 0.1µF capacitors to ground. 30064711 FIGURE 10. Equivalent Input Switched Capacitance S/H Mode CDS Mode Biasing Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode. This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD waveform have little bearing on the resulting differential result. However, the DC bias point does need to be established to ensure the CCD waveform’s common mode voltage is within rated operating ranges. 30064713 FIGURE 12. CDS Mode Input Bias Current Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel. This results in a much lower input bias current, whose main source is parasitic impedances and leakage currents. As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node over the length of a line will require a much smaller AC input coupling capacitor. VCLP DAC The VCLP pin can be used to provide the reference level for incoming signals in Sample and Hold Mode. The pin is driven by the VCLP DAC, the VCLP DAC has five bits and has an approximate range of 2.9V. The VCLP DAC is controlled by the VCLP Control Register (0x04), and programmable through the serial interface. 30064712 FIGURE 11. CDS Mode Simplified Input Diagram www.national.com 26 The LM98640QML provides two independent gain stages. The first stage is in the input CDS/SH circuit. The second is in the form of a Programmable Gain Amplifier (PGA). PGA Gain Plots The PGA has an 8-bit resolution with a gain range of -3dB to 18dB. Figure 13 below shows a plot for the gain. Each channel has a independent PGA controlled by registers CH1 PGA and CH2 PGA, and programmable through the serial interface. CDS/SH Stage Gain The CDS/SH gain is programmable to either 0dB or 6dB gain. The load presented to the user in 6dB mode is roughly twice the switched load of 0dB mode. The CDS/SH gain settings 30064714 FIGURE 13. PGA Gain vs. PGA Gain Code 27 www.national.com LM98640QML affect both channels. The CDS/SH gain bit is located in bit 2 of the Main Configuration register, and programmable through the serial interface. Programmable Gain LM98640QML ficient range with moderate step sizes, while the Fine DAC is for designs which need a finely tuned offset. The correction voltage is applied to the "Video" level for both Sample & Hold and CDS input modes. Because of the DACs location in the signal path, the correction range lowers as CDS gain increases, and the output referred correction steps and ranges increase with PGA gain. Table 1 provides the range and step size of each DAC. Programmable Analog Offset Correction The LM98640QML provides two analog DACs per channel to provide flexibility in offset control. Each channel has a Coarse DAC and Fine DAC which have +/-8bit resolutions (8bit + Sign). The two DACs can be used independently or as Coarse/Fine configuration. The Coarse DAC provides a suf- TABLE 1. Analog Offset DAC Specifications CDS/SH Gain Coarse DAC Fine DAC Range* Step Size* Output ADC Codes 1x +/- 250mV 1mV +/- 2048 2x +/- 125mV 500µV +/- 2048 1x +/- 5mV 20µV +/- 41 2x +/- 2.5mV 10µV +/- 41 *Referred to Input To use the Offset Correction DACs, the Coarse DAC and Fine DAC must be enabled using bits[6:5] of the Main Configuration Register (0x00). Then the desired correction value should be entered into the CDAC or FDAC register of the appropriate channel. The Offset Correction DACs use a signed binary format which is summarized in Table 2. TABLE 2. Analog Offset Correction DAC Format CDAC / FDAC Input Value CDAC Correction (Codes) FDAC Correction (Codes) 1 1111 1111 +2048 +41 1 0111 1111 +1024 +20 0 1111 1111 0 0 0 0111 1111 -1024 -20 0 0000 0000 -2048 -41 respectively. The DNL performance is +/-0.5LSB and +/-2LSB for INL for a 14bit out. The noise floor is -79dB at 2V with a programmable gain of 0dB. If an out of range pixel is presented to the ADC, the ADC will return to full compliance within two cycles of the pixel clock. Analog to Digital Converter The LM98640QML has a 14bit Analog to Digital Converts (ADC) for each channel. Each ADC has maximum and minimum conversion rate of 40 MSPS and 5 MSPS per channel www.national.com 28 LVDS Output Voltage The LM98640QML output data is presented in LVDS format. Table 3 shows the available LVDS differential output voltage (VOD) settings and its associated offset voltage (VOS). TABLE 3. LVDS Differential Output Voltage Settings VOD VOS 250mV 1.2V 300mV 1.2V 350mV 1.1V 400mV 1.1V LVDS Output Modes The LM98640QML has a unique serial LVDS output format to protect data transfer during ionizing doses. The format provides a buffer on either side of the data word, this is accomplished by clocking a 14bit word using a 16bit clock rate. In the event of an ionizing dose that affects the DLL the output clock period could fluctuate; with no buffer for the data word this fluctuation could cause the loss of one or more of the data word bits, but because the LM98640QML provides the buffer the fluctuation does not cause any data loss. The data can also be sent out in two modes: Dual or Quad Lane. The following sections describe these two modes. Output Mode 1 - Dual Lane In Dual Lane mode each input channel has its own data output presented at 16X the pixel clock rate. A frame signal (TXFRM) is output at the pixel clock rate with the rising edge occurring coincident with the transition of the MSB of the data. In Sample/Hold Modes of operation, the falling edge is coincident with the transition of bit 7 of the data. In CDS Mode, the falling edge of TXFRM toggles between the ransition of bit 9 and bit 7 of the data. A differential clock is also output with transitions aligned with the center of the data eye. Data rates for Dual Lane mode range from 80Mbps, with a 5MHz clock, up to 640Mbps, with a 40MHz clock. TXFRM Output The LM98640QML output includes a frame signal (TXFRM) that should be used to locate the beginning and end of a particular pixel's serial data word. The rising edge of TXFRM is coincident with the pixel's leading bit transition (TXOUT MSB). This TXFRM rising edge can be detected by the capturing FPGA or ASIC to mark the start of the serial data word. 30064752 FIGURE 14. Dual Lane LVDS Output Timing Diagram 29 www.national.com LM98640QML In CDS mode, the input sampling amplifier has two physical paths through which a particular pixel will be sampled. These two sampling paths are a requirement in the Correlated Double Sampling architecture. The sampling of the one pixel will travel the first path (arbritrarily called an even pixel), and the sampling of the next pixel will travel the second path (called an odd pixel). The sampling will continue in an even/odd/ even/odd fashion for all pixels processed in a particular channel. Due to slight variances in the sampling paths (most commonly a difference in switched capacitor matching), the processing of identical pixels through the two different paths may result in a small offset in ADC output data between the two paths. To correct this, a simple digital offset can be applied in post processing to either the even pixel data or the odd pixel data. To simplify this action, the LM98640QML will indicate (with the TXFRM signal) whether the pixel traveled the even path or the odd path. For all "Odd" pixels, the TXFRM signal is high for three TXCLK periods. For "Even" pixels, the TXFRM signal is high for two TXCLK periods. In Sample and Hold Mode there is only one sampling path, therefore there is no need to indicate an even or odd pixel. As a result, the TXFRM signal is the same for every pixel in Sample and Hold mode (i.e. high for three TXCLK periods). LVDS Output LM98640QML coincident with the transition of bits 10 and 3 of the data lanes for an odd output value, and coincident with the transition of bits 11 and 4 for a even output value. A differential clock is also output with rising edge transitions aligned within each data eye. Data rates for Quad Lane mode range from 40Mbps, with a 5MHz clock, up to 320Mbps, with a 40MHz clock. Output Mode 2 - Quad Lane In Quad Lane mode each input channel is split into two data lanes which are presented at 8X the pixel rate. The MSBs (bits 13 through 7) will be presented to one channel while the LSBs (bits 6 through 0) will be presented to the other. A frame signal is run at the pixel clock rate with the rising edge coincident with the transition of the MSB of the data and the falling edge 30064753 FIGURE 15. Quad Lane LVDS Data Output Timing Diagram To start the test pattern generation, enable Test Mode using bit[1] of the Test and Scan Register (0x3D). Then load all parameters for the desired test pattern into the registers, and set Pattern Enable bit of the Test Pattern Control Register (0x34). Changing pattern parameters after the Pattern Enable bit is set may result in undesired output. The pattern will start at the next leading edge of CLPIN. LVDS Test Modes The LVDS test modes present programmable data patterns to the input of the LVDS serializer block. The type of pattern is selectable through the Test Pattern Control register. Once the LVDS test mode is enabled the patterns are output indefinitely. Table 4 below shows the available test pattern modes. TABLE 4. Test Pattern Modes Test Pattern Control[6:4] Test Mode 0 - Fixed Pattern This test mode provides an LVDS output with a fixed value output during the valid pixel region. The fixed value is set via the Test Pattern Value registers. The Test Pattern Value register is split into two registers the upper 6 bits of the test code in first register, and the lower 8 bits of the test code in the second. Test Mode 000 Fixed Code 001 Horizontal Gradient 010 Vertical Gradient 011 Lattice Pattern 100 Strip Pattern 101 LVDS Test Pattern (Synchronous) 110 LVDS Test Pattern (Asynchronous) 111 Reserved Test Mode 1 - Horizontal Gradient This mode provides LVDS data that progresses horizontally from dark to light output values. This mode is highly variable, allowing control over the starting value of the gradient, the width of the gradient, and the increment rate of the gradient. The starting value can be set in the Test Pattern Value register, the width (in number of pixels) of each gradient step is set via Test Pattern Pitch register, and increment rate (in LSBs) is set via the Test Pattern Step register. When the LVDS Horizontal Gradient test pattern is selected, the ramp begins immediately and counts to the maximum value, and then repeats throughout the entire Valid Pixel region. Each pattern consists of a Start Period and Valid Pixel region. During the Start Period the output is the minimum code (0x0000). The Valid Pixel region contains the selected Test Pattern Mode output. The length (in pixels) of the Start period is set using the Test Pattern Start register, and the width of the Valid Pixel region is set using the Test Pattern Width register. www.national.com 30 Test Mode 6 - LVDS Test Pattern (Asynchronous) This mode provides an LVDS output with a fixed value repeated continuously. The pattern starts asynchronously without CLPIN. The fixed value is set via the Test Pattern Value registers. The Test Pattern Value register is split into two registers the upper 8 bits of the test code in first register, and the lower 8 bits of the test code in the second. This is useful for system debugging of the LVDS link and receiver circuitry. Test Mode 3 - Lattice Pattern This mode provides LVDS data that creates a lattice grid. The lattice is made of dark lines on a light background. The line output value is set by Test Pattern Step register, and background value is set by Test Pattern Value register. The number of pixels & lines in the lattice is set via Test Pattern Pitch register. Psuedo Random Number Mode This mode provides LVDS data produced from the following polynomial: P(x) = X14 + X13 + X11 + X9 + 1 To start the Psuedo Random Number mode, set the Test Mode bit of the Test and Scan Register. Then load the seed value in the Test Pattern Value register, and set the Psuedo Random Enable bit of the Test Pattern Control register. The pattern will start outputting after the next leading edge of CLPIN. Test Mode 4 - Stripe Pattern This mode provides LVDS data that creates a vertical stripe pattern. The stripe pattern is made of dark and light lines. The output value of the dark portion is set via Test Pattern Step register, and the light portion is set via Test Pattern Value register. The stripe width in pixels is set via Test Pattern Pitch register. Clock Receiver Test Mode 5 - LVDS Test Pattern (Synchronous) This mode provides an LVDS output with a fixed value repeated continuously. The pattern starts at the leading edge of CLPIN. The fixed value is set via the Test Pattern Value registers. The Test Pattern Value register is split into two registers the upper 8 bits of the test code in first register, and the lower 8 bits of the test code in the second. This is useful for system debugging of the LVDS link and receiver circuitry. A differential clock receiver is used to generate all clock signals on the LM98640QML. The clock input should be externally terminated with 100 Ohms between the input clock pins. The clock may be DC or AC coupled to the AFE. 31 www.national.com LM98640QML Test Mode 2 - Vertical Gradient This mode is similar to the Horizontal Gradient, only the gradient is in the vertical direction. See the Horizontal Gradient mode description for details. LM98640QML ters are common for both channels PGA and ADC. Using these registers the user can control the current of the two stages of the PGA, and the current for the two levels of the ADC. The following table provides a set of baseline configurations for various operating frequencies and gain ranges. These configurations should be treated as baseline values and can be tuned to your specific application. Power Trimming The LM98640QML provides an adaptive power scaling feature that allows the user to optimize power consumption based on the maximum operating frequency and the maximum amount of gain required. The power scaling mode is selectable through the PGA Power Trimming and ADC Power Trimming registers (0x02,0x03). The settings in these regisOperating Frequency 1-4x Max PGA Gain 1-8x Max PGA Gain 5 - 15 MSPS PGA Power Trimming = 0x00 ADC Power Trimming = 0x00 PGA Power Trimming = 0x01 ADC Power Trimming = 0x00 15 - 25 MSPS PGA Power Trimming = 0x01 ADC Power Trimming = 0x00 PGA Power Trimming = 0x09 ADC Power Trimming = 0x00 25 - 40 MSPS PGA Power Trimming = 0x01 ADC Power Trimming = 0x08 PGA Power Trimming = 0x09 ADC Power Trimming = 0x08 down Control Register bits. To place the part in Single Channel Mode each block of the unused channel can be powered down using their respective control bits (Powerdown Control, bits[5:0]). If an external reference clamp is used the VCLP block can be powered down during any Power mode. For applications operating at a low enough frequency additional power can be saved by powering down one channel reference buffer, then externally tie both channel's reference pins together. Powerdown Modes The LM98640QML provides several ways to save power when the device is not in normal usage mode. Using the Powerdown Control Register (0x01) the part can be placed into Powerdown Mode, or Single Channel Mode. In Powerdown Mode (Powerdown Control, bit[7]) the following blocks are placed in a Powerdown mode: VCLP, Channel 1 & 2 Reference Buffers, Channel 1 & 2 PGA OpAmps, and Channel 1 & 2 Amplifiers. Powerdown Mode will override all other Power- www.national.com 32 A serial interface is used to write and read the configuration registers. The interface is a four wire interface using SCLK, SEN, SDI, and SDO connections. The serial interface clock (SCLK) must be less than the main input clock (INCLK) for INCLK speeds of less than 20MHz, for INCLK speeds greater than 20MHz SCLK must remain below 20MHz. The main input clock (INCLK) to the LM98640QML must be active during all Serial Interface commands. The Serial Interface pins are high impedance while SEN is high, this allows multiple slave devices to be used with a single master device. After power-up, the configuration registers must be written with the baseline values, using the serial interface, to place the part in a valid state. Reading the Serial Registers To read to the serial registers using the four wire interface, the timing diagram shown in Figure 17 must be met. Reading the registers takes two cycles. To start the first cycle, SEN is toggled low. At the rising edge of the first clock, the master should assume control of the SDI pin and begin issuing the read command. The read command is built of a "read" bit (1), device address bit (0), six bit register address, and eight "don't care" bits. SDI is clocked into the LM98640QML at the rising edge of SCLK. SEN is toggled high for a delay of at least tSENW (see Figure 18). The second cycle begins when SEN is toggled low. The LM98640QML assumes control of the SDO pin during the first eight clocks of the cycle. During this period, data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the previously addressed register. The next command can be sent on the SDI pin simultaneously during this second cycle. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the beginning of the next command. Writing to the Serial Registers To write to the serial registers using the four wire interface, the timing diagram shown in Figure 16 must be met. First, SEN is toggled low. At the rising edge of the first clock, the master should assume control of the SDI pin and begin issuing the write command. The write command is built of a "write" bit (0), device address bit (0), six bit register address, and eight bit register value to be written. SDI is clocked into the LM98640QML at the rising edge of SCLK. The LM98640QML assumes control of the SDO pin during the first eight clocks of the cycle. During this period, data is clocked out of the de- 30064759 FIGURE 16. Four Wire Serial Write 33 www.national.com LM98640QML vice at the rising edge of SCLK. The eight bit value clocked out is the contents of the previously addressed register, regardless if the previous command was a read or a write. When SEN toggles high, the register is written to, and the LM98640QML now functions with this new data. Serial Interface LM98640QML 30064760 FIGURE 17. Four Wire Serial Read Serial Interface Timing Details 30064761 FIGURE 18. Serial Interface Specification Diagram www.national.com 34 Power Planes Power for the LM98640QML should be provided through a broad plane which is located on one layer adjacent to the ground plane(s). Placing the power and ground planes on adjacent layers will provide low impedance decoupling of the AFE supplies, especially at higher frequencies. The output of a linear regulator should feed into the power plane through a low impedance multi-via connection. The power plane should be split into individual power peninsulas near the AFE. Each peninsula should feed a particular power bus on the AFE, with decoupling for that power bus connecting the peninsula to the ground plane near each power/ground pin pair. Using this technique can be difficult on many printed circuit CAD tools. To work around this, zero ohm resistors can be used to connect the power source net to the individual nets for the different AFE power buses. As a final step, the zero ohm resistors can be removed and the plane and peninsulas can be connected manually after all other error checking is completed. Radiation Environments Careful consideration should be given to environmental conditions when using a product in a radiation environment. Total Ionizing Dose Testing and qualification of this product is done on a wafer level according to MIL-STD-883, Test Method 1019. Wafer level TID data is available with lot shipments. Single Event Latch-Up and Functional Interrupt One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. SEL testing was conducted with the junction temperature at 125°C. The linear energy transfer threshold (LETth) shown in the Key Specifications table on the front page is the maximum LET tested. A test report is available upon request. Bypass Capacitors The general recommendation is to have one 100nF capacitor for each power/ground pin pair. The capacitors should be surface mount multi-layer ceramic chip capacitors. Single Event Effects A report on single event upset (SEU) is available upon request. Ground Plane Grounding should be done using continuous full ground planes to minimize the impedance for all ground return paths, and provide the shortest possible image/return path for all signal traces. 35 www.national.com LM98640QML Thermal Management The exposed pad on bottom of the package is attached to the back of the die to act as a heat sink. Connecting this pad to the PCB ground planes with a low thermal resistance path is the best way to remove heat from the AFE. This pad should also be connected to the ground planes through low impedance path for electrical purposes. Supply/Grounding, Layout and Thermal Recommendations www.national.com 36 Reserved Reserved Reserved Reserved 00 1101 00 1110 00 1111 CDAC1 CDAC1 FDAC1 FDAC1 Reserved PGA1 Reserved Reserved CDAC2 CDAC2 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001 Gain & Offset DAC Configuration Reserved 00 1100 Status 00 0111 00 1011 Sample & Hold 00 0110 Reserved LVDS Output Modes 00 0101 00 1010 VCLP Control 00 0100 Reserved ADC Power Trimming 00 0011 Clock Monitor PGA Power Trimming 00 0010 00 1001 Powerdown Control 00 0001 00 1000 Main Configuration 00 0000 VCLP Powerdown Master Powerdown Ch2 PGA Powerdown Reserved 1111 1111 0000 0000 0000 0000 0000 0000 0110 0001 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 Offset Value bits 7:0 Not Used Not Used Not Used PGA Gain Value Not Used Offset Value bits 7:0 Not Used Offset Value bits 7:0 Not Used Not Used Not Used Not Used Not Used Not Used Enable/Select Reserved Not Used Not Used Reserved Quad Lane Enable 0000 0000 Not Used Bit 3 CLPIN Gating Enable ADC Current Trimming 2 Buffer Enable VCLP Enable Reserved Ch1 Ref Buf Powerdown Reserved Bit 4 Ch2 ADC Powerdown Reserved Bit 1 Ch1 ADC Powerdown CDS Enable Bit 0 Not Used Ref Buf Power Level LVDS Enable Offset Bit 8 Offset bit 8 Offset bit 8 False Lock Reserved LVDS Control ADC Current Trimming 1 PGA Stage 1 Bias Current Trimming Ch1 PGA Powerdown CDS Gain Enable Bit 2 VCLP Voltage Level Register/Bit Description PGA Stage 2 Bias Current Trimming Ch2 Ref Buf Powerdown Fine DAC Enable Bit 5 Not Used S/H Enable Clear Not Used Reserved Reserved Coarse DAC Enable Not Used Bit 6 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0001 0000 1110 0111 0100 0101 1011 0010 0100 0000 0000 0000 0100 Bit 7 Registers need to be written with baseline values after power-up to place part in a valid state. Register Title (Mnemonic) Baseline (Binary) Analog Configuration Address (Binary) Configuration Registers LM98640QML Reserved Reserved 01 1110 01 1111 Reserved Reserved Reserved Reserved Reserved 10 1011 10 1100 10 1101 10 1110 10 1111 Test Pattern Start Test Pattern Start Test Pattern Width Test Pattern Width Test Pattern Control Test Pattern Pitch Test Pattern Step 11 0000 11 0001 11 0010 11 0011 11 0100 11 0101 11 0110 Digital Configuration Registers Reserved 10 1010 Reserved 10 0110 Reserved INCLK Range 10 0101 10 1001 Reserved 10 0100 Reserved Sample End 10 0011 DLL Configuration Sample Start 10 0010 10 1000 Clamp End 10 0001 10 0111 Clamp Start 10 0000 Timing Configuration PGA2 Reserved 01 1101 FDAC2 01 1100 FDAC2 01 1011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0010 0011 0100 0011 1100 0010 1000 0001 1100 0000 1000 0000 0000 0000 0000 0000 0000 0110 0001 1111 1111 0000 0000 Not Used Not Used Not Used Not Used Pattern Enable Not Used Bit 7 Bit 6 Pattern Mode INCLK Range Bit 5 Bit 3 Bit 2 Start Lower Bits Test Pattern Step Code Test Pattern Pitch Pseudo Random Enable Width Lower Bits Width Upper Bits Seed Enable Not Used Sample End Index Sample Start Index Clamp End Index Clamp Start Index Start Upper Bits Not Used Not Used Not Used Not Used Not Used Not Used Not Used Reserved Not Used Not Used Reserved Not Used Not Used Not Used PGA Gain Value Offset Value bits 7:0 Not Used Bit 4 Register/Bit Description Registers need to be written with baseline values after power-up to place part in a valid state. Register Title (Mnemonic) Baseline (Binary) 01 1010 Address (Binary) DLL Reset Reserved Offset Bit 8 Bit 0 Pattern Output Channel Bit 1 LM98640QML 37 www.national.com www.national.com 38 Test Pattern Channel Offset Test Pattern Value Test Pattern Value Reserved Reserved Digital Configuration Test & Scan Control Device ID Reserved 11 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Register Title (Mnemonic) Baseline (Binary) Address (Binary) Bit 7 Not Used Bit 6 Bit 3 Not Used Not Used Device Revision ID Not Used Not Used Not Used Pattern Lower Bits Pattern Upper Bits Bit 4 Register/Bit Description Pattern U-Wire Voting Voting Enable Enable Not Used Bit 5 Bit 2 Bit 1 Test Reset Test Mode Test Pattern Channel Offset Registers need to be written with baseline values after power-up to place part in a valid state. Not Used Auto Read Bit 0 LM98640QML LM98640QML Register Definitions Register Definitions - Analog Configuration Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) 00 0000 Main Configuration 0000 0100 [7:0] Description Main Configuration [7] Not Used [6] Coarse DAC Enable 0 Disable 1 Enable [5] Fine DAC Enable 0 Disable 1 Enable [4] Reserved [3] CLPIN Gating Enable 0 CLPIN not gated by CLAMP 1 CLPIN gated by CLAMP (=logical "and" of CLPIN and CLAMP) [2] Gain Mode Select. Selects either a 1x or 2x gain mode in the CDS/Sample/Hold Block 0 1x Gain in the CDS/Sample/Hold Block 1 2x Gain in the CDS/Sample/Hold Block [1] Reserved. Set to 0. [0] CDS / Sample/Hold Mode select. 0 Disabled. Correlated Double Sample Mode disabled. 1 Enabled. Correlated Double Sample Mode enabled. 39 www.national.com LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) 00 0001 Powerdown Control 0000 0000 [7:0] www.national.com Description Powerdown Control Register [7] Master Powerdown 0 Fully Powered. 1 Powerdown Mode. Over rides bits [6:0]. [6] VCLP Powerdown 0 VCLP Fully Powered. 1 VCLP Powerdown Mode. [5] Channel 2 Reference Buffer Powerdown 0 Reference Buffer Fully Powered. 1 Reference Buffer Powerdown Mode. [4] Channel 1 Reference Buffer Powerdown 0 Reference Buffer Fully Powered. 1 Reference Buffer Powerdown Mode. [3] Channel 2 PGA Powerdown 0 OpAmp Fully Powered. 1 OpAmp Powerdown Mode. [2] Channel 1 PGA Powerdown 0 OpAmp Fully Powered. 1 OpAmp Powerdown Mode. [1] Channel 2 ADC Powerdown 0 Amplifier Fully Powered. 1 Amplifier Powerdown Mode. [0] Channel 1 ADC Powerdown 0 ADC Fully Powered. 1 ADC Powerdown Mode. 40 LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) 00 0010 00 0011 00 0100 Register Title Baseline (Binary) PGA Power Trimming 0010 0100 ADC Power Trimming 0101 1011 VCLP Control 0111 0100 Bit(s) Description [7:0] PGA Power Trimming Register. [7:6] Not Used [5:3] PGA Stage 1 Current Trimming Tunable between 000-Weak to 111-Strong (Default 100) [2:0] PGA Stage 2 Current Trimming Tunable between 000-Weak to 111-Strong (Default 100) [7:0] ADC Power Trimming Register. [7:6] Reserved. Set to 2'b01. [5:3] ADC Current Trimming 2(Not Binary Weighted) 000 25% Power 001 50% Power 011 75% Power (Default) 111 100% Power [2:0] ADC Current Trimming 1 (Not Binary Weighted) 000 25% Power 001 50% Power 011 75% Power (Default) 111 100% Power [7:0] Voltage Clamp Buffer Control Register. [7] Not Used [6] Buffer Enable 0 Disabled. Resistor Ladder is driving VCLP pin. 1 Enabled. Resistor Ladder is buffered to VCLP pin. [5] VCLP Enable 0 Disabled. VCLP pin can be externally driven. 1 Enabled. VCLP pin is in output mode. [4:0] Voltage Level of VCLP pin. VCLP range is 200mV to 3.1V in 100mV steps for (binary) settings 00000 to 11101. Settings 11110 and 11111 are not used. 41 www.national.com LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) 00 0101 Register Title Baseline (Binary) LVDS Output Modes 0000 1110 Bit(s) [7:0] [7] [6:4] 00 0110 Sample & Hold 1000 0001 Description LVDS Output Configuration Register. Serializer Data Reset. (Not self-clearing) Not Used. [3] LVDS Output Mode 0 Dual Lane Mode (see ) 1 Quad Lane Mode (see ) [2] LVDS Driver Enable. 0 LVDS Drivers Disabled 1 LVDS Drivers Enabled (Note: In Dual Lane Mode TX0 and TX3 are disabled regardless of driver enable) [1:0] LVDS Amplitude and Common Mode Voltage. 00 250mV (1.2V DC Offset) 01 300mV (1.2V DC Offset) 10 350mV (1.1V DC Offset) 11 400mV (1.1V DC Offset) [7:0] Sample & Hold Mode Register [7] Sample & Hold Mode Enable 0 Disabled. 1 Enabled. [6:3] Not Used. [2:1] Reference Buffer Power Level 11 100% Power. Used for FINCLK = 20-40MHz. 10 60% Power. Used for FINCLK = 10-20MHz. 01 60% Power. Used for FINCLK = 10-20MHz. 00 30% Power. Used for FINCLK = 5-10MHz. [0] 00 0111 Status 0000 0000 Status Register. (Read Only) [7:1] Not Used. [0] www.national.com Reserved. [7:0] False Lock Detect. Indicates if DLL is locked into a half frequency state. 42 LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) Description 00 1001 Clock Monitor 0000 0000 [7:0] Internal Clock Signal Monitor Register [7:5] Not Used. [4:3] Enable and select clocks to be monitored on the Digital Timing Monitor. (DTM) 00 Disable Digital Timing Monitor Pins (DTM0, DTM1) 01 Send CLAMPEVEN to DTM0 pin, and SAMPLEEVEN to DTM1 10 Send CLAMPODD to DTM0 pin, and SAMPLEODD to DTM1 11 Send ODD tag and ADC Clock to the DTM. [2:0] Reserved. Set to 000. Register Definitions - GAIN & Offset DAC Configuration Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) Description 01 0000 CDAC1 0000 0000 [7:0] Channel 1 Coarse DAC Register. [7:1] Not Used. [0] Bit 8 of Channel 1 Coarse DAC Offset Value. 01 0001 CDAC1 1111 1111 [7:0] Channel 1 Coarse DAC Offset Value bits 7:0. 01 0010 FDAC1 0000 0000 [7:0] Channel 1 Fine DAC Register. [7:1] Not Used. [0] Bit 8 of Channel 1 Fine DAC Offset Value. 01 0011 FDAC1 1111 1111 [7:0] Channel 1 Fine DAC Offset Value bits 7:0. 01 0101 PGA1 0110 0001 [7:0] Channel 1 Programmable Gain Amplifier Value. 01 1000 CDAC2 0000 0000 [7:0] Channel 2 Coarse DAC Register. [7:1] Not Used. [0] Bit 8 of Channel 2 Coarse DAC Offset Value. 01 1001 CDAC2 1111 1111 [7:0] Channel 2 Coarse DAC Offset Value bits 7:0. 01 1010 FDAC2 0000 0000 [7:0] Channel 2 Fine DAC Register. [7:1] Not Used. [0] Bit 8 of Channel 2 Fine DAC Offset Value. 01 1011 FDAC2 1111 1111 [7:0] Channel 2 Fine DAC Offset Value bits 7:0. 01 1100 PGA2 0110 0001 [7:0] Channel 2 Programmable Gain Amplifier Value. 43 www.national.com LM98640QML Register Definitions - Timing Configuration Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) 10 0000 Clamp Start 0000 1000 [7:0] Clamp Start Register. [7:6] Not Used. [5:0] CLAMP Starting Index. 0-63d position for rising edge of CLAMP signal. Valid only in CDS Mode. [7:0] Clamp End Register. [7:6] Not Used. [5:0] CLAMP End Index. 0-63d position for falling edge of CLAMP signal. Valid only in CDS Mode. [7:0] Sample Start Register. [7:6] Not Used. [5:0] SAMPLE starting Index. 0-63d position for rising edge of SAMPLE signal. [7:0] Sample End Register. [7:6] Not Used. [5:0] SAMPLE End Index. 0-63d position for falling edge of SAMPLE signal. [7:0] INCLK Range Register. 10 0001 10 0010 10 0011 10 0101 Clamp End Sample Start Sample End INCLK Range 0001 1100 0010 1000 0011 1100 0000 0010 [7] www.national.com Description Not Used. [6:4] INCLK Range. 000 25-40MHz Operation 001 14-25MHz Operation 010 10-14MHz Operation 011 7.5-10MHz Operation 100 6-7.5MHz Operation 101 5-6MHz Operation 110 Not Used 111 Not Used [3:2] Not Used. [1:0] DLL Range 11 Reserved 10 14-40MHz Operation 01 7.5-14MHz Operation 00 5 -7.5MHz Operation 44 LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) 10 1000 DLL Configuration 0000 1111 [7:0] DLL Configuration Register [7:1] Reserved [0] Description DLL Reset. (Self Clearing) Register Definitions - Digital Configuration Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) Description 11 0000 Test Pattern Start 0000 0000 [15:8] Upper 8 bits of the Test Pattern start value. Specifies the number of pixels after the leading edge of CLPIN to the Valid Pixel region. 11 0001 Test Pattern Start 0000 0000 [7:0] Lower 8 bits of the Test Pattern start value. Specifies the number of pixels after the leading edge of CLPIN to the Valid Pixel region. 11 0010 Test Pattern Width 0000 0000 [15:8] Upper 8 bits of the Test Pattern Width value. Specifies, in number of pixels, the width of the Valid Pixel region. 11 0011 Test Pattern Width 0000 0000 [7:0] Lower 8 bits of the Test Pattern Width value. Specifies, in number of pixels, the width of the Valid Pixel region. 11 0100 Test Pattern Control 0000 0000 [7:0] Test Pattern Control Register. [7] [6:4] 11 0101 Test Pattern Pitch 0000 0000 Programmable Pattern Switch 0 Disabled. Normal LVDS output operation. 1 Enabled. AFE outputs LVDS test patterns. Test Pattern Mode 000 Fixed Code 001 Horizontal Gradient Scan (Main Scan) 010 Vertical Gradient Scan (Sub Scan) 011 Grid Scan (Lattice Pattern) 100 Strip Pattern 101 LVDS Test Pattern. (Synchronous to CLPIN) 110 LVDS Test Pattern. (Asynchronous) 111 Not Used. [3] Pseudo Random Pattern Enable. Overrides Programmable Patter Switch setting (bit 7). Normally only one should be on. [2] Load Seed Enable. When set, the seed value in the Test Pattern Value Register is loaded in the LFSR at the leading edge of CLPIN. [1:0] Test Pattern Output Channel Select. 00 Both Channels 01 Channel 1 10 Channel 2 11 Not Used [7:0] Test Pattern pitch, specifies number of pixels for H Gradient pattern and Stripe pattern, or number of lines in the V Gradient pattern, or specifies pixels & lines in the Lattice pattern. 45 www.national.com LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) Description 11 0110 Test Pattern Step 0000 0000 [7:0] Test Pattern Step Code. Specifies step size in LSB codes the pattern is incremented in H Gradient and V Gradient pattern. In Lattice and Stripe pattern it specifies the code during the lower step. Test Pattern Channel 0000 0000 Offset [7:0] Test Pattern Channel Offset Register. [7:4] Not Used. [3:0] Test Pattern Channel Offset. This specifies the number of lines the pattern on Channel 2 is delayed from Channel 1. This offset is maintained throughout the pattern. 11 0111 11 1000 Test Pattern Value 0000 0000 [15:8] Upper 8 bits of Test Pattern Value Register. Specifies the upper 8 bits of the test value code during Fixed Pattern and LVDS test, initial value during H Gradient & V Gradient pattern, and higher value in the Lattice and Stripe Pattern. 11 1001 Test Pattern Value 0000 0000 [7:0] Lower 6 bits of Test Pattern Value Register. Specifies the lower 6 bits of the test code value during Fixed Pattern and LVDS test, initial value during H Gradient & V Gradient pattern, and higher value in the Lattice and Stripe Pattern. 11 1100 Digital Configuration 0000 0000 [7:0] Serial Communication Configuration Register. [7:1] Not Used. [0] Micro-Wire Automatic Read Disable. 0 Read data is always sent out on SDO during the first 8 SCLK cycles. The register is selected by the register address in the previous cycle. (read or write) 1 Automatic read is disabled. To read from a register two cycles need to be initiated by the master, first cycle should be a read with the correct register address and second can be a dummy read or read from another address or a write cycle, and the data is sent first 8 SCLK of the second cycle. After a write command SDO remains in Tri-State during first 8 SCLK. www.national.com 46 LM98640QML Registers need to be written with baseline values after power-up to place part in a valid state. Address (Binary) Register Title Baseline (Binary) Bit(s) 11 1101 Test & Scan Control 0000 0000 [7:0] Test & Scan Control Register [7:6] Not Used. 11 1110 Device ID 0000 0001 Description [5] Test Pattern Voting Switch. 0 Enable. Circuit Redundancy Voting is active. 1 Disable. First redundancy block output is used. [4] Micro-wire Voting Switch. 0 Enable. Circuit Redundancy Voting is active. 1 Disable. First Micro-wire block output is used. [3] Not Used. [2] Test Reset. Resets the test block when High, normal test block function when Low. This bit is not self-clearing. [1] Test Mode Enable. 0 Disable. 1 Enable. Needed to run Test Pattern functions. [0] Not Used. [7:0] Device Revision ID. 47 www.national.com LM98640QML Revision History Date Released Section Changes 05/10/2010 A Initial Release New Product Initial Release 01/13/2011 B Abs Max & Elec. Tables Changed Thermal Res. Unit of measure & Tjc Limit www.national.com Revision 48 LM98640QML Physical Dimensions inches (millimeters) unless otherwise noted 68-Lead Ceramic QFP with Exposed Pad (Opt. 1) NS Package Number EL68D Exposed pad is for thermal dissipation and must be soldered to ground plane to ensure rated performance. 49 www.national.com LM98640QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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