PHILIPS AN10872 Tl application with uba2014 Datasheet

AN10872
TL application with UBA2014
Rev. 01 — 9 December 2010
Application note
Document information
Info
Content
Keywords
UBA2014, half-bridge, ballast, tube lamp
Abstract
This application note describes the design of an application using the
UBA2014 to drive T5 and T8 fluorescent tubes.
AN10872
NXP Semiconductors
TL application with UBA2014
Revision history
Rev
Date
Description
v.1
20101209
initial version
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
2 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
1. Introduction
The function of an electronic ballast is to preheat, ignite and control a fluorescent Tube
Lamp (TL) and to monitor its condition. If there is no ignition, or the lamp reaches an End
Of Life (EOL) condition, the ballast must shut down immediately to avoid damage to the
ballast, and/or overheating of the lamp caps.
The application described here is built using a UBA2014 IC, which is a monolithic
integrated circuit designed to electronically drive ballasted fluorescent TLs using mains
voltages of up to 277 V RMS (nominal value).
The circuit uses a 650 V bipolar CMOS DMOS (BCD) power-logic process. The IC
provides a drive function for two discrete power MOSFETs and includes:
•
•
•
•
•
•
Level-shift circuit
Oscillator
Lamp voltage monitor
Current control
Timer
Protection
1.1 Features
•
•
•
•
•
•
•
•
•
Adjustable preheat time
Adjustable preheat current
Current controlled operation
Single ignition attempt
Adaptive non-overlap time control
Integrated high voltage level shift function
Power-down function
Protection against damage due to lamp failures or lamp removal
Capacitive mode protection
2. Scope and structure of document
2.1 Scope
This application note describes the use of a UBA2014 half-bridge driver IC in HF-TL
applications. It covers single tube applications only. For support and/or examples of
multiple lamp applications please consult your local NXP Semiconductors support office.
The circuits described in this application note are intended to be supplied with a fixed DC
voltage provided by a Power Factor Controller (PFC). Alternatively, instead of the DC
input, a charge pump, or valley fill topology can be used, but these topologies are not
covered in this document.
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
3 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
2.2 Structure of the application note
The information in this application note is set out in discrete sections. Where possible,
typical values are given. A block diagram is shown in Figure 1
Section 1 “Introduction”.
Section 2 “Scope and structure of document”.
Section 3 “Pin description” - gives an IC pin overview with a summary and description of
the IC pin functions and their typical voltage and current levels.
Section 4 “Series resonant single lamp application circuit” describes the building blocks of
a T8 36 W typical application, explains the development steps of the individual sub circuits
and gives component values.
Section 5 “Start-up sequence states” - gives preheat, ignition/operating state diagrams of
the UBA2014 and shows which IC blocks are active in which state.
Section 6 “EOL detection/protection” - gives an overview of possible additional protection
circuits that can be used to avoid damage to the ballast, or the lamp electrodes due to
overheating in the case of a degraded lamp.
Section 7 “Debugging a UBA2014 ballast” - gives a sequential procedure for incrementally
powering up a ballast, rather than applying full power immediately.
Section 8 “PCB design and layout guidelines” - gives the layout of the PCB to ensure that
any ballast will function correctly. Suggestions for placing of components is given together
with indication of the current loops that should be kept small.
Section 9 “Inductive mode heating” - shows that Inductive mode heating is achieved by
using two small extra windings on the resonant tank coil. Together with a small capacitor
in series, these secondary windings are placed across the filament. Values are given for
the resonance tank coil and capacitor, secondary inductance and secondary capacitance
for TL5/TLD lamps operated in an Inductive mode topology.
2.3 Related documents and tools
Further information and design tools can be found on the NXP Semiconductors internet
Product Information Page (PIP) of the UBA2014, or through the local sales office.
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
4 of 38
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14
3V
9
Vpd
SUPPLY
LEVEL
SHIFTER
reference
voltages
digital
FVDD
BOOTSTRAP
HS
DRIVER
10
11
supply (5 V)
LS
DRIVER
analog
UBA2014
6
GH
SH
NXP Semiconductors
7
3. Pin description
AN10872
Application note
VREF
VDD
GL
VDD(L)
5
DRIVER
LOGIC
reset
LOGIC
1
8
LAMP
VOLTAGE
SENSOR
15
16
AVERAGE
CURRENT
SENSOR
I
Vlamp(fail)
V
Fig 1.
Block diagram
PCS
13
FREQUENCY
CONTROL
2
CF
LVS
CSW
CSP
CSN
AN10872
3
Vlamp(max)
019aaa129
IREF
ACM
TL application with UBA2014
5 of 38
© NXP B.V. 2010. All rights reserved.
4
PCS
12
LOGIC
VOLTAGE
CONTROLLED
OSCILLATOR
REFERENCE
CURRENT
• RESET STATE
• START-UP STATE
• PREHEAT STATE
• IGNITION STATE
• BURN STATE
• HOLD STATE
• POWER-DOWN STATE
LOGIC
PREHEAT TIMER
CT
ANT/CMD
STATE LOGIC
COUNTER
Rev. 01 — 9 December 2010
All information provided in this document is subject to legal disclaimers.
GND
AN10872
NXP Semiconductors
TL application with UBA2014
Table 1.
UBA 2014 pin functionality
Pin
Name
Function description summary
1
CT
Preheat timer output: A capacitor to ground is connected to the CT pin. The
preheat timer (PRT) block determines the preheat and ignition times. The
preheat time is determined by a capacitor connected to the CT pin and a resistor
(typically 33 kΩ) connected to the IREF pin. The maximum ignition time tign is
one period at CT, and the preheat time tph is seven periods.
The PRT circuit is operational during IC start-up and in the event of a fault
condition, is triggered by the Lamp Voltage Sensor via the LVS pin. The preheat
time begins when the VCO starts oscillating. The ignition state follows the
preheat state as shown in formulas below:
C CT
R IREF
- × ------------------t ph = 1.8 × ------------------------–9
3
330 × 10
33 × 10
C CT
R IREF
- × ------------------t ign = 0.26 × ------------------------–9
3
330 × 10
33 × 10
2
CSW
Voltage controlled oscillator output: The capacitor connected to the CSW pin
together with the capacitor connected to the CF pin determine the running
frequency. If the voltage on the CSW pin is 0 V (start-up condition), the
frequency is then at the maximum the controller can produce (which is
determined by the CF capacitor value). The capacitor will be charged after
start-up, lowering the operating frequency until the correct preheat frequency is
reached.
After preheat, the capacitor on the CSW pin is again charged until the minimum
frequency of the controller is reached. The value of the capacitor on the CSW
pin governs the speed of the ramp down from the preheat frequency to the
minimum frequency for ignition, which is important for correct ignition.
During operation of the lamp, the value of the capacitor on the CSW pin
determines the speed with which the frequency changes. The UBA2014 uses
the feedback control loop, with the CSP and CSN pins as input for this loop.
For full lamp power only, a 220 nF 50 V capacitor connected to ground is
normally used. For deep dimming, an RC network can be used to increase the
small signal frequency response. If the UBA2014 detects capacitive mode the
CSW capacitor is discharged instantly.
3
CF
Oscillator timing capacitor pin: The VCO generates a sawtooth shaped voltage
between 0 V and 2.5 V. The frequency is determined by the value of the
capacitor connected to the CF pin, the resistor connected to the IREF pin and
the voltage at the CSW pin. The maximum frequency (fmax), at which the circuit
starts oscillating, is 2.5 times the minimum frequency (fmin). The driver logic
drives the HS and LS drivers at a frequency half of the VCO frequency.
A 5 % tolerance, 50 V CP dielectric type capacitor is recommended. A suitable
value would be 100 pF which gives a switching frequency fmin = 40 kHz,
fmax = 100 kHz
– 12
3
33 × 10
3 100 × 10
f min = 40.5 × 10 × ---------------------------- × -------------------C CF
R IREF
f max = 2.5 × f min
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
6 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
Table 1.
UBA 2014 pin functionality
Pin
Name
Function description summary
4
IREF
Internal reference current input: Connect with 33 kΩ resistor (1 % tolerance) to
ground.
5
GND
Ground
6
GL
Gate output for the low-side switch: The gates of the power MOSFETs are
connected to the GH and GL pins. Connect this pin to the gate directly, or via a
gate resistor of up to 47 Ω. The level of the GL pin switches between GND and
VDD.
On the first switching cycle, the drive signal for the LS-driver is extended to
enable the bootstrap to charge the externally connected bootstrap capacitor
(between pins FVDD and SH).
7
VDD
Low-voltage supply: It is essential that this voltage remains below 14 V at all
times. During standby, an internal Zener diode is active; during operation, the
design should ensure this voltage is not exceeded.
8
PCS
Preheat current sensor input: This pin is to be connected to a sense resistor in
the source of the lower half-bridge MOSFET. At start-up the capacitor connected
to the CSW pin is connected to the input of the VCO and will be charged,
ensuring a defined frequency sweep which will start at the maximum frequency.
By charging the capacitor with a constant current controlled by the PCS, the
frequency will decrease until the preheat voltage measured at the PCS pin
exceeds an internally fixed voltage of 0.6 V.
9
FVDD
Floating supply voltage: supply for high-side switch
10
GH
Gate output for the high-side switch: The gates of the power MOSFETs are
connected to pins GH and GL. Connect this pin to the gate directly, or via a gate
resistor of up to 47 Ω. The level of this pin switches between the voltage on pin
SH and pin SH voltage plus VDD.
11
SH
Ground (MOSFET source) reference for the high-side switch supply voltage,
connect to the half-bridge output.
12
ACM
Capacitive mode detection input: When operating correctly, the voltage at pin
ACM consists of a positive pulse with a minimal amplitude of 100 mV during the
rising slope of the half-bridge, and a pulse below −85 mV during the falling edge
of the half-bridge. It is typically measured across an externally connected
resistor in the VDD generation circuit.
These pulses input to the Adaptive Non-overlap Timer (ANT) block, which
ensures that both power MOSFETs have the same on-time, independent of the
frequency. The same signal is used to avoid hard switching (adaptive
non-overlap) and to detect Capacitive mode (see Figure 1 “Block diagram”).
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
7 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
Table 1.
UBA 2014 pin functionality
Pin
Name
Function description summary
13
LVS
Lamp voltage sensor input: Used to monitor lamp behavior and trigger
protections if required. The lamp voltage must be monitored to ensure that if the
lamp does not ignite, or the lamp fails during operation, the ballast will not
subsequently be damaged.
Two voltage levels are defined: Vlamp(fail) (0.8 V) and Vlamp(max), (1.5 V)
measured at pin LVS. The ignition level of a properly functioning lamp should be
between these two levels. Passing the Vlamp(fail) level starts the ignition timer
(re-using the CT timer). If the lamp ignites, the lamp voltage will drop and the
voltage measured at the LVS pin will also drop. If the lamp does not ignite, the
UBA2014 in its ignition state, will limit the frequency ramp down, so that
Vlamp(max) is not exceeded, and will hold this level for the maximum time allowed
by the ignition timer. If the lamp has not ignited at the end of the ignition timing,
the UBA2014 will switch to standby, and will stay in this state until a power cycle
is done.
During lamp operation, the LVS pin protects the ballast against worn or defective
lamps. As soon as Vlamp(fail) is exceeded (e.g. worn lamp), the UBA2014 goes to
standby after a time-out period of one CT cycle. If during operation Vlamp(max) is
exceeded (e.g. broken filaments), the UBA2014 will immediately go to its initial
state and restart.
14
VREF
Reference voltage output (2.95 V): Can be used to set the desired lamp current
level on the CSP pin, and for lamp End Of Life (EOL) detection.
15
CSP
Positive input error amplifier and average current sensor: This is the desired
lamp current level. It can come from a microprocessor with a Dali interface, or
from a galvanic separated 0 V to 10 V interface, or from a potentiometer. If no
dimming is required, it can be a fixed voltage derived from Vref.
16
CSN
Negative input error amplifier and average current sensor: The average lamp
current measurement is usually achieved by developing a voltage across a
resistor and applying this to the CSN pin. The output voltage of the ACS block is
fed to the VCO regulating the switching frequency and, as a result, the lamp
current. If CSP is higher than CSN the ACS circuit will lower the frequency in
order to increase the lamp current until the level set by CSP. If CSP is lower than
CSN, the ACS circuit will increase the frequency in order to reduce the lamp
current.
During lamp operation, the capacitor on the CSW pin determines the speed with
which the frequency is changed by the feedback control loop.
4. Series resonant single lamp application circuit
When the resonant tank inductor is used, the lamp electrodes and a capacitor in series
give the easiest and most economical application. This is commonly known as the series
resonant topology. Figure 2 gives the series resonant configuration using a TL8 36 W
lamp as an example.
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
AN10872
Application note
F1
1A
D1
BYD77D
9 FVDD
C5
100 nF
10 GH
BOOTSTRAP
HIGH SIDE
DRIVER
VDD 7
T1
IRF820
R10
1 MΩ
R1
1 MΩ
L1
11 SH
1.9 mH
C6
1.2 nF
DRIVER
CONTROL
SUPPLY
T2
IRF820
6 GL
LOW SIDE
DRIVER
Rev. 01 — 9 December 2010
All information provided in this document is subject to legal disclaimers.
C10
5.6 nF
ADAPTIVE
NON-OVERLAP TIMING
AND CAPACITIVE
MODE DETECTOR
UBA2014
12 ACM
R16
1.5 Ω
+
VPFC
V1
Z1
12 V
CT 1
PREHEAT
TIMER
C7
330 nF
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
REFERENCE
CURRENT
PREHEAT
CURRENT
SENSOR
8 PCS
LAMP
VOLTAGE
SENSOR
13 LVS
AVERAGE
CURRENT
SENSOR
5
3
2
14
GND
CF
CSW
VREF
C14
100 pF
C13
220 nF
R20
220 kΩ
16 CSN
R8
15 CSP
8.2 kΩ
C19
56 nF
R5
10 kΩ
D4
C17
6.8 nF
LAMP
C22
8.2 nF
TLT836W
BYD77D
C2
12 nF
R14
1Ω
R3
220 kΩ
C3
1 nF
R2
8.2
kΩ
R18
180 kΩ
019aaa130
Application diagram: series resonant topology
AN10872
9 of 38
© NXP B.V. 2010. All rights reserved.
Fig 2.
C20
68 nF
TL application with UBA2014
R12
33 kΩ
+
C8
330 pF
47 Ω
C23
100 nF
4
IREF
R4
1 MΩ
C15
330 nF
R13
150 Ω
−
C24
100 nF
R9
AN10872
NXP Semiconductors
TL application with UBA2014
4.1 Resonant tank
Coil L1 and capacitor C22 form the resonant tank. The combination of these two
components generates the ignition voltage, and will ensure correct operation and preheat
current for the lamp. The two power MOSFETs T1, T2 driven by the UBA2014 generate
the square wave that drives the resonant tank.
The performance of the MOSFETs plus the resonant tank, should be such that at
minimum frequency, the UBA2014 can generate (fmin), and output approximately 10 %
more than the required operating power for the lamp. This allows the feedback control
system enough margin to ensure proper operation. The coil should not saturate at the
maximum ignition voltage allowed by the overvoltage protection circuit. The choice of
capacitor C22 should be one with low dielectric losses at 50 kHz.
Capacitor C20 is used for DC blocking. Its value should be such that there is minimum
possible ripple voltage. A capacitor of 68 nF is suitable for most ballasts. Resistor R18 is
used to avoid striation.
4.2 Over voltage/no ignition protection sub circuit
The small signal voltage input to the LVS at pin 13 is derived from the voltage on the lamp
connector via a voltage reduction divider circuit comprising C8, C17, R20, R5 and D4.
4.3 Feedback control loop for lamp power sub circuit
The voltage across resistor R14 due to the lamp current is applied to the CSN pin. The
input to the CSP pin is obtained from the reference voltage of 2.95 V via the dimming
combination of potentiometer R4 and resistor R3.
Resistor R8 and capacitor C2 filter any HF noise from the CSN pin input. Resistors R8
and R2 have the same value to cancel out bias current offset in the error amplifier.
4.4 VDD supply sub circuit
The VDD supply uses components Z1, D1, C6, C10 during lamp operation. During
start-up, the resistors R1, R10 raise VDD until Vstart (if a tube is inserted). In this way, the
ballast will restart itself after the tube is replaced.
Adaptive non-overlap and Capacitive mode are controlled via resistor R16.
4.5 UBA2014 ballast controller configuration components
Timing capacitors C13, C14, C15 and reference resistor R12 (at pins 2, 3, 1 and 4
respectively) are required for correct circuit operation (see Table 1 for functional details).
4.6 Resonant tank values for series resonant (TL5/TL8 lamps)
Figure 3 is a simplified circuit set-up for the lamp, showing the resonant capacitor, resistor
and inductor. A set of suggested values for the most commonly used TL5 and TL8 lamp
families is given in Table 2.
Figure 4 shows a simplified circuit set-up for the lamp with inclusion of a PTC thermistor.
Table 3 gives a set of suggested values.
AN10872
Application note
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Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
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AN10872
NXP Semiconductors
TL application with UBA2014
For some burners it is not possible to find a capacitor value whereby the voltage at the
burner is not too high during preheat, where there is sufficient preheat current, and not too
much current through the filament during lamp operation. For these burners a circuit with
a PTC as in Figure 4 can be used.
T1
Lres
1
2
A1
VPFC
A2
T2
+
V1
lamp
TLD36W
B1
Rsense
Cres
B2
3
4
DC blocking
019aaa051
Fig 3.
Simplified TL lamp series resonant circuit
Table 2.
Lamp
Lres
(mH)
Cres
(nF)
fpreheat Rsense
(kHz) (Ω)
Vbus
(V)
Preheat
current
(RMS)
(mA)
Vlamp
during
preheat
(V)
Preheat
time tph
(s)
TLD 36 W
1.9
8.2
70
1
400
600
230
1.7
TLD 58 W
1.4
10
60
0.82
400
700
170
1.7
TL5 HE 14 W
3.9
5.6
54
3.3
400
225
180
1.5
TL5 HE 21 W
3.7
5.6
54
3.3
400
225
180
1.5
TL5 HE 21 W
4.0
3.9
58
3.3
400
225
230
1.5
TL5 HE 35 W
4.0
3.9
58
3.3
400
225
230
1.5
TL5 HO 39 W
2.0
10
52
1
400
560
240
1.5
TL5 HO 49 W
2.6
6.8
52
2.2
400
370
240
1.5
TL5 HO 54 W
1.5
10
55
0.75
400
800
330
1.5
[1]
AN10872
Application note
Suggested resonant tank values for different lamp types[1]
Frequency for nominal power = 42 kHz.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
11 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
Lres
1
2
A1
A2
RT1
PTC
Cres1
Θ
lamp
TLD36W
B1
B2
3
Cres2
4
DC blocking
019aaa052
Fig 4.
TL lamp series resonant circuit with PTC thermistor
Table 3.
Suggested values for resonant tank for different lamp types
Lamp
Lres
(mH)
Cres1
(nF)
Cres2
(nF)
Rsense Vbus
(Ω)
(V)
Preheat
current
(RMS)
(mA)
Vlamp
PTC
during type
preheat
(V)
Preheat
time tph
(s)
TLD 18 W
2.3
22
15
1.2
400
530
180
150E
1.7
TLD 32 W
2.2
22
12
0.82
400
610
280
150E
1.7
4.7 Preheat circuit
The preheat current through the electrodes and the lamp capacitor is controlled by the
preheat current sensor circuit (PCS, pin 8 of the controller, see also Figure 2), and is
determined by the values of resistors R14, R13 and R9. The controller generates a
preheat frequency so the voltage on pin 8 reaches 0.6 V peak at the end of the lower gate
drive MOSFET ‘on time’.
The RMS value of a sine wave shape current, is the peak divided by √2 for a triangle √3.
In most cases, as short as possible a preheat time is chosen so that the current will be
close to a sine wave. In the example of Figure 2 the peak current is 0.788 A giving an
RMS preheat current of 0.56 A.
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
12 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
4.8 Feedback loop control
VPFC
10
GH
T1
L1
1.9 mH
UBA2014
6
GL
T2
C24
100nF
−
AVERAGE
CURRENT
SENSOR +
R8
16 CSN
8.2 kΩ
15 CSP
lamp
TLD36W
14
VREF
R4
1 MΩ
C2
12 nF
R14
1Ω
C23
R3
220 kΩ
100nF
C3
1 nF
R2
8.2 kΩ
R18
180 kΩ
C20
68 nF
019aaa053
Fig 5.
LC tank with signals CSN and CSP
The lamp power can be controlled by the ballast frequency. The feedback control loop
inside the UBA2014 adjusts the frequency so that the voltage at the CSN pin is equal to
the voltage on the CSP pin. The UBA2014 control loop regulates the current, so there is a
linear relationship between the voltage on pin CSP and the lamp current.
Resistor R8 (recommended value 8.2 kΩ), and capacitor C2 (recommended value 12 nF)
form a low pass filter which results in a DC voltage for the CSN pin. The circuit can use
either a potentiometer or fixed resistors for dimming. Vref is divided to provide the voltage
for CSP that matches the voltage on Rsense at the desired dimming level. The nominal
voltage on pin CSN is equal to the lamp current times Rsense, therefore, for full operational
lamp power, the voltage at the CSP pin must be equal to this voltage.
Care must be taken to ensure that there is some allowance for component tolerance on
fmin, so the nominal operating frequency should be about 3 kHz to 5 kHz above fmin.
The frequency at which the lowest dimming level is reached, should be lower than fmax. If
it is not, the L and C values must be changed. The values in the Table 2 and Table 3 will
ensure dimming down to 10 %.
Taking the L, C and Vbus (DC) values from the T8 36 W lamp example of Figure 2
(L = 1.9 mH, C = 8.2 nF, Vbus (DC) = 400 V respectively), a power versus frequency graph
can be calculated as shown in Figure 6. 10 % dimming is reached below fmax and
operating power is reached just above fmin.
AN10872
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
13 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
019aaa054
60
lamp
power
(W)
400
l
(mA)
(1)
45
300
(2)
30
200
15
100
0
0
40
50
60
70
f (Hz)
(1) Power.
(2) Current.
Fig 6.
Power and current as functions of frequency (series resonant)
4.9 VDD supply and Capacitive mode protection
4.9.1 IC voltage supply (see Figure 7)
Before start-up, the VDD supply capacitor C7, is charged via the start-up resistors, R1,
R10 (Figure 2) up to the DC bus voltage. The IC circuit action begins when the supply
voltage exceeds VDD(start). The half-bridge starts to switch, and the IC is supplied via the
dV/dt capacitor C6, connected to the half-bridge. The value of this capacitor is determined
by the MOSFETs used. To drive larger MOSFETs, the IC will require a greater supply
current, which in turn requires a larger dV/dt capacitor. However, if the dV/dt capacitor is
too large, the half-bridge may be hard-switching at the higher frequencies. This capacitor
also helps to reduce the reactive current flow through the bulk diode of the MOSFET into
the buffer capacitor, and then back via the Ron of the MOSFET. In most use cases, a
capacitor of between 1 nF and 1.5 nF is a good compromise. Fine tuning is done by
simulation or experimentation.
As there can be an initial high voltage overload of the start-up resistors, if Surface
Mounted Devices (SMD) are used, the voltage should be reduced by a factor of 2 or 3.
The maximum permissible voltage overload of a typical 0805 size SMD resistor is 200 V.
The current through the dV/dt capacitor C6, is fed to the VDD supply capacitor via diode
D1. This device should have a fast recovery time. A suitable type would be the 1N4148 or
BYD77D. The voltage is clamped by a 0.5 W Zener diode, Z1.
Typically during ignition, more power will be pulled from the VDD supply capacitor C7, than
is put in, so when MOSFETs with a relative large gate capacitance are used, the value of
this capacitor must be increased. A typical value of 330 nF 25 V is generally sufficient.
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TL application with UBA2014
VPFC
9 FVDD
D1
BYD77D
C5
100 nF
10 GH
BOOTSTRAP
HIGH SIDE
DRIVER
T1
IRF820
11 SH
C6
1.2 nF
VDD 7
SUPPLY
LOW SIDE
DRIVER
6 GL
T2
IRF820
C10
5.6 nF
Z1
12 V
C7
330 nF
UBA2014
R14
1Ω
R16
1.5 Ω
019aaa055
Fig 7.
IC supply circuit
4.9.2 Capacitive mode
If the load (resonant tank plus lamp), monitored by the half-bridge (voltage and
frequency), is sensed to be capacitive, the body diode of one of the MOSFETs is
conducting current at the moment the other MOSFET is switched on (see Figure 8d).
Capacitive mode operation of the resonant tank will cause damage to the ballast.
Capacitive mode (even with a well designed ballast) can occur when the input voltage is
too low (failure of the PFC circuit or the direct rectified mains), or because of a lamp
failure. The UBA2014 is designed to detect Capacitive mode and prevent damage caused
as a result.
The Capacitive mode detection with the UBA2014 is as follows:
• After the preheat phase, the signal RACM across resistor R16 (Figure 2), (input at pin
ACM) gives information about the switching behavior of the half-bridge.
• Capacitive mode (see Figure 8) is only detected in the ignition or burn states (not
during preheat), when one of the following error situations occur:
– The voltage on the ACM pin does not exceed the +100 mV at any time during the
non-overlap between LS off and HS on,
– The voltage on the ACM pin does not go below −100 mV during the non-overlap
time between HS off and LS on,
• The frequency will immediately increase to the maximum, bringing back the Inductive
mode condition, and thereby avoiding component damage in the application.
Figure 8 shows the possible operating modes of the half-bridge.
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HS gate
LS gate
GH
GL
HS gate
LS gate
GH
GL
HS/LS FET
LS diode
lind
inductive
HS/LS FET
LS diode
inductive
lind
HS/LS FET
HS diode
normal
inductive mode
half-bridge
voltage
HS/LS FET
HS diode
in-phase
hard switching
half-bridge
voltage
+ 100 mV
+ 100 mV
VACM
− 100 mV
VACM
− 100 mV
019aaa075
019aaa056
a. Normal/good - Inductive mode
b. Inductive mode - hard switching
HS gate
LS gate
HS gate
LS gate
GH
GL
GH
GL
HS/LS FET
LS diode
HS/LS FET
LS diode
lnductive
lind
lind
capacitive
HS/LS FET
HS diode
HS/LS FET
HS diode
half-bridge
voltage
inductive mode
hard switching
half-bridge
voltage
capacitive mode
hard switching
+ 100 mV
+ 100 mV
VACM
VACM
− 100 mV
− 100 mV
019aaa076
019aaa074
c. Indeterminate/interim situation
Fig 8.
d. Capacitive mode
Half-bridge modes of operation
The gate drive signals are GL (pin 6) and GH (pin 10). The half-bridge voltage VRpre is the
voltage at the intersection of the two MOSFETs is the ACM input, across sense resistor
R16 (see Figure 2 “Application diagram: series resonant topology”).
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The normal/good Inductive mode of operation is shown In Figure 8a. The adaptive
non-overlap timing of this IC will switch on the power MOSFETs when V RACM returns to
zero. This is a unique feature of this IC. Other controllers have a fixed non self adaptive
dead time. With the adaptive non overlap, the MOSFETs are switched on at the optimal
time to reduce the current through the body diode to a minimum.
In Figure 8b the circuit is still in Inductive mode, but with very small coil energy during
non-overlap, making it impossible to pull the half-bridge point from ground level to the
DC-supply rail or back. This causes hard-switching.
The situation shown in Figure 8c cannot occur due to the adaptive non-overlap timing.
The moment of switching is determined by either the crossing of the positive pulse at the
ACM pin through zero, or at the end of the minimum non-overlap time, when the minimum
non-overlap time has not yet been reached.
Figure 8d shows the Capacitive mode. A voltage pulse at V RACM is present during the
low to high and high to low transition, but only after the gate drive has become active, not
during the dead time.
The typical value of RACM is 1.5 W. In designs with a high bus voltage (multiple lamp in
series may run at voltages of > 500 V), and MOSFETs with a high gate drive capacitance
(requiring a higher charge pump capacitor value for VDD generation), the value of RACM
should be reduced, to avoid exceeding the IC’s maximum rating during the ballast
start-up.
4.10 Choosing values for the UBA2014 timing components
4.10.1 Preheat (Pin 1)
The preheat time has to be selected to meet the requirements of the lamp. Typical times
are 1.5 s to 1.7 s for a series resonant topology as shown in Figure 3 and 1 s to 1.2 s for
the inductive heating topology as described in Section 9.
The value for the capacitor C15 between pin 1 (CT) and ground can be calculated by the
formula in the data sheet and the pin description, see Table 1.
4.10.2 CSW (Pin 2)
The value of the CSW capacitor C13 has to be chosen to meet conflicting requirements. It
must be large enough for the resonant tank to build up the ignition voltage and the stability
of the control loop. It must also be a small enough value to avoid visible fluctuations in the
lamp current.
A value of 220 nF will be adequate for most applications. For deep dimming applications
an RC network can be used instead of a single capacitor (see an example drawing in
Section 9), to increase the small signal loop response time. It is advised to keep VCSW
10 % below 2.7 V in order to have the loop regulating at nominal lamp power.
4.10.3 CF (Pin 3)
Capacitor C14 determines CF fmin and fmax. The typical value of 100 pF will give an fmin of
40 kHz and an fmax of 100 kHz.
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4.10.4 IREF (Pin 4)
The value of resistor R12 (IREF) must be 33 kΩ. This value is critical to internal
voltages/currents and must not be changed.
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5. Start-up sequence states
The sequence for correct ballast operation as shown in Figure 9 is:
1. Preheat
2. Ignition
3. Operation
The UBA2014 has a built in state machine to match this.
VDD = 0
RESET STATE
VDD < VDD(rst)
- LOW-SIDE OFF, HIGH-SIDE OFF
- VREF OFF
- DISCHARGE CF, CT
- RESET POWERDOWN AND PREHEAT
COUNTER
VDD > VDD(rst)
VDD < VDD(rst)
VDD < VDD(rst)
START-UP STATE
- HIGH-SIDE OFF > AFTER ON-TIME
- LOW-SIDE OFF
- DISABLED: ACS, ANT, CMD, LVS, PCS
PRT, VCO
- DISCHARGE CF, CT
VDD > VDD(start)
VDD < VDD(stop)
POWERDOWN STATE
PREHEAT STATE
- VREF OFF
- DISABLED: ACS, ANT, CMD, LVS, PCS
PRT, VCO
- HIGH SIDE OFF > AFTER ON-TIME
- LOW SIDE OFF
- VDD LIMITED TO VDD(clamp)
- VREF ON
- ENABLED: ANT, LVSm, PCS, PRT, VCO
- DISABLED: ACS, LVSf, CMD
- FREQUENCY REGULATED BY PCS
HOLD STATE
- HIGH SIDE OFF > AFTER ON-TIME
- LOW SIDE OFF
- VREF OFF
- DISABLED: ACS, ANT, CMD, LVS, PCS
PRT, VCO
- DISCHARGE CF, CT
VDD < VDD(start)
end preheat time
IGNITION STATE
ignition failed
- ENABLED: ANT, CMD, PRT, LVSm/f, VCO
- DISABLED: PCS, ACS
- FREQUENCY DOWNLOADS
MAXIMUM
FREQUENCY
VDD < VDD(stop)
ignition succeeded
CM detected
BURN STATE
lampfault detected
VDD < VDD(stop)
- ENABLED: ACS, ANT, LVSm/f, VCO, CMD
- DISABLED: PCS, PRT(STANDBY)
- FREQUENCY REGULATED BY ACS
CM detected
Fig 9.
MAXIMUM
FREQUENCY
019aaa058
UBA2014 flowchart
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TL application with UBA2014
from ignition state
Vlamp > Vlamp(fail)
START IGNITION
TIMER
Vlamp > Vlamp(max)
FREQUENCY
REGULATED BY
LVS
f = fmin
Vlamp < Vlamp(fail)
STOP IGNITION
TIMER
timer ended and
Vlamp > Vlamp(fail)
CONCLUSION:
IGNITION
SUCCEEDED
CONCLUSION:
IGNITION
FAILED
back to burn state
to powerdown state
019aaa059
Fig 10. Ignition detection (LVS, ignition state)
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5.1 Reset state
After a negative DC voltage is applied to the rail, capacitor C7 (CVDD) connected to the
VDD pin is charged through start-up resistors Rstart (R1 in Figure 2) and RVDD (R10 in
Figure 2). With the configuration as shown in Figure 2, this will only occur if a lamp
(cathode) is present. First the digital supply is initially established. If the voltage at the VDD
pin is below the reset level (VDD(rst)), the logic, the power-down and the preheat counter
are reset. In the rest and start-up of the circuit both half-bridge MOSFETs are
non-conductive.
If the UBA2014 is suddenly stopped due to tube arcing detection, the VDD can be pulled
down via a resistor of 100 Ω to allow the state machine time to shut down safely without
causing cross conduction.
5.2 Start-up state
The voltages of capacitors C15 (CT, pin 1) and C13 (CF, pin 3) are kept at zero during the
start-up state. Capacitor C13 (CSW, pin 2), which is the input of the voltage controlled
oscillator, is actively discharged, ensuring a defined start of the frequency sweep at the
maximum frequency.
In the start-up state, the reset has ended and the IC is ready to start. If the low voltage
supply at the VDD pin rises further and reaches the value of VDD(start), the internal analog
supply is activated and the circuit will begin to oscillate.
5.3 Preheat state
Oscillation starts with a long first stroke of approximately 50 μs on the lower half-bridge
MOSFET to ensure that the bootstrap capacitor is fully charged.
The preheat time begins at the moment the circuit starts oscillating. Capacitor C13 (CSW)
is charged from a constant source-current controlled by the preheat current sense block,
thereby decreasing the frequency until the preheat voltage level at the PCS pin is
exceeded.
The preheat current sensor then starts to discharge capacitor C13 (CSW) with an average
current that is equal to the opposite of the charge current, thus raising the frequency with
the same sweep rate. The preheat is therefore regulated around a predefined level until
the end of the preheat time. During this time, the average current sensor circuit is
disabled.
There is an internal filter of 30 ns at the PCS pin to improve immunity from hard switching
noise or from ringing by parasitic inductances.
5.4 Ignition state
After the preheat time, the ignition state is entered and the frequency sweeps further
down, due to charging of the capacitor at the CSW pin with an internally fixed current.
During this continuously decreasing frequency, the circuit approaches the resonance
frequency of the load. This will cause a high voltage across the lamp, which will then
normally ignite.
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The ignition voltage of a lamp is normally above the Vlamp(fail) level. If the lamp voltage
passes the Vlamp(fail) level the ignition timer is started (see Figure 11a). The lamp can also
ignite without exceeding the Vlamp(fail) level (see Figure 11b)
Lamp ignition is detected by the lamp voltage sensor (LVS). When a lamp ignites, the
voltage normally drops from a value at ignition, to a much lower burn level, and so the
voltage at the LVS pin drops below the Vlamp(fail) level again. The circuit will enter the burn
state.
This decision process is graphically represented in Figure 9. If the lamp ignites after
preheat, and before the Vlamp(fail) level is reached, the voltage at the CS pin will continue
to increase until the minimum frequency is reached. The logic will now assume that the
lamp has ignited, and the circuit will enter the burn state. This can result in a small light
flash.
preheat state
Vlamp
ignition state
Vlamp(max)
burn detection
Vlamp(fail)
burn
timer
start timer
on
off
time
019aaa057
a. failure mode during ignition
preheat state
Vlamp
ignition state
Vlamp(fail)
burn state
timer
on
off
time
019aaa909
b. normal ignition
Fig 11. Ignition states
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5.5 Burn state
During the Burn state the Average Current Sensor (ACS) is enabled. The load current,
which reached a maximum during ignition, will decrease, and therefore so will the
averaged voltage across Rsense. As soon as this voltage, measured at the input CSN pin,
reaches the reference level at CSP pin, the control loop is closed, and the average current
sensor will take over the control of the load current. By comparing both inputs, the ACS
controls/changes the frequency of the oscillator and thereby the half-bridge.
The averaged voltage across Rsense is a measure of the power dissipated in the system. If
we assume negligible power losses in the switches and the lamp coil, the power
dissipated in the lamp can therefore be controlled by regulating the average current
through Rsense. This current can be varied by changing the half-bridge frequency, thereby
changing the operating point on the LC curve and so the load current/lamp power.
Dimming is possible by decreasing the reference voltage on the CSP pin of the ACS.
During the ramp down in frequency for ignition, the state machine shown in Figure 10 is
active to avoid lamp over voltage.
The lamp voltage is monitored during lamp operation, and the UBA2014 will be switched
to standby if the lamp fails (see Figure 12).
In Figure 2 an example LVS circuit can be seen. C6 and C7 first divide the voltage down
by a factor of 20, after which the voltage is divided again by low pass filter R20, R5 and
C19. The values of the filter components are chosen so that a voltage of 1.5 V is present
at pin LVS at the maximum ignition voltage of the burner.
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from burn state
Vlamp > Vlamp(fail)
START IGNITION
TIMER
Vlamp > Vlamp(max)
CSW REGULATED
BY LVS
Vlamp < Vlamp(fail)
timer ended and
Vlamp > Vlamp(fail)
STOP IGNITION
TIMER
CONCLUSION:
NO LAMP FAULT
CONCLUSION:
LAMP FAULT
DETECTED
back to burn state
to power-down state
019aaa060
Fig 12. Lamp fault detection (LVS, burn state)
5.6 Power down state
The power-down state is entered if the lamp voltage becomes too high for too long a time
period (one CT timer tick) during the ignition state or burn state. When the lamp fails to
ignite or its voltage becomes too high during lamp operation (symmetrical aging) the
UBA2014 stays in the power-down state until a power cycle has taken place.
6. EOL detection/protection
6.1 IEC requirements
When a lamp reaches its EOL, a tube can show electrical characteristics that can cause
overheating of the filament and/or damage to the ballast. Ref. 1 requires the proper
operation of the ballast under the following conditions.
1. The lamp, or one of the lamps, is not inserted.
2. The lamp does not start because one of the electrodes is broken.
3. The lamp does not start, although the electrode circuits are intact (de-activated lamp).
4. The lamp operates, but one of the electrodes is de-activated or broken (rectifying
effect).
5. A short circuit of the starter switch, if present (not applicable for an HF ballast).
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List item 1, List item 2 and List item 3 are already covered by the standard application
schematic (Figure 2). The rectifying effect (List item 4) can best be understood by
reference to the EOL lamp replacement schematic, Figure 13.
List item 5 is not applicable.
ballast output
ballast output
REOLL(t)
Rarc(t)
Θ
Θ
Rlamp
Rlamp
ballast output
ballast output
019aaa061
Fig 13. EOL lamp replacement circuit for arcing and rectification
For simulating the end of lamp life effects, Ref. 1 describes three tests:
• Asymmetric pulse test
• Asymmetric power dissipation test
• Open filament test.
6.2 Bringing the UBA2014 into power-down
The UBA2014 can be brought into standby state by putting a 0.8 V pulse for one CT timer
tick (about 150 ms depending on the preheat time) on its LVS input pin. The LVS pin
detects and protects against “no ignition” failure, and additionally EOL detection is added.
The UBA2014 can also be stopped instantly by pulling VDD to ground. Use a resistor of
about 100 Ω so the IC is not allowed to finish the shutdown procedure via the hold state as
described in the flowchart (Figure 9).
This immediate power down without timeout can be used for arcing protection if the lamp
connector is made of lower quality heat resistive plastic, for example. The UBA2014 will
restart though if the filament used for lamp detection (R1, R10 path shown in Figure 2) is
still in place. What happens is that after this instant stop, and the consequent restart, the
broken lamp will not ignite and subsequently the UBA2014 will run into time-out and enter
the power-down state. The only way to leave the power down state is via a power cycle.
6.3 UBA2014 EOL circuits
There are many options for detecting the EOL of a lamp. This application note only
features circuits for some of the many implementations available.
Example circuits:
• Circuit based on rectification (using DC blocking voltage).
• Circuit based on arcing/restriking and over power
• Circuit based on over power
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6.4 Overpower detection
The voltage on the sense resistor, used for preheat current sensing (R14 in Figure 2 and
R5 in Figure 21), can also be used to detect overpower. With a single diode and a resistor
added to the standard application diagram, the ballast can be switched off if the current
through this sense resistor is too high for too long. This overpower protection protects the
ballast electronics, but is not guaranteed to prevent local overheating of a filament (see
Figure 17).
6.5 Rectification detection
VPFC
T1
lamp 1
lamp 2
Lres
T2
DETECTOR
CIRCUIT
Cres
C2
019aaa062
Fig 14. EOL DC blocking capacitor voltage
The voltage on the DC blocking capacitor indicates the asymmetric power by an
asymmetric voltage across C2 (see Figure 14).
If the lamp has a rectifying effect (EOL), the voltage on DC blocking capacitor C2 will no
longer be VPFC / 2, but higher or lower. This voltage can be monitored with a circuit (see
Figure 15). If the DC blocking capacitor voltage becomes too high or low, the ballast
switches off.
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lamp
B1
3
B2
4
L3S2
25 mH
broken lower
filament detection
C32
33 nF, 100 V
R3
100 kΩ
D3
VPFC(400 V)
1N4007
rectification EOL port
BC558B
R2
100 kΩ
47 kΩ
68 nF, 400V
blocking
capacitor
Vref (3 V)
1N4007
rectification
EOL port
D1
1N4935
15 kΩ
BC558B
47 kΩ
R7
1.4 kΩ
15 kΩ
LVS
019aaa063
Fig 15. UBA2014 rectification EOL detection circuit
Figure 15 shows that the DC blocking voltage (normally VPFC / 2), is divided with two
resistors to 3 V. The circuit in Figure 15 is for a 400 V VPFC. If a different PFC voltage is
used, the two resistors values should be chosen according to Equation 1
V PFC × R1
--------------------------------- = 3V
2 × ( R1 + R2 )
(1)
Two transistors monitor the divided DC blocking capacitor voltage, and if it rises above
3.7 V, or falls below 2.3 V, the circuit will trigger the IC protection. For a 400 V operated
VPFC, this means the “window “is between 170 V and 230 V.
The asymmetrical power as defined in Ref. 1 is given in Equation 2
abs ( 2 × V CDC – V bus ) × I lamp
P EOL = -----------------------------------------------------------------------2
(2)
For T5 tubes 7.5 W and for T4 5 W maximum asymmetrical power is allowed. No IEC
specification exists for T8 tubes, but 10 W is a good limiting value.
The same circuit as in Figure 15 can be used with a difference reference voltage that can
be made easily from VDD to get a smaller detection window.
It is difficult to acquire/prepare a tube with rectification. For this purpose the IEC has made
a test diagram, see Figure 16.
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C
D
R1
W
R3
lamp 1
D1
G
B
D2
R2
S1
A
F
E
019aaa064
Fig 16. IEC EOL simulation circuit
6.6 Arcing/restriking detection
A lamp that is arcing/restriking will show spikes on the lamp voltage. Monitoring these
spikes is the easiest way to detect arcing.
optional
restrike/arcing protection
R57
D34
1 kΩ
1N4148
(1)
D27
D7
R46
33 V
1N4148
10 kΩ
LVS
C78
10 nF
C77
12 nF
R52
D51
C81
220 kΩ
1N4148
330 pF, 1 kV
Vref (3 V)
Q6
BC858B
R58
470 kΩ
C25
270 nF
LVS
lamp voltage
R53
10 kΩ
D12
1N4148
C82
6.8 nF, 50 V
019aaa065
(1) R14 (see Figure 2)
Fig 17. Arc/restrike detection combined with overpower
The lamp voltage is connected to C81. It is first divided by C81 and C82 and then divided
again by R52, R53 to match the range of the UBA2014 LVS pin. The circuit D27, D7 and
R46 detects large spikes and charges C25. Resistor R58 discharges C25. If there are too
many restrikes (or arcing) in too short a time, the ballast will go to into standby.
An alternative is to put the Zener diodes D14 and D6 in series with the resistor R24, so the
circuit with Q5, R34, R38 and C24 is then not required. The time constant of C41, R27
should not be changed so much that the control loop inside the UBA2014 (used to limit the
lamp voltage in case of no ignition), does not work properly.
6.6.1 Additional tests
In addition to more complex circuits from the IEC, one very simple test should be done
with each new design. This test is to disconnect the lamp electrode wires one by one. This
should be done at start-up, and during lamp operation. As a result, either the lamp keeps
on running without damage to the ballast, or overheating of the electrodes, or the ballast
switches into low power Standby protection mode.
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7. Debugging a UBA2014 ballast
If a prototype ballast PCB application is switched on at full power, any design or layout
soldering error can cause a large part of the circuit to be destroyed.
Limiting the power by using a current limited DC supply will only partly help as there is a
minimum amount of power needed for tube ignition. This is more than enough power to
damage the board.
The following steps that can be used to progressively debug a newly designed ballast
PCB.
1. Connect a 13 V Zener (13.6 V, two times 6.8 V) across the UBA2014 VDD supply. Use
a 100 mA current limited 20 V lab supply to feed VDD via a 470 Ω resistor. See
Figure 18. The UBA2014 should be seen to start running at around 100 kHz.
Depending on the protection circuit, it can stop after preheat or continue running. The
gate drive on the low side MOSFET should be present.
Remark: Do not continue with the following steps until this is observed.
2. Attach the 20 V DC supply to the half-bridge (instead of the PFC voltage). A square
wave should be seen on the half-bridge and on the drive of both MOSFETs. The
current in the resonant tank (even though small) can be measured.
3. Optional - The preheat capacitor can be grounded to CT (pin 1). The UBA2014 will
stay in Preheat mode (the Capacitive mode protection is disabled in this state). Apply
a voltage from a lab supply of 0.5 V to CSW (pin 2) via a 4.7 KΩ resistor. Remove the
20 V lab supply and the 470 Ω resistor mentioned in List item 1.
Attach a high voltage scope probe on the lamp connector (LC resonance point).
Apply the full DC VPFC voltage. The half-bridge should be observed running at
approximately 80 kHz, and with some preheat current in the burner.
4. Using a lab supply, the UBA2014 frequency can be changed, the lamp can even be
ignited, but extreme care must be taken to increase the frequency slowly, so that if the
lamp does not ignite, the maximum voltage of the resonance capacitor is not
exceeded. The frequency must not be increased to below the resonance frequency,
as this will cause Capacitive mode hard switching, and possible subsequent damage
to the ballast. To avoid such a situation, the resonance capacitance should be
doubled for this experiment. With this doubled value it is safe to bring the ballast
frequency all the way down to fmin without causing any damage.
AN10872
Application note
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Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
29 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
470 Ω
VDD
lab supply
10
GH
T1
GL
T2
7
UBA2014
13 V
C1
6
OSCILLOSCOPE
019aaa066
Fig 18. Debugging circuit
8. PCB design and layout guidelines
The following design considerations must be observed to ensure a good PCB layout.
1. Keep the high current loops short (see Figure 19).
2. Do not use the same ground PCB track that carries the large signal current for CT,
CSW, CF and IREF (pins 1 to 4). This will inject noise into these pins, and that can
cause a malfunction. Make the connection as shown in Figure 19.
3. Place the bulk capacitor close to the half-bridge. A PFC only charges this bulk
capacitor, a resonant converter will have a current flow out but also back into the bulk
capacitor (the current through the resonant capacitor Cres is reactive current). See
Figure 19.
AN10872
Application note
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Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
30 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
VPFC
CT
CSW
CF
IREF
VREF
1
LPAR
VDD
IC1
7
9
2
10
3
11
4
6
UBA2014
14
8
12
CSN
CSP
16
13
15
5
FVDD
D1
4.7 Ω
T1
33 Ω
GH
1.5 A at ignition
for T8 36 W
LPAR
Lres
SH
load
GL
33 Ω
PCS
4.7 Ω
LPAR
T2
bulk
capacitor
ACM
lamp
Cres
LPAR
LVS
R5
1Ω
LPAR
GND
019aaa067
Fig 19. PCB layout circuit diagram
Overshoots and undershoots on gate and drain voltage should be limited in order to avoid
damage to the UBA2014 and the MOSFETs. It is advisable to leave a 25 V to 50 V margin
in the MOSFET breakdown voltage for this. So a half-bridge running on 400 V should
have 450 V MOSFETs. Figure 20 shows an example board. The large buffer capacitor is
C34 and Q2, Q3 (= T1, T2) are the half-bridge MOSFETs, on the top pins 8 to 16 of the
UBA2014T.
T1
T2
019aaa068
Fig 20. PCB: top view (partial)
8.1 Gate resistors
The gate drive circuit is an RLC series circuit. For an RLC series circuit, the condition
giving no oscillation in case of a step response, is as given in Equation 3
AN10872
Application note
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31 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
(3)
R2C2 – 4LC> = 0
The resistor R should be low enough so the gate drive does not open itself due to the
Miller capacitance. The capacitance is known from the MOSFET specification, the
inductor is the result of layout plus parasitic inductance of the MOSFET. Spice simulation
is the most effective method to achieve optimal starting component values. Measurement
is needed to verify/fine tune these values.
8.2 Coil air gap and windings
Do not place sensitive tracks, such as the ones to/from pins 1 to 4 of the UBA2014, close
to the air gap of the resonant coil. This is a very noisy area (the location of the air gap
depends on the specific coil design). Connecting the half-bridge to the inner winding of the
coil will cause less radiated emission.
8.3 High dV/dt traces
The tracks driving the MOSFETs and the half-bridge signal can have a high dV/dt
(particularly when hard switching). Leave 200 μm or more distance around these tracks to
avoid capacitive coupling (or shield them with ground).
9. Inductive mode heating
In addition to the series resonant, inductive mode heating is also commonly used.
Figure 21 shows the Inductive mode configuration with a TL8 36 W lamp. This topology is
also known (mainly in the USA) as “Voltage mode”.
The main difference with the series resonant topology is that in the Inductive mode
heating topology two secondary windings L1a and L1b are made on the resonant coil L1.
So, in series resonant it the resonant inductor is a coil, in Inductive mode a transformer.
As the secondary windings have little inductance (usually in the range 5 μH to 25 μH) the
primary winding is dominant for the resonant tank. Figure 21 includes the optional EOL
protection. The IEC requires either arcing or rectification, and either one can be used.
Capacitors are connected in series with the secondary windings, to make the transformer
a voltage transformer, rather than a current transformer.
AN10872
Application note
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Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
32 of 38
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
over power
protection
R57
D34
1 kΩ
1N4148
D27
D7
R46
33 V
1N4148
10 kΩ
C77
12 nF
D51
220 kΩ
1N4148
R53
10 kΩ
D12
1N4148
startup resistor 1
R54
R74
220 kΩ
220 kΩ
R56
2.7 kΩ
R64
15 kΩ
LVS
startup resistor 2
Rev. 01 — 9 December 2010
All information provided in this document is subject to legal disclaimers.
R16
R15
220 kΩ
220 kΩ
12 V
D10
6.8 V
VDD
C16
D29
6.8 V
CT
7
1
9
FVDD
220 nF
CSW
2
10
GH
C15
220 nF
CF
3
11
1
T1
IRFBC40LCPBF
100 nF
R48
6
4
R49
C19
33 kΩ
Vref (3 V) VREF
UBA2014
8
14
C19
10 nF
12
PCS
Vref (3 V)
D11
12 V
R59
470 kΩ
J6
R73
CSN
CSP
16
13
15
5
LVS
GND
100 kΩ
ballast controller
C80
10 nF
T6
D33
1N4148
B2
4
C79
R7
0.5 Ω
(1 W)
R65
100 kΩ
100 kΩ
R8
2.4 Ω
(0.5 W)
adaptive none
overlap sense
inductive
mode heating
R51
33 of 38
© NXP B.V. 2010. All rights reserved.
Fig 21. Application diagram: Inductive mode heating (Voltage mode)
C43
68 nF
(25 W)
R50
10 Ω
(1 W)
D31
BAS29
R96
56 kΩ
Q9
BC858C
R66
22 kΩ
R103
DC blocking
voltage
DC blocking
capacitor
D30
BAS29
C1
2.2 nF
VPFC
D28
1N4007
rectification EOL prot
for DC blocking cap
D32
1N4007
rectification EOL prot
for DC blocking cap
019aaa069
AN10872
1 kΩ
C45
220 pF
lamp current sense
1 MΩ
220 kΩ
C44
68 nF
(400 V)
CSN
R67
12 V
220 kΩ
BST82
D50
1N4148
R75
33 nF
(400 V)
R97
over power
protection
R14
1 MΩ
optional
broken lower filament
or lamp removal detection
L1b
25 mH
resonance c
1 kΩ
C38
470 nF
33 nF
(400 V)
TL application with UBA2014
R60
47 kΩ
C11
5.6 nF
R61
ACM
12 V
Vref (3 V)
B1
3
C76
8.2 nF
(1kV)
33 kΩ
C12
10 nF
A2
TLD36W
C10
1.5 nF
(1kV)
T2
IRFBC40LCPBF
L1a
25 mH
C42
2
lamp
resonance l
SH
GL
A1
D8
1N4148
L1
2 mH, 25A
100 pF
IREF
inductive
mode heating
C13
33 kΩ
C14
conector 2
R47
15 kΩ
Q7
BC858B
47 kΩ
conector 2
1
R45
47 kΩ
Vref (3 V)
1
2
R55
220 kΩ
R62
VPFC(400 V)
2
dimming
control
LVS
330 pF
(1 kV)
C82
6.8 nF
(50 V)
J5
R11
1 kΩ
Q8
BC858B
DC blocking
voltage
lamp voltage
from PFC
circuit
C17
680 nF
C25
270 nF
C81
R52
optional
rectification EOL protection
Q6
BC858B
R58
470 kΩ
LVS
C78
10 nF
Vref (3 V)
NXP Semiconductors
AN10872
Application note
optional
restrike/arcing protection
AN10872
NXP Semiconductors
TL application with UBA2014
9.1 Inductive mode preheat
A high end ballast has a short preheat time, less than 1.5 s. So, it is desirable to generate
as much preheat energy as possible given a secondary inductance and capacitance, as
this shortens the preheat time needed to fulfill the burner specifications.
Running at the maximum frequency of the UBA2014, fmax will give the highest preheat
energy (using the Inductive mode topology). The circuit around T3 in Figure 21 is optional.
It disables adaptive non-overlap during preheat, and by doing that, increases the preheat
energy, thus allowing a shorter preheat time. Inductive mode heating typically gives a
constant preheat energy, while the series resonant topology gives a constant preheat
current. Burner specifications give both energy and current values.
9.1.1 Lamp electrode operating currents
The value of the secondary inductance and capacitance determine the currents through
the electrodes during operation. These currents have a minimum, target and maximum
value of the Sum of Squares (SoS). In Figure 22 the lamp discharge current ID = ILH − ILL.
ILH
ILH = Lead High current
ID = lamp (discharge) current
ID
ILL = Lead Low current
SoS = I2LH + I2LL
ILL
019aaa070
Fig 22. Sum of Squares (SoS) definition
Table 4 lists the most commonly used T5 and T8 lamps with primary/secondary
inductance and capacitance values that will ensure operation close to the target
specifications of the tube lamps.
The polarity of the secondary windings indicated in the Figure 21 must be correct or the
SoS will be higher. The polarity does not make a difference for preheat but does
during lamp operation.
9.1.2 Lamp current measurement
The UBA2014 has a feedback control loop based on lamp current measurement. With
Inductive mode heating, the lamp current alone can be measured (with series resonant,
the sense resistor measures the lamp current plus the resonant capacitor current). As
(only) the lamp current is measured, Inductive mode heating allows deeper dimming than
series resonant.
AN10872
Application note
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Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
34 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
L1a
C42
VPFC
UBA2014
VCONTROL
T1
VCO
CSP 15
lamp
L1
L1b
T2
CSN 16
2
C79
CSW
C76
C44
D31
D30
Vsense
R50
C43
Rsense
019aaa071
Component numbers also relate to components in Figure 21
Fig 23. Current feedback control loop
The lamp current is rectified and measured across a sense resistor. The measured value
is compared with a control voltage applied to the CSP pin. The control loop changes the
half-bridge frequency until the measured voltage is equal to the control voltage. The
advised full scale input of the CSN pin is 2.5 V. Rsense is given by Equation 4:
4
R sense = -----------------------I lamp ( RMS )
(4)
After Rsense has been picked from the E series, the CSP circuit can be optimized. For
example 0 V to 10 V input the ratio of input voltage to CSP voltage can be calculated such
that at 10 V input the maximum lamp current is reached. Many operating frequencies
versus resonant tank coil and capacitor combinations are possible that will give the correct
power. Table 4 gives suggested values for various TL5 and TLD lamps. The values given
in Table 4 and shown in Figure 24 are such, that over the full lamp operation range, the
SoS is close to the SoS target. The nominal full power frequency is around 45 kHz. If
there is no need for deep dimming, a much lower secondary inductance (range 1 μH to
4 μH) and a much higher secondary capacitance (100 nF to 220 nF) can also be used.
AN10872
Application note
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Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
35 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
019aaa072
0.5
SoS
(1)
0.4
0.3
(2)
0.2
(3)
0.1
(4)
0
0
100
200
300
400
ID (mA)
(1) SoSmax
(2) SoStarget
(3) SoSactual
(4) SoSmin
Fig 24. SOS lines for the values of the TLD (T8) 36 W lamp, as shown in Table 4; C(dV/dt) (capacitance on the
half-bridge for VDD power supply) = 1 nF.
Table 4.
Suggested values for resonant tank for different lamp types
Lamp
Resonant
coil (mH)
Resonant
Secondary
capacitor (nF) inductance
(μH)
Secondary
capacitance
(nF)
Vbus (V)
Preheat
energy (J)
Preheat
time (s)
TLD 18 W
2.14
4.7
11
39
400
4
1.2
TLD 36 W
1.9
8.2
14
33
400
4.6
1.2
TLD 58 W
1.38
8.2
14
27
400
5
1.2
TLD 70 W
1.3
8.2
17
27
400
6.5
1.2
TL5 HO 24 W 2
4.7
10
33
400
3.2
1.2
TL5 HO 39 W 1.8
4.7
10
27
400
3
1.2
TL5 HO 54 W 1.3
4.7
8
33
400
3.8
1.2
TL5 HO 49 W 2.7
4.7
20
15
450
2.8
1.2
TL5 HO 80 W 1.1
8.2
15
22
400
5.8
1.2
TL5 HE 14 W 3.65
4.7
18
22
400
2.2
1.2
TL5 HE 21 W 3.56
4.7
18
22
400
2.2
1.2
TL5 HE 28 W 3.83
4.7
16
22
450
2.2
1.2
TL5 HE 35 W 3.88
4.7
16
22
480
2.2
1.2
10. References
[1]
IEC 61347-2
AN10872
Application note
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36 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
11. Legal information
11.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
11.2
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
AN10872
Application note
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
11.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 December 2010
© NXP B.V. 2010. All rights reserved.
37 of 38
AN10872
NXP Semiconductors
TL application with UBA2014
12. Contents
1
1.1
2
2.1
2.2
2.3
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.9.1
4.9.2
4.10
4.10.1
4.10.2
4.10.3
4.10.4
5
5.1
5.2
5.3
5.4
5.5
5.6
6
6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Scope and structure of document . . . . . . . . . . 3
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Structure of the application note . . . . . . . . . . . . 4
Related documents and tools . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Series resonant single lamp application
circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resonant tank. . . . . . . . . . . . . . . . . . . . . . . . . 10
Over voltage/no ignition protection sub
circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Feedback control loop for lamp power sub
circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VDD supply sub circuit. . . . . . . . . . . . . . . . . . . 10
UBA2014 ballast controller configuration
components . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resonant tank values for series resonant
(TL5/TL8 lamps) . . . . . . . . . . . . . . . . . . . . . . . 10
Preheat circuit. . . . . . . . . . . . . . . . . . . . . . . . . 12
Feedback loop control . . . . . . . . . . . . . . . . . . 13
VDD supply and Capacitive mode protection . 14
IC voltage supply (see Figure 7). . . . . . . . . . . 14
Capacitive mode . . . . . . . . . . . . . . . . . . . . . . . 15
Choosing values for the UBA2014 timing
components . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Preheat (Pin 1) . . . . . . . . . . . . . . . . . . . . . . . . 17
CSW (Pin 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CF (Pin 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IREF (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Start-up sequence states . . . . . . . . . . . . . . . . 19
Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Start-up state . . . . . . . . . . . . . . . . . . . . . . . . . 21
Preheat state . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ignition state . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Burn state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power down state . . . . . . . . . . . . . . . . . . . . . . 24
EOL detection/protection . . . . . . . . . . . . . . . . 24
IEC requirements . . . . . . . . . . . . . . . . . . . . . . 24
Bringing the UBA2014 into power-down. . . . . 25
UBA2014 EOL circuits . . . . . . . . . . . . . . . . . . 25
Overpower detection . . . . . . . . . . . . . . . . . . . 26
Rectification detection . . . . . . . . . . . . . . . . . . 26
Arcing/restriking detection . . . . . . . . . . . . . . . 28
Additional tests . . . . . . . . . . . . . . . . . . . . . . . . 28
Debugging a UBA2014 ballast . . . . . . . . . . . . 29
8
8.1
8.2
8.3
9
9.1
9.1.1
9.1.2
10
11
11.1
11.2
11.3
12
PCB design and layout guidelines . . . . . . . .
Gate resistors. . . . . . . . . . . . . . . . . . . . . . . . .
Coil air gap and windings. . . . . . . . . . . . . . . .
High dV/dt traces . . . . . . . . . . . . . . . . . . . . . .
Inductive mode heating . . . . . . . . . . . . . . . . .
Inductive mode preheat . . . . . . . . . . . . . . . . .
Lamp electrode operating currents . . . . . . . .
Lamp current measurement. . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31
32
32
32
34
34
34
36
37
37
37
37
38
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
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Date of release: 9 December 2010
Document identifier: AN10872