IDT IDT82V2048LDAG Octal t1/e1 short haul analog front end Datasheet

OCTAL T1/E1 SHORT HAUL
ANALOG FRONT END
IDT82V2048L
FEATURES
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Octal T1/E1 short haul analog front end which supports 100 Ω
T1 twisted pair, 120 Ω E1 twisted pair and 75 Ω E1 coaxial
applications
Built-in transmit pre-equalization meets G.703 & T1.102
Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 7
Low impedance transmit drivers with high-Z
Selectable hardware and parallel/serial host interface
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Hitless Protection Switching (HPS) for 1 to 1 protection without
relays
JTAG boundary scan for board test
3.3 V supply with 5 V tolerant I/O
Low power consumption
Operating temperature range: -40°C to +85°C
Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
FUNCTIONAL BLOCK DIAGRAM
One of Eight Identical Channels
LOS
Detector
RTIPn
LOSn
RCn
RDPn
RDNn
Slicer
RRINGn
Peak
Detector
TTIPn
Line
Driver
TRINGn
TCLKn
TDPn
TDNn
Waveform
Shaper
Transmit
All Ones
JTAG TAP
VDDIO
VDDT
VDDD
VDDA
TRST
TCK
TMS
TDI
TDO
Control Interface
OE
CLKE
MODE[2:0]
CS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
D[7:0]/AD[7:0]
MC[3:0]/A[4:0]
Register
File
Clock
Generator
MCLK
G.772
Monitor
Figure-1 Block Diagram
July, 2005
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
 2005 Integrated Device Technology, Inc.
DSC-6527/1
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
IDT82V2048L
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TDP7
TCLK7
LOS6
RDN6
RDP6
RC6
TDN6
TDP6
TCLK6
MCLK
MODE2
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
VDDIO
GNDIO
VDDD
GNDD
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
TCLK1
TDP1
TDN1
RC1
RDP1
RDN1
LOS1
TCLK0
TDN4
RC4
RDP4
RDN4
LOS4
OE
CLKE
VDDT4
TTIP4
TRING4
GNDT4
RTIP4
RRING4
GNDT5
TRING5
TTIP5
VDDT5
RRING5
RTIP5
VDDT6
TTIP6
TRING6
GNDT6
RTIP6
RRING6
GNDT7
TRING7
TTIP7
VDDT7
RRING7
RTIP7
LOS7
RDN7
RDP7
RC7
TDN7
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TDP4
TCLK4
LOS5
RDN5
RDP5
RC5
TDN5
TDP5
TCLK5
TDI
TDO
TCK
TMS
TRST
IC
IC
VDDIO
GNDIO
VDDA
GNDA
MODE0
CS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
TCLK2
TDP2
TDN2
RC2
RDP2
RDN2
LOS2
TCLK3
TDP3
PIN CONFIGURATIONS
Figure-2 TQFP144 Package Pin Assignment
2
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
TDN3
RC3
RDP3
RDN3
LOS3
RTIP3
RRING3
VDDT3
TTIP3
TRING3
GNDT3
RRING2
RTIP2
GNDT2
TRING2
TTIP2
VDDT2
RTIP1
RRING1
VDDT1
TTIP1
TRING1
GNDT1
RRING0
RTIP0
GNDT0
TRING0
TTIP0
VDDT0
MODE1
LOS0
RDN0
RDP0
RC0
TDN0
TDP0
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
D
E
F
G
INDUSTRIAL TEMPERATURE RANGES
A
B
C
H
J
K
L
M
N
P
1
RC7
TCLK
7
RC6
TCLK
MCLK
6
MC
1
D6
D7
TCLK
1
RC1
TCLK
0
RC0
1
2
RDP
7
TDP
7
RDP
6
TDP
6
MODE
2
MC
2
D0
D2
D5
MODE
1
TDP
1
RDP
1
TDP
0
RDP
0
2
3
RDN
7
TDN
7
RDN
6
TDN
6
LOS
6
MC
3
MC
0
D1
D4
LOS
1
TDN
1
RDN
1
TDN
0
RDN
0
3
4
VDDT
7
VDDT
7
VDDT
6
VDDT
6
LOS
7
A4
D3
LOS
0
VDDT
1
VDDT
1
VDDT
0
VDDT
0
4
5
TRING
7
TTIP
7
TRING
6
TTIP
6
TTIP
1
TRING
1
TTIP
0
TRING
0
5
6
GNDT GNDT GNDT GNDT
7
7
6
6
GNDT GNDT GNDT GNDT
1
1
0
0
6
7
RTIP
7
RRING
7
RTIP
6
RRING
6
8
RTIP
4
RRING
4
RTIP
5
RRING
5
9
GNDT GNDT GNDT GNDT
4
4
5
5
10
TRING
4
TTIP
4
TRING
5
TTIP
5
11
VDDT
4
VDDT
4
VDDT
5
VDDT
5
LOS
4
TMS
GNDIO GNDA
CS
12
RDN
4
TDN
4
RDN
5
TDN
5
LOS
5
TDI
TRST
MODE
0
13
RDP
4
TDP
4
RDP
5
TDP
5
CLKE
TDO
IC
IC
14
RC4
TCLK
4
RC5
TCLK
5
OE
TCK
A
B
C
D
E
F
VDDIO VDDD
GNDIO GNDD
RRING
1
RTIP
1
RRING
0
RTIP
0
7
RRING
2
RTIP
2
RRING
3
RTIP
3
8
GNDT GNDT GNDT GNDT
2
2
3
3
9
TTIP
2
TRING
2
TTIP
3
TRING
3
10
LOS
3
VDDT
2
VDDT
2
VDDT
3
VDDT
3
11
TS
2
LOS
2
TDN
2
RDN
2
TDN
3
RDN
3
12
TS
1
INT
TDP
2
RDP
2
TDP
3
RDP
3
13
TS
0
SDO
TCLK
2
RC2
TCLK
3
RC3
14
J
K
L
M
N
P
IDT82V2048L
(Bottom View)
VDDIO VDDA
G
H
Figure-3 PBGA160 Package Pin Assignment
3
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
1
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
TQFP144
Description
PBGA160
Transmit and Receive Line Interface
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
Analog
Output
Analog
Input
45
52
57
64
117
124
129
136
N5
L5
L10
N10
B10
D10
D5
B5
46
51
58
63
118
123
130
135
P5
M5
M10
P10
A10
C10
C5
A5
48
55
60
67
120
127
132
139
P7
M7
M8
P8
A8
C8
C7
A7
49
54
61
66
121
126
133
138
N7
L7
L8
N8
B8
D8
D7
B7
TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7
These pins are the differential line driver outputs. They will be in high impedance state if pin OE is low or
the corresponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In
host mode, each pin can be in high impedance by programming a ‘1’ to the corresponding bit in register
OE(1).
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7
These pins are the differential line receiver inputs.
1. Register name is indicated by bold capital letter. For example, OE indicates Output Enable Register.
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IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
Description
PBGA160
Transmit and Receive Digital Data Interface
TDP0
TDP1
TDP2
TDP3
TDP4
TDP5
TDP6
TDP7
37
30
80
73
108
101
8
1
N2
L2
L13
N13
B13
D13
D2
B2
TDN0
TDN1
TDN2
TDN3
TDN4
TDN5
TDN6
TDN7
38
31
79
72
109
102
7
144
N3
L3
L12
N12
B12
D12
D3
B3
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
36
29
81
74
107
100
9
2
N1
L1
L14
N14
B14
D14
D1
B1
40
33
77
70
111
104
5
142
P2
M2
M13
P13
A13
C13
C2
A2
41
34
76
69
112
105
4
141
P3
M3
M12
P12
A12
C12
C3
A3
39
32
78
71
110
103
6
143
P1
M1
M14
P14
A14
C14
C1
A1
I
RDP0
RDP1
RDP2
RDP3
RDP4
RDP5
RDP6
RDP7
RDN0
RDN1
RDN2
RDN3
RDN4
RDN5
RDN6
RDN7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
I
O
High
Impedance
O
High
Impedance
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
The NRZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are
active high and are sampled on the falling edges of TCLKn.
TDPn
0
0
1
1
TDNn
0
1
0
1
Output Pulse
Space
Negative Pulse
Positive Pulse
Space
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as Table-2
System Interface Configuration.
RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
These pins output the raw RZ sliced data. The active polarity of RDPn/RDNn is determined by pin CLKE.
When pin CLKE is low, RDPn/RDNn is active low. When pin CLKE is high, RPDn/RDNn is active high.
RDPn/RDNn will remain active during LOS. RDPn/RDNn is set into high impedance when the corresponding receiver is powered down.
RCn: Receive Pulse for Channel 0~7
RCn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock
is recovered from the signal on RCn. If receiver n is powered down, the corresponding RCn will be in high
impedance.
5
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
MCLK
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
Type
Pin No.
TQFP144
Description
PBGA160
I
10
E1
O
42
35
75
68
113
106
3
140
K4
K3
K12
K11
E11
E12
E3
E4
MCLK: Master Clock
This is an independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz
(for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.
When MCLK is low, all the receivers are powered down, and the output pins RCn, RDPn and RDNn are
switched to high impedance.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (See Table-2
System Interface Configuration for details).
NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided.
LOSn: Loss of Signal Output for Channel 0~7
A high level on this pin indicates the loss of signal when there is no transition over a specified period of
time or no enough ones density in the received signal. The transition will return to low automatically when
there is enough transitions over a specified period of time with a certain ones density in the received signal. The LOS assertion and desertion criteria are described in 2.4.3 Loss of Signal (LOS) Detection.
Hardware/Host Control Interface
MODE2: Control Mode Select 2(2)
The signal on this pin determines which control mode is selected to control the device:
MODE2
Low
VDDIO/2
High
I
MODE2
(Pulled to
VDDIO/2)
11
E2
Control Interface
Hardware Mode
Serial Host Interface
Parallel Host Interface
Hardware control pins include MODE[2:0], TS[2:0], CLKE and OE.
Serial host Interface pins include CS, SCLK, SDI, SDO and INT.
Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The
device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions
below for details):
MODE[2:0]
100
101
110
111
MODE1
MODE0
I
I
43
88
K2
MODE1: Control Mode Select 1(2)
In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin
is low, and operates with multiplexed address and data bus when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
H12
MODE0: Control Mode Select 0(2)
In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin
is low, or for Intel compatible hosts when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
J11
CS: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must
occur on this pin for each read/write operation and the level must not return to high until the operation is
over.
In hardware control mode, this pin should be pulled to VDDIO/2.
I
CS
(Pulled to
VDDIO/2)
87
Host Interface
Non-multiplexed Motorola Mode Interface
Non-multiplexed Intel Mode Interface
Multiplexed Motorola Mode Interface
Multiplexed Intel Mode Interface
2. In host mode, register e-AFE has to be set to ‘FFH’ for proper device operation. See Expanded Register Description on page 28 for more details.
6
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
Description
PBGA160
TS2: Template Select 2
In hardware control mode, the signal on this pin is the most significant bit for the transmit template select.
Refer to 2.5.1 Waveform Shaper for details.
TS2/SCLK/
ALE/AS
I
86
J12
SCLK: Shift Clock
In serial host mode, the signal on this pin is the shift clock for the serial interface. Data on pin SDO is
clocked out on falling edges of SCLK if pin CLKE is high, or on rising edges of SCLK if pin CLKE is low.
Data on pin SDI is always sampled on rising edges of SCLK.
ALE: Address Latch Enable
In parallel Intel multiplexed host mode, the address on AD[4:0] is sampled into the device on the falling
edges of ALE (signals on AD[7:5] are ignored). In non-multiplexed host mode, ALE should be pulled high.
AS: Address Strobe (Active Low)
In parallel Motorola multiplexed host mode, the address on AD[4:0] is latched into the device on the falling
edges of AS (signals on AD[7:5] are ignored). In non-multiplexed host mode, AS should be pulled high.
TS1: Template Select 1
In hardware control mode, the signal on this pin is the second most significant bit for the transmit template
select. Refer to 2.5.1 Waveform Shaper for details.
TS1/RD/R/W
I
85
J13
RD: Read Strobe (Active Low)
In parallel Intel multiplexed or non-multiplexed host mode, this pin is active low for read operation.
R/W: Read/Write Select
In parallel Motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and
high for read operation.
TS0: Template Select 0
In hardware control mode, the signal on this pin is the least significant bit for the transmit template select.
Refer to 2.5.1 Waveform Shaper for details.
SDI: Serial Data Input
In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on the rising
edges of SCLK.
TS0/SDI/WR/
DS
I
84
J14
WR: Write Strobe (Active Low)
In parallel Intel host mode, this pin is active low during write operation. The data on D[7:0] (in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges of WR.
DS: Data Strobe (Active Low)
In parallel Motorola host mode, this pin is active low. During a write operation (R/W = 0), the data on D[7:0]
(in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges
of DS. During a read operation (R/W = 1), the data is driven to D[7:0] (in non-multiplexed mode) or AD[7:0]
(in multiplexed mode) by the device on the rising edges of DS.
In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus
A[4:0] are latched into the device on the falling edges of DS.
7
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
Description
PBGA160
SDO: Serial Data Output
In serial host mode, the data is output on this pin. In serial write operation, SDO is always in high impedance. In serial read operation, SDO is in high impedance only when SDI is in address/command byte. Data
on pin SDO is clocked out of the device on the falling edges of SCLK if pin CLKE is high, or on the rising
edges of SCLK if pin CLKE is low.
SDO/RDY/ACK
O
83
K14
RDY: Ready Output
In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed,
while low reports the host must insert wait states.
ACK: Acknowledge Output (Active Low)
In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write operation.
INT
D7/AD7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
D1/AD1
D0/AD0
O
Open
Drain
I/O
High
Impedance
82
K13
28
27
26
25
24
23
22
21
K1
J1
J2
J3
J4
H2
H3
G2
INT: Interrupt (Active Low)
This is an open drain, active low interrupt output. Two sources may cause the interrupt. Refer to 2.19 Interrupt Handling for details.
Dn: Data Bus 7~0
In non-multiplexed host mode, these pins are the bi-directional data bus.
ADn: Address/Data Bus 7~0
In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.
In hardware mode, these pins should be tied to VDDIO/2.
In serial host mode, these pins should be grounded.
8
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
Type
I
Pin No.
TQFP144
12
13
14
15
16
Description
PBGA160
F4
F3
F2
F1
G3
MCn: Performance Monitor Configuration 3~0
In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select a transmitter or
receiver of channel 1 to 7 for non-intrusive monitoring. Channel 0 is used as the monitoring channel. If a
transmitter is monitored, signals on the corresponding pins TTIPn and TRINGn are internally transmitted
to RTIP0 and RRING0 pins. If a receiver is monitored, signals on the corresponding pins RTIPn and
RRINGn are internally transmitted to RTIP0 and RRING0 pins. The monitored is then output to RDP0 and
RDN0 pins.
Performance Monitor Configuration determined by MC[3:0] is shown below. Note that if MC[2:0] = 000, the
device is in normal operation of all the channels.
MC[3:0]
Monitoring Configuration
0000
Normal operation without monitoring
0001
Monitor Receiver 1
0010
Monitor Receiver 2
0011
Monitor Receiver 3
0100
Monitor Receiver 4
0101
Monitor Receiver 5
0110
Monitor Receiver 6
0111
Monitor Receiver 7
1000
Normal operation without monitoring
1001
Monitor Transmitter 1
1010
Monitor Transmitter 2
1011
Monitor Transmitter 3
1100
Monitor Transmitter 4
1101
Monitor Transmitter 5
1110
Monitor Transmitter 6
Monitor Transmitter 7
1111
In host mode operation, the monitoring channel is selected in the PMON register. The signals monitored
by channel 0 can be routed to TTIP0/RING0 by activating the remote loopback in this channel (refer to
2.13 G.772 Monitoring).
An: Address Bus 4~0
When pin MODE1 is low, the parallel host interface operates with separate address and data bus. In this
mode, the signal on this pin is the address bus of the host interface.
When pin MODE1 is high or in serial host mode, these pins should be tied to GND.
OE
I
114
E14
OE: Output Driver Enable
Pulling this pin low can drive all driver output into high impedance for redundancy application without
external mechanical relays. In this condition, all other internal circuits remain active.
CLKE
I
115
E13
CLKE: Clock Edge Select
The signal on this pin determines the active edge of RCn, RDPn, RDNn and SCLK. Refer to 2.3 Clock
Edges for details.
JTAG Signals
I
TRST
95
G12
TRST: JTAG Test Port Reset (Active Low)
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor
and can be left disconnected.
96
F11
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and can be left disconnected.
F14
TCK: JTAG Test Clock
The clock of the JTAG test is input on this pin. The data on TDI and TMS are clocked into the device on rising edges of TCK while the data on TDO pin is clocked out of the device on falling edges of TCK. This pin
should be connected to GNDIO or VDDIO pin when unused.
Pull-up
I
TMS
Pull-up
TCK
I
97
9
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
O
TDO
High
Impedance
98
F13
TDO: JTAG Test Data Output
The serial data of the JTAG test is output on this pin. The data on TDO pin is clocked out of the device on
the falling edges of TCK. TDO is a high impedance output signal. It is active only when scanning of data is
over. This pin should be left float when unused.
99
F12
TDI: JTAG Test Data Input
The serial data of the JTAG test is input on this pin. The data on TDI pin is clocked into the device on the
rising edges of TCK. This pin has an internal pull-up resistor and it can be left disconnected.
I
TDI
Description
PBGA160
Pull-up
Power Supplies and Grounds
VDDIO
-
17
92
G1
G14
3.3 V I/O Power Supply
GNDIO
-
18
91
G4
G11
I/O GND
-
44
53
56
65
116
125
128
137
N4, P4
L4, M4
L11, M11
N11, P11
A11, B11
C11, D11
C4, D4
A4, B4
GNDT0
GNDT1
GNDT2
GNDT3
GNDT4
GNDT5
GNDT6
GNDT7
-
47
50
59
62
119
122
131
134
N6, P6
L6, M6
L9, M9
N9, P9
A9, B9
C9, D9
C6, D6
A6, B6
VDDD
VDDA
-
19
90
H1
H14
3.3 V Digital/Analog Core Power Supply
GNDD
GNDA
-
20
89
H4
H11
Digital/Analog Core GND
VDDT0
VDDT1
VDDT2
VDDT3
VDDT4
VDDT5
VDDT6
VDDT7
3.3 V/5 V Power Supply for Transmitter Driver
All VDDT pins must be connected to 3.3 V or all VDDT must be connected to 5 V. It is not allowed to leave
any of the VDDT pins open (not-connected) even if the channel is not used.
T1 is only 5V VDDT.
Analog GND for Transmitter Driver
Others
IC
-
93
G13
IC: Internal Connection
Internal use. Leave it open for normal operation.
IC
-
94
H13
IC: Internal Connection
Internal use. Leave it open for normal operation.
10
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
2
FUNCTIONAL DESCRIPTION
2.1
OVERVIEW
The Dual Rail interface consist of TDPn1, TDNn, TCLKn, RDPn,
RDNn and RCn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface. The interface of the AFE is
shown in Figure-4. Pin RDPn and RDNn, are raw RZ slice outputs and
internally connected to an XOR which is fed to the RCn output for
external clock recovery applications.
The IDT82V2048L is a fully integrated octal short-haul analog front
end (AFE), which contains eight transmit and receive channels for use in
either T1 or E1 applications. The raw sliced data (no retiming) is output
to the system. Transmit equalization is implemented with low-impedance
output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. Moreover, testing functions, such as
JTAG boundary scan is provided. The device is optimized for flexible
software control through a serial or parallel host mode interface. Hardware control is also available. Figure-1 on page 1 shows one of the eight
identical channels operation.
2.2
INDUSTRIAL TEMPERATURE RANGES
2.2.1.1 SYSTEM INTERFACE CONFIGURATION
For normal transmit and receive operation, the device is configured
as follows:
In host mode, MCLK can be either clocked or pulled high. If MCLK is
pulled high, TCLK1 has to be provided for proper device operation. In
addition, register e-AFE2 has to be set to ‘FFH’ to ensure proper device
operation. See Expanded Register Description on page 28 for details.
T1/E1 MODE SELECTION
In hardware mode, MCLK has to be pulled high and TCLK1 has to be
provided for proper device operation.
T1/E1 mode selection configures the device globally. In Hardware
control Mode, the template selection pins TS[2:0], determine whether
the operation mode is T1 or E1 (see Table-5 on page 14). In Software
Mode, the register TS determines whether the operation mode is T1 or
E1.
Depending on the state of TCLK1 and TCLKn, the transmitter will
Transmit All Ones (TAOS), will go into power down, or will go into high
impedance.
The status of TCLK1 and TCLKn has no effect on the receive paths.
By setting MCLK low, all the receive paths are powered down.
2.2.1 SYSTEM INTERFACE
The system interface of each channel operates in Dual Rail Mode
with data recovery, that is, with raw data slicing only and without clock
recovery.
Table-2 summarizes the different combinations between MCLK and
TCLKn.
1.
2.
11
The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels.
The first letter ‘e-’ indicates expanded register.
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-2 System Interface Configuration
Host or Hardware Mode
MCLK
TCLK1
TCLKn
AFEn in e-AFE
Transmitter Mode
Transmit and Receive Normal Operation
Host(1) only
Host or Hardware(2)
Clocked
Clocked
High
Clocked
Clocked
1
Clocked
DC
Normal operation
(3)
Normal operation
Transmit Interface Modes
Host only
High (≥ 16 MCLK)
Clocked
Transmit All Ones (TAOS) signals to the line side in the
corresponding transmit channel.
1
Corresponding transmit channel is set into power down state.
Low (≥ 64 MCLK)
TCLK1 is clocked
Host or Hardware
Transmit All Ones (TAOS) signals to the line side in the corresponding transmit channel.
TCLKn is high
(≥ 16 TCLK1)
TCLKn is low
(≥ 64 TCLK1)
High/Low
TCLK1 is unavailable.
DC
Corresponding transmit channel is set into power down state.
All eight transmitters (TTIPn & TRINGn) are in high impedance.
DC
Receive Interface Modes
Host or Hardware
1.
Low
The receive path is not affected by the
status of TCLK1 or TCLKn.
DC
All the receive paths are powered down.
In host mode, register e-AFE must be set to ‘FFH’ for proper operation. See Expanded Register Description on page 28 for details.
2. In hardware mode, MCLK must be pulled high and TCLK1 provided for proper operation.
3. DC means Don’t Care
LOS
Detector
RTIPn
One of Eight Identical Channels
RCn
RDPn
RDNn
Slicer
RRINGn
LOSn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Waveform
Shaper
Transmit
All Ones
Figure-4 Analog Front End (AFE) Interface
12
TCLKn
TDPn
TDNn
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
2.3
INDUSTRIAL TEMPERATURE RANGES
CLOCK EDGES
The active edge of SCLK is selectable. If pin CLKE is high, the active
edge of SCLK is the falling edge. On the contrary, if CLKE is low, the
active edge SCLK is the rising edge. Pin SDO is always active high, and
the output signals are valid on the active edge of SCLK. See Table-3
Active Clock Edge and Active Level for details. Pin CLKE is used to set
the active level for RDPn/RDNn raw slicing output: high for active high
polarity and low for active low. It should be noted that data on pin SDI
are always active high and are sampled on the rising edges of SCLK.
The data on pin TDPn or TDNn are also always active high but are
sampled on the falling edges of TCLKn, despite the level on CLKE.
Table-3 Active Clock Edge and Active Level
2.4
Pin CLKE
Pin RDPn and RDNn
Slicer Output
High
Active High
SCLK
Active High
Low
Active Low
SCLK
Active High
Pin SDO
RECEIVER
2.4.2 DATA RECOVERY
The analog line signal are converted to RZ digital bit streams on the
RDPn/RDNn pins and internally connected to an XOR which is fed to the
RCn output for external clock recovery applications.
In receive path, the line signals couple into RRINGn and RTIPn via a
transformer and are converted into RZ digital pulses by a data slicer.
Adaptation for attenuation is achieved using an integral peak detector
that sets the slicing levels. The recovered data on pin RDPn/RDNn in an
undecoded dual rail RZ format. Loss of signal is detected. This change
in status may be enabled to generate an interrupt.
2.4.3 LOSS OF SIGNAL (LOS) DETECTION
The Loss of Signal Detector monitors the amplitude and density of
the received signal on receiver line before the transformer (measured on
port A, B shown in Figure-7). The loss condition is reported by pulling pin
LOSn high. At the same time, LOS alarm registers track LOS condition.
When LOS is detected or cleared, an interrupt will generate if not
masked. In host mode, the detection supports the ANSI T1.231 for T1
mode, ITU G.775 and ETSI 300 233 for E1 mode. In hardware mode, it
supports the ITU G.775 and ANSI T1.231.
2.4.1 PEAK DETECTOR AND SLICER
The slicer determines the presence and polarity of the received
pulses. The raw positive slicer output appears on RDPn while the negative slicer output appears on RDNn. The slicer circuit has a built-in peak
detector from which the slicing threshold is derived. The slicing
threshold is default to 50% (typical) of the peak value.
Table-4 summarizes the conditions of LOS. During LOS, the RDPn/
RDNn continue to output the sliced data.
Signals with an attenuation of up to 12 dB (from 2.4 V) can be recovered by the receiver. To provide immunity from impulsive noise, the peak
detectors are held above a minimum level of 0.150 V typically, despite
the received signal level.
Table-4 LOS Condition
Standard
LOS
Detected
Continuous Intervals
LOS
Cleared
Density
Amplitude(1)
Amplitude(1)
1.
ANSI T1.231 for T1
G.775 for E1
ETSI 300 233 for E1
175
32
2048 (1 ms)
below typical 200 mVp
below typical 200 mVp
below typical 200 mVp
12.5% (16 marks in a sliding 128-bit 12.5% (4 marks in a sliding 32-bit
period) with no more than 99 contin- period) with no more than 15 conuous zeros
tinuous zeros
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 continuous zeros
exceed typical 250 mVp
exceed typical 250 mVp
exceed typical 250 mVp
LOS levels at device (RTIPn, RRINGn) with all ones signal. For more detail regarding the LOS parameters, please refer to Receiver Characteristics on page 38.
13
Signal on
LOSn
High
Low
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
2.5
INDUSTRIAL TEMPERATURE RANGES
TRANSMITTER
1.2
In transmit path, data in NRZ format is clocked into the device on
TDPn and TDNn. The data is sampled into the device on falling edges of
TCLKn. The shape of the pulses are user programmable to ensure that
the T1/E1 pulse template is met after the signal passes through different
cable lengths or types.
1
Normalized Amplitude
0.8
2.5.1 WAVEFORM SHAPER
T1 pulse template, specified in the DSX-1 Cross-Connect by ANSI
T1.102, is illustrated in Figure-5. The device has built-in transmit waveform templates, corresponding to 5 levels of pre-equalization for cable of
a length from 0 to 655 ft with each increment of 133 ft.
0.6
0.4
0.2
0
-0.2
-0.4
E1 pulse template, specified in ITU-T G.703, is shown in Figure-6.
The device has built-in transmit waveform templates for cable of 75 Ω or
120 Ω.
-0.6
0
250
500
750
1000
1250
Time (ns)
Figure-5 DSX-1 Waveform Template
Any one of the six built-in waveforms can be chosen in both hardware mode and host mode. In hardware control mode, setting pins
TS[2:0] can select the required waveform template for all the transmitters, as shown in Table-5. In host mode, the waveform template can be
configured on a per-channel basis. Bits TSIA[2:0] in register TSIA are
used to select the channel and bits TS[2:0] in register TS are used to
select the required waveform template.
1.20
1.00
Normalized Amplitude
0.80
The built-in waveform shaper uses an internal high frequency clock
which is 16XMCLK as the clock reference. This function will be
bypassed when MCLK is unavailable.
0.60
0.40
0.20
0.00
-0.20
-300
-200
-100
0
Time (ns)
100
200
300
Figure-6 CEPT Waveform Template
Table-5 Built-in Waveform Template Selection
1.
TS2
TS1
TS0
Service
Clock Rate
Cable Length
Maximum Cable Loss (dB)(1)
0
0
0
E1
2.048 MHz
120 Ω/75 Ω Cable
-
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Reserved
T1
0-133 ft. ABAM
133-266 ft. ABAM
266-399 ft. ABAM
399-533 ft. ABAM
533-655 ft. ABAM
1.544 MHz
Maximum cable loss at 772 kHz.
2.6
LINE INTERFACE CIRCUITRY
The transmit and receive interface RTIPn/RRINGn and TTIPn/
TRINGn connections provide a matched interface to the cable. Figure-7
shows the appropriate external components to connect with the cable
for one transmit/receive channel. Table-6 summarizes the component
values based on the specific application.
14
0.6
1.2
1.8
2.4
3.0
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-6 External Components Values
E1
T1
100 Ω Twisted Pair, VDDT = 5.0 V
9.1 Ω ± 1%
12.4 Ω ± 1%
2200 pF
1000 pF
Nihon Inter Electronics - EP05Q03L, 11EQS03L, EC10QS04, EC10QS03L; Motorola - MBR0540T1
75 Ω Coax
9.5 Ω ± 1%
9.31 Ω ± 1%
RT
RR
Cp
D1 - D4
120 Ω Twisted Pair
9.5 Ω ± 1%
15 Ω ± 1%
One of Eight Identical Channels
1
A
2:1
• •
•
0.22 µF
RX Line
•
•
B
1
2:1
• •
1 kΩ
RTIPn
RR
RR
1 kΩ VDDT
D4
RT
D3
TX Line
Cp
RRINGn
·
TTIPn
IDT82V2048L
Component
VDDT
2
VDDT
D2
RT
D1
•
VDDDn
0.1 µF
•
GNDTn
·
68 µF3
TRINGn
NOTE:
1. Pulse T1124 transformer is recommended to be used in Standard (STD) operating temperature range (0°C to 70°C), while Pulse T1114
transformer is recommended to be used in Extended (EXT) operating temperature range is -40°C to +85°C. See Transformer Specifications Table
for details.
2. Typical value. Adjust for actual board parasitics to obtain optimum return loss.
3. Common decoupling capacitor for all VDDT and GNDT pins. One per chip.
Figure-7 External Transmit/Receive Line Circuitry
2.7
TRANSMIT DRIVER POWER SUPPLY
In T1 mode, only 5.0 V can be selected, 100 Ω lines are driven
through a pair of 9.1 Ω series resistors and a 1:2 transformer.
All transmit driver power supplies must be 5.0 V or 3.3 V.
In harsh cable environment, series resistors are required to improve
the transmit return loss performance and protect the device from surges
coupling into the device.
In E1 mode, despite the power supply voltage, the 75 Ω/120 Ω lines
are driven through a pair of 9.5 Ω series resistors and a 1:2 transformer.
Table-7 Transformer Specifications(1)
Part No.
STD Temp. EXT Temp.
T1124
T1114
Turns Ratio (Pri: sec ± 2%)
Transmit
Receive
1:2CT
1CT:2
Electrical Specification @ 25°C
OCL @ 25°C (mH MIN)
LL (µH MAX)
Transmit
Receive
Transmit
Receive
1.2
1.2
.6
.6
CW/W (pF MAX)
Transmit Receive
35
35
Package/Schematic
TOU/3
1. Pulse
T1124 transformer is recommended to be used in Standard (STD) operating temperature range (0°C to 70°C), while Pulse T1114 transformer is recommended to be used in
Extended (EXT) operating temperature range is -40°C to +85°C.
2.8
POWER DRIVER FAILURE MONITOR
2.9
An internal power Driver Failure Monitor (DFMON), parallel
connected with TTIPn and TRINGn, can detect short circuit failure
between TTIPn and TRINGn pins. Bit SCPB in register GCF decides
whether the output driver short circuit protection is enabled. When the
short circuit protection is enabled, the driver output current is limited to a
typical value: 180 mAp. Also, register DF, DFI and DFM will be available.
When DFMON will detect a short circuit, register DF will be set. With a
short circuit failure detected, register DFI will be set and an interrupt will
be generated on pin INT.
TRANSMIT LINE SIDE SHORT CIRCUIT
In E1 or T1 with 5 V VDDT, a pair of 9.5 Ω serial resistors connect
with TTIPn and TRINGn pins and limit the output current. In this case,
the output current is a limited value which is always lower than the
typical line short circuit current 180 mAp, even if the transmit line side is
shorted.
Refer to Table-6 External Components Values for details.
15
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
2.10 LINE PROTECTION
2.12 TRANSMIT ALL ONES (TAOS)
In transmit side, the Schottky diodes D1~D4 are required to protect
the line driver and improve the design robustness. In receive side, the
series resistors of 1 kΩ are used to protect the receiver against current
surges coupled in the device. The series resistors do not affect the
receiver sensitivity, since the receiver impedance is as high as 120 kΩ
typically.
In hardware mode, the TAOS mode is set by pulling pin TCLKn high
for more than 16 MCLK cycles. In host mode, TAOS mode is set by
programming register TAO. In addition, automatic TAOS signals are
inserted by setting register ATAO when Loss of Signal occurs. Note that
the TAOS generator adopts MCLK as a timing reference. In order to
assure that the output frequency is within specified limits, MCLK must
have the applicable stability.
2.11 HITLESS PROTECTION SWITCHING (HPS)
Refer to Figure-8 TAOS Data Path.
The IDT82V2048L transceivers include an output driver with high
impedance feature for T1/E1 redundancy applications. This feature
reduces the cost of redundancy protection by eliminating external relays.
Details of HPS are described in relative Application Note.
LOS
Detector
RTIPn
One of Eight Identical Channels
LOSn
RCn
RDPn
RDNn
Slicer
RRINGn
Peak
Detector
TTIPn
TRINGn
Line
Driver
TCLKn
TDPn
TDNn
Waveform
Shaper
Transmit
All Ones
Figure-8 TAOS Data Path
2.13 G.772 MONITORING
In monitoring mode, a clock and data recovery circuit can be enabled
for Remote Loopback operation. In Remote Loopback operation, the
signal which is being monitored will be also output on TTIP0 and
TRING0 pins. The output signal can then be connected to a standard
test equipment for non-intrusive monitoring. RC0 pin will also output the
recovered clock (DPLL).
The eight channels of IDT82V2048L can all be configured to work as
regular transceivers. In applications using only seven channels (channels 1 to 7), channel 0 is configured to non-intrusively monitor any of the
other channels’ inputs or outputs on the line side. The monitoring is nonintrusive per ITU-T G.772. Figure-9 shows the Monitoring Principle. The
receiver path or transmitter path to be monitored is configured by pin
MC[3:0] in hardware mode or by PMON in host mode.
The remote loopback is only available in host mode operation.
To enable the remote loopback, bit 0 in register RL0 has to be set,
and bit 0 in register e-AFE has to be cleared. The register setting are:
register RL0 set ‘01’H, register e-AFE set ‘FE’H.
The signal which is monitored can be observed digitally at the output
pin RC0, RDP0 and RDN0. LOS detector is still in use in channel 0 for
the monitored signal.
For normal operation register RL0 has to be set ‘00H’ and register eAFE has to be set ‘FFH’.
16
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Channel N ( 7 > N > 1 )
LOS
Detector
RTIPn
LOSn
RCn
RDPn
RDNn
Slicer
RRINGn
Peak
Detector
TTIPn
Line
Driver
TRINGn
TCLKn
TDPn
TDNn
Waveform
Shaper
Transmit
All Ones
Channel 0
G.772
Monitor
LOS
Detector
RTIP0
Slicer
RRING0
Remote
Loopback
CDR
TRING0
Line
Driver
RC0
RDP0
RDN0
Remote
Loopback
Peak
Detector
TTIP0
LOS0
Waveform
Shaper
TCLK0
TDP0
TDN0
Transmit
All Ones
Figure-9 Monitoring Principle
2.14 SOFTWARE RESET
2.16 POWER DOWN
Writing register RS will cause software reset by initiating about 1 µs
reset cycle. This operation set all the registers to their default value.
2.15 POWER ON RESET
Each transmit channel will be powered down by pulling pin TCLKn
low for more than 64 MCLK cycles (if MCLK is available) or about 30 µs
(if MCLK is not available). In host mode, each transmit channel will also
be powered down by setting bit TPDNn in register e-TPDN to ‘1’.
During power up, an internal reset signal sets all the registers to
default values. The power-on reset takes at least 10 µs, starting from
when the power supply exceeds 2/3 VDDA.
All the receivers will be powered down when MCLK is low. When
MCLK is clocked or high, setting bit RPDNn in register e-RPDN to ‘1’ will
configure the corresponding receiver to be powered down.
2.17 INTERFACE WITH 5 V LOGIC
The IDT82V2048L can interface directly with 5 V TTL family devices.
The internal input pads are tolerant to 5 V output from TTL and CMOS
family devices.
17
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
2.18 HOST INTERFACE
INDUSTRIAL TEMPERATURE RANGES
2.18.1 PARALLEL HOST INTERFACE
The interface is compatible with Motorola and Intel host. Pins
MODE[1:0] are used to select the operating mode of the parallel host
interface. When pin MODE1 is pulled low, the host uses separate
address bus and data bus. When high, multiplexed address/data bus is
used. When pin MODE0 is pulled low, the parallel host interface is
configured for Motorola compatible hosts. When pin MODE0 is pulled
high, the parallel host interface is configured for Intel compatible hosts.
See Table-1 Pin Description for more details. The host interface pins in
each operation mode is tabulated in Table-8:
The host interface provides access to read and write the registers in
the device. The interface consists of serial host interface and parallel
host interface. By pulling pin MODE2 to VDDIO/2 or high, the device can
be set to work in serial mode and in parallel mode respectively. In host
mode operation, expanded register e-FAE has to be set to ‘FFH’ for
proper device operation. See Expanded Register Description on page
28 for details.
Table-8 Parallel Host Interface Pins
MODE[2:0]
100
101
110
111
Host Interface
Non-multiplexed Motorola interface
Non-multiplexed Intel interface
Multiplexed Motorola interface
Multiplexed Intel interface
Generic Control, Data and Output Pin
CS, ACK, DS, R/W, AS, A[4:0], D[7:0], INT
CS, RDY, WR, RD, ALE, A[4:0], D[7:0], INT
CS, ACK, DS, R/W, AS, AD[7:0], INT
CS, RDY, WR, RD, ALE, AD[7:0], INT
CS
SCLK
SDI
2
2
1
R/W A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7
Address/Command Byte
SDO
Input Data Byte
D0 D1 D2 D3 D4 D5 D6 D7
High Impedance
Driven while R/W=1
1. While R/W=1, read from IDT82V2048L; While R/W=0, write to IDT82V2048L.
2. Ignored.
Figure-10 Serial Host Mode Timing
2.18.2 SERIAL HOST INTERFACE
By pulling pin MODE2 to VDDIO/2, the device operates in the serial
host Mode. In this mode, the registers are accessible through a 16-bit
word which contains an 8-bit command/address byte (bit R/W and 5address-bit A1~A5, A6 and A7 bits are ignored) and a subsequent 8-bit
data byte (D7~D0), as shown in Figure-10. When bit R/W is set to ‘1’,
data is read out from pin SDO. When bit R/W is set to ‘0’, data on pin
SDI is written into the register whose address is indicated by address
bits A5~A1. Refer to Figure-10 Serial Host Mode Timing.
18
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
2.19 INTERRUPT HANDLING
2.19.2 INTERRUPT ENABLE
The IDT82V2048L provides a latched interrupt output (INT) and the
two kinds of interrupts are all reported by this pin. When the Interrupt
Mask register: LOSM and DFM, are set to ‘1’, the Interrupt Status
register: LOSI and DFI, are enabled respectively. Whenever there is a
transition (‘0’ to ‘1’ or ‘1’ to ‘0’) in the corresponding status register, the
Interrupt Status register will change into ‘1’, which means an interrupt
occurs, and there will be a high to low transition on INT pin. An external
pull-up resistor of approximately 10 kΩ is required to support the wireOR operation of INT. When any of the two Interrupt Mask registers is set
to ‘0’ (the power-on default value is ‘0’), the corresponding Interrupt
Status register is disabled and the transition on status register is
ignored.
2.19.1 INTERRUPT SOURCES
There are two kinds of interrupt sources:
1. Status change in register LOS. The analog/digital loss of signal
detector continuously monitors the received signal to update the
specific bit in register LOS which indicates presence or absence
of a LOS condition.
2. Status change in register DF. The automatic power driver circuit
continuously monitors the output drivers signal to update the
specific bit in register DFM which indicates presence or absence
of an output driver short circuit condition.
2.19.3 INTERRUPT CLEARING
When an interrupt occurs, the Interrupt Status registers: LOSI and
DFI, are read to identify the interrupt source. These registers will be
cleared to ‘0’ after the corresponding status registers: LOS and DF are
read. The Status registers will be cleared once the corresponding conditions are met.
Interrupt Allowed
No
INDUSTRIAL TEMPERATURE RANGES
Pin INT is pulled high when there is no pending interrupt left. The
interrupt handling in the interrupt service routine is shown in Figure-11.
Interrupt Condition
Exist?
Yes
Read Interrupt Status Register
Read Corresponding Status
Register
Service the Interrupt
Figure-11 Interrupt Service Routine
19
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
3
PROGRAMMING INFORMATION
The Register ADDP, addressed as 11111 or 1F Hex, switches
between primary registers bank and expanded registers bank.
3.1
REGISTER LIST AND MAP
By setting register ADDP to ‘AAH’, the 5 address bits point to the
expanded register bank, that is, 4 expanded registers are available. By
clearing register ADDP, the primary registers are available.
There are 18 primary registers (including an Address Pointer Control
Register and 4 expanded registers in the device).
3.2
Whatever the control interface is, 5 address bits are used to set the
registers. In non-multiplexed parallel interface mode, the five dedicated
address bits are A[4:0]. In multiplexed parallel interface mode, AD[4:0]
carries the address information. In serial interface mode, A[5:1] are used
to address the register.
RESERVED AND TEST REGISTERS
Primary Registers, whose address are 01H, 0CH, 13H to 1EH, are
reserved. Expanded registers, whose address are 00H, 01H, 05H, 06H,
08H to 0FH, are reserved. Expanded registers, whose address are 10H
to 1EH, are used for test and must be set to ‘0’ (default).
Table-9 Primary Register List
Address
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
Serial Interface A7-A1
XX00000
XX00001
XX00010
XX00011
XX00100
XX00101
XX00110
XX00111
XX01000
XX01001
XX01010
XX01011
XX01100
XX01101
XX01110
XX01111
XX10000
XX10001
XX10010
XX10011
XX10100
XX10101
XX10110
XX10111
XX11000
XX11001
XX11010
XX11011
XX11100
XX11101
XX11110
Parallel Interface A7-A0
XXX00000
XXX00001
XXX00010
XXX00011
XXX00100
XXX00101
XXX00110
XXX00111
XXX01000
XXX01001
XXX01010
XXX01011
XXX01100
XXX01101
XXX01110
XXX01111
XXX10000
XXX10001
XXX10010
XXX10011
XXX10100
XXX10101
XXX10110
XXX10111
XXX11000
XXX11001
XXX11010
XXX11011
XXX11100
XXX11101
XXX11110
1F
XX11111
XXX11111
Register
R/W
ID
R
RL0
TAO
LOS
DF
LOSM
DFM
LOSI
DFI
RS
PMON
R/W
R/W
R
R
R/W
R/W
R
R
W
R/W
LAC
ATAO
GCF
TSIA
TS
OE
R/W
R/W
R/W
R/W
R/W
R/W
Explanation
Device ID Register
Reserved
G.772 Monitoring, Remote Loopback Configuration Register
Transmit All Ones Configuration Register
Loss of Signal Status Register
Driver Fault Status Register
LOS Interrupt Mask Register
Driver Fault Interrupt Mask Register
LOS Interrupt Status Register
Driver Fault Interrupt Status Register
Software Reset Register
Performance Monitor Configuration Register
Reserved
LOS/AIS Criteria Configuration Register
Automatic TAOS Configuration Register
Global Configuration Register
Indirect Address Register for Transmit Template Select
Transmit Template Select Register
Output Enable Configuration Register
Reserved
ADDP
R/W
Address pointer control Register for switching between primary register bank and
expanded register bank
20
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-10 Expanded (Indirect Address Mode) Register List
Address
Register
R/W
e-AFE
e-RPDN
e-TPDN
R/W
R/W
R/W
Explanation
Hex Serial Interface A7-A1 Parallel Interface A7-A0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
XX00000
XX00001
XX00010
XX00011
XX00100
XX00101
XX00110
XX00111
XX01000
XX01001
XX01010
XX01011
XX01100
XX01101
XX01110
XX01111
XX10000
XX10001
XX10010
XX10011
XX10100
XX10101
XX10110
XX10111
XX11000
XX11001
XX11010
XX11011
XX11100
XX11101
XX11110
XXX00000
XXX00001
XXX00010
XXX00011
XXX00100
XXX00101
XXX00110
XXX00111
XXX01000
XXX01001
XXX01010
XXX01011
XXX01100
XXX01101
XXX01110
XXX01111
XXX10000
XXX10001
XXX10010
XXX10011
XXX10100
XXX10101
XXX10110
XXX10111
XXX11000
XXX11001
XXX11010
XXX11011
XXX11100
XXX11101
XXX11110
1F
XX11111
XXX11111
Reserved
AFE Enable Register
Receiver n Powerdown Enable/Disable Register
Transmitter n Powerdown Enable/Disable Register
Reserved
e-EQUA
R/W
Enable Equalizer Enable/Disable Register
Reserved
Test
ADDP
R/W
21
Address pointer control register for switching between primary register bank
and expanded register bank
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-11 Primary Register Map
Register
ID
RL0
TAO
LOS
DF
LOSM
DFM
LOSI
DFI
RS
PMON
LAC
ATAO
GCF
TSIA
Address
R/W
Default
00H
R
Default
02H
R/W
Default
03H
R/W
Default
04H
R
Default
05H
R
Default
06H
R/W
Default
07H
R/W
Default
08H
R
Default
09H
R
Default
0AH
W
Default
0BH
R/W
Default
0DH
R/W
Default
0EH
R/W
Default
0FH
R/W
Default
10 Hex
R/W
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID 7
R
0
R/W
0
TAO 7
R/W
0
LOS 7
R
0
DF 7
R
0
LOSM 7
R/W
0
DFM 7
R/W
0
LOSI 7
R
0
DFI 7
R
0
RS 7
W
1
R/W
0
LAC 7
R/W
0
ATAO 7
R/W
0
R/W
0
R/W
0
ID 6
R
0
R/W
0
TAO 6
R/W
0
LOS 6
R
0
DF 6
R
0
LOSM 6
R/W
0
DFM 6
R/W
0
LOSI 6
R
0
DFI 6
R
0
RS 6
W
1
R/W
0
LAC 6
R/W
0
ATAO 6
R/W
0
R/W
0
R/W
0
ID 5
R
0
R/W
0
TAO 5
R/W
0
LOS 5
R
0
DF 5
R
0
LOSM 5
R/W
0
DFM 5
R/W
0
LOSI 5
R
0
DFI 5
R
0
RS 5
W
1
R/W
0
LAC 5
R/W
0
ATAO 5
R/W
0
SCPB
R/W
0
R/W
0
ID 4
R
1
R/W
0
TAO 4
R/W
0
LOS 4
R
0
DF 4
R
0
LOSM 4
R/W
0
DFM 4
R/W
0
LOSI 4
R
0
DFI 4
R
0
RS 4
W
1
R/W
0
LAC 4
R/W
0
ATAO 4
R/W
0
R/W
0
R/W
0
ID 3
R
0
R/W
0
TAO 3
R/W
0
LOS 3
R
0
DF 3
R
0
LOSM 3
R/W
0
DFM 3
R/W
0
LOSI 3
R
0
DFI 3
R
0
RS 3
W
1
MC 3
R/W
0
LAC 3
R/W
0
ATAO 3
R/W
0
R/W
0
R/W
0
ID 2
R
0
R/W
0
TAO 2
R/W
0
LOS 2
R
0
DF 2
R
0
LOSM 2
R/W
0
DFM 2
R/W
0
LOSI 2
R
0
DFI 2
R
0
RS 2
W
1
MC 2
R/W
0
LAC 2
R/W
0
ATAO 2
R/W
0
R/W
0
TSIA 2
R/W
0
ID 1
R
0
R/W
0
TAO 1
R/W
0
LOS 1
R
0
DF 1
R
0
LOSM 1
R/W
0
DFM 1
R/W
0
LOSI 1
R
0
DFI 1
R
0
RS 1
W
1
MC 1
R/W
0
LAC 1
R/W
0
ATAO 1
R/W
0
R/W
0
TSIA 1
R/W
0
ID 0
R
0
RL0
R/W
0
TAO 0
R/W
0
LOS 0
R
0
DF 0
R
0
LOSM 0
R/W
0
DFM 0
R/W
0
LOSI 0
R
0
DFI 0
R
0
RS 0
W
1
MC 0
R/W
0
LAC 0
R/W
0
ATAO 0
R/W
0
R/W
0
TSIA 0
R/W
0
22
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-11 Primary Register Map (Continued)
Register
TS
OE
ADDP
Address
R/W
Default
11 Hex
R/W
Default
12 Hex
R/W
Default
1F Hex
R/W
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
0
OE 7
R/W
0
ADDP 7
R/W
0
R/W
0
OE 6
R/W
0
ADDP 6
R/W
0
R/W
0
OE 5
R/W
0
ADDP 5
R/W
0
R/W
0
OE 4
R/W
0
ADDP 4
R/W
0
R/W
0
OE 3
R/W
0
ADDP 3
R/W
0
TS 2
R/W
0
OE 2
R/W
0
ADDP 2
R/W
0
TS 1
R/W
0
OE 1
R/W
0
ADDP 1
R/W
0
TS 0
R/W
0
OE 0
R/W
0
ADDP 0
R/W
0
23
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-12 Expanded (Indirect Address Mode) Register Map
Register
e-AFE(1)
e-RPDN
e-TPDN
e-EQUA
ADDP
1.
Address
R/W
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
02H
R/W
Default
03H
R/W
Default
04H
R/W
Default
07H
R/W
Default
1FH
R/W
Default
AFE 7
R/W
0
RPDN 7
R/W
0
TPDN 7
R/W
0
EQUA 7
R/W
0
ADDP 7
R/W
0
AFE 6
R/W
0
RPDN 6
R/W
0
TPDN 6
R/W
0
EQUA 6
R/W
0
ADDP 6
R/W
0
AFE 5
R/W
0
RPDN 5
R/W
0
TPDN 5
R/W
0
EQUA 5
R/W
0
ADDP 5
R/W
0
AFE 4
R/W
0
RPDN 4
R/W
0
TPDN 4
R/W
0
EQUA 4
R/W
0
ADDP 4
R/W
0
AFE 3
R/W
0
RPDN 3
R/W
0
TPDN 3
R/W
0
EQUA 3
R/W
0
ADDP 3
R/W
0
AFE 2
R/W
0
RPDN 2
R/W
0
TPDN 2
R/W
0
EQUA 2
R/W
0
ADDP 2
R/W
0
AFE 1
R/W
0
RPDN 1
R/W
0
TPDN 1
R/W
0
EQUA 1
R/W
0
ADDP 1
R/W
0
AFE 0
R/W
0
RPDN 0
R/W
0
TPDN 0
R/W
0
EQUA 0
R/W
0
ADDP 0
R/W
0
In host mode, register e-AFE has to be set to ‘FFH’ for proper device operation. See e-AFE: AFE Enable Selection Register (R/W, Expanded Address = 02H) on page 28 for more details.
24
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
3.3
REGISTER DESCRIPTION
3.3.1
PRIMARY REGISTERS
INDUSTRIAL TEMPERATURE RANGES
ID: Device ID Register (R, Address = 00H)
Symbol
Position
Default
ID[7:0]
ID.7-0
10H
Description
An 8-bit word is pre-set into the device as the identification and revision number. This number is different with the functional
changes and is mask programmed.
RL0: G.772 Monitoring, Remote Loopback Configuration Register (R/W, Address = 02H)
Symbol
-
Position
RL.7-1
Default
0000000
RL[0]
RL.0
0
Description
Reserved
0 = Normal operation. (Default)
1 = Remote loopback enabled.
TAO: Transmit All Ones Configuration Register (R/W, Address = 03H)
Symbol
Position
Default
TAO[7:0]
TAO.7-0
00H
Description
0 = Normal operation. (Default)
1 = Transmit all ones.
LOS: Loss of Signal Status Register (R, Address = 04H)
Symbol
LOS[7:0]
Position
LOS.7-0
Default
00H
Description
0 = Normal operation. (Default)
1 = Loss of signal detected.
DF: Driver Fault Status Register (R, Address = 05H)
Symbol
DF[7:0]
Position
DF.7-0
Default
00H
Description
0 = Normal operation. (Default)
1 = Driver fault detected.
LOSM: Loss of Signal Interrupt Mask Register (R/W, Address = 06H)
Symbol
LOSM[7:0]
Position
LOSM.7-0
Default
00H
Description
0 = LOS interrupt is not allowed. (Default)
1 = LOS interrupt is allowed.
DFM: Driver Fault Interrupt Mask Register (R/W, Address = 07H)
Symbol
Position
Default
DFM[7:0]
DFM.7-0
00H
Description
0 = Driver fault interrupt not allowed. (Default)
1 = Driver fault interrupt allowed.
LOSI: Loss of Signal Interrupt Status Register (R, Address = 08H)
Symbol
Position
Default
LOSI[7:0]
LOSI.7-0
00H
Description
0 = (Default). Or after a LOS read operation.
1 = Any transition on LOSn (Corresponding LOSMn is set to ‘1’).
25
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
DFI: Driver Fault Interrupt Status Register (R, Address = 09H)
Symbol
Position
Default
DFI[7:0]
DFI.7-0
00H
Description
0 = (Default). Or after a DF read operation.
1 = Any transition on DFn (Corresponding DFMn is set to ‘1’).
RS: Software Reset Register (W, Address = 0AH)
Symbol
Position
Default
RS[7:0]
RS.7-0
FFH
Description
Writing to this register will not change the content in this register but initiate a 1 µs reset cycle, which means all the registers
in the device are set to their default values.
PMON: Performance Monitor Configuration Register (R/W, Address = 0BH)
Symbol
Position
Default
-
PMON.7-4
0000
MC[3:0]
PMON.3-0
0000
Description
0 = Normal operation. (Default)
1 = Reserved.
0000 = Normal operation without monitoring (Default)
0001 = Monitor Receiver 1
0010 = Monitor Receiver 2
0011 = Monitor Receiver 3
0100 = Monitor Receiver 4
0101 = Monitor Receiver 5
0110 = Monitor Receiver 6
0111 = Monitor Receiver 7
1000 = Normal operation without monitoring
1001 = Monitor Transmitter 1
1010 = Monitor Transmitter 2
1011 = Monitor Transmitter 3
1100 = Monitor Transmitter 4
1101 = Monitor Transmitter 5
1110 = Monitor Transmitter 6
1111 = Monitor Transmitter 7
LAC: LOS/AIS Criteria Configuration Register (R/W, Address = 0DH)
Symbol
LAC[7:0]
Position
LAC.7-0
Default
00H
Description
For E1 mode, the criterion is selected as below:
0 = G.775 (Default)
1 = ETSI 300 233
For T1 mode, the criterion meets T1.231.
ATAO: Automatic TAOS Configuration Register (R/W, Address = 0EH)
Symbol
Position
Default
ATAO[7:0]
ATAO.7-0
00H
Description
0 = No automatic transmit all ones. (Default)
1 = Automatic transmit all ones to the line side during LOS.
26
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
GCF: Global Configuration Register (R/W, Address = 0FH)
Symbol
Position
Default
-
GCF.7-6
00
SCPB
GCF.5
0
-
GCF.4-0
00000
Description
0 = Normal operation.
1 = Reserved.
0 = Short circuit protection is enabled.
1 = Short circuit protection is disabled.
0 = Normal operation.
1 = Reserved.
TSIA: Indirect Address Register for Transmit Template Select Registers (R/W, Address = 10H)
Symbol
Position
Default
-
TSIA.7-3
00000
TSIA[2:0]
TSIA.2-0
000
Description
0 = Normal operation. (Default)
1 = Reserved.
000 = Channel 0 (Default)
001 = Channel 1
010 = Channel 2
011 = Channel 3
100 = Channel 4
101 = Channel 5
110 = Channel 6
111 = Channel 7
TS: Transmit Template Select Register (R/W, Address = 11H)
Symbol
Position
Default
-
TS.7-3
00000
TS[2-0]
TS.2-0
000
Description
0 = Normal operation. (Default)
1 = Reserved.
TS[2:0] pins select one of eight built-in transmit template for different applications.
TS[2:0]
000
001
010
011
100
101
110
111
Mode
E1
Cable Length
75 Ω coaxial cable/120 Ω twisted pair cable.
Reserved.
T1
T1
T1
T1
T1
0 - 133 ft.
133 - 266 ft.
266 - 399 ft.
399 - 533 ft.
533 - 655 ft.
OE: Output Enable Configuration Register (R/W, Address = 12H)
Symbol
Position
Default
OE[7:0]
OE.7-0
00H
Description
0 = Transmit drivers enabled. (Default)
1 = Transmit drivers in high impedance state.
ADDP: Address Pointer Control Register (R/W, Address = 1F H)
Symbol
Position
Default
ADDP[7:0]
ADDP.7-0
00H
Description
Two kinds of configuration in this register can be set to switch between primary register bank and expanded register bank.
When power up, the address pointer will point to the top address of primary register bank automatically.
00H = The address pointer points to the top address of primary register bank (default).
AAH = The address pointer points to the top address of expanded register bank.
27
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
3.3.2
INDUSTRIAL TEMPERATURE RANGES
EXPANDED REGISTER DESCRIPTION
e-AFE: AFE Enable Selection Register (R/W, Expanded Address = 02H)
Symbol
Position
Default
AFE[7:0]
AFE.7-0
00H(1)
Description
0 = Reserved (Default) Note: For remote loopback operation in G.772 monitoring mode, bit 0 can be set to '0'.
1 = AFE mode enabled.
1. In host mode, AFE[7:0] bits must be set to ‘FFH’ for normal device operation.
e-RPDN: Receiver n Powerdown Register (R/W, Expanded Address = 03H)
Symbol
RPDN[7:0]
Position
RPDN.7-0
Default
00H
Description
0 = Normal operation. (Default)
1 = Receiver n is powered down.
e-TPDN: Transmitter n Powerdown Register (R/W, Expanded Address = 04H)
Symbol
Position
Default
TPDN[7:0]
TPDN.7-0
00H
Description
0 = Normal operation. (Default)
1 = Transmitter n is powered down(1) (the corresponding transmit output driver enters a low power high impedance mode).
1. Transmitter n is powered down when either pin TCLKn is pulled low or TPDNn is set to ‘1’
e-EQUA: Receive Equalizer Enable/Disable Register (R/W, Expanded Address = 07H)
Symbol
Position
Default
Description
EQUA[7:0]
EQUA.7-0
00H
0 = Normal operation. (Default)
1 = Equalizer in Receiver n is enabled, which can improve the receive performance when transmission length is more than
200 m.
28
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
4
IEEE STD 1149.1 JTAG TEST
ACCESS PORT
The JTAG boundary scan registers includes BSR (Boundary Scan
Register), IDR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure-12 for architecture.
The IDT82V2048L supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
4.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR)
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the TMS and TCK pins. Data is
shifted into the registers via the TDI pin, and shifted out of the registers
via the TDO pin. JTAG test data are clocked at a rate determined by
JTAG test clock.
Digital output pins
INDUSTRIAL TEMPERATURE RANGES
The IR with instruction decode block is used to select the test to be
executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register. See
Table-13 Instruction Register Description on page 30 for details of the
codes and the instructions related.
Digital input pins
parallel latched output
BSR (Boundary Scan Register)
MUX
IDR (Device Identification Register)
TDI
MUX
BR (Bypass Register)
IR (Instruction Register)
Control<6:0>
TMS
TRST
TAP
(Test Access Port)
Controller
Select
High-Z Enable
TCK
Figure-12 JTAG Architecture
29
TDO
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-13 Instruction Register Description
IR Code
Instruction
Comments
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the
EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be
sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by
shifting the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading
patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
100
Sample/Preload
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
between TDI and TDO. The normal path between IDT82V2048L logic and the I/O pins is maintained. Primary device
inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
110
Idcode
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
111
Bypass
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used
to bypass the device.
000
4.2.2
Table-14 Device Identification Register Description
4.2
Bit No.
Comments
0
Set to ‘1’
1~11
Producer Number
12~27
Part Number
28~31
Device Revision
BYPASS REGISTER (BR)
The BR consists of a single bit. It can provide a serial path between
the TDI input and TDO output, bypassing the BSR to reduce test access
times.
4.2.3
BOUNDARY SCAN REGISTER (BSR)
The BSR can apply and read test patterns in parallel to or from all the
digital I/O pins. The BSR is a 98 bits long shift register and is initialized
and read using the instruction EXTEST or SAMPLE/PRELOAD. Each
pin is related to one or more bits in the BSR. Please refer to Table-15 for
details of BSR bits and their functions.
JTAG DATA REGISTER
4.2.1 DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the producer number, part number and
the device revision, which can be used to verify the proper version or
revision number that has been used in the system under test. The IDR is
32 bits long and is partitioned as in Table-14. Data from the IDR is
shifted out to TDO LSB first.
Table-15 Boundary Scan Register Description
Bit No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit Symbol
POUT0
PIN0
POUT1
PIN1
POUT2
PIN2
POUT3
PIN3
POUT4
PIN4
POUT5
PIN5
POUT6
PIN6
POUT7
PIN7
Pin Signal
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Comments
30
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-15 Boundary Scan Register Description (Continued)
Bit No.
Bit Symbol
Pin Signal
Type
16
PIOS
N/A
-
17
18
19
20
21
22
TCLK1
TDP1
TDN1
RC1
RDP1
RDN1
TCLK1
TDP1
TDN1
RC1
RDP1
RDN1
I
I
I
O
O
O
23
HZEN1
N/A
-
24
25
26
27
28
29
30
LOS1
TCLK0
TDP0
TDN0
RC0
RDP0
RDN0
LOS1
TCLK0
TDP0
TDN0
RC0
RDP0
RDN0
O
I
I
I
O
O
O
31
HZEN0
N/A
-
32
33
34
35
36
LOS0
MODE1
LOS3
RDN3
RDP3
LOS0
MODE1
LOS3
RDN3
RDP3
O
I
O
O
O
37
HZEN3
N/A
-
38
39
40
41
42
43
44
RC3
TDN3
TDP3
TCLK3
LOS2
RDN2
RDP2
RC3
TDN3
TDP3
TCLK3
LOS2
RDN2
RDP2
O
I
I
I
O
O
O
45
HZEN2
N/A
-
46
47
48
49
50
51
RC2
TDN2
TDP2
TCLK2
INT
ACK
RC2
TDN2
TDP2
TCLK2
INT
ACK
O
I
I
I
O
O
52
SDORDYS
N/A
-
53
54
55
WRB
RDB
ALE
DS
R/W
ALE
I
I
I
Comments
Controls pins D[7:0].
When ‘0’, the pins are configured as outputs. The output values to the pins are set in POUT 7~0.
When ‘1’, the pins are in high impedance. The input values to the pins are read in PIN 7~0.
Controls pin RDP1, RDN1 and RC1.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Controls pin RDP0, RDN0 and RC0.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Controls pin RDP3, RDN3 and RC3.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Controls pin RDP2, RDN2 and RC2.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Control pin ACK.
When ‘0’, the output is enabled on pin ACK.
When ‘1’, the pin is in high impedance.
31
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-15 Boundary Scan Register Description (Continued)
Bit No.
56
57
58
59
60
61
62
63
Bit Symbol
CSB
MODE0
TCLK5
TDP5
TDN5
RC5
RDP5
RDN5
Pin Signal
CS
MODE0
TCLK5
TDP5
TDN5
RC5
RDP5
RDN5
Type
I
I
I
I
I
O
O
O
64
HZEN5
N/A
-
65
66
67
68
69
70
71
LOS5
TCLK4
TDP4
TDN4
RC4
RDP4
RDN4
LOS5
TCLK4
TDP4
TDN4
RC4
RDP4
RDN4
O
I
I
I
O
O
O
72
HZEN4
N/A
-
73
74
75
76
77
78
LOS4
OE
CLKE
LOS7
RDN7
RDP7
LOS4
OE
CLKE
LOS7
RDN7
RDP7
O
I
I
O
O
O
79
HZEN7
N/A
-
80
81
82
83
84
85
86
RC7
TDN7
TDP7
TCLK7
LOS6
RDN6
RDP6
RC7
TDN7
TDP7
TCLK7
LOS6
RDN6
RDP6
O
I
I
I
O
O
O
87
HZEN6
N/A
-
88
89
90
91
92
93
94
95
96
97
98
RC6
TDN6
TDP6
TCLK6
MCLK
MODE2
A4
A3
A2
A1
A0
RC6
TDN6
TDP6
TCLK6
MCLK
MODE2
A4
A3
A2
A1
A0
O
I
I
I
I
I
I
I
I
I
I
Comments
Controls pin RDP5, RDN5 and RC5.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Controls pin RDP4, RDN4 and RC4.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Controls pin RDP7, RDN7 and RC7.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
Controls pin RDP6, RDN6 and RC6.
When ‘0’, the outputs are enabled on the pins.
When ‘1’, the pins are in high impedance.
32
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
4.3
TEST ACCESS PORT CONTROLLER
INDUSTRIAL TEMPERATURE RANGES
instruction registers. The value shown next to each state transition in
this figure states the value present at TMS at each rising edge of TCK.
Refer to Table-16 for details of the state description.
The TAP controller is a 16-state synchronous state machine. Figure13 shows its state diagram A description of each state follows. Note that
the figure contains two main branches to access either the data or
Table-16 TAP Controller State Description
State
Description
Test Logic Reset
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register
with the IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5
rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically enters this state at power-up.
Run-Test/Idle
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The
instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller
moves to the Select-DR state.
Select-DR-Scan
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction
retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR
state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller
moves to the Select-IR-Scan state.
Capture-DR
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction
does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in
this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
Shift-DR
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward
its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising
edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
Exit1-DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR
state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-DR
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI
and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test
sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller
moves to the Exit2-DR state.
Exit2-DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-DR
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST
and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into
the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes
only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state.
Select-IR-Scan
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and
a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction
does not change during this state.
Capture-IR
In this controller state, the shift register contained in the instruction register loads a fixed value of ‘100’ on the rising edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1IR state if TMS is held high, or the Shift-IR state if TMS is held low.
Shift-IR
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its
serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction
does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR
state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
33
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-16 TAP Controller State Description (Continued)
State
Description
Exit1-IR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-IR
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected
by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as
long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
Exit2-IR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-IR
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK.
When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction
retain their previous value.
1
Test-logic Reset
0
0
Run Test/Idle
1
Select-DR
1
Select-IR
0
1
0
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
Exit1-DR
1
Exit1-IR
0
0
0
0
Pause-DR
Pause-IR
1
0
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
0
1
Figure-13 JTAG State Diagram
34
1
Update-IR
1
0
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING
Symbol
VDDA, VDDD
VDDIO0, VDDIO1
VDDT0-7
Min
Max
Unit
Core Power Supply
Parameter
-0.5
4.0
V
I/O Power Supply
-0.5
4.0
V
Transmit Power Supply
-0.5
7.0
V
GND-0.5
5.5
V
GND-0.5
VDDA+ 0.5
VDDD+ 0.5
V
V
100
mA
10
mA
±100
mA
Input Voltage, any digital pin
Vin
Input Voltage(1), RTIPn pins and RRINGn pins
ESD Voltage, any pin(2)
Transient Latch-up Current, any pin
Iin
2000
Input Current, any digital pin(3)
V
-10
DC Input Current, any analog pin(3)
Pd
Ts
Maximum Power Dissipation in package
-65
Storage Temperature
1.6
W
+150
°C
CAUTION: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.
Referenced to ground
2. Human body model
3.
Constant input current
RECOMMENDED OPERATING CONDITIONS
Symbol
VDDA, VDDD
Parameter
Min
Typ
Max
Unit
Core Power Supply
3.13
3.3
3.47
V
VDDIO
I/O Power Supply
3.13
3.3
3.47
V
VDDT(1)
Transmitter Supply
3.3 V
3.13
3.3
3.47
V
5V
4.75
5.0
5.25
V
-40
25
25
85
°C
Ω
55
65
mA
15
25
mA
230
440
mA
mA
TA
RL
IVDD
IVDDIO
IVDDT
Ambient Operating Temperature
Output load at TTIPn pins and TRINGn pins
Average Core Power Supply Current(2)
I/O Power Supply Current(3)
Average transmitter power supply current, T1 mode
50% ones density data:
100% ones density data:
(2),(4),(5)
1. T1 is only 5V VDDT.
2.
Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.
3.
Digital output is driving 50 pF load, digital input is within 10% of the supply rails.
4.
T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101).
5.
Power consumption includes power absorbed by line load and external transmitter components.
35
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
POWER CONSUMPTION
Symbol
Parameter
LEN
Min
Typ
Max(1)(2)
Unit
000
000
-
662
1100
1177
mW
mW
000
000
-
576
930
992
mW
mW
E1, 3.3 V, 75 Ω Load
50% ones density data:
100% ones density data:
E1, 3.3 V, 120 Ω Load
50% ones density data:
100% ones density data:
E1, 5.0 V, 75 Ω Load
50% ones density data:
100% ones density data:
E1, 5.0 V, 120 Ω Load
50% ones density data:
100% ones density data:
000
000
-
910
1585
1690
mW
mW
000
000
-
785
1315
1410
mW
mW
T1, 5.0 V, 100 Ω Load(3)
50% ones density data:
100% ones density data:
101
111
-
1185
2395
2670
mW
mW
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.
2. Power consumption includes power absorbed by line load and external transmitter components.
3.
T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101).
DC CHARACTERISTICS
Symbol
VIL
Parameter
Min
Typ
1
--3
All other digital inputs pins
Input Mid Level Voltage
1
--3
MODE2 and Dn pins
VIH
1.
1
--- VDDIO
2
V
0.8
V
2
--- VDDIO-0.2
3
V
2
--- VDDIO+ 0.2
3
All other digital inputs pins
V
2.0
VOL
Output Low level Voltage(1) (Iout = 1.6 mA)
VOH
Output High level Voltage(1) (Iout = 400 µA)
Analog Input Quiescent Voltage (RTIPn/RRINGn pin while floating)
Input High Level Current (MODE2 and Dn pins)
Input Low Level Current (MODE2 and Dn pins)
Input Leakage Current
TMS, TDI and TRST pins
All other digital input pins
High Impedance Leakage Current
Output High Impedance on TTIPn and TRINGn pins
IZL
ZOH
VDDIO+0.2
VDDIO-0.2
Input High Voltage
MODE2 and Dn pins
VMA
IH
IL
II
Unit
Input Low Level Voltage
MODE2 and Dn pins
VIM
Max
0.4
Output drivers will output CMOS logic levels into CMOS loads.
36
2.4
1.33
-10
-10
150
1.4
V
V
VDDIO
V
1.47
50
50
V
µA
µA
50
10
10
µA
µA
µA
kΩ
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
TRANSMITTER CHARACTERISTICS
Symbol
Vo-p
VO-S
Parameter
Min
Typ
Max
Unit
Output Pulse Amplitudes
E1, 75 Ω load
E1, 120 Ω load
T1, 100 Ω load
2.14
2.7
2.4
2.37
3.0
3.0
2.6
3.3
3.6
V
V
V
Zero (space) Level
E1, 75 Ω load
E1, 120 Ω load
T1, 100 Ω load
-0.237
-0.3
-0.15
0.237
0.3
0.15
V
V
V
-1
+1
%
200
mV
256
362
ns
ns
(1)
Transmit Amplitude Variation with supply
Difference between pulse sequences for 17 consecutive pulses
TPW
RTX
Output Pulse Width at 50% of nominal amplitude
E1:
T1:
232
338
Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval
0.95
Transmit Return Loss
1.05
(2)
E1, 75 Ω
E1, 120 Ω
T1
(VDDT = 5 V)
Td
Transmit Path Delay
ISC
Line Short Circuit Current (3)
51 kHz – 102 kHz
102 kHz – 2.048 MHz
2.048 MHz – 3.072 MHz
51 kHz – 102 kHz
102 kHz – 2.048 MHz
2.048 MHz – 3.072 MHz
51 kHz – 102 kHz
102 kHz – 2.048 MHz
2.048 MHz – 3.072 MHz
1. E1: measured at the line output ports; T1: measured at the DSX
2.
244
350
Test at IDT82V2048L evaluation board
3. Measured on device, between TTIPn and TRINGn
37
15
15
15
15
15
15
15
15
15
dB
dB
dB
dB
dB
dB
dB
dB
dB
3
U.I.
180
mAp
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
RECEIVER CHARACTERISTICS
Symbol
ATT
IA
Parameter
Min
Typ
Permissible Cable Attenuation (E1: @ 1024 kHz, T1: @ 772 kHz)
0.1
Input Amplitude
Max
Unit
15
dB
0.9
Vp
SIR
Signal to Interference Ratio Margin
SRE
Data Decision Threshold (refer to peak input voltage)
50
%
Data Slicer Threshold
150
mV
(1)
-15
dB
(2)
Analog Loss Of Signal
Declare/Clear:
120/150
Allowable consecutive zeros before LOS
E1, G.775:
E1, ETSI 300 233:
T1, T1.231-1993
12.5
mVp
% ones
Peak to Peak Intrinsic Receive Jitter (JA disabled)
E1 (wide band):
T1 (wide band):
0.0625
0.0625
U.I.
U.I.
ZDM
Receiver Differential Input Impedance
ZCM
Receiver Common Mode Input Impedance to GND
10
kΩ
RRX
Receive Return Loss
51 kHz – 102 kHz
102 kHz – 2.048 MHz
2.048 MHz – 3.072 MHz
20
20
20
dB
dB
dB
120
Receive Path Delay
3
1. E1: per G.703, O.151 @ 6 dB cable attenuation. T1: @ 655 ft. of 22 ABAM cable
2.
280/350
32
2048
175
LOS Reset
Clock Recovery Mode
JRXp-p
200/250
Measured on device, between RTIPn and RRINGn, all ones signal
38
kΩ
U.I.
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
TRANSCEIVER TIMING CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
MCLK Frequency
2.048
1.544
E1:
T1:
MHz
MHz
MCLK Tolerance
-100
100
ppm
MCLK Duty Cycle
40
60
%
Transmit Path
TCLK Frequency
2.048
1.544
E1:
T1:
t1
t2
TCLK Tolerance
-50
+50
TCLK Duty Cycle
10
90
Transmit Data Setup Time
40
Transmit Data Hold Time
40
Delay time of TCLK low to driver High Impedance
RX Data Prop. Delay(2)
(2)
t6
Receive Rise Time
t7
Receive Fall Time(2)
1. 0 dB cable loss
2.
%
ns
40
44
200
300
244
324
1
µs
48
µs
RDN/RDP Pulse Width(1)
E1:
T1:
t5
ppm
ns
Delay time of OE low to driver High Impedance
Receive Path
t4
MHz
MHz
15 pF load
39
ns
ns
40
ns
14
ns
12
ns
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
TCLKn
t1
t2
TDPn
TDNn
Figure-14 Transmit System Interface Timing
RTIPn, RRINGn
t5
t4
RDPn
(CLKE = 1)
RDNn
(CLKE = 1)
t6
t5
t7
t4
t6
t7
t6
t7
t5
t4
RDPn
(CLKE = 0)
t6
t7
t5
t4
RDNn
(CLKE = 0)
t4
t4
t6
t7
XOR, RDPn + RDNn
Figure-15 Receive System Interface Timing
40
t4
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
JTAG TIMING CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
t1
TCK Period
200
ns
t2
TMS to TCK setup Time
TDI to TCK Setup Time
50
ns
t3
TCK to TMS Hold Time
TCK to TDI Hold Time
50
ns
t4
TCK to TDO Delay Time
100
t1
TCK
t2
t3
TMS
TDI
t4
TDO
Figure-16 JTAG Interface Timing
41
ns
Comments
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
PARALLEL HOST INTERFACE TIMING CHARACTERISTICS
INTEL MODE READ TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
1.
Parameter
Min
Active RD Pulse Width
Active CS to Active RD Setup Time
Inactive RD to Inactive CS Hold Time
Valid Address to Inactive ALE Setup Time (in Multiplexed Mode)
Invalid RD to Address Hold Time (in Non-Multiplexed Mode)
Active RD to Data Output Enable Time
Inactive RD to Data High Impedance Delay Time
Active CS to RDY delay time
Inactive CS to RDY High Impedance Delay Time
Inactive RD to Inactive INT Delay Time
Address Latch Enable Pulse Width (in Multiplexed Mode)
Address Latch Enable to RD Setup Time (in Multiplexed Mode)
Address Setup time to Valid Data Time (in Non-Multiplexed Mode)
Inactive RD to Active RDY Delay Time
Active RD to Active RDY Delay Time
Inactive ALE to Address Hold Time (in Multiplexed Mode)
The t1 is determined by the start time of the valid data when the RDY signal is not used.
42
90
0
0
5
0
7.5
7.5
6
6
10
0
18
10
30
5
Typ
Max
15
15
12
12
20
32
15
85
Unit
Comments
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
t2
CS
t3
t1
RD
ALE(=1)
t13
t5
ADDRESS
A[4:0]
t6
t7
DATA OUT
D[7:0]
t14
t8
t9
RDY
t15
t10
INT
Figure-17 Non-Multiplexed Intel Mode Read Timing
t2
CS
t3
t1
RD
t11
t12
ALE
t13
t16
t4
AD[7:0]
t6
t7
ADDRESS
DATA OUT
t14
t8
t9
RDY
t15
INT
Figure-18 Multiplexed Intel Mode Read Timing
43
t10
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
INTEL MODE WRITE TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Parameter
Min
Active WR Pulse Width
Active CS to Active WR Setup Time
Inactive WR to Inactive CS Hold Time
Valid Address to Latch Enable Setup Time (in Multiplexed Mode)
Invalid WR to Address Hold Time (in Non-Multiplexed Mode)
Valid Data to Inactive WR Setup Time
Inactive WR to Data Hold Time
Active CS to Inactive RDY Delay Time
Active WR to Active RDY Delay Time
Inactive WR to Inactive RDY Delay Time
Invalid CS to RDY High Impedance Delay Time
Address Latch Enable Pulse Width (in Multiplexed Mode)
Inactive ALE to WR Setup Time (in Multiplexed Mode)
Inactive ALE to Address hold time (in Multiplexed Mode)
Address setup time to Inactive WR time (in Non-Multiplexed Mode)
Typ
Max
90
0
0
5
2
5
10
6
30
10
6
10
0
5
5
12
85
15
12
Unit
Comments
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
1. The t1 can be 15 ns when RDY signal is not used.
CS
t2
t1
t3
WR
ALE(=1)
t15
t5
ADDRESS
A[4:0]
t7
t6
WRITE DATA
D[7:0]
t10
t8
t11
RDY
t9
Figure-19 Non-Multiplexed Intel Mode Write Timing
t2
t3
CS
t1
WR
t12
t13
ALE
t14
t4
AD[7:0]
t6
ADDRESS
t8
t7
WRITE DATA
t11
t9
RDY
t10
Figure-20 Multiplexed Intel Mode Write Timing
44
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
MOTOROLA MODE READ TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
Min
Active DS Pulse Width
Active CS to Active DS Setup Time
Inactive DS to Inactive CS Hold Time
Valid R/W to Active DS Setup Time
Inactive DS to R/W Hold Time
Valid Address to Active DS Setup Time (in Non-Multiplexed Mode)
Active DS to Address Hold Time (in Non-Multiplexed Mode)
Active DS to Data Valid Delay Time (in Non-Multiplexed Mode)
Active DS to Data Output Enable Time
Inactive DS to Data High Impedance Delay Time
Active DS to Active ACK Delay Time
Inactive DS to Inactive ACK Delay Time
Inactive DS to Invalid INT Delay Time
Active AS to Active DS Setup Time (in Multiplexed Mode)
Typ
Max
90
0
0
0
0.5
5
10
20
7.5
7.5
30
10
35
15
15
85
15
20
5
1. The t1 is determined by the start time of the valid data when the ACK signal is not used.
CS
t4
t5
R/W
t1
t2
t3
DS
ALE(=1)
t6
t7
ADDRESS
A[4:0]
t10
t8
DATA OUT
D[7:0]
t9
ACK
t12
t11
t13
INT
Figure-21 Non-Multiplexed Motorola Mode Read Timing
CS
t2
t3
R/W
t1
t4
t5
DS
t14
AS
t6
AD[7:0]
t7
ADDRESS
t8
t9
t10
DATA OUT
t11
t12
ACK
t13
INT
Figure-22 Multiplexed Motorola Mode Read Timing
45
Unit
Comments
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
MOTOROLA MODE WRITE TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
Min
Active DS Pulse Width
Active CS to Active DS Setup Time
Inactive DS to Inactive CS Hold Time
Valid R/W to Active DS Setup Time
Inactive DS to R/W Hold Time
Valid Address to Active DS Setup Time (in Non-Multiplexed Mode)
Valid DS to Address Hold Time (in Non-Multiplexed Mode)
Valid Data to Inactive DS Setup Time
Inactive DS to Data Hold Time
Active DS to Active ACK Delay Time
Inactive DS to Inactive ACK Delay Time
Active AS to Active DS (in Multiplexed Mode)
Inactive DS to Inactive AS Hold Time (in Multiplexed Mode)
Typ
Max
90
0
0
10
0
10
10
5
10
30
10
0
15
85
15
1. The t1 can be 15ns when the ACK signal is not used.
CS
t4
t5
R/W
t1
t2
t3
DS
ALE(=1)
t6
t7
ADDRESS
A[4:0]
t8
t9
WRITE DATA
t11
D[7:0]
t10
ACK
Figure-23 Non-Multiplexed Motorola Mode Write Timing
CS
t2
t3
R/W
t4
t1
t5
DS
t12
t13
AS
t6
AD[7:0]
t8
t7
ADDRESS
t9
WRITE DATA
t10
ACK
Figure-24 Multiplexed Motorola Mode Writing Timing
46
t11
Unit
Comments
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
SERIAL HOST INTERFACE TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Parameter
Min
SCLK High Time
SCLK Low Time
Active CS to SCLK Setup Time
Last SCLK Hold Time to Inactive CS Time
CS Idle Time
SDI to SCLK Setup Time
SCLK to SDI Hold Time
Rise/Fall Time (any pin)
SCLK Rise and Fall Time
SCLK to SDO Valid Delay Time
SCLK Falling Edge to SDO High Impedance Hold Time (CLKE = 0) or CS
Rising Edge to SDO High Impedance Hold Time (CLKE = 1)
Typ
Max
Unit
Comments
100
50
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load = 50 pF
25
25
10
50
50
5
5
25
100
ns
CS
t3
t1
t4
t2
t5
SCLK
t6
SDI
t7
t7
LSB
MSB
LSB
CONTROL BYTE
DATA BYTE
Figure-25 Serial Interface Write Timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
t10
t4
CS
SDO
0
1
2
3
4
5
t11
7
6
Figure-26 Serial Interface Read Timing with CLKE = 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS
t4
t10
t11
SDO
0
1
2
3
4
Figure-27 Serial Interface Read Timing with CLKE = 1
47
5
6
7
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXXXX
Device Type
XX
Package
X
Process/
Temperature
Range
Blank
Industrial (-40 °C to + 85 °C)
BB
BBG
DA
DAG
Plastic Ball Grid Array (PBGA, BB160)
Green Plastic Ball Grid Array (PBGA, BBG160)
Thin Quad Flatpack (TQFP, DA144)
Green Thin Quad Flatpack (TQFP, DAG144)
82V2048L T1/E1 Short Haul Analog Front End
DATASHEET DOCUMENT HISTORY
07/29/2005
pgs. 1, 4, 5, 7 to 10, 13, 15 to 17, 19, 20, 22, 23, 25, 25, 28, 32, 35, 37 to 40, 43 to 47
for SALES:
1-800-345-7015 or 408-284-8200
fax: 408-284-2775
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
www.idt.com
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
48
for Tech Support:
408-360-1552
email:[email protected]
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