LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 LMK01000 Family LMK01000 Family 1.6 GHz High Performance Clock Buffer, Divider, and Distributor Check for Samples: LMK01000 FEATURES 1 • • • 2 • • 30 fs additive jitter (100 Hz to 20 MHz) Dual clock inputs Programmable output channels (0 to 1600 MHz) External synchronization Pin compatible family of clocking devices • • 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Device LVDS Outputs LVPECL Outputs LMK01000 3 5 LMK01010 8 0 LMK01020 0 8 TARGET APPLICATIONS • • • • • • High performance Clock Distribution Wireless Infrastructure Medical Imaging Wired Communications Test and Measurement Military / Aerospace DESCRIPTION The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners. The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains. Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com System Diagram CLKout0 LMK010x0 LMX2531 CLKin1 PLL+VCO Clock Divider and Distributor ADC CLKout7 ADC CLKout0 CLKin0 LMK010x0 Clock Divider and Distributor CLKin1 Serializer/ Deserializer CLKout1 CLKout4 LMX2531 CLKout7 PLL+VCO FPGA ADC Functional Block Diagram CLK CLKin0 CLKin0* Mux Distribution Path CLKin1 CLKin1* DATA Control Registers PWire Port LE CLKout0 CLKout0* Mux CLKout1 CLKout1* Mux CLKout2 CLKout2* Mux CLKout3 CLKout3* Mux Divider Divider Delay GOE SYNC* Mux CLKout4 CLKout4* Mux CLKout5 CLKout5* Mux CLKout6 CLKout6* Mux CLKout7 CLKout7* Delay Divider Divider Delay Delay Divider Divider Delay Delay Divider Divider Delay Delay Device Control Low Clock Buffers High Clock Buffers 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 Connection Diagram CLKout7* CLKout7 Vcc14 CLKout6* CLKout6 Vcc13 CLKout5* CLKout5 Vcc12 CLKout4* CLKout4 Vcc11 Figure 1. 48-Pin LLP Package 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 Bias NC 2 35 CLKin1* Vcc1 3 34 CLKin1 CLKPWire 4 33 Vcc10 DATAPWire 5 32 NC 31 Vcc9 LLP-48 Top Down View LEPWire 6 NC 7 30 Vcc8 Vcc2 8 29 CLKin0* NC 9 28 CLKin0 NC 10 27 SYNC* 26 Vcc7 25 GND 14 15 16 17 18 19 20 21 22 23 24 CLKout1 CLKout1* Vcc5 CLKout2 CLKout2* Vcc6 CLKout3 CLKout3* Vcc3 13 Vcc4 12 CLKout0 11 Test CLKout0* GOE DAP Pin Functions Pin Descriptions Pin # Pin Name I/O Description 1, 25 GND - Ground 2, 7, 9,10, 32 NC - No Connect. Pin is not connected to the die. 3, 8, 13, 16, 19, 22, 26, 30, 31, 33, 37, 40, 43, 46 Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14 - Power Supply 4 CLKuWire I MICROWIRE Clock Input 5 DATAuWire I MICROWIRE Data Input 6 LEuWire I MICROWIRE Latch Enable Input 11 GOE I Global Output Enable 12 Test O This is an output pin used strictly for test purposes and should be not connected for normal operation. However, any load of an impedance of more than 1 kΩ is acceptable. 14, 15 CLKout0, CLKout0* O Clock Output 0 17, 18 CLKout1, CLKout1* O Clock Output 1 20, 21 CLKout2, CLKout2* O Clock Output 2 23, 24 CLKout3, CLKout3* O Clock Output 3 27 SYNC* I Global Clock Output Synchronization Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 3 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Pin Descriptions (continued) Pin # Pin Name I/O 28, 29 CLKin0,CLKin0* I CLKin 0 Input; Must be AC coupled Description 34, 35 CLKin1, CLKin1* I CLKin 1 Input; Must be AC coupled 36 Bias I Bias Bypass 38, 39 CLKout4, CLKout4* O Clock Output 4 41, 42 CLKout5, CLKout5* O Clock Output 5 44, 45 CLKout6, CLKout6* O Clock Output 6 47, 48 CLKout7, CLKout7* O Clock Output 7 DAP DAP - Die Attach Pad should be connected to ground. The LMK01000 family is footprint compatible with the LMK03000/02000 family of devices. All CLKout pins are pin-to-pin compatible, and CLKin0 and CLKin1 are equivalent to OSCin and Fin, respectively. Device Configuration Information Output LMK01000 LMK01010 LMK01020 CLKout0 LVDS LVDS LVPECL CLKout1 LVDS LVDS LVPECL CLKout2 LVDS LVDS LVPECL CLKout3 LVPECL LVDS LVPECL CLKout4 LVPECL LVDS LVPECL CLKout5 LVPECL LVDS LVPECL CLKout6 LVPECL LVDS LVPECL CLKout7 LVPECL LVDS LVPECL These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Parameter Symbol Ratings Units V Power Supply Voltage VCC -0.3 to 3.6 Input Voltage VIN -0.3 to (VCC + 0.3) V TSTG -65 to 150 °C Lead Temperature (solder 4 s) TL +260 °C Junction Temperature TJ 125 °C Storage Temperature Range (1) (2) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV. Recommended Operating Conditions Symbol Min Typ Max Units Ambient Temperature Parameter TA -40 25 85 °C Power Supply Voltage VCC 3.15 3.3 3.45 V 4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 Package Thermal Resistance Package 48-Lead LLP (1) (1) θJA θJ-PAD (Thermal Pad) 27.4° C/W 5.8° C/W Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 5 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 Electrical Characteristics www.ti.com (1) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Symbol Parameter Conditions Min Typ Max Units Current Consumption All outputs enabled, no divide or delay ( CLKoutX_MUX = Bypassed ) Power Supply Current ICC (2) Per channel, no divide or delay (CLKoutX_MUX = Bypassed ) ICCPD Power Down Current LMK01000 271 LMK01010 160 LMK01020 338 LVDS 17.8 LVPECL (Includes Emitter Resistors) mA 40 POWERDOWN = 1 1 CLKin0, CLKin0*, CLKin1, CLKin1* fCLKin CLKin Frequency Range 1 1600 MHz (3) (4) SLEWCLKin CLKin Frequency Input Slew Rate DUTYCLKin CLKin Frequency Input Duty Cycle PCLKin Input Power Range for CLKin or CLKin* V/ns 0.5 fCLKin ≤ 800 MHz 30 70 fCLKin > 800 MHz 40 60 AC coupled -13 5 % dBm Clock Distribution Section--Delays DelayCLKout Maximum Allowable Delay fCLKoutX ≤ 1 GHz (Delay is limited to maximum programmable value) (4) 2250 fCLKoutX > 1 GHz (Delay is limited to 1/2 of a period) 0.5/f ps CLKou tX Clock Distribution Section - Divides DivideCLKoutX Allowable divide range. (Note that 1 is the only allowable odd divide value) fCLKinX ≤ 1300 MHz 1 510 1300 MHz < fCLKinX ≤ 1600 MHz 1 2 n/a Clock Distribution Section - LVDS Clock Outputs JitterADD Noise Floor (1) (2) (3) (4) (5) 6 Additive RMS Jitter (5) Divider Noise Floor (5) RL = 100 Ω Bandwidth = 100 Hz to 20 MHz Vboost = 1 RL = 100 Ω Vboost = 1 fCLKoutX = 200 MHz 80 fCLKoutX = 800 MHz 30 fCLKoutX = 1600 MHz 25 fCLKoutX = 200 MHz -156 fCLKoutX = 800 MHz -153 fCLKoutX = 1600 MHz -148 fs dBc/Hz The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. See section 3.2 for more current consumption / power dissipation calculation information. For all frequencies the slew rate, SLEWCLKin1, is measured between 20% and 80%. Specification is guaranteed by characterization and is not tested in production. The noise floor of the divider is measured as the far out phase noise of the divider. Typically this offset is 40 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. If the delay is used, then use section 1.3. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Symbol Parameter Conditions Equal loading and identical clock configuration RL = 100 Ω (4) Min Typ Max Units -30 ±4 30 ps 250 350 450 tSKEW CLKoutX to CLKoutY VOD Differential Output Voltage ΔVOD Change in magnitude of VOD for complementary output states RL = 100 Ω -50 VOS Output Offset Voltage RL = 100 Ω 1.07 0 ΔVOS Change in magnitude of VOS for complementary output states RL = 100 Ω ISA ISB Clock Output Short Circuit Current single ended ISAB Clock Output Short Circuit Current differential (6) Vboost=0 Vboost=1 mV 390 50 mV 1.37 0 V -35 35 mV Single ended outputs shorted to GND -24 24 mA Complementary outputs tied together -12 12 mA 1.25 Clock Distribution Section - LVPECL Clock Outputs JitterADD Noise Floor RL = 100 Ω Bandwidth = 100 Hz to 20 MHz Vboost = 1 Additive RMS Jitter (5) RL = 100 Ω Vboost = 1 Divider Noise Floor (7) (8) tSKEW CLKoutX to CLKoutY VOH Output High Voltage VOL Output Low Voltage VOD Differential Output Voltage fCLKoutX = 200 MHz 65 fCLKoutX = 800 MHz 25 fCLKoutX = 1600 MHz 25 fCLKoutX = 200 MHz -158 fCLKoutX = 800 MHz -154 fCLKoutX = 1600 MHz -148 Equal loading and identical clock configuration Termination = 50 Ω to Vcc - 2 V -30 Termination = 50 Ω to Vcc - 2 V (9) Vboost = 0 660 Vboost = 1 Digital LVTTL Interfaces ±3 fs dBc/Hz 30 ps Vcc 0.98 V Vcc 1.8 V 810 965 865 mV (10) VIH High-Level Input Voltage VIL Low-Level Input Voltage 2.0 IIH High-Level Input Current VIH = Vcc IIL Low-Level Input Current Vcc V 0.8 V -5.0 5.0 µA VIL = 0 -40.0 5.0 µA Vcc 0.4 VOH High-Level Output Voltage IOH = +500 µA VOL Low-Level Output Voltage IOL = -500 µA V 0.4 V (6) (7) See characterization plots to see how this parameter varies over frequency. The noise floor of the divider is measured as the far out phase noise of the divider. Typically this offset is 40 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. If the delay is used, then use section 1.3. (8) Specification is guaranteed by characterization and is not tested in production. (9) See characterization plots to see how this parameter varies over frequency. (10) Applies to GOE, LD, and SYNC*. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 7 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Symbol Parameter Conditions Digital MICROWIRE Interfaces Min Typ Max Units Vcc V (11) VIH High-Level Input Voltage 1.6 VIL Low-Level Input Voltage 0.4 V IIH High-Level Input Current VIH = Vcc -5.0 5.0 µA IIL Low-Level Input Current VIL = 0 -5.0 5.0 µA tCS Data to Clock Set Up Time See Data Input Timing 25 ns tCH Data to Clock Hold Time See Data Input Timing 8 ns tCWH Clock Pulse Width High See Data Input Timing 25 ns tCWL Clock Pulse Width Low See Data Input Timing 25 ns tES Clock to Enable Set Up Time See Data Input Timing 25 ns tCES Enable to Clock Set Up Time See Data Input Timing 25 ns tEWH Enable Pulse Width High See Data Input Timing 25 ns MICROWIRE Timing (11) Applies to CLKuWire, DATAuWire, and LEuWire. Serial Data Timing Diagram MSB DATAuWire D27 LSB D26 D25 D24 D23 D0 A3 A2 A1 A0 CLKuWire tCES tCS tCH tCWH tCWL tES LEuWire tEWH Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. The slew rate of CLKuWire, DatauWire, and LEuWire should be at least 30 V/µs. 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 Functional Description The LMK01000 family includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer in each channel. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to up to eight system components. This family of devices comes in a 48-pin LLP package that is pin-to-pin and footprint compatible with other LMK02000/LMK03000 family of clocking devices. BIAS PIN To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. CLKin0/CLKin0* and CLKin1/CLKin1 INPUT PORTS The device can be driven either by the CLKin0/CLKin0* or the CLKin1/CLKin1* pins. The choice of which one to use is software selectable. These input ports must be AC coupled. To drive these inputs in a single ended fashion, AC ground the complementary input. When choosing AC coupling capacitors for clock signals 0.1 µF is a good starting point, but lower frequencies may require higher value capacitors while higher frequencies may use lower value capacitors. CLKout DELAYS Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a 150 ps step size and range from 0 to 2250 ps of total delay. When the delay is enabled it adds to the output noise floor; the total additive noise is 10(log( 10^(Output Noise Floor/10) + 10^(Delay Noise Floor/10) ). Refer to the Typical Performance Characteristics plots for the Delay Noise Floor information. LVDS/LVPECL OUTPUTS Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0. GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. When the SYNC* pin goes high, the divided clock outputs are activated and will transition to a high state simultaneously. Clocks in the Bypassed state are not affected by SYNC* and are always synchronized with the divided outputs. The SYNC* pin must be held low for greater than one clock cycle of the Frequency Input port, also known as the distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more cycles. When the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more distribution path clock cycles have passed. See the SYNC* timing diagram for further detail. In the timing diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4. SYNC* Timing Diagram Distribution Path SYNC* CLKout0 CLKout1 CLKout2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 9 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock output synchronization is not guaranteed. CONNECTION TO LVDS OUTPUTS LMK01000 and LMK01010 LVDS outputs can be connected in AC or DC coupling configurations; however, in DC coupling configuration, proper conditions must be presented by the LVDS receiver. To ensure such conditions, we recommend the usage of LVDS receivers without fail-safe or internal input bias such as National Semiconductor's DS90LV110T. The LMK01000 family LVDS drivers provide the adequate DC bias for the LVDS receiver. We recommend AC coupling when using LVDS receivers with fail-safe or internal input bias. CLKout OUTPUT STATES Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or EN_CLKout_Global is set to 0. CLKoutX _EN bit EN_CLKout _Global bit GOE pin Clock X Output State 1 1 Low Low Don't care 0 Don't care Off 0 Don't care Don't care Off 1 1 High / No Connect Enabled When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt. GLOBAL OUTPUT ENABLE The GOE pin provides an internal pull-up resistor. If it is not terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit. POWER-ON-RESET When supply voltage to the device increases monotonically from ground to Vcc, the power-on-reset circuit sets all registers to their default values, which are specified in the General Programming Information section. Voltage should be applied to all Vcc pins simultaneously. General Programming Information The LMK01000 family device is programmed using several 32-bit registers. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. During programming, LEuWire is low and serial data is clocked in on the rising edge of clock (MSB first). When LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers R0 to R7 and R14 need to be programmed for proper device operation. It is required to program register R14. RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to ensure the device is in a default state. It is not necessary to program R0 again, but if R0 is programmed again, the reset bit is programmed clear (RESET = 0). An example programming sequence is shown below. • Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset bit is set in R0, the other R0 bits are ignored. – If R0 is programmed again, the reset bit is programmed clear (RESET = 0). 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com • • SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings. Program R14 with global clock output bit, power down setting. – R14 must be programmed in accordance with the register map as shown in the register map (See Section 2.2). Table 1. Register Map Re gis ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Data [27:0] 3 2 1 0 A3 A2 A1 A0 R0 RE SE T 0 0 0 0 0 0 0 0 0 0 0 0 CLKout0 _MUX [1:0] CL Ko ut0 _E N R1 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout1 _MUX [1:0] CL Ko ut1 _E N CLKout1_DIV [7:0] CLKout1_DLY [3:0] 0 0 0 1 R2 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout2 _MUX [1:0] CL Ko ut2 _E N CLKout2_DIV [7:0] CLKout2_DLY [3:0] 0 0 1 0 0 CLKout3 _MUX [1:0] CL Ko ut3 _E N CLKout3_DIV [7:0] CLKout3_DLY [3:0] 0 0 1 1 0 CLKout4 _MUX [1:0] CL Ko ut4 _E N CLKout4_DIV [7:0] CLKout4_DLY [3:0] 0 1 0 0 CL Ko ut5 _E N CLKout5_DIV [7:0] CLKout5_DLY [3:0] 0 1 0 1 R3 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout0_DIV [7:0] CLKout0_DLY [3:0] 0 0 0 0 R5 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout5 _MUX [1:0] R6 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout6 _MUX [1:0] CL Ko ut6 _E N CLKout6_DIV [7:0] CLKout6_DLY [3:0] 0 1 1 0 R7 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout7 _MUX [1:0] CL Ko ut7 _E N CLKout7_DIV [7:0] CLKout7_DLY [3:0] 0 1 1 1 R9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Vb o ost 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 1 CL Kin _S EL EC T 0 EN _C LK out _G lob al 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 R1 4 0 PO W ER DO W N 0 REGISTER R0 to R7 Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 7. Table 2. Default Register Settings after Power-on-Reset Bit Name RESET Default Bit Value 0 Bit State No reset, normal operation Bit Description Reset to power on defaults Register Bit Location R0 31 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 11 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 2. Default Register Settings after Power-on-Reset (continued) Default Bit Value Bit Name Bit State Bit Description CLKoutX_MUX 0 Bypassed CLKoutX mux mode CLKoutX_EN 0 Disabled CLKoutX enable CLKoutX_DIV 1 Divide by 2 CLKoutX clock divide CLKoutX_DLY 0 0 ps CLKoutX clock delay CLKin_SELECT 0 CLKin1 Select CLKin0 or CLKin1 EN_CLKout_Global 1 Normal - CLKouts normal Global clock output enable POWERDOWN 0 Normal - Device active Device power down Register Bit Location 18:17 R0 to R7 16 15:8 7:4 29 R14 27 26 Reset Bit -- R0 only This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power-on-reset condition and therefore automatically clears this bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and RESET = 0. CLKoutX_MUX[1:0] -- Clock Output Multiplexers These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes changes the blocks in the signal path and therefore incurs a delay relative to the Bypassed mode. The different MUX modes and associated delays are listed below. CLKoutX_MUX[1:0] Mode Added Delay Relative to Bypassed Mode 0 Bypassed (default) 0 ps 1 Divided 100 ps 2 Delayed 400 ps (In addition to the programmed delay) 3 Divided and Delayed 500 ps (In addition to the programmed delay) CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See Section 2.3.2) bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned (See Section 1.5). By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred. The actual Clock Output Divide value is twice the binary value programmed as listed in the table below. CLKoutX_DIV[7:0] 12 Clock Output Divider value 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2 (default) 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 . . . . . . . . ... 1 1 1 1 1 1 1 1 510 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 CLKoutX_DLY[3:0] -- Clock Output Delays These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX (See Section 2.3.2) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is incurred in addition to the delay shown in the table below. CLKoutX_DLY[3:0] Delay (ps) 0 0 (default) 1 150 2 300 3 450 4 600 5 750 6 900 7 1050 8 1200 9 1350 10 1500 11 1650 12 1800 13 1950 14 2100 15 2250 CLKoutX_EN bit -- Clock Output Enables These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. CLKoutX_EN bit Conditions CLKoutX State 0 EN_CLKout_Global bit = 1 GOE pin = High / No Connect 1 Disabled (default) 1 Enabled REGISTER R9 R9 only needs to be programmed if Vboost is set to 1. Program all other bits in R9 as indicated in register map (See Section 2.2) Vboost - Voltage Boost Bit Enabling this bit sets all clock outputs in voltage boost mode which increases the voltage at these outputs. This can improve the noise floor performance of the output, but also increases current consumption, and can cause the outputs to be too high to meet the LVPECL/LVDS specifications. Vboost bit fCLKoutX < 1300 MHz 1300 MHz ≤ fCLKoutX < 1500 MHz 1500 MHz ≤ fCLKoutX ≤ 1600 MHz 0 Recommended to hit voltage level specifications for LVPECL/LVDS Insufficient voltage level for LVDS/LVPECL specifications, but saves current 1 Voltage May overdrive LVPECL/LVDS specifications, but noise floor is about 2-4 dB better and current consumption is increased Voltage is sufficient for LVDS/LEVPECL specifications. Current consumption is increased, but noise floor is about the same. Insufficient voltage for LVDS/LVPECL specifications, but still higher than when Vboost=0. Increased current consumption. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 13 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com REGISTER R14 The LMK01000 family requires register R14 to be programmed as shown in the register map (See Section 2.2). POWERDOWN Bit -- Device Power Down This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of the state of any of the other bits or pins. POWERDOWN bit Mode 0 Normal Operation (default) 1 Entire Device Powered Down EN_CLKout_Global Bit -- Global Clock Output Enable This bit overrides the individual CLKoutX_EN bits. When thisbit is set to 0, all clock outputs are disabled, regardless of thestate of any of the other bits or pins. EN_CLKout_Global bit Clock Outputs 0 All Off 1 Normal Operation (default) CLKin_SELECT Bit -- Device CLKin Select This bit determines which CLKin pin is used. CLKin bit Mode 0 CLKin1 (default) 1 CLKin0 Application Information SYSTEM LEVEL DIAGRAM C2_LF R2_LF 100 pF CLKin1* ... CLKout7 CLKout7* VregDIG Vtune CPout VregPLL2 VregPLL1 To Other Devices CLKout0 CLKout0* C1_LF 10 nF 470 nF 470 nF 0.22 : 10 nF VregBUF VrefVCO VregVCO 3.3 : 0.22 : 10 nF 4.7 PF The following shows a typical application for a LMK01000 family device. In this setup the clock may be divided, skewed, and redistributed. 100 pF Fout CLKin1 CLKuWire CLK LMK010X0 3.0 V 100 nF LEuWire DATA CLK LE ... ... Vcc13 Vcc14 GOE SYNC* CE Bias LEuWire Test DATAuWire LE Vcc1 Vcc2 DATA VccDIG Test VccPLL VccBUF VccVCO OSCin* 100 nF 100 nF OSCin LMX2531 3.3 V Microcontroller Figure 2. Typical Application 14 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS (Vcc = 3.3 V, TA = 25° C) Current Consumption at 3.3 V (mA) Power Dissipated in device (mW) Power Dissipated in LVPECL emitter resistors (mW) 19 62.7 - Low clock buffer The low clock buffer is enabled anytime one of CLKout0 through (internal) CLKout3 are enabled 9 29.7 - High clock buffer (internal) 9 29.7 - Block Condition Core Current All outputs disabled. Includes input buffer currents. The high clock buffer is enabled anytime one of the CLKout4 through CLKout7 are enabled LVDS output, Bypassed mode Output buffers 17.8 58.7 - LVPECL output, Bypassed mode (includes 120 Ω emitter resistors) 40 72 60 LVPECL output, disabled mode (includes 120 Ω emitter resistors) 17.4 38.3 19.1 0 0 - LVPECL Output 0.5 1.65 - LVDS Output 1.5 5.0 LVPECL output, disabled mode. No emitter resistors placed; open outputs Vboost Additional current per channel due to setting Vboost from 0 to 1. Divide circuitry per output Divide enabled, divide = 2 5.3 17.5 - Divide enabled, divide > 2 8.5 28.0 - Delay circuitry per output Delay enabled, delay < 8 5.8 19.1 - Delay enabled, delay > 7 9.9 32.7 - Entire device LMK01000 CLKout0 & LMK01010 CLKout4 enabled in LMK01020 Bypassed mode 85.8 223.1 60 63.6 209.9 - 108 236.4 120 Entire device LMK01000 all outputs LMK01010 enabled with no delay and divide LMK01020 value of 2 323.8 768.5 300 212.8 702.3 - 390.4 808.3 480 From the above table, the current can be calculated in any configuration. For example, the current for the entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output in Bypassed mode can be calculated by adding up the following blocks: core current, low clock buffer, high clock buffer, one LVDS output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from the current draw is dissipated in the external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are switched in, then the additional current for these stages needs to be added as well. For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) operating at 3.3 volts for LMK01000, we calculate 3.3 V × (10 + 9 + 9 + 17.8 + 40) mA = 3.3 V × 85.8 mA = 283.1 mW. Because the LVPECL output (CLKout4) has the emitter resistors hooked up and the power dissipated by these resistors is 60 mW, the total power dissipation is 283.1 mW - 60 mW = 223.1 mW. When the LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the LVPECL Voh & Vol typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.9 V)2 / 120 Ω = 30 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW. THERMAL MANAGEMENT Power consumption of the LMK01000 family device can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 15 LMK01000 SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 3. More information on soldering LLP packages can be obtained at www.national.com. 5.0 mm, min 0.33 mm, typ 1.2 mm, typ Figure 3. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 3 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. TERMINATION AND USE OF CLOCK OUTPUTS When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: • Transmission line theory should be followed for good impedance matching to prevent reflections. • Clock drivers should be presented with the proper loads. – LVDS drivers are current drivers and require a closed current loop. – LVPECL drivers are open emitter and require a DC path to ground. • Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled. It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK01000 family, OSCin/OSCin* should be AC coupled because OSCin/ OSCin* biases the signal to the proper DC level, see Figure 2. This is only slightly different from the AC coupled cases described (See Section 3.4.2) because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same, which is the receiver (OSCin/ OSCin*) set the input to the optimum DC bias voltage (common mode voltage), not the driver. Termination for DC Coupled Differential Operation For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 4. To ensure proper LVDS operation when DC coupling it is recommend to use LVDS receivers without fail-safe or internal input bias such as National Semiconductor's DS90LV110T. The LVDS driver will provide the DC bias level for the LVDS receiver. For operation with LMK01000 family LVDS drivers it is recommend to use AC coupling with LVDS receivers that have an internal DC bias voltage. Some fail-safe circuitry will present a DC bias (common mode voltage) which will prevent the LVDS driver from working correctly. This precaution does not apply to the LVPECL drivers. 16 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 100: CLKoutX 100: Trace (Differential) LVDS Driver LVDS Receiver CLKoutX* Figure 4. Differential LVDS Operation, DC Coupling For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2 V as shown in Figure 5. Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resitors) as shown in Figure 6 for Vcc = 3.3 V. 50: Vcc - 2 V CLKoutX 100: Trace (Differential) LVPECL Driver LVPECL Receiver 50: CLKoutX* Vcc - 2 V Figure 5. Differential LVPECL Operation, DC Coupling 82: 120: Vcc CLKoutX 100: Trace (Differential) LVPECL Driver LVPECL Receiver 82: 120: CLKoutX* Vcc Figure 6. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level. When driving LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 7. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 17 LMK01000 www.ti.com 0.1 PF CLKoutX LVDS Driver 100: Trace (Differential) 50: SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 LVDS Receiver 50: Vbias CLKoutX* 0.1 PF Figure 7. Differential LVDS Operation, AC Coupling LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 11. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor connected to Vcc and a 120 Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is a valid termination as shown in Figure 8 for Vcc = 3.3 V. Note: this Thevenin circuit is different from the DC coupled example in Figure 6. 82: 120: 0.1 PF LVPECL Driver 0.1 PF LVPECL Reciever 82: 120: CLKoutX* 100: Trace (Differential) 120: CLKoutX 120: Vcc Vcc Figure 8. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal. It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the LMK01000 family LVPECL drivers, the termination should still be 50 Ω to Vcc - 2 V as shown in Figure 9. Again the Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) is a valid termination as shown in Figure 10 for Vcc = 3.3 V. 50: Vcc - 2V CLKoutX 50: Trace LVPECL Driver Vcc - 2V CLKoutX* Load 50: Figure 9. Single-Ended LVPECL Operation, DC Coupling 18 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 LMK01000 www.ti.com SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 120: Vcc CLKoutX Vcc 82: 50: Trace 120: LVPECL Driver Load 82: CLKoutX* Figure 10. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent 0.1 PF LVPECL Driver 50: Trace 50: CLKoutX 120: When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensure a 50 Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See Section 3.4.1). If the other driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 V DC) is expected for safe and proper operation. The internal 50 Ω termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 11. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. 50: CLKoutX* 120: 0.1 PF Load Figure 11. Single-Ended LVPECL Operation, AC Coupling Conversion to LVCMOS Outputs To drive an LVCMOS input with an LMK01000 family LVDS or LVPECL output, an LVPECL/LVDS to LVCMOS converter such as National Semiconductor's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For best noise performance, LVPECL provides a higher voltage swing into input of the converter. OSCin INPUT In addition to LVDS and LVPECL inputs, OSCin can also be driven with a sine wave. The OSCin input can be driven single-ended or differentially with sine waves. These configurations are shown in Figure 12 and Figure 13. 0.1 PF Clock Source 50: 50: Trace LMK Input 0.1 PF Figure 12. Single-Ended Sine Wave Input Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 19 LMK01000 www.ti.com 100: Trace (Differential) 100: SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009 0.1 PF 0.1 PF LMK Input Clock Source Figure 13. Differential Sine Wave Input Figure 14 shows the recommended power level for sine wave operation for both differential and single-ended sources over frequency. The part will operate at power levels below the recommended power level, but as power decreases the PLL noise performance will degrade. The VCO noise performance will remain constant. At the recommended power level the PLL phase noise degradation from full power operation (8 dBm) is less than 2 dB. 10 5 Minimum Recommended Power for Single-Ended Operation POWER (dBm) 0 -5 Minimum Recommended Power for Differential Operation -10 -15 -20 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) Figure 14. Recommended OSCin Power for Operation with a Sine Wave Input MORE THAN EIGHT OUTPUTS WITH AN LMK01000 FAMILY DEVICE The LMK01000 family device can be used in conjunction with a LMK02000, LMK03000, LMK04000, or even another LMK01000 device in order to produce more than 8 outputs. When doing this, attention needs to be given to how the frequencies are assigned for each output to eliminate synchronization issues. Refer to AN-1864 for more details. GLOBAL DELAY THROUGH AN LMK01000 FAMILY DEVICE The delay from CLKin to CLKout is determinsic, but can vary based on the engaged delays and divides as discussed in Section 2.3.2 for the CLKoutX_MUX bit. In addition, there can be variations based on voltage, temperature, and frequency. AN-1864 discusses this global delay in more detail. 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LMK01000 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMK01000ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01000 I LMK01000ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01000 I LMK01000ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01000 I LMK01010ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01010 I LMK01010ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01010 I LMK01010ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01010 I LMK01020ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01020 I LMK01020ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01020 I LMK01020ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01020 I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMK01000ISQ/NOPB WQFN RHS 48 LMK01000ISQE/NOPB WQFN RHS LMK01000ISQX/NOPB WQFN RHS LMK01010ISQ/NOPB WQFN LMK01010ISQE/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK01010ISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK01020ISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK01020ISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK01020ISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK01000ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK01000ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK01000ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK01010ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK01010ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK01010ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK01020ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK01020ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK01020ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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