ACTIVE-SEMI ACT8849QM614-T Advanced pmu for multi-core application processor Datasheet

ACT8849
Rev PrB, 12-Jun-14
Advanced Product Information―All Information Subject to Change
Advanced PMU for Multi-core Application Processors
FEATURES
GENERAL DESCRIPTION
INTEGRATED POWER SUPPLIES
The ACT8849 is a complete, cost effective, and
highly-efficient ActivePMUTM power management
solution optimized for the power, voltage
sequencing and control requirements of Samsung
Exynos4412 and other application processors.
(Please See Ordering Information Section and its
Appendix.)
• Four DC/DC Step-Down (Buck) Regulators
− 2 x 2.8A, 2 x 1.5A
• Five Low-Noise LDOs
− 2 x 150mA, 3 x 350mA
• Three Low-Input Voltage LDOs
The ACT8849 features four fixed-frequency,
current-mode, synchronous PWM step-down
converters that achieve peak efficiencies of up to
97%. These regulators operate with a fixed
frequency of 2.25MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. These buck regulators supply up to
2.8A of output current and can fully satisfy the
power and control requirements of the multi-core
application processor. Dynamic Voltage Scaling
(DVS) is supported either by dedicated control pins,
or through I2C interface to optimize the energy-pertask performance for the processor. This device
also include eight low-noise LDOs (up to 350mA
per LDO), one always-ON LDO and an integrated
backup battery charger to provide a complete
power system for the processor.
− 1 x 150mA, 2 x 350mA
• One Low IQ Keep-Alive LDO
• Backup Battery Charger
SYSTEM CONTROL AND INTERFACE
• Six General Purpose I/O with PWM Drivers
• I2C Serial Interface
• Interrupt Controller
SYSTEM MANAGEMENT
• Reset Interface and Sequencing Controller
− Power on Reset
− Soft / Hard Reset
− Watchdog Supervision
− Multiple Sleep Modes
The power sequence and reset controller provides
power-on reset, SW-initiated reset, and power cycle
reset for the processor. It also features the
watchdog supervisory function. Multiple sleep
modes with autonomous sleep and wake-up
sequence control are supported.
• Thermal Management Subsystem
APPLICATIONS
•
•
•
•
The thermal management and protection
subsystem allows the host processor to manage the
power dissipation of the PMU and the overall
system dynamically. The PMU provides a thermal
warning to the host processor when the
temperature reaches a certain threshold such that
the system can turn off some of the non-essential
functions, reduce the clock frequency and etc to
manage the system temperature.
Tablet PC
Mobile Internet Devices (MID)
Ebooks
Personal Navigation Devices
The ACT8849 is available in a compact, Pb-Free
and RoHS-compliant TQFN66-48 package.
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I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2014 Active-Semi, Inc.
ACT8849
Rev PrB, 12-Jun-14
TABLE OF CONTENTS
General Information ..................................................................................................................................... p. 01
Functional Block Diagram ............................................................................................................................ p. 03
Ordering Information .................................................................................................................................... p. 04
Pin Configuration ......................................................................................................................................... p. 04
Pin Descriptions ........................................................................................................................................... p. 05
Absolute Maximum Ratings ......................................................................................................................... p. 07
I2C Interface Electrical Characteristics ........................................................................................................ p. 08
Global Register Map .................................................................................................................................... p. 09
Register and Bit Descriptions ...................................................................................................................... p. 11
System Control Electrical Characteristics.................................................................................................... p. 16
Step-Down DC/DC Electrical Characteristics .............................................................................................. p. 17
Low-Noise LDO Electrical Characteristics ................................................................................................... p. 18
Low-Input Voltage LDO Electrical Characteristics ....................................................................................... p. 19
Low-Power (Always-On) LDO Electrical Characteristics ............................................................................. p. 20
Typical Performance Characteristics……………………………………………………………………………..p. 21
System Control Information ......................................................................................................................... p. 25
Interfacing with the Samsung Exynos4412 Processors ................................................................... p. 25
Control Signals ................................................................................................................................. p. 27
Push-Button Control ......................................................................................................................... p. 28
Control Sequences ........................................................................................................................... p. 28
Watch-Dog Supervision ................................................................................................................... p. 29
Software-Initiated Power Cycle ........................................................................................................ p. 29
Functional Description ................................................................................................................................. p. 30
I2C Interface ..................................................................................................................................... p. 30
Housekeeping Functions.................................................................................................................. p. 30
Thermal Protection ........................................................................................................................... p. 30
Step-Down DC/DC Regulators .................................................................................................................... p. 31
General Description.......................................................................................................................... p. 31
100% Duty Cycle Operation ............................................................................................................. p. 31
Operating Mode................................................................................................................................ p. 31
Synchronous Rectification ................................................................................................................ p. 31
Soft-Start .......................................................................................................................................... p. 31
Compensation .................................................................................................................................. p. 31
Configuration Options....................................................................................................................... p. 31
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 32
PCB Layout Considerations ............................................................................................................. p. 32
Low-Noise, Low-Dropout Linear Regulators................................................................................................ p. 33
General Description.......................................................................................................................... p. 33
Output Current Limit ......................................................................................................................... p. 33
Compensation .................................................................................................................................. p. 33
Configuration Options....................................................................................................................... p. 33
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 33
PCB Layout Considerations ............................................................................................................. p. 33
Always-On LDO (REG13) ............................................................................................................................ p. 34
General Description.......................................................................................................................... p. 34
Reverse-Current Protection ............................................................................................................. p. 34
Typical Application ........................................................................................................................... p. 34
TQFN66-48 Package Outline and Dimensions ........................................................................................... p. 35
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ACT8849
Rev PrB, 12-Jun-14
FUNCTIONAL BLOCK DIAGRAM
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ACT8849
Rev PrB, 12-Jun-14
ORDERING INFORMATIONcd
PART NUMBER
VOUT1 VOUT2 VOUT3
VOUT4 VOUT5 VOUT6
VOUT7
VOUT8
VOUT9 VOUT10 VOUT11 VOUT12 VOUT13
ACT8849QM614-T
2.8V
1.2V
2.8V
2.8V
1.8V
1.8V
PACKAGE
PINS
TEMPERATURE RANGE
TQFN66-48
48
-40°C to +85°C
2.0V
1.8V
1.8V
1.0V
1.2V
1.0V
1.8V
c: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
d: ACT8849QM614-T and ACT8847QM600-T is the association application for Samsung Exynos4412/ 4212 platforms; please see the
Appendix of ACT8847QM600-T for its specification.
PIN CONFIGURATION
OUT13
GPIO4
OUT7
OUT6
INL1
OUT5
GPIO3
GPIO2
GPIO1
OUT3
VP3
VP3
TOP VIEW
SW3
SW3
GPIO6
GP3
nIRQ
OUT10
nRSTO
OUT11
PWRHLD
INL3
nPBIN
OUT12
VP1
VSELR2
OUT1
ACT8849
nPBSTAT
GP2
SW1
GP14
EP
SW2
SW4
SW2
SCL
SDA
OUT8
OUT4
GA
OUT9
INL2
REFBP
PWREN
OUT2
VP2
VP2
VP4
Thin - QFN (TQFN66-48)
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Copyright © 2014 Active-Semi, Inc.
ACT8849
Rev PrB, 12-Jun-14
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1, 2
SW3
Switch Node for REG3.
3
GP3
Power Ground for REG3. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
4
OUT10
REG10 output. Bypass it to ground with a 2.2µF capacitor.
5
OUT11
REG11 output. Bypass it to ground with a 2.2µF capacitor.
6
INL3
7
OUT12
8
VSELR2
9
nPBSTAT
10
GP2
Power ground for REG2. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
11, 12
SW2
Switch Node for REG2.
13, 14
VP2
Power input for REG2. Bypass to GP2 with a high quality ceramic capacitor placed as
close to the IC as possible.
15
OUT2
16
PWREN
Power enable input.
17
REFBP
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This
pin is discharged to GA in shutdown.
18
INL2
Power Input for REG8, REG9.
19
OUT9
REG9 output. Bypass it to ground with a 2.2µF capacitor.
20
GA
21
OUT4
Output voltage sense for REG4.
22
OUT8
REG8 output. Bypass it to ground with a 2.2µF capacitor.
23
SDA
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
24
SCL
Clock Input for I2C Serial Interface.
25
VP4
Power input for REG4. Bypass to GP14 with a high quality ceramic capacitor placed
as close to the IC as possible.
Power input for REG10, REG11 and REG12.
REG12 output. Bypass it to ground with a 2.2µF capacitor.
Output Voltage Selection for REG2. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage.
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low
whenever the nPBIN is pushed, and is high-Z otherwise.
Output Voltage Sense for REG2.
Analog Ground.
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Copyright © 2014 Active-Semi, Inc.
ACT8849
Rev PrB, 12-Jun-14
PIN DESCRIPTIONS CONT’D
PIN
NAME
DESCRIPTION
26
SW4
Switch Node for REG4.
27
GP14
Power Ground for REG1 and REG4. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
28
SW1
Switch Node for REG1.
29
OUT1
Output Voltage Sense for REG1.
30
VP1
31
nPBIN
32
PWRHLD
33
nRSTO
34
nIRQ
35
GPIO6
General Purpose I/O #6. Configured as REG3 Output Power-OK Status.
36
GPIO5
General Purpose I/O #5. Configured as Power Enable Pin for REG1.
37
OUT13
REG13 output. Bypass it to ground with a 2.2µF capacitor.
38
OUT7
REG7 output. Bypass it to ground with a 2.2µF capacitor.
39
GPIO4
General Purpose I/O #4. Configured as Power Enable Pin for REG5.
40
OUT6
REG6 output. Bypass it to ground with a 2.2µF capacitor.
41
INL1
Power Input for REG5, REG6, REG7.
42
OUT5
REG5 output. Bypass it to ground with a 2.2µF capacitor.
43
GPIO3
General Purpose I/O #3. Configured as Power Enable Pin for REG4.
44
GPIO2
General Purpose I/O #2. Configured as VSELR1 for Voltage Selection of REG1. Drive to
logic low to select default output voltage. Drive to logic high to select secondary output
voltage.
45
GPIO1
General Purpose I/O #1. Configured as VSELR3 for Voltage Selection of REG3. Drive to
logic low to select default output voltage. Drive to logic high to select secondary output
voltage.
46
OUT3
Output Voltage Sense for REG3.
47,48
VP3
Power input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close
to the IC as possible.
EP
EP
Exposed Pad. Must be soldered to ground on PCB.
Power Input for REG1. Bypass to GP14 with a high quality ceramic capacitor placed as close
to the IC as possible.
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive
nPBIN directly to GA to assert a Manual-Reset condition.
Power hold Input. PWRHLD is internally pulled down to GA through a 900kΩ resistor.
Configured as Power Enable Pin for REG2, REG6, REG7 and REG11.
Open-Drain Interrupt Output.
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Copyright © 2014 Active-Semi, Inc.
ACT8849
Rev PrB, 12-Jun-14
ABSOLUTE MAXIMUM RATINGSc
PARAMETER
VALUE
UNIT
INL1, INL2, INL3 to GA; VP1, SW1, OUT1 to GP14; VP2, SW2, OUT2 to GP2; VP3,
SW3, OUT3 to GP3; VP4, SW4, OUT4 to GP14
-0.3 to 6
V
-0.3 to + 0.3
V
OUT5, OUT6, OUT7, OUT13 to GA
-0.3 to INL1 + 0.3
V
OUT8, OUT9, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, VSELR2, nPBIN,
nRSTO, nIRQ, nPBSTAT, PWREN, PWRHLD, REFBP, SCL, SDA to GA
-0.3 to INL2 + 0.3
V
OUT10, OUT11, OUT12 to GA
-0.3 to INL3 + 0.3
V
Junction to Ambient Thermal Resistance
21
°C/W
Operating Ambient Temperature Range
-40 to 85
°C
Operating Junction Temperature
-40 to 125
°C
Storage Temperature
-55 to 150
°C
300
°C
GP14, GP2, GP3 to GA
Lead Temperature (Soldering, 10 sec)
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
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ACT8849
Rev PrB, 12-Jun-14
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
SCL, SDA Input Low
VINL2 = 3.1V to 5.5V, TA = -40ºC to 85ºC
SCL, SDA Input High
VINL2 = 3.1V to 5.5V, TA = -40ºC to 85ºC
TYP
MAX
UNIT
0.35
V
1.55
V
SDA Leakage Current
1
µA
SCL Leakage Current
1
µA
0.35
V
SDA Output Low
IOL = 5mA
SCL Clock Period, tSCL
1.5
µs
SDA Data Setup Time, tSU
100
ns
SDA Data Hold Time, tHD
300
ns
Start Setup Time, tST
For Start Condition
100
ns
Stop Setup Time, tSP
For Stop Condition
100
ns
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
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ACT8849
Rev PrB, 12-Jun-14
GLOBAL REGISTER MAP CONT’D
BLOCK
ADDRESS
SYS
0x00
BITS
NAME
DEFAULT
SYS
0x01
REG1
0x10
0x11
REG1
0x12
0x20
REG2
0x21
0x22
REG3
0x30
0x31
REG3
0x32
0x40
0x41
0x42
0x50
REG5
0x51
0x58
REG6
0x59
BATLEV[0]
R
R
0
1
0
0
1
Reserved
Reserved
Reserved
0
0
0
0
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
1
1
0
c
0
NAME
Reserved
DEFAULTc
0
NAME
ON
c
0
NAME
Reserved
DEFAULTc
0
NAME
Reserved
c
0
NAME
ON
DEFAULTc
0
NAME
Reserved
c
0
NAME
Reserved
DEFAULTc
0
NAME
ON
c
NAME
1
Reserved
c
NAME
0
Reserved
c
NAME
0
ON
c
Reserved Reserved Reserved
Reserved VSET1[5] VSET1[4] VSET1[3]
0
1
1
0
Reserved Reserved Reserved Reserved
1
0
0
0
Reserved VSET0[5] VSET0[4] VSET0[3]
0
0
1
1
Reserved VSET1[5] VSET1[4] VSET1[3]
0
0
1
1
Reserved Reserved Reserved Reserved
1
0
0
0
Reserved VSET0[5] VSET0[4] VSET0[3]
0
1
0
1
Reserved VSET1[5] VSET1[4] VSET1[3]
0
1
0
1
Reserved Reserved Reserved Reserved
1
0
0
0
Reserved VSET0[5] VSET0[4] VSET0[3]
0
1
1
0
Reserved VSET1[5] VSET1[4] VSET1[3]
0
1
1
0
Reserved Reserved Reserved Reserved
1
0
0
VSET1[2]
VSET1[1]
VSET1[0]
1
0
0
PHASE
nFLTMSK
OK
0
0
R
VSET0[2]
VSET0[1]
VSET0[0]
0
0
0
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
PHASE
nFLTMSK
OK
0
0
R
VSET0[2]
VSET0[1]
VSET0[0]
0
0
0
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
PHASE
nFLTMSK
OK
1
0
R
VSET0[2]
VSET0[1]
VSET0[0]
1
0
0
VSET1[2]
VSET1[1]
VSET1[0]
1
0
0
PHASE
nFLTMSK
OK
0
1
0
0
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
1
1
0
0
1
0
0
NAME
ON
DIS
nFLTMSK
OK
c
Reserved Reserved Reserved Reserved
0
1
0
0
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
1
1
0
0
1
0
0
NAME
ON
DIS
nFLTMSK
OK
1
0
R
DEFAULT
REG6
BATLEV[1]
nBATSTAT VBATDAT Reserved BATLEV[3] BATLEV[2]
0
DEFAULT
REG5
D0
0
DEFAULT
REG4
D1
R
DEFAULT
REG4
D2
TSTAT
DEFAULT
REG4
D3
0
DEFAULT
REG3
D4
nTMSK
DEFAULT
REG2
D5
NAME
DEFAULT
REG2
D6
DEFAULTc
DEFAULT
REG1
c
D7
nBATLEVMSK
0
DEFAULT
c
0
Reserved Reserved Reserved Reserved
1
0
1
0
c: Default values of ACT8849QM614-T.
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Copyright © 2014 Active-Semi, Inc.
ACT8849
Rev PrB, 12-Jun-14
GLOBAL REGISTER MAP CONT’D
BLOCK
ADDRESS
REG7
0x60
BITS
NAME
0x61
REG8
0x68
0x69
REG9
0x70
0x71
REG10
0x80
0x81
0x90
0x91
0xA0
REG12
0xA1
0xB1
PB
0xC0
0xC1
0xC2
PB
0xC3
0xC5
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
1
0
0
DIS
nFLTMSK
OK
DEFAULTc
0
1
0
1
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
c
0
1
1
0
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULTc
1
1
0
1
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
c
0
1
1
0
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULTc
1
1
0
1
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
1
0
1
0
0
0
0
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
1
1
0
1
0
1
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
1
0
1
1
0
0
0
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
0
1
0
1
0
1
0
R
c
NAME
c
NAME
c
NAME
c
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
0
1
0
1
0
0
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
1
1
0
1
0
1
0
R
c
NAME
ON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULTc
1
0
0
0
0
0
0
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
c
NAME
Reserved WDSREN WDPCEN
0
0
0
INTADR[7] INTADR[6] INTADR[5] INTADR[4] INTADR[3] INTADR[2] INTADR[1] INTADR[0]
c
R
R
R
R
R
R
R
R
NAME
PBASTAT
PBDSTAT
PBDAT
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULTc
R
R
R
0
R
R
R
R
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SIPC
0
0
0
0
0
0
0
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCSTAT
SRSTAT
DEFAULTc
0
0
0
0
0
0
R
R
DEFAULT
PB
VSET[5]
Reserved
DEFAULT
PB
Reserved
1
DEFAULT
PB
Reserved
c
Reserved
DEFAULT
REG13
D0
1
DEFAULT
REG12
D1
Reserved
DEFAULT
REG11
D2
1
DEFAULT
REG11
D3
Reserved
DEFAULT
REG10
D4
0
DEFAULT
REG9
D5
ON
DEFAULT
REG8
D6
NAME
DEFAULT
REG7
D7
c
c: Default values of ACT8849QM614-T.
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ACT8849
Rev PrB, 12-Jun-14
REGISTER AND BIT DESCRIPTIONS
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Battery Voltage Level Interrupt Mask. Set this bit to 1 to unmask
the interrupt. See the Programmable Battery Voltage Monitor
section for more information
SYS
0x00
[7]
nBATLEVMSK
R/W
SYS
0x00
[6]
nBATSTAT
R
Battery Voltage Status. Value is 1 when BATLEV interrupt is
generated, value is 0 otherwise.
SYS
0x00
[5]
VBATDAT
R
Battery Voltage Monitor real time status. Value is 1 when VBAT <
BATLEV, value is 0 otherwise.
SYS
0x00
[4]
-
R/W
Reserved.
SYS
0x00
[3:0]
BATLEV
R/W
Battery Voltage Detect Threshold. Defines the BATLEV voltage
threshold. See the Programmable Battery Voltage Monitor
section for more information.
SYS
0x01
[7]
nTMSK
R/W
Thermal Interrupt Mask. Set this bit to 1 to unmask the interrupt.
SYS
0x01
[6]
TSTAT
R
Thermal Interrupt Status. Value is 1 when a thermal interrupt is
generated, value is 0 otherwise.
SYS
0x01
[5:0]
-
R/W
Reserved.
REG1
0x10
[7:6]
-
R
Reserved.
REG1
0x10
[5:0]
VSET0
R/W
Primary Output Voltage Selection. See the Output Voltage
Programming section for more information
REG1
0x12
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
0x12
[6:3]
-
R
REG1
0x12
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG1
0x12
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG1
0x12
[0]
OK
R
REG2
0x20
[7:6]
-
R
Reserved.
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information
REG2
0x20
[5:0]
VSET0
R/W
REG2
0x21
[7:6]
-
R
REG2
0x21
[5:0]
VSET1
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG2
0x22
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG2
0x22
[6:3]
-
R
REG2
0x22
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG2
0x22
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG2
0x22
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3
0x30
[7:6]
-
R
Reserved.
REG3
0x30
[5:0]
VSET0
R/W
Innovative PowerTM
Reserved.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information
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ACT8849
Rev PrB, 12-Jun-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
REG3
0x31
[7:6]
-
R
REG3
0x31
[5:0]
VSET1
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG3
0x32
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG3
0x32
[6:3]
-
R
REG3
0x32
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG3
0x32
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG3
0x32
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4
0x40
[7:6]
-
R
Reserved.
REG4
0x40
[5:0]
VSET0
R/W
REG4
0x41
[7:6]
-
R
REG4
0x41
[5:0]
VSET1
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG4
0x42
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG4
0x42
[6:3]
-
R
Reserved.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information
Reserved.
Reserved.
REG4
0x42
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG4
0x42
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG4
0x42
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG5
0x50
[7:6]
-
R
Reserved.
REG5
0x50
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG5
0x51
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG5
0x51
[6:3]
-
R
Reserved.
REG5
0x51
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG5
0x51
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG5
0x51
[0]
OK
R
REG6
0x58
[7:6]
-
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Reserved.
REG6
0x58
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG6
0x59
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
Innovative PowerTM
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
REG6
0x59
[6:3]
NAME
ACCESS
-
R
DESCRIPTION
Reserved.
REG6
0x59
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG6
0x59
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG6
0x59
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
0x60
[7:6]
-
R
Reserved.
REG7
0x60
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG7
0x61
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG7
0x61
[6:3]
-
R
Reserved.
REG7
0x61
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG7
0x61
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG7
0x61
[0]
OK
R
REG8
0x68
[7:6]
-
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Reserved.
REG8
0x68
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG8
0x69
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG8
0x69
[6:3]
-
R
Reserved.
REG8
0x69
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG8
0x69
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG8
0x69
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG9
0x70
[7:6]
-
R
Reserved.
REG9
0x70
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG9
0x71
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG9
0x71
[6:3]
-
R
Reserved.
REG9
0x71
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG9
0x71
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG9
0x71
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG10
0x80
[7:6]
-
R
Reserved.
Innovative Power
TM
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
REG10
0x80
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG10
0x81
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG10
0x81
[6:3]
-
R
Reserved.
REG10
0x81
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG10
0x81
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG10
0x81
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG11
0x90
[7:6]
-
R
Reserved.
REG11
0x90
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG11
0x91
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG11
0x91
[6:3]
-
R
Reserved.
REG11
0x91
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG11
0x91
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG11
0x91
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG12
0xA0
[7:6]
-
R
Reserved.
REG12
0xA0
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG12
0xA1
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG12
0xA1
[6:3]
-
R
Reserved.
REG12
0xA1
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG12
0xA1
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG12
0xA1
[0]
OK
R
REG13
0xB1
[7]
ON
R/W
REG13
0xB1
[6:0]
-
R
PB
0xC0
7
nPBAMSK
R/W
nPBIN Assertion Interrupt Control. Set this bit to 1 to generate
an interrupt when nPBIN is asserted.
PB
0xC0
6
nPBDMSK
R/W
nPBIN De-assertion Interrupt Control. Set this bit to 1 to
generate an interrupt when nPBIN is de-asserted.
PB
0xC0
[5:2]
-
R
PB
0xC0
1
WDSREN
Innovative PowerTM
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
Reserved.
Reserved.
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
PB
PB
0xC0
0xC0
[5:2]
1
NAME
ACCESS
-
R
WDSREN
DESCRIPTION
Reserved.
R/W
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
Watchdog Power-Cycle Enable. Set this bit to 1 to enable
watchdog function. When watchdog timer expires, the PMU
commence a power cycle. This bit is automatically reset to 0
when entering sleep mode.
PB
0xC0
0
WDPCEN
R/W
PB
0xC1
[7:0]
INTADR
R
Interrupt Address. It holds the address of the block that triggers
the interrupt. This byte defaults to 0xFF and is automatically set
to 0xFF after being read. Bit 7 is the MSB while Bit 0 is the LSB.
PB
0xC2
7
PBASTAT
R
nPBIN Assertion Interrupt Status. The value of this bit is 1 if the
nPBIN Assertion Interrupt is triggered.
PB
0xC2
6
PBDSTAT
R
nPBIN De-assertion Interrupt Status. The value of this bit is 1 if
the nPBIN De-assertion Interrupt is triggered.
PB
0xC2
5
PBASTAT
R
nPBIN Status bit. This bit contains the real-time status of the
nPBIN pin. The value of this bit is 1 if nPBIN is asserted, and is 0
if nPBIN is de-asserted.
PB
0xC2
[4:0]
-
R
Reserved.
PB
0xC3
[7:1]
-
R
Reserved.
PB
0xC3
0
SIPC
R/W
PB
0xC5
[7:2]
-
R
PB
0xC5
1
PCSTAT
R/W
Power-cycle Flag. The value of this bit is 1 after a power cycle.
This bit is automatically cleared to 0 after read.
PB
0xC5
0
SRSTAT
R/W
Soft-reset Flag. The value of this bit is 1 after a soft-reset. This
bit is automatically cleared to 0 after read.
Innovative PowerTM
Software Initiated Power Cycle. When this bit is set, the PMU
commences a power cycle after 8ms delay.
Reserved.
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Input Voltage Range
MIN
TYP
3.0
MAX
UNIT
5.5
V
3.0
V
UVLO Threshold Voltage
VINL2 Rising
UVLO Hysteresis
VINL2 Hysteresis
200
Operating Supply Current
All Regulators Enabled but no load
0.6
1.2
mA
Shutdown Supply Current
All Regulators Disabled except REG13
10
20
µA
2.25
2.5
MHz
2.6
Oscillator Frequency
2.0
Logic High Input Voltage
1.4
2.8
V
Logic Low Input Voltage
Leakage Current
V[nIRQ] = 4.2V
Low Level Output Voltage
nIRQ, ISINK = 5mA
Thermal Shutdown Temperature
Temperature rising
Thermal Shutdown Hysteresis
Innovative PowerTM
mV
0.4
V
1
µA
0.3
V
160
°C
20
°C
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = VVP4 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Operating Voltage Range
MIN
TYP
2.7
UVLO Threshold
Input Voltage Rising
UVLO Hysteresis
Input Voltage Falling
100
Standby Supply Current
VOUT = 103%, Regulator Enabled
72
Shutdown Current
VVP = 5.5V, Regulator Disabled
0
Output Voltage Accuracy
2.5
2.6
VOUT ≥ 1.0V, IOUT = 10mA
-1%
VOUT < 1.0V, IOUT = 10mA
-10
VNOM
c
MAX
UNIT
5.5
V
2.7
V
mV
100
µA
2
µA
1%
V
10
mV
Line Regulation
VVP = Max (VNOM1 +1V, 3.2V) to 5.5V
0.15
%/V
Load Regulation REG1/4
IOUT = 10mA to IMAX2
1.70
%/A
Load Regulation REG2/3
IOUT = 10mA to IMAX
1.00
%/A
Power Good Threshold
VOUT Rising
93
%VNOM
Power Good Hysteresis
VOUT Falling
2
%VNOM
Switching Frequency
2
VOUT ≥ 20% of VNOM
2
VOUT = 0V
2.25
2.5
MHz
550
kHz
Soft-Start Period
400
µs
Minimum On-Time
75
ns
REG1 AND REG4
Maximum Output Current
1.5
Current Limit
1.8
A
2.2
2.7
A
PMOS On-Resistance
ISW = -100mA
0.11
Ω
NMOS On-Resistance
ISW = 100mA
0.08
Ω
SW Leakage Current
VVP = 5.5V, VSW = 0 or 5.5V
0
2
µA
Input Capacitor
4.7
µF
Output Capacitor
33
µF
Power Inductor
1.0
2.2
3.3
µH
REG2 AND REG3
Maximum Output Current
2.8
Current Limit
3.5
A
4.2
A
PMOS On-Resistance
ISW = -100mA
0.07
Ω
NMOS On-Resistance
ISW = 100mA
0.08
Ω
SW Leakage Current
VVP = 5.5V, VSW = 0 or 5.5V
0
2
µA
Input Capacitor
10
µF
Output Capacitor
44
µF
Power Inductor
0.5
1
2.2
µH
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
Innovative PowerTM
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL1 = VINL2 = 3.6V, COUT5 = COUT6 = COUT7 = COUT8 = COUT9 = 2.2µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
MIN
TYP
2.5
VOUT ≥ 1.0V, IOUT = 10mA
-1
VOUT < 1.0V, IOUT = 10mA
-10
VNOM
c
MAX
UNIT
5.5
V
1
%
10
mV
Line Regulation
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
0.5
mV
Load Regulation
IOUT = 1mA to IMAX
0.1
V/A
f = 1kHz, IOUT = 20mA, VOUT = 1.2V
75
f = 10kHz, IOUT = 20mA, VOUT = 1.2V
65
Regulator Enabled
25
Regulator Disabled
0
Power Supply Rejection Ratio
Supply Current per Output
2
dB
2
µA
Soft-Start Period
VOUT = 3.0V
140
µs
Power Good Threshold
VOUT Rising
92
%
Power Good Hysteresis
VOUT Falling
3.5
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
30
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
LDO rated at 150mA (REG5 & REG6)
Dropout Voltagee
IOUT = 80mA, VOUT > 3.1V
Maximum Output Current
Current Limitf
VOUT = 95% of regulation voltage
140
280
mV
150
mA
180
mA
Recommend Output Capacitor
2.2
µF
LDO rated at 350mA (REG7, REG8 & REG9)
Dropout Voltagee
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
f
VOUT = 95% of regulation voltage
140
280
mV
350
mA
400
mA
Recommend Output Capacitor
2.2
µF
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
f: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 50% (typ.)
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ACT8849
Rev PrB, 12-Jun-14
LOW-INPUT VOLTAGE LDO ELECTRICAL CHARACTERISTICS
(VINL3 = 3.6V, COUT10 = COUT11 = COUT12 = 2.2µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
MIN
TYP
1.7
VOUT ≥ 1.0V, IOUT = 10mA
-1
VOUT < 1.0V, IOUT = 10mA
-10
VNOM
c
MAX
UNIT
5.5
V
1
%
10
mV
Line Regulation
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
0.5
mV
Load Regulation
IOUT = 1mA to IMAX2
0.1
V/A
Power Supply Rejection Ratio
Supply Current per Output
f = 1kHz, IOUT = 20mA, VOUT = 1.2V
50
f = 10kHz, IOUT = 20mA, VOUT = 1.2V
40
Regulator Enabled
22
Regulator Disabled
0
dB
2
µA
Soft-Start Period
VOUT = 3.0V
100
µs
Power Good Threshold
VOUT Rising
92
%
Power Good Hysteresis
VOUT Falling
3.5
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
30
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
IOUT = 80mA, VOUT > 3.1V
100
LDO rated at 150mA (REG10)
Dropout Voltagee
Maximum Output Current
Current Limitf
VOUT = 95% of regulation voltage
200
mV
150
mA
180
mA
Recommend Output Capacitor
2.2
µF
LDO rated at 350mA (REG11 & REG12)
Dropout Voltagee
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
f
VOUT = 95% of regulation voltage
100
200
mV
350
mA
400
mA
Recommend Output Capacitor
2.2
µF
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
f: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 50% (typ)
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ACT8849
Rev PrB, 12-Jun-14
LOW-POWER(ALWAYS-ON) LDO ELECTRICAL CHARACTERISTICS
(VINL1 = 3.6V, COUT13 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
REG13 — VNOM = 1.8V
Operating Voltage Range
2.5
Output Voltage Accuracy
Line Regulation
-3
VINL1 = Max (VOUT + 0.2V, 2.5V) to 5.5V
VNOM
13
Supply Current from VINL1
5
Maximum Output current
Recommend Output Capacitor
c
3
%
mV
µA
50
mA
0.47
µF
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
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ACT8849
Rev PrB, 12-Jun-14
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
2.340
Frequency (MHz)
VREF (V)
1.200
ACT8849-002
2.360
ACT8849-001
1.204
1.196
1.192
1.188
2.320
2.300
2.280
2.260
2.240
2.220
2.200
1.184
-40
-20
0
20
40
60
80
100
120
2.180
-40
140
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
Startup of OUT13
Startup of OUT3/5/2/6/7/11
ACT8849-004
ACT8849-003
CH1
CH2
CH1
CH3
CH2
CH4
CH5
CH6
CH1: VIN, 2V/div
CH2: VOUT13, 1V/div
TIME: 1ms/div
CH1: VOUT3, 2V/div
CH2: VOUT5, 2V/div
CH3: VOUT2, 1V/div
CH4: VOUT6, 2V/div
CH5: VOUT7, 2V/div
CH6: VOUT11, 1V/div
TIME: 400µs/div
Sleep/Wakeup of OUT6/7/11/10/12
Startup of OUT3/10/12/8/9
ACT8849-006
ACT8849-005
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH5
CH6
CH5
CH1: VPWREN, 2V/div
CH2: VOUT6, 2V/div
CH3: VOUT7, 2V/div
CH4: VOUT11, 1V/div
CH5: VOUT10, 1V/div
CH6: VOUT12, 1V/div
TIME: 1ms/div
CH1: VOUT3, 2V/div
CH2: VOUT10, 1V/div
CH3: VOUT12, 1V/div
CH4: VOUT8, 2V/div
CH5: VOUT9, 1V/div
TIME: 400µs/div
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ACT8849
Rev PrB, 12-Jun-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Sleep/Wakeup of OUT8/9
nPBIN and nPBSTAT
ACT8849-008
ACT8849-007
CH1
CH1
CH2
CH2
CH3
CH4
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
TIME: 10ms/div
CH1: VPWREN, 2V/div
CH2: VOUT8, 2V/div
CH3: VOUT9, 2V/div
TIME: 1ms/div
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG1 Efficiency vs. Output Current
VIN = 3.6V
VIN = 5.0V
60
VOUT = 1.2V
VIN = 5.0V
VIN = 4.0V
40
20
0
VIN = 4.0V
60
40
20
0
0
1
10
1000
100
10000
0
1
Output Current (mA)
10000
VOUT = 1.1V
VIN = 3.6V
80
Efficiency (%)
VIN = 5.0V
100
ACT8849-012
VIN = 3.6V
80
Efficiency (%)
1000
100
REG4 Efficiency vs. Output Current
ACT8849-011
VOUT = 1.1V
10
Output Current (mA)
REG3 Efficiency vs. Output Current
100
VIN = 3.6V
80
Efficiency (%)
Efficiency (%)
80
100
ACT8849-010
VOUT = 1.2V
REG2 Efficiency vs. Output Current
ACT8849-009
100
60
VIN = 4.0V
40
20
VIN = 5.0V
60
VIN = 4.0V
40
20
0
0
0
1
10
100
1000
10000
0
Output Current (mA)
1
10
100
1000
10000
Output Current (mA)
REG5/6 Dropout Voltage vs. IOUT
ACT8849-013
400
Dropout Voltage (mV)
350
300
250
200
150
100
50
0
0
50
100
150
200
250
Output Current (mA)
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ACT8849
Rev PrB, 12-Jun-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG7/8/9 Dropout Voltage vs. IOUT
REG10 Dropout Voltage vs. IOUT
ACT8849-014
Dropout Voltage (mV)
Dropout Voltage (mV)
300
250
200
100
0
ACT8849-015
400
200
150
100
50
0
50
0
100
150
200
250
300
350
0
400
100
150
200
Output Current (mA)
Output Current (mA)
REG12 Dropout Voltage vs. IOUT
REG11 Dropout Voltage vs. IOUT
Dropout Voltage (mV)
200
150
100
50
ACT8849-017
250
ACT8849-016
250
Dropout Voltage (mV)
50
200
150
100
50
0
0
0
100
200
300
0
400
200
300
400
Output Current (mA)
Output Current (mA)
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ACT8849
Rev PrB, 12-Jun-14
SYSTEM CONTROL INFORMATION
Interfacing with the Samsung Exynos4412 processors
The ACT8849 is optimized for the Samsung
Exynos4412 and other application processors,
supporting both the power domains as well as the
signal interface. The following paragraphs describe
how to design ACT8849 with the Exynos4412
processors.
While the ACT8849 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8849 pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
the ACT8849 pin names and the Exynos4412
processors pin names are provided. When this is
done, the Exynos4412 pin names are located after
the ACT8849 pin names, and are italicized and
located inside parentheses. For example, PWREN
(XPWRRGTON) refers to the logic signal applied to
the ACT8849's PWREN input, identifying that it is
driven from the Exynos4412's XPWRRGTON
output.
Table 1:
ACT8847QM600 + ACT8849QM614 and Exynos4412 Signal Interface
ACT8847
DIRECTION
EXYNOS4412
PWREN
XPWRRGTON
SCL
Xi2cSCL[0]
SDA
Xi2cSDA[0]
VSELR2
DVS_GPIO1
GPIO1/VSELR3
DVS_GPIO2
GPIO2/VSELR4
DVS_GPIO3
nRSTO
XnRESET
nIRQ
XEINT0
nPBSTAT
XEINT1
PWRHLD
XPSHOLD
ACT8849
DIRECTION
EXYNOS4412
PWREN
XPWRRGTON
SCL
Xi2cSCL[0]
SDA
Xi2cSDA[0]
GPIO3/EN4
XMMC0CDN
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ACT8849
Rev PrB, 12-Jun-14
ACT8847QM600 + ACT8849QM614 and Samsung Exynos4412 Power Domains
ACT8847
REGULATOR
POWER DOMAIN
DEFAULT VOLTPOWER UP
MAX CURRENT
AGE
ORDER
ON/OFF @
SLEEP
TYPE
DC/DC Step Down
REG1(OUT1.1)
VDD_MIF
1.0V
1500mA
3
OFF
REG2(OUT1.2)
VDD_ARM
1.3V
2800mA
3
OFF
DC/DC Step Down
REG3(OUT1.3)
VDD_G3D
1.0V
2800mA
3
OFF
DC/DC Step Down
REG4(OUT1.4)
VDD_INT
VDD18_ABB0
VDD18_ABB1
VDD18_ABB2
VDD_CAM _3V3
VDD1_E
VDDQ_AUD
VDDQ_CAM
VDDQ_SBUS
VDDQ_M0
VDDQ_MMC3
VDDQ_GPS
VDDQ_ISP
VDDQ_EXT
VDDQ_MIPIHSI
VDDQ_CKO
VDDQ_LCD
VDDQ_SYS00
VDDQ_SYS02
VDDQ_SYS33
VDD33_UOTG
1.125V
1500mA
3
OFF
DC/DC Step Down
1.8V
150mA
2
OFF
Low-Noise LDO
3.0V
150mA
2
OFF
Low-Noise LDO
1.8V
350mA
4
OFF
Low-Noise LDO
3.3V
350mA
8
OFF
Low-Noise LDO
3.3V
350mA
8
ON
Low-Noise LDO
1.1V
150mA
3
OFF
Low Input-Voltage LDO
REG11(OUT1.11)
VDD_LCD
VDD10_MPLL
VDD10_VPLL
VDD10_APLL
VDD10_EPLL
VDD_CAM_1V8
1.8V
350mA
3
OFF
Low Input-Voltage LDO
REG12(OUT1.12)
VDD_ALIVE
1.0V
350mA
1
ON
Low Input-Voltage LDO
REG13(OUT1.13)
VDD_RTC
1.8V
50mA
Always-ON
REG5(OUT1.5)
REG6(OUT1.6)
REG7(OUT1.7)
REG8(OUT1.8)
REG9(OUT1.9)
REG10(OUT1.10)
ACT8849
REGULATOR
POWER DOMAIN
DEFAULT VOLTPOWER UP
MAX CURRENT
AGE
ORDER
ON
Always-ON LDO
ON/OFF @
SLEEP
TYPE
REG1(OUT2.1)
VDD_OFF
2.8V
1500mA
EN1
EN1
DC/DC Step Down
REG2(OUT2.2)
VDD_MEM
(VDDQ_E1
VDDQ_E2
VDDCA_E1
VDDCA_E2
VDD2_E
VDDQ_CKEM1_2)
1.2V
2800mA
5
ON
DC/DC Step Down
REG3(OUT2.3)
VDD_INL3
2.0V
2800mA
0
ON
DC/DC Step Down
REG4(OUT2.4)
VDDF_EMMC
2.8V
1500mA
EN4
OFF
DC/DC Step Down
REG5(OUT2.5)
VDDQ_PRE
1.8V
150mA
4
OFF
Low-Noise LDO
1.8V
150mA
5
OFF
Low-Noise LDO
2.8V
350mA
5
OFF
Low-Noise LDO
1.8V
350mA
7
OFF
Low-Noise LDO
1.8V
350mA
7
OFF
Low-Noise LDO
1.0V
150mA
6
OFF
Low Input-Voltage LDO
1.2V
350mA
5
OFF
Low Input-Voltage LDO
1.0V
350mA
6
OFF
Low Input-Voltage LDO
1.8V
50mA
No Use
No Use
Always-ON LDO
REG6(OUT2.6)
REG7(OUT2.7)
REG8(OUT2.8)
REG9(OUT2.9)
REG10(OUT2.10)
REG11(OUT2.11)
REG12(OUT2.12)
REG13(OUT2.13)
VDDQ_C2C
VDDQ_C2C_W
VDDQ_MMC01
VDDQ_MMC2
VDD18_MIPI
VDD18_MIPI2L
VDD18_HDMI_OSC
VDD18_TS
VDD18_ADC
VDD18_HSIC
VDD10_HSIC
VDD10_UOTG
VDDQ_M1
VDDQ_M2
VDD10_HDMI
VDD10_HDMI_PLL
VDD10_MIPI
VDD10_MIPI_PLL
VDD10_MIPI2L
No Use
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ACT8849
Rev PrB, 12-Jun-14
Control Signals
nPBSTAT Output
Enable Inputs
The ACT8849 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input.
nPBIN Multi-Function Input
The ACT8849 features the nPBIN multi-function
pin, which combines system enable/disable control
with a hardware reset function. Select either of the
two pin functions by asserting this pin, either
through a direct connection to GA, or through a
50kΩ resistor to GA, as shown in Figure 2.
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kΩ).
An internal timer detects the duration of the MR
event:
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage through
a 10kΩ or greater resistor.
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kΩ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8849's functions support interruptgeneration as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
If the MR is asserted for more than 4s, ACT8849
commences a power cycle routine in which case all
regulators are turned off and then turned back on. A
status bit, PCSTAT[ ], is set after the power cycle.
The PCSTAT[ ] bit is automatically cleared to 0 after
read.
Figure 2:
nPBIN Input
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ACT8849
Rev PrB, 12-Jun-14
Push-Button Control
The ACT8849 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8849 automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWREN or PWRHLD.
Control Sequences
The ACT8849 features a variety of control
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of the
Samsung Exynos4412 processors.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever the
nPBIN is asserted low via 50KΩ resistance. The
power control diagram is shown in Figure 3. During
the boot sequence, the microprocessor must assert
PWRHLD
(XPSHOLD),
and
PWREN
(XPWRRGTON), to ensure that the system remains
powered after nPBIN is released. Once the powerup routine is completed, the system remains
enabled after the push-button is released as long as
PWRHLD is asserted high. If the processor does
not assert PWRHLD before the user releases the
push-button, the boot-up sequence is terminated
and all regulators are disabled. This provides
protection against "false-enable", when the pushbutton is accidentally depressed, and also ensures
that the system remains enabled only if the
processor successfully completes the boot-up
sequence.
up routine has been completed, SLEEP mode may
be initiated through a variety of software-controlled
mechanisms.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts the nPBIN input,
which asserts the nPBSTAT output, which
interrupts the processor. In response to this
interrupt the processor should de-assert
PWREN(XPWRRGTON),
disabling
REG6/7/8/9/10/11/12. PWRHLD should remain
asserted during SLEEP mode so that REG1/6/7/12
remain enabled.
The ACT8849 wakes up from SLEEP mode when
either the push-button and/or PWREN
(XPWRRGTON)
is asserted. In either case,
REG2/3/4/5/8/9/10/11 are enable which allow the
system to resume normal operation.
Watch-Dog Supervision
The ACT8849 features a watchdog supervisory
function. An internal watchdog timer of 4s is
unmasked by setting either WDSREN[ ] or
WDPCEN [ ] bit to one. Once enabled, the
watchdog timer is reset whenever there is I2C
activity for the PMU. In the case where the system
software stops responding and that there is no I2C
transactions for 4s, the watchdog timer expires. As
a result, the PMU either perform a soft-reset or
power cycle, depending on whether WDSREN [ ] or
WDPCEN [ ] is set.
Software-Initiated Power Cycle
ACT8849 supports software-initiated power cycle.
Once the SIPC[ ] bit is set, the PMU waits for 8ms
and then initiate a power cycle to restart the entire
system.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before the processor finally de-asserts PWRHLD.
SLEEP Mode Sequence
The ACT8849 supports Exynos4412 processors’
SLEEP mode operation. Once a successful powerInnovative PowerTM
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ACT8849
Rev PrB, 12-Jun-14
Figure 3:
Power Control Sequence
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ACT8849
Rev PrB, 12-Jun-14
FUNCTIONAL DESCRIPTION
I2C Interface
The ACT8849 features an I2C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8849, and I2C read-byte commands are used to
read the ACT8849’s internal registers. The ACT8849
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a readoperation or a write-operation, [1010101x].
Table 2:
BATLEV Falling Threshold
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
Housekeeping Functions
Programmable battery Voltage Monitor
The ACT8849 features a programmable batteryvoltage monitor, which monitors the voltage at INL2
(which should be connected directly to the battery)
and compares it to a programmable threshold
voltage. The VBATMON comparator is designed to
be immune to noise resulting from switching, load
transients, etc. The BATMON comparator is disable
by default; to enable it, set the BATLEV[3:0] register
to one of the value in Table 2. Note that there is a
200mV hysteresis between the rising and falling
threshold for the comparator. The VBATDAT [-] bit
reflects the output of the BATMON comparator. The
value of VBATDAT[ ] is 1 when VINL2 < BATLEV;
value is 0 otherwise.
The VBATMON comparator can generate an
interrupt when VINL2 is lower than BATLEV[ ] voltage.
The interrupt is masked by default by can be
unmasked by setting VBATMSK[ ] = 1.
Innovative PowerTM
BATLEV[3:0]
BATLEV Falling
Threshold
0000
2.5
0001
2.6
0010
2.7
0011
2.8
0100
2.9
0101
3.0
0110
3.1
0111
3.2
1000
3.3
1001
3.4
1010
3.5
1011
3.6
1100
3.7
1101
3.8
1110
3.9
1111
4.0
Thermal Protection
The ACT8849 integrates thermal shutdown
protection circuitry to prevent damage resulting
from excessive thermal stress, as may be
encountered under fault conditions.
Thermal Interrupt
If the thermal interrupt is unmasked (by setting
nTMSK[ ] to 1), ACT8849 can generate an interrupt
when the die temperature reaches 120°C (typ).
Thermal Protection
If the ACT8849 die temperature exceeds 160°C, the
thermal protection circuitry disables all regulators
and prevents the regulators from being enabled until
the IC temperature drops by 20°C (typ).
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ACT8849
Rev PrB, 12-Jun-14
STEP-DOWN DC/DC REGULATORS
General Description
REG1, REG2, REG3, and REG4 are fixed-frequency,
current-mode, synchronous PWM step-down
converters that achieves peak efficiencies of up to
97%. These regulators operate with a fixed frequency
of 2.25MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. Additionally, REG1, REG2, REG3, and
REG4 are available with a variety of standard and
custom output voltages, and may be softwarecontrolled via the I2C interface for systems that
require advanced power management functions.
100% Duty Cycle Operation
REG1, REG2, REG3, and REG4 are capable of
operating at up to 100% duty cycle. During 100%
duty cycle operation, the high-side power MOSFETs
are held on continuously, providing a direct
connection from the input to the output (through the
inductor), ensuring the lowest possible dropout
voltage in battery powered applications.
Operating Mode
By default, REG1, REG2, REG3, and REG4 operate
in fixed-frequency PWM mode at medium to heavy
loads, then transition to a proprietary power-saving
mode at light loads in order to save power.
Synchronous Rectification
REG1, REG2, REG3, and REG4 each feature
integrated synchronous rectifiers, maximizing
efficiency and minimizing the total solution size and
cost by eliminating the need for external rectifiers.
Soft-Start
REG1, REG2, REG3, and REG4 include internal 400
us soft-start ramps which limit the rate of change of
the output voltage, minimizing input inrush current
and ensuring that the output powers up in a
monotonic manner that is independent of loading on
the outputs. This circuitry is effective any time the
regulator is enabled, as well as after responding to a
short-circuit or other fault condition.
Compensation
REG1, REG2, REG3, and REG4 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. No
compensation design is required; simply follow a few
simple guide lines described below when choosing
external components.
Innovative PowerTM
Input Capacitor Selection
The input capacitor reduces peak currents and noise
induced upon the voltage source. A 10μF ceramic
capacitor is recommended for each regulator in most
applications.
Output Capacitor Selection
REG1, REG2, REG3, and REG4 were designed to
take advantage of the benefits of ceramic capacitors,
namely small size and very-low ESR. REG1, REG2,
REG3 and REG4 are designed to operate with 33uF
or 44uF output capacitor over most of their output
voltage ranges, although more capacitance may be
desired depending on the duty cycle and load step
requirements.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
Inductor Selection
REG1, REG2, REG3, and REG4 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. These
devices were optimized for operation with 2.2μH or
1μH inductors. Choose an inductor with a low DCresistance, and avoid inductor saturation by choosing
inductors with DC ratings that exceed the maximum
output current by at least 30%.
Configuration Options
Output Voltage Programming
By default, each regulator powers up and regulates to
its default output voltage. For REG2, REG3 and
REG4, the output voltage is selectable by setting
corresponding VSEL pin that when VSEL is low,
output voltage is programmed by VSET0[-] bits, and
when VSEL is high, output voltage is programmed by
VSET1[-] bits. Also, once the system is enabled,
each regulator's output voltage may be independently
programmed to a different value. Program the output
voltages via the I2C serial interface by writing to the
regulator's VSET0[-] register if VSEL is low or
VSET1[-] register if VSEL is high as shown in Table
3.
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the powerOK threshold, typically 7% below the programmed
regulation voltage, that regulator's OK[ ] bit will be 0.
If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8849
will interrupt the processor if that DC/DC's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in regulation,
and the OK[ ] bit has been read via I2C.
PCB Layout Considerations
gradients in the ground plane, both of which can
result in instability or regulation errors.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator's power
loop should be connected at a single point in a starground configuration, and this point should be
connected to the backside ground plane with multiple
via. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using
multiple via to achieve low electrical and thermal
resistance.
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
Table 3:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[2:0]
REGx/VSET[5:3]
000
001
010
011
100
101
110
111
000
0.600
0.800
1.000
1.200
1.600
2.000
2.400
3.200
001
0.625
0.825
1.025
1.250
1.650
2.050
2.500
3.300
010
0.650
0.850
1.050
1.300
1.700
2.100
2.600
3.400
011
0.675
0.875
1.075
1.350
1.750
2.150
2.700
3.500
100
0.700
0.900
1.100
1.400
1.800
2.200
2.800
3.600
101
0.725
0.925
1.125
1.450
1.850
2.250
2.900
3.700
110
0.750
0.950
1.150
1.500
1.900
2.300
3.000
3.800
111
0.775
0.975
1.175
1.550
1.950
2.350
3.100
3.900
Innovative PowerTM
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
General Description
Output Discharge
ACT8849 features eight low-noise, low-dropout
linear regulators (LDOs) that supply up to 350mA.
Three of these LDOs (REG10, REG11, and
REG12) supports extended input voltage range
down to 1.7V. Each LDO has been optimized to
achieve low noise and high-PSRR.
Each of the LDOs features an optional output
discharge function, which discharges the output to
ground through a 1.5kΩ resistance when the LDO is
disabled. This feature may be enabled or disabled
by setting DIS[-]; set DIS[-] to 1 to enable this
function, clear DIS[-] to 0 to disable it.
Output Current Limit
OK[ ] and Output Fault Interrupt
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Each LDO features a power-OK status bit that
be read by the system microprocessor via
interface. If an output voltage is lower than
power-OK threshold, typically 11% below
programmed regulation voltage, the value of
regulator's OK[-] bit will be 0.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Input Capacitor Selection
can
the
the
the
that
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8849
will interrupt the processor if that LDO's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in
regulation, and the OK[-] bit has been read via I2C.
PCB Layout Considerations
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1μF. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
The ACT8849’s LDOs provide good DC, AC, and
noise performance over a wide range of operating
conditions, and are relatively insensitive to layout
considerations. When designing a PCB, however,
careful layout is necessary to prevent other circuitry
from degrading LDO performance.
Output Capacitor Selection
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
Each LDO requires a small 2.2μF ceramic output
capacitor for stability . For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 5.
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit.
Innovative PowerTM
REFBP is a noise-filtered reference, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
ALWAYS-ON LDO (REG13)
General Description
REG13 is an always-on, low-dropout linear
regulator (LDO) that is optimized for RTC and
backup-battery applications. REG13 features lowquiescent supply current, current-limit protection,
and reverse-current protection, and is ideally suited
for always-on power supply applications, such as
for a real-time clock, or as a backup-battery or
super-cap charger.
Reverse-Current Protection
REG13 features internal circuitry that limits the
reverse supply current to less than 1µA when the
input voltage falls below the output voltage, as can
be encountered in backup-battery charging
applications. REG13's internal circuitry monitors the
input and the output, and disconnects internal
circuitry and parasitic diodes when the input voltage
falls below the output voltage, greatly minimizing
backup battery discharge.
Typical Application
Voltage Regulators
REG13 is ideally suited for always-on voltageregulation applications, such as for real-time clock
and memory keep-alive applications. This regulator
requires only a small ceramic capacitor with a
minimum capacitance of 0.47μF for stability. For
best performance, the output capacitor should be
connected directly between the output and GA, with
a short and direct connection.
Figure 4:
Typical Application of RTC LDO
Backup Battery Charging
REG13 features a constant current-limit, which
protects the IC under output short-circuit conditions
as well as provides a constant charge current, when
operating as a backup battery charger.
Innovative PowerTM
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I2CTM is a trademark of NXP.
ACT8849
Rev PrB, 12-Jun-14
TQFN66-48 PACKAGE OUTLINE AND DIMENSIONS
SYMBOL
A
A1
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN
MAX
MIN
MAX
0.700
0.800
0.032
0.036
0.200 REF
0.008 REF
A2
0.000
0.050
0.000
0.002
b
0.150
0.250
0.006
0.010
D
6.00
0.24
E
6.00
0.24
D2
4.15
4.40
0.166
0.176
E2
4.15
4.40
0.166
0.176
e
L
R
0.400 BSC
0.300
0.500
0.300
0.016 BSC
0.012
0.020
0.012
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
[email protected] or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
Innovative PowerTM
- 35 -
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Active-Semi Confidential―Do Not Copy or Distribute
Copyright © 2014 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.