ON NCP81071CMNTXG Dual 5 a high speed low-side mosfet driver Datasheet

NCP81071
Dual 5 A High Speed
Low-Side MOSFET Drivers
with Enable
NCP81071 is a high speed dual low−side MOSFETs driver. It is
capable of providing large peak currents into capacitive loads. This
driver can deliver 5 A peak current at the Miller plateau region to help
reduce the Miller effect during MOSFETs switching transition. This
driver also provides enable functions to give users better control
capability in different applications. ENA and ENB are implemented
on pin 1 and pin 8 which were previously unused in the industry
standard pin−out. They are internally pulled up to driver’s input
voltage for active high logic and can be left open for standard
operations. This part is available in MSOP8−EP package, SOIC8
package and WDFN8 3 mm x 3 mm package.
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MARKING
DIAGRAMS
8
XXXX
ALYW
G
SOIC−8
D SUFFIX
CASE 751
1
XXXX
AYW
G
Features
•
•
•
•
•
•
•
•
•
•
High Current Drive Capability ±5 A
TTL/CMOS Compatible Inputs Independent of Supply Voltage
Industry Standard Pin−out
High Reverse Current Capability (6 A) Peak
Enable Functions for Each Driver
8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load
Typical Propagation Delay Times of 20 ns with Input Falling and
20ns with Input Rising
Input Voltage from 4.5 V to 20 V
Dual Outputs can be Paralleled for Higher Drive Current
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•
•
•
•
•
•
•
•
MSOP−8
Z SUFFIX
CASE 846AM
1
1
XX MG
G
WDFN8
MN SUFFIX
CASE 511CD
XX
A
L
Y
W
M
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
Server Power
Telecommunication, Datacenter Power
Synchronous Rectifier
Switch Mode Power Supply
DC/DC Converter
Power Factor Correction
Motor Drive
Renewable Energy, Solar Inverter
PIN CONNECTIONS
1
8
ENB
ENA
INA
OUTA
GND
VDD
OUTB
INB
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 3
1
Publication Order Number:
NCP81071/D
NCP81071
VDD
VDD
VDD
VDD
ENA
ENA
VDD
VDD
Ref
Ref
VDD
Logic
A Channel
Logic
A Channel
VDD
OUTA
INA
VDD
OUTA
INA
VDD
Ref
VDD
Ref
VDD
VDD
UVLO
ENB
VDD
UVLO
VDD
ENB
OUTB
OUTB
Ref
Ref
VDD
Logic
B Channel
Logic
B Channel
GND
INB
GND
INB
Ref
Ref
NCP81071A
NCP81071B
VDD
VDD
ENA
VDD
Ref
VDD
Logic
A Channel
VDD
OUTA
INA
VDD
Ref
VDD
VDD
UVLO
ENB
OUTB
Ref
Logic
B Channel
GND
INB
Ref
NCP81071C
Figure 1. NCP81071 Block Diagram
Table 1. PIN DESCRIPTION
Pin No.
Symbol
Description
1
ENA
Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to enable and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high operation. The output of the pin when the device is disabled will be always low.
2
INA
Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be
connected to either VDD or GND. It should not be left unconnected.
3
GND
Common ground. This ground should be connected very closely to the source of the power MOSFET.
4
INB
Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be
connected to either VDD or GND. It should not be left unconnected.
5
OUTB
Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET.
6
VDD
Supply voltage. Use this pin to connect the input power for the driver device.
7
OUTA
Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET.
8
ENB
Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to enable and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high operation. The output of the pin when the device is disabled will be always low.
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2
NCP81071
TYPICAL APPLICATION CIRCUIT
NCP81071
ENA
INA
1
8
2
7
ENB
OUTA
VDD
GND
INB
3
6
4
5
OUTB
Table 2. ABSOLUTE MAXIMUM RATINGS
Value
Supply Voltage
VDD
Output Current (DC)
Iout_dc
Min
Max
Unit
−0.3
24
V
0.3
A
Reverse Current (Pulse< 1 ms)
6.0
A
Output Current (Pulse < 0.5 ms)
Iout_pulse
Input Voltage
INA, INB
−6.0
VDD+0.3
Enable Voltage
ENA, ENB
−0.3
VDD+0.3
Output Voltage
OUTA, OUTB
−0.3
VDD+0.3
V
Output Voltage (Pulse < 0.5 ms)
OUTA, OUTB
−3.0
VDD+3.0
V
Junction Operation Temperature
TJ
−40
150
°C
Storage Temperature
Tstg
−65
Electrostatic Discharge
Human body model, HBM
4000
Charge device model, CDM
1000
6.0
OUTA OUTB Latch−up Protection
A
V
160
V
500
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
VDD supply Voltage
INA, INB input voltage
ENA, ENB input voltage
Junction Temperature Range
Rating
Unit
4.5 to 20
V
−5.0 to VDD
V
0 to VDD
V
−40 to +140
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. THERMAL INFORMATION
qJA (5C/W)
qJC (5C/W)
SOIC−8
115
50
MSOP−8 EP
39
4.7
WDFN8 3x3
39
4.7
Package
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3
NCP81071
Table 5. INPUT/OUTPUT TABLE
NCP81071A
NCP81071B
NCP81071C
ENA
ENB
INA
INB
OUTA
OUTB
OUTA
OUTB
OUTA
OUTB
H
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
Any
Any
L
L
L
L
L
L
Any
Any
x (Note 1)
x (Note 1)
L
L
L
L
L
L
x (Note 1)
x (Note 1)
L
L
H
H
L
L
H
L
x (Note 1)
x (Note 1)
L
H
H
L
L
H
H
H
x (Note 1)
x (Note 1)
H
L
L
H
H
L
L
L
x (Note 1)
x (Note 1)
H
H
L
L
H
H
L
H
1. Floating condition, internal resistive pull up or pull down configures output condition
PRODUCT MATRIX
NCP81071A
NCP81071B
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4
NCP81071C
NCP81071
Table 6. ELECTRICAL CHARACTERISTICS
(Typical values: VDD =12 V, 1 mF from VDD to GND, TA = TJ = −40°C to 140°C, typical at TAMB = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
3.5
4.0
4.5
V
SUPPLY VOLTAGE
VDD Under Voltage Lockout (rising)
VCCR
VDD Under Voltage Lockout
(hysteresis)
VCCH
Operating Current (no switching)
IDD
VDD Under Voltage Lockout to Output
Delay (Note 2)
VDD rising
400
INA = 0, INB = 5 V, ENA = ENB = 0
INA = 5 V, INB = 0, ENA = ENB = 0
INA = 0, INB = 5 V, ENA = ENB = 5 V
INA = 5 V, INB = 0, ENA = ENB = 5 V
1.4
VDD rising
10
mV
3
mA
ms
INPUTS
High Threshold
VthH
Input rising from logic low
1.8
2.0
2.2
V
Low Threshold
VthL
Input falling from logic high
0.8
1.0
1.2
V
INA, INB Pull−Up Resistance
OUTA = OUTB = Inverter Configuration
200
kW
INA, INB Pull−Down Resistance
OUTA = OUTB = Buffer Configuration
200
kW
OUTPUTS
Output Resistance High
ROH
IOUT = −10 mA
0.8
2
W
Output Resistance Low
ROL
IOUT = +10 mA
0.8
2
W
Peak Source Current (Note 3)
ISource
OUTA/OUTB = GND
200 ns Pulse
5
A
Miller Plateau Source Current (Note 3)
ISource
OUTA/OUTB = 5.0 V
200 ns Pulse
4.5
A
Peak Sink Current (Note 3)
ISink
OUTA/OUTB = VDD
200 ns Pulse
5
A
Miller Plateau Sink Current (Note 3)
ISink
OUTA/OUTB = 5.0 V
200 ns Pulse
3.5
A
ENABLE
High−Level Input Voltage
VIN_H
Low to High Transition
1.8
2.0
2.2
V
Low−Level Input Voltage
VIN_L
High to Low Transition
0.8
1.0
1.2
V
ENA, ENB pull−up resistance
200
kW
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
td3
CLoad = 1.8 nF
16
20
29
ns
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
td4
CLoad = 1.8 nF
16
20
29
ns
Propagation Delay Time Low to High,
IN Rising (IN to OUT) (Notes 2, 4)
td1
CLoad = 1.8 nF
16
20
29
ns
Propagation Delay Time High to Low,
IN Falling (IN to OUT) (Notes 2, 4)
td2
CLoad = 1.8 nF
16
20
29
ns
Rise Time (Note 4)
tr
CLoad = 1.8 nF
8
15
ns
Fall Time (Note 4)
tf
CLoad = 1.8 nF
8
15
ns
Delay Matching between 2 Channels
(Note 5)
tm
INA = INB, OUTA and OUTB at 50%
Transition Point
1
4
ns
SWITCHING CHARACTERISTICS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Not production tested, guaranteed by design and statistical analysis.
4. See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5.
5. Guaranteed by characterization.
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5
NCP81071
2V
2V
Input
Input
1V
1V
2V
2V
Enable
Enable
1V
1V
90%
90%
Output
Output
10%
10%
t d3
t d4
t d3
Figure 2. Enable Function for
Non−inverting Input Driver Operation
t d4
Figure 3. Enable Function for Inverting
Input Driver Operation
2V
2V
Input
Input
1V
1V
2V
2V
Enable
Enable
1V
1V
90%
90%
Output
Output
10%
10%
t d1 t r
t d2 t f
t d1
Figure 4. Non−inverting Input Driver Operation
t d2
Figure 5. Inverting Input Driver Operation
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NCP81071
TYPICAL CHARACTERISTICS
100
180
10 nF
80
VDD = 4.5 V
70
60
4.7 nF
50
40
30
2.2 nF
20
1 nF
10
0
120
100
4.7 nF
80
60
2.2 nF
40
1 nF
470 pF
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
250
500
750
1000
1250
1500 1750 2000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 6. Supply Current vs. Switching
Frequency (VDD = 4.5 V)
Figure 7. Supply Current vs. Switching
Frequency (VDD = 8 V)
270
270
10 nF
240
SUPPLY CURRENT (mA)
240
SUPPLY CURRENT (mA)
VDD = 8.0 V
140
20
470 pF
0
VDD = 12 V
210
180
150
4.7 nF
120
90
2.2 nF
60
1 nF
30
VDD = 15 V
210
180
4.7 nF
10 nF
150
120
90
2.2 nF
60
1 nF
30
470 pF
0
0
250
500
750
1000
1250
470 pF
0
1500 1750 2000
0
250
500
750
1000
1250
1500 1750 2000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. Supply Current vs. Switching
Frequency (VDD = 12 V)
Figure 9. Supply Current vs. Switching
Frequency (VDD = 15 V)
120
270
240
VDD = 18 V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10 nF
160
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
90
210
180
10 nF
150
120
4.7 nF
2.2 nF
90
60
1 nF
30
470 pF
100
CLOAD = 2.2 nF
2 MHz
80
60
1 MHz
100 kHz
50 kHz
40
500 kHz
20
200 kHz
0
0
0
250
500
750
1000
1250
1500 1750 2000
4
6
8
10
12
14
16
18
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
Figure 10. Supply Current vs. Switching
Frequency (VDD = 18 V)
Figure 11. Supply Current vs. Supply Voltage
(CLOAD = 2.2 nF)
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7
20
NCP81071
TYPICAL CHARACTERISTICS
2.0
160
2 MHz
1.8
CLOAD = 4.7 nF
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
140
120
100
1 MHz
80
500 kHz
100 kHz
60
50 kHz
40
200 kHz
20
6
8
10
12
14
16
18
0.8
0.6
0.4
4
20
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 12. Supply Current vs. Supply Voltage
(CLOAD = 4.7 nF)
Figure 13. Supply Current vs. Supply Voltage
(NCP81071A)
2.0
20
2.0
1.8
1.8
Input = GND
1.6
1.4
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.2
1.0
0
4
Input = VDD
1.2
1.0
0.8
0.6
0.4
0.2
Input = GND
1.6
1.4
Input = VDD
1.2
1.0
0.8
0.6
0.4
0.2
0
0
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 14. Supply Current vs. Supply Voltage
(NCP81071B)
Figure 15. Supply Current vs. Supply Voltage
(NCP81071C)
12
20
12
10
10
VDD = 15 V
tf, FALL TIME (ns)
tr, RISE TIME (ns)
Input = VDD
1.4
0.2
0
8
VDD = 20 V
6
4
Input = GND
1.6
VDD = 10 V
VDD = 5 V
VDD = 15 V
8
VDD = 20 V
6
4
VDD = 10 V
VDD = 5 V
2
2
0
−40 −20
0
20
40
60
80
100
120
0
−40 −20
140
0
20
40
60
80
100
120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Rise Time vs. Temperature
Figure 17. Fall Time vs. Temperature
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NCP81071
30
30
25
25
td2, DELAY TIME (ns)
td1, DELAY TIME (ns)
TYPICAL CHARACTERISTICS
20
15
10 nF
4.7 nF
2.2 nF
1.0 nF
470 pF
10
5
20
15
10 nF
4.7 nF
2.2 nF
1.0 nF
470 pF
10
5
0
0
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
VDD, SUPPLY VOLTAGE (V)
VDD, SUPPLY VOLTAGE (V)
Figure 18. Propagation Delay td1 vs. Supply
Voltage
Figure 19. Propagation Delay td2 vs. Supply
Voltage
30
35
25
30
20
10 nF
tr, RISE TIME (ns)
tf, FALL TIME (ns)
10 nF
20
4.7 nF
15
10
1.0 nF
2.2 nF
5
25
20
4.7 nF
15
1.0 nF
10
2.2 nF
5
470 pF
470 pF
0
0
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
VDD, SUPPLY VOLTAGE (V)
VDD, SUPPLY VOLTAGE (V)
Figure 20. Fall Time tf vs. Supply Voltage
Figure 21. Rise Time tr vs. Supply Voltage
VDD
20
VDD
Output
Output
Figure 22. Output Behavior vs. Supply Voltage
NCP81071A (Inverting) 10 nF between Output
and GND, INA = GND, ENA = VDD
Figure 23. Output Behavior vs. Supply Voltage
NCP81071A (Inverting) 10 nF between Output
and GND, INA = GND, ENA = VDD
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NCP81071
TYPICAL CHARACTERISTICS
VDD
VDD
Output
Output
Figure 25. Output Behavior vs. Supply Voltage
NCP81071A (Inverting) 10 nF between Output
and GND, INA = VDD, ENA = VDD
Figure 24. Output Behavior vs. Supply Voltage
NCP81071A (Inverting) 10 nF between Output
and GND, INA = VDD, ENA = VDD
VDD
VDD
Output
Output
Figure 26. Output Behavior vs. Supply Voltage
NCP81071B (Non−Inverting) 10 nF between
Output and GND, INA = VDD, ENA = VDD
Figure 27. Output Behavior vs. Supply Voltage
NCP81071B (Non−Inverting) 10 nF between
Output and GND, INA = VDD, ENA = VDD
VDD
VDD
Output
Output
Figure 29. Output Behavior vs. Supply Voltage
NCP81071B (Non−Inverting) 10 nF between
Output and GND, INA = GND, ENA = VDD
Figure 28. Output Behavior vs. Supply Voltage
NCP81071B (Non−Inverting) 10 nF between
Output and GND, INA = GND, ENA = VDD
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NCP81071
LAYOUT GUIDELINES
Keep low level signal lines away from high level power
lines with a lot of switching noise.
Place a ground plane for better noise shielding. Beside
noise shielding, ground plane is also useful for heat
dissipation.
NCP81071 DFN and MSOP package have thermal pad
for: 1) quiet GND for all the driver circuits; 2) heat sink for
the driver. This pad must be connected to a ground plane and
no switching currents from the driven MOSFET should pass
through the ground plane under the driver. To maximize the
heatsinking capability, it is recommended several ground
layers are added to connect to the ground plane and thermal
pad. A via array within the area of package can conduct the
heat from the package to the ground layers and the whole
PCB board. The number of vias and the size of ground plane
are determined by the power dissipation of NCP81071
(VDD voltage, switching frequency and load condition), the
air flow condition and its maximum junction temperature.
The switching performance of NCP81071 highly depends
on the design of PCB board. The following layout design
guidelines are recommended when designing boards using
these high speed drivers.
Place the driver as close as possible to the driven
MOSFET.
Place the bypass capacitor between VDD and GND as
close as possible to the driver to improve the noise filtering.
It is preferred to use low inductance components such as
chip capacitor and chip resistor. If vias are used, connect
several paralleled vias to reduce the inductance of the vias.
Minimize
the
turn-on/sourcing
current
and
turn-off/sinking current paths in order to minimize stray
inductance. Otherwise high di/dt established in these loops
with stray inductance can induce significant voltage spikes
on the output of the driver and MOSFET Gate terminal.
Keep power loops as short as possible by paralleling the
source and return traces (flux cancellation).
ORDERING INFORMATION
Part Number
Output Configuration
NCP81071ADR2G
dual inverting
NCP81071BDR2G
dual non inverting
NCP81071CDR2G
One inverting
one non inverting
NCP81071AZR2G
dual inverting
NCP81071BZR2G
dual non inverting
NCP81071CZR2G
One inverting
one non inverting
NCP81071AMNTXG
dual inverting
NCP81071BMNTXG
dual non inverting
NCP81071CMNTXG
One inverting
one non inverting
Temperature Range (5C)
−40 to +140
Package Type
Shipping†
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MSOP8 EP
(Pb−Free)
3000 / Tape & Reel
WDFN8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NCP81071
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP81071
PACKAGE DIMENSIONS
MSOP8 EP, 3x3
CASE 846AM
ISSUE O
A
D
8
E
PIN ONE
INDICATOR
ÉÉ
ÉÉ
1
5
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN
EXCESS OF MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15
MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 MM PER SIDE.
DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DATUMS A AND B TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE
BODY.
F
B
E1
L
L2
C
DETAIL A
4
e
8X
b
0.08
TOP VIEW
M
C B
S
A
S
DETAIL A
A
DIM
A
A1
b
c
D
D2
E
E1
E2
e
L
L2
A1
0.10 C
C
c
END VIEW
SEATING
PLANE
SIDE VIEW
D2
E2
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
8X
8X
0.85
0.42
5.35
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
13
MILLIMETERS
MIN
MAX
−−−
1.10
0.05
0.15
0.25
0.40
0.13
0.23
2.90
3.10
1.78 REF
4.75
5.05
2.90
3.10
1.42 REF
0.65 BSC
0.40
0.70
0.254 BSC
NCP81071
PACKAGE DIMENSIONS
WDFN8 3x3, 0.65P
CASE 511CD
ISSUE O
B
A
D
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
0.10 C
2X
0.10 C
2X
ÇÇÇ
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.05 C
MOLD CMPD
DETAIL B
A3
ÉÉÉ
ÇÇÇ
ÇÇÇ
A1
ALTERNATE
CONSTRUCTIONS
0.05 C
A3
NOTE 4
SIDE VIEW
DETAIL A
A1
D2
1
C
8X
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
3.00 BSC
2.05
2.25
3.00 BSC
1.10
1.30
0.65 BSC
0.20
−−−
0.30
0.50
0.00
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
L
8X
2.31
PACKAGE
OUTLINE
4
0.63
E2
3.30
1.36
K
8
5
e/2
e
8X
BOTTOM VIEW
b
0.10 C A B
0.05 C
1
NOTE 3
0.65
PITCH
8X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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14
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NCP81071/D
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