TI1 LP592201DSCR 2-a low-noise, adjustable ldo with low input- and output-voltage capability Datasheet

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LP5922
SNVSAG0 – NOVEMBER 2016
LP5922 2-A Low-Noise, Adjustable LDO With Low Input- and Output-Voltage Capability
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
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•
•
The LP5922 is 2-A low dropout (LDO) linear regulator
with 200-mV typical dropout voltage at maximum
current levels. The LP5922 device can operate from a
voltage rail down to 1.3 V without additional bias
supply. System efficiency is maximized and power
dissipation minimized by the low dropout and low VIN
capability. The device also features low quiescent
current and very low shutdown current.
1
Wide Input Voltage Range: 1.3 V to 6 V
Low VIN Voltage Without Extra Bias Voltage
Adjustable Output Voltage: 0.5 V to 5 V
Low Dropout: 200 mV at 2-A Load
Low Output Voltage Noise: 25 μVRMS
Output Current: 2 A
–40˚C to +125°C Operating Junction Temperature
Programmable Soft Start Limits Inrush Current
3-mm × 3-mm × 0.75-mm 10-Pin WSON Package
Thermal-Overload and Short-Circuit Protection
Output Voltage Tolerance: ±1.5%
Shutdown Supply Current : 0.1 μA
PSRR: 70 dB at 1 kHz
Power Good Output
2 Applications
•
•
•
•
Space-Constrained Applications
Noise- and Ripple-Sensitive High Current Analog
or RF Systems
Target Sectors
– Medical, Test and Measurement Equipment
– Portable and Consumer electronics
– Telecom and Networking Cards
– Wireless Infrastructure
– Industrial Applications
Typical Systems
– Radio Transceivers, Power Amplifiers,
PLL/Synthesizer, Clocking, VCO, GPRS, 3G
Modules, FPGAs, DSP, GPUs, and others
The LP5922 device was designed to have high PSRR
and low output noise to support sensitive analog
applications without additional filtering. The output
noise can be reduced even further by implementing a
small capacitor on the SS/NR pin.
The output voltage is adjustable from 0.5 V to 5 V by
an external resistor divider. Enable pin, adjustable
soft start and optional Power Good features help with
system power sequencing. Inrush current is
controlled with the soft start and the device has short
circuit and thermal protections.
Device Information(1)
PART NUMBER
LP5922
space
space
space
space
space
space
space
LP5922
VIN
PSRR
FB
PG
GND
EN
SS/NR
0
VOUT
1.8 V
-20
PSRR (dB)
OUT
OUT
IN
IN
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
2.5 V
PACKAGE
WSON (10)
-40
-60
-80
IOUT = 1 mA
IOUT = 1 A
IOUT = 2 A
Copyright © 2016, Texas Instruments Incorporated
-100
10 20
100
1000
10000 100000 1000000
Frequency (Hz)
1E+7
D014
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5922
SNVSAG0 – NOVEMBER 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Input and Output Capacitors .....................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 12
8
Applications and Implementation ...................... 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
Related Documentation .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
2
DATE
REVISION
NOTES
November 2016
*
Initial release.
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5 Pin Configuration and Functions
DSC Package
10-Pin WSON With Thermal Pad
Top View
OUT
1
10
IN
OUT
2
9
IN
FB
3
8
GND
GND
4
7
SS/NR
PG
5
6
EN
Pin Functions
PIN
NUMBER
NAME
I/O
DESCRIPTION
1
OUT
O
Regulated output voltage, connect directly to pin 2
2
OUT
O
Regulated output voltage, connect directly to pin 1
3
FB
I
Voltage feedback input to the internal error amplifier
4
GND
Ground
5
PG
O
Power Good to indicate the status of output voltage. Requires an external pull-up resistor.
When PG pin voltage is high the output voltage is considered good.
Enable
Ground; connect to device pin 8.
6
EN
I
7
SS/NR
I/O
Soft-start and noise reduction pin
8
GND
Ground
Ground —connect to device pin 4.
9
IN
I
Supply voltage input — connect directly to pin 10.
10
IN
I
Supply voltage input —connect directly to pin 9.
Thermal Pad
—
Exposed pad
The exposed thermal pad on the bottom of the package must be connected to a copper area
under the package on the PCB. Connect to ground potential. Do not connect to any potential
other than the same ground potential seen at device pins 4 and 8 (GND). See Power
Dissipation for more information.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
IN pin voltage, VIN
MIN
MAX
UNIT
–0.3
7
V
OUT pin voltage, VOUT
See
(3)
EN pin voltage, VEN
–0.3
7
V
PG pin voltage, VPG
–0.3
7
V
SS/NR pin voltage, VSS/NR
–0.3
3.6
V
FB pin voltage, VFB
–0.3
3.6
V
150
°C
Junction temperature, TJ
Continuous power dissipation (4)
Internally limited
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pin.
Absolute maximum VOUT is the lesser of VIN + 0.3 V, or 7 V.
Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage, VIN
1.3
Output voltage, VOUT
0.5
FB voltage, VFB
NOM
MAX
UNIT
6
V
5
V
0.5
V
EN input voltage, VEN
0
VIN
V
Recommended load current, IL
0
2
A
–40
125
°C
Operating junction temperature, TJ-MAX-OP
6.4 Thermal Information
LP5922
THERMAL METRIC (1)
DSC (WSON)
UNIT
10 PINS
RθJA (2)
Junction-to-ambient thermal resistance, High K
49.5 (3)
RθJC(top)
°C/W
Junction-to-case (top) thermal resistance
38.2
°C/W
RθJB
Junction-to-board thermal resistance
24.0
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
24.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.0
°C/W
(1)
(2)
(3)
4
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
The PCB for the WSON/DSC package RθJA includes four (4) thermal vias, in a 2 × 2 array, under the exposed thermal pad per
EIA/JEDEC JESD51-5.
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6.5 Electrical Characteristics
VIN = VOUT(NOM) + 0.5 V or 1.3 V, whichever is greater; VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to
GND, VFB = 0.5 V, CSS/NR = 0.12 µF, CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor (unless otherwise
noted). (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VIN
Input voltage range
1.3
UVLO
Undervoltage lock-out
threshold
VIN Rising (↑) until output is ON
1.2
ΔUVLO
UVLO hysteresis
VIN Falling (↓) from UVLO threshold until output is
OFF
160
6
V
1.25
V
mV
OUTPUT VOLTAGE AND REGULATION
VOUT
ΔVOUT
Output voltage range
0.5
V
IOUT = 5 mA, 1.3 V ≤ VIN ≤ 6 V
Load regulation
5 mA ≤ IOUT ≤ 2 A
0.1
VIN = 1.4 V, IOUT = 2 A
220
400
VIN = 2.5 V, IOUT = 2 A
100
180
VIN = 5.3 V, IOUT = 2 A
90
160
500
507.5
mV
100
nA
Dropout voltage (4)
VDO
5
Line regulation
0.02
%/V
%/A
mV
FB
VFB
FB voltage
IOUT = 5 mA to 2 A
492.5
IFB
FB pin input current
VFB = 0.5 V
–100
CURRENT LEVELS
VIN ≥ 1.3 V
IL
Maximum load current
ISC
Short-circuit current limit (5)
IGND
IGND(SD)
A
3
3.8
Ground-current minimum
load (6)
VIN = 6 V, IOUT = 0 mA
0.7
Ground-current maximum
load (6)
VIN = 1.3 V, IOUT = 2 A
1
4
Shutdown current (7)
VIN = 6 V, VEN = 0 V, VPG = 0 V
0.1
15
VIN ≥ 1.4 V, ƒ = 1 kHz, IOUT = 2 A
70
VIN ≥ 1.4 V, ƒ = 10 kHz, IOUT = 2 A
55
VIN ≥ 1.4 V, ƒ = 100 kHz, IOUT = 2 A
40
VIN ≥ 1.4 V, ƒ = 1 MHz, IOUT = 2 A
30
VIN= 2.5 V, VOUT= 1.8 V
BW = 10 Hz to 100 kHz
25
VIN to VOUT RIPPLE REJECTION
PSRR
2
2.2
Power-supply rejection
ratio
A
mA
µA
(8)
dB
OUTPUT NOISE VOLTAGE
eN
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Noise voltage (8)
µVRMS
All voltages are with respect to the GND pin.
Minimum and maximum limits are design targeted limits over the junction temperature (TJ) range of –40°C to +125°C, unless otherwise
stated. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
CIN, COUT: Low-ESR surface-mount-ceramic capacitors (MLCCs) used in setting electrical characteristics.
Dropout voltage is the voltage difference between the input and the output at which the FB voltage drops to 97% of its nominal value.
Short-circuit current (ISC) is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with VOUT pulled to
100 mV below its nominal voltage.
Ground current is defined here as the total current flowing to ground as a result of all voltages applied to the device
IGND = ( (IIN – IOUT) + IEN + ILKG(PG))
Ground current in shutdown mode, IGND(SD), does NOT include current from PG pin.
This specification is verified by design.
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Electrical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V or 1.3 V, whichever is greater; VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to
GND, VFB = 0.5 V, CSS/NR = 0.12 µF, CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor (unless otherwise
noted).(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.35
V
LOGIC INPUT THRESHOLDS
VIL(EN)
EN pin low threshold
VEN falling (↓) until output is OFF
VIH(EN)
EN pin high threshold
IEN
Input current at EN pin
PGHTH
PG high threshold (% of
nominal VOUT)
VOUT rising (↑) until PG goes high
94%
PGLTH
PG low threshold (% of
nominal VOUT)
VOUT falling (↓) until PG goes low
90%
VOL(PG)
PG pin low-level output
voltage
VOUT < PGLTH, sink current = 1 mA
ILKG(PG)
PG pin leakage current
VOUT > PGHTH, VPG = 6 V
VEN rising (↑) until output is ON
(9)
1.2
V
VIN = 6 V, VEN = 6 V
3
µA
400
mV
1
µA
SOFT START
SS/NR pin charging
current
ISS
6.2
µA
THERMAL SHUTDOWN
TSD
Thermal shutdown
temperature
165
°C
ΔTSD
Thermal shutdown
hysteresis
15
°C
TRANSITION CHARACTERISTICS
Line transients
ΔVIN = 0.5 V, VOUT = 2.8 V,
tRISE = tFALL = 5 μs
Load transients
VOUT = 3.3 V, IOUT = 10 mA to 2 A to 10 mA
tRISE = tFALL = 1 V/μs
Output discharge pulldown resistance
VEN = 0 V, VIN = 2.3 V
ΔVOUT
RAD
(9)
3
mV
25
400
Ω
There is a 2-MΩ resistor between EN and ground (pulldown) on the device.
6.6 Input and Output Capacitors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CIN
Input capacitance (1)
COUT
Output capacitance
(1)
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
22
VOUT ≤ 0.8 V
34
47
VOUT > 0.8 V
15
22
µF
µF
Typically input capacitance placed close to the device is in the same order as output capacitance. See also Input Capacitor, CIN.
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6.7 Typical Characteristics
VIN = VOUT + 0.5 V, VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to GND, VFB = 0.5 V, CSS/NR = 0.12 µF,
CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor and TJ = 25°C, unless otherwise stated.
1.3
3.5
1.2
3.25
3
2.75
1
2.5
IGND (mA)
0.9
0.8
0.7
2.25
2
1.75
1.5
0.6
1.25
0.5
1
VEN(ON)
VEN(OFF)
0.75
1
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
VIN = 5.5 V, VOUT = 5.0 V
0.5
0.3
0
6
0.2
0.6
1
1.2
IOUT (A)
1.4
1.6
1.8
2
D017
5.5
500
5
500
4.5
450
4.5
450
4
400
3.5
350
3
300
2.5
250
2
200
1.5
150
0.5
0
-2
0
2
4
6
VOUT = 5 V
8
10
Time (ms)
12
Voltage (V)
550
5
VSS/NR Voltage (V)
5.5
1
VIN, VEN
100
VOUT
VSS/NR
50
VPG
0
14
16
18
550
4
400
3.5
350
3
300
2.5
250
2
200
1.5
150
1
0.5
0
-2
0
2
4
VEN = VIN
IOUT = 1 mA
VOUT = 5 V
Figure 3. Power Up
360
300
2.4
240
1.8
180
100
1.2
120
50
0.6
60
2.5
250
2
200
1.5
150
1
0.5
VOUT = 5 V
35
VEN = VIN
40
45
5.4
4.8
0
50
Voltage (V)
300
6
VSSINR Voltage (V)
3
20 25 30
Time (ms)
IOUT = 2 A
3
350
15
D009
VEN = VIN
3.6
3.5
10
14
4.2
4
4.5
5
12
600
VIN,VEN
540
VOUT
VSS/NR 480
VPG
420
VIN,VEN
500
VOUT
VSS/NR 450
VPG
400
0
8
10
Time (ms)
VIN,VEN
100
VOUT
VSS/NR
50
VPG
0
16
18
Figure 4. Power Up
550
5
0
-5
6
D008
5.5
Voltage (V)
0.8
Figure 2. Ground Current vs Output Current
Figure 1. VEN Thresholds vs Input Voltage
Voltage (V)
0.4
D007
VSS/NR Voltage (V)
0.4
0
-5
0
5
10
D010
IOUT = 1 mA
VOUT = 5 V
Figure 5. Power Down
15
20 25 30
Time (ms)
35
VEN = VIN
40
45
VSS/NR Voltage (V)
VEN Threshold (V)
1.1
0
50
D011
IOUT = 2 A
Figure 6. Power Down
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Typical Characteristics (continued)
3
360
2.5
300
Voltage (V)
4
2
240
1.5
180
1
120
0.5
5
4
60
0
-5
0
5
VOUT = 5 V
10
15
20 25 30
Time (ms)
35
40
45
3.5
500
VEN
450
VOUT
VSS/NR 400
VPG
350
4.5
Voltage (V)
3.5
600
VEN
540
VOUT
VSS/NR 480
VPG
420
VSS/NR Voltage (V)
5
4.5
3
300
2.5
250
2
200
1.5
150
1
100
0.5
0
50
50
0
-50
0
50
100
D012
IOUT = 1 mA
300
350
400
0
450
D013
IOUT = 2 A
Figure 8. Power Down
4 VOUT
4 VOUT
IOUT
IOUT
IOUT = 10 mA to 2 A
150 200 250
Time (us)
VOUT = 5 V
Figure 7. Power Down
VOUT = 2.8 V
VSS/NR Voltage (V)
VIN = VOUT + 0.5 V, VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to GND, VFB = 0.5 V, CSS/NR = 0.12 µF,
CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor and TJ = 25°C, unless otherwise stated.
trise = 1 V/µs
VOUT = 2.8 V
Figure 9. Load Transient Response
IOUT = 2 A to 10 mA
tfall = 1 V/µs
Figure 10. Load Transient Response
0.25
VIN = 1.4 V
VIN = 2.5 V
VIN = 3.7 V
VIN = 5.3 V
0.225
Dropout Voltage (mV)
0.2
VIN
4 VOUT
4 VOUT
0.175
0.15
0.125
0.1
0.075
0.05
0.025
IOUT
0
0
VOUT = 2.8 V
VIN 3.3 V to 3.8V to 3.3 V
0.4
0.6
0.8
1
1.2
IOUT (A)
1.4
1.6
1.8
2
D015
tfall = 1 V/µs
Figure 11. Line Transient Response
8
0.2
Figure 12. Dropout Voltage (VDO) vs Load Current
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Typical Characteristics (continued)
VIN = VOUT + 0.5 V, VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to GND, VFB = 0.5 V, CSS/NR = 0.12 µF,
CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor and TJ = 25°C, unless otherwise stated.
0
10
Noise (PV/—Hz)
-20
PSRR (dB)
IOUT = 0 A
IOUT= 0.1 A
IOUT = 0.5 A
IOUT = 2 A
5
3
2
-40
-60
-80
100
VIN = 5.5 V
1000
10000 100000 1000000
Frequency (Hz)
0.5
0.3
0.2
0.1
0.05
0.03
0.02
IOUT = 1 mA
IOUT = 1 A
IOUT = 2 A
-100
10 20
1
1E+7
0.01
10 20
50 100
D014
VIN = 2.5 V
VOUT = 5 V
1000
10000
Frequency (Hz)
100000
1000000
D016
VOUT = 1.8 V
Figure 14. Noise Density vs Frequency
Figure 13. PSRR vs Frequency
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7 Detailed Description
7.1 Overview
The LP5922 is a low-noise, high PSRR, low-dropout regulator capable of sourcing a 2-A load. The LP5922 can
operate down to 1.3-V input voltage and 0.5-V output voltage. This combination of low noise, high PSRR, and
low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from
noise-sensitive communication components to battery-powered system.
The LP5922 block diagram contains several features, including:
• Low-noise, 0.5-V reference
• Internal protection circuit, such as current limit and thermal shutdown
• Programmable soft-start circuit
• Power Good output
7.2 Functional Block Diagram
IN
VIN
OUT
Current
Limit
IN
OUT
VOUT
RAD
AVDD
EA
VSS
98%
FB
VREF
Reference
0.5 V
VFB
VSS
RF
PG
CF
VREF
VEN
EN
ULVO
Enable
2 0Ÿ
GND
GND
SS/NR
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7.3 Feature Description
7.3.1 Output Voltage
The LP5922 output voltage can be set to any value from 0.5 V to 5 V using two external resistors shown as
RUPPER and RLOWER in Figure 15. The value for the RLOWER should be less than or equal to 100 kΩ for good loop
compensation. RUPPER can be selected for a given VOUT using Equation 1:
(VOUT VFB ) u RLOWER
RUPPER
VFB
where
•
10
VFB = 0.5 V
(1)
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Feature Description (continued)
7.3.2 Enable
The LP5922 EN pin is internally held low by a 2-MΩ resistor to GND. The EN pin voltage must be higher than the
VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must
be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is
activated.
7.3.3 Output Automatic Discharge
The LP5922 output employs an internal 400-Ω (typical) pulldown resistance to discharge the output capacitor
when the EN pin is low, and the device is disabled.
7.3.4 Programmable Soft Start and Noise Reduction
The output voltage of LP5922 ramps up linearly in a constant slew rate until reaching the target regulating
voltage after a stable VIN (greater than VOUT + VDO) is supplied and EN pin is pulled high. The slew rate of VOUT
ramping is programmable by an external capacitor on the SS/NR pin; therefore, the duration for soft-start period
is programmable as well. Once the LP5922 is enabled, the SS/NR pin sources a constant 6-µA current to charge
the external CSS/NR capacitor until the voltage at the SS/NR pin reaches 98% of the internal reference voltage
(VREF) of 500 mV typical. The final 2% of CSS/NR charge is determined by a RC time constant. During the softstart period, the current flowing into the IN pin primarily consists of the sum of the load current at the LDO output
and the charging current into the output capacitor. The soft-start period can be calculated by Equation 2:
CSS/NR u VFB
t SS
ISS
where
•
•
•
VFB = 0.5 V - this is the voltage that CSS/NR charges to;
CSS/NR is the value of the capacitor connected between the SS/NR pin and ground; and
ISS = 6.2 µA is the typical charging current to the SS/NR pin during start-up period.
(2)
The recommended value for CSS/NR is 100 nF or larger. Equation 2 is most accurate for these values. The CSS/NR
capacitor is also the filter capacitor for internal reference for noise reduction purpose. An integrated resistor and
the CSS/NR capacitor structure a RC low-pass filter to remove the noise on the internal reference voltage.
7.3.5 Internal Current Limit
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current
limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting
in a thermal shutdown of the output.
7.3.6 Thermal Overload Protection
Thermal shutdown disables the output when the junction temperature rises to TSD level, which allows the device
to cool. When the junction temperature cools by ΔTSD, the output circuitry enables. Based on power dissipation,
thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal
cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.
The internal protection circuitry of the LP5922 is designed to protect against thermal overload conditions. The
circuitry is not intended to replace proper heat sinking. Continuously running the LP5922 into thermal shutdown
degrades device reliability.
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Feature Description (continued)
7.3.7
Power Good Output
The LP5922 has a Power-Good function that works by toggling the state of the PG output pin. When the output
voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages (low impedance to
GND). When the output voltage rises above the PG threshold voltage (PGHTH), the PG pin becomes highimpedance. By connecting a pullup resistor to an external supply, any downstream device can receive PG as a
logic signal. User must make sure that the external pullup supply voltage results in a valid logic signal for the
receiving device or devices; use a pullup resistor from 10 kΩ to 100 kΩ for best results.
In Power-Good function, the PG output pin pulled high immediatelly after output voltage rises above the PG
threshold voltage.
7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP5922 enable (EN) pin is internally held low by a 2-MΩ resistor to GND. If the EN pin is open the output is
OFF. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under
all operating conditions. When the EN pin is pulled low, and the output is disabled, the output automatic
discharge circuit is activated. Any charge on the OUT pin is discharged to GND through the internal pulldown
resistance.
7.4.2 Undervoltage Lockout (UVLO)
The LP5922 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP5922 disabled
while a rising VIN is less than 1.2 V (typical). The rising UVLO threshold is approximately 100 mV below the
recommended minimum operating VIN of 1.3 V.
7.4.3 Minimum Operating Input Voltage
The LP5922 internal circuit is not fully functional until VIN is at least 1.3 V. The output voltage is not regulated
until VIN has reached at least the greater of 1.3 V or (VOUT + VDO).
12
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP5922 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR,
low quiescent current, and low line or load transient response figures. The device offers excellent noise
performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a
value of 22 µF. The LP5922 delivers this performance in an industry-standard WSON package which, for this
device, is specified with an operating junction temperature (TJ) of –40°C to +125°C.
8.2 Typical Application
Figure 15 shows the typical application circuit for the LP5922. Input and output capacitances may need to be
increased above 22 µF minimum for some applications.
VIN
1.3 V ± 6 V
OUT
OUT
IN
IN
CIN
22 µF
LP5922
VIN
VOUT
0.5 V ± 5 V
RUPPER
CFF
FPGA
VIN
COUT
22 µF
FB
RLOWER
100 k
PG
GND
EN
SS/NR
CSS/NR
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Figure 15. LP5922 Typical Application
8.2.1 Design Requirements
For typical LP5922 applications, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.25 V to 2.75 V
Output voltage
1.8 V
Output current
2000 mA
Output capacitor range
22 µF to 47 µF
Output capacitor ESR range
2 mΩ to 500 mΩ
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8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
The LP5922 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the
input, output, and the noise-reduction pin (SS/NR). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended, but must be used with good judgment. Ceramic
capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability
across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in
capacitance. Additionally, the case size has a direct impact on the capacitance versus applied voltage derating.
Regardless of the ceramic capacitor type selected, the actual capacitance varies with the applied operating
voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output
capacitors recommended herein account for a effective capacitance derating of approximately 50%, but at high
applied voltage conditions the capacitance derating can be greater than 50% and must be taken into
consideration. The minimum capacitance values declared in Input and Output Capacitors must be met across the
entire expected operating voltage range and temperature range.
8.2.2.2 Input Capacitor, CIN
An input capacitor is required for stability. A capacitor with a value of at least 22 μF must be connected between
the LP5922 IN pin and ground for stable operation over full load current range. It is acceptable to have more
output capacitance than input, as long as the input is at least 22 μF.
The input capacitor must be located as close as possible to, but at a distance not more than 1 cm from, the IN
pin and returned to the device GND pin with a clean analog ground. This will minimize the trace inductance
between the capacitor and the device. Any good quality ceramic or tantalum capacitor may be used at the input.
8.2.2.3 Output Capacitor, COUT
The LP5922 is designed to work specifically with a low ESR ceramic (MLCC) output capacitor, typically 22 μF. A
ceramic capacitor (dielectric types X5R or X7R) in the 22-μF to 100-μF range, with an ESR not exceeding 500
mΩ, is suitable in the LP5922 application circuit having an output voltage greater than 0.8 V. For output voltages
of 0.8 V or less, the output capacitance must be increased to typically 47 μF. The output capacitor must be
connected between the device OUT and GND pins. The output capacitor must meet the requirement for the
minimum value of capacitance and have an ESR value that does not exceed 500 mΩ to ensure stability.
It is possible to use tantalum capacitors at the device output, but these are not as attractive for reasons of size,
cost, and performance.
A combination of multiple output capacitors in parallel boosts the high-frequency PSRR. The combination of one
0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized, 10-µF ceramic capacitors with a sufficient
voltage rating optimizes PSRR response in the frequency range of 400 kHz to 700 kHz (which is a typical range
for dc-dc supply switching frequency). This 47-µF || 10-µF || 10-µF combination also ensures that at high input
voltage and high output voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47µF ceramic capacitors have a voltage derating of approximately 60% to 75% at 5 V, so the addition of the two
10-µF capacitors ensures that the capacitance is at or above 22 µF.
8.2.2.4 Soft-Start and Noise-Reduction Capacitor, CSS/NR
Recommended value for CSS/NR is 100 nF or larger. The soft-start period can be calculated by Equation 2. The
CSS/NR capacitor is also the filter capacitor for internal reference for noise reduction purpose.
8.2.2.5 Feed-Forward Capacitor, CFF
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a 10nF external CFF optimizes the transient, noise, and PSRR performance. A higher capacitance CFF value can be
used; however, the start-up time may be longer and the Power-Good signal may incorrectly indicate that the
output voltage is settled. The maximum recommended value is 100 nF
To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the
time constant from CFFx. For a detailed description, see the application report Pros and Cons of Using a FeedForward Capacitor with a Low Dropout Regulator (SBVA042).
14
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8.2.2.6 No-Load Stability
The LP5922 remains stable, and in regulation, with no external load.
8.2.2.7 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the exposed thermal
pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage,
and load conditions and can be calculated with Equation 3.
PD(MAX) = (VIN(MAX) – VOUT) × IOUT
(3)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that is greater than the dropout voltage (VDO). However, keep in mind that higher voltage
drops result in better dynamic (that is, PSRR and transient) performance.
On the WSON (DSC) package, the primary conduction path for heat is through the exposed thermal pad into the
PCB. To ensure the device does not overheat, connect the exposed thermal pad, through multiple thermal vias,
to an internal ground plane with an appropriate amount of PCB copper area.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 4 or Equation 5:
TJ(MAX) = TA(MAX) + (RθJA × PD(MAX))
PD = (TJ(MAX) – TA(MAX)) / RθJA
(4)
(5)
If the VIN-VOUT voltage is known, the maximum allowable output current can be calculated with Equation 6
IOUT(MAX) = ( ( (125°C - TA) / RθJA ) / (VIN – VOUT) )
(6)
Unfortunately, the RθJA value is highly dependent on the heat-spreading capability of the particular PCB design,
and therefore varies according to the PCB size, total copper area, copper weight, any thermal vias, and location
of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7
standard for PCB and copper spreading area, and is to be used only as a relative measure of package thermal
performance. For a well designed thermal layout, RθJA is actually the sum of the package junction-to-case
(bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper area acting as
a heat sink.
8.2.2.8 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the Thermal Information table and are used in accordance with Equation 7 and Equation 8.
TJ(MAX) = TTOP + (ΨJT × PD(MAX))
where
•
TTOP is the temperature measured at the center-top of the device package.
•
PD(MAX) is described at Equation 3
TJ(MAX) = TBOARD + (ΨJB × PD(MAX))
(7)
where
•
•
TBOARD is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
PD(MAX) is described at Equation 3
(8)
For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal
Metrics ; for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics ; and for more
information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report Thermal
Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available
at www.ti.com.
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8.2.2.9 Recommended Continuous Operating Area
The continuous operational area of an LDO is limited by the input voltage (VIN), the output voltage (VOUT), the
dropout voltage (VDO), the output current (IOUT), and the junction temperature (TJ). The recommended area for
continuous operation for a linear regulator can be separated into the following steps, and is shown in Figure 16.
• Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output
(VIN – VOUT) at a given output current level.
• Limited by the rated output current: The rated output current limits the maximum recommended output current
level. Exceeding this rating causes the device to fall out of specification.
• Limited by thermals: This portion of the boundary is defined by Equation 6. The slope is nonlinear because
the junction temperature of the LDO is controlled by the power dissipation (PD) across the LDO; therefore,
when VIN – VOUT increases, the output current must decrease in order to ensure that the rated maximum
operating junction temperature of the device is not exceeded. Exceeding the maximum operating junction
temperature rating can cause the device to fall out of specifications, reduces long-term reliability, and may
activate the thermal shutdown protection circuitry.
• Limited by VIN range: The rated operating input voltage range governs both the minimum and maximum of
VIN – VOUT.
IOUT (A)
Limited by
Rated Output Current
Limited by
Thermals
Limited by
Dropout
Recommended Area for
Continuous Operation
Limited by
Minimum Operating VIN
0
0
Limited by
Maximum Operating VIN
VIN ± VOUT (V)
Figure 16. Recommended Continuous Operating Area
Figure 17 to Figure 22 show the recommended continuous operating area boundaries for this device in the
WSON (DSC) package mounted to a EIA/JEDEC High-K printed circuit board, as defined by JESD51-7, with an
RθJA rating of 49.5°C/W.
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2200
2200
TA = 25°C
TA = 50°C
TA = 85°C
TA = 100°C
2000
1600
1800
1600
Output Current
Output Current (mA)
1800
1400
1200
1000
800
1200
1000
800
600
400
400
200
200
0
0
0.5
1
1.5 2 2.5 3 3.5 4
Input Voltage Output Voltage
4.5
5
0
5.5
0.5
D001
Figure 17. Recommended Continuous Operating Area for
VOUT = 0.8 V
1
1.5
2
2.5
3
3.5
Input Voltage Output Voltage
4
4.5
5
D002
Figure 18. Recommended Continuous Operating Area for
VOUT = 1.2 V
2200
2200
TA = 25°C
TA = 50°C
TA = 85°C
TA = 100°C
1800
1600
TA = 25°C
TA = 50°C
TA = 85°C
TA = 100°C
2000
1800
Output Current (mA)
2000
Output Current (mA)
1400
600
0
1400
1200
1000
800
600
1600
1400
1200
1000
800
600
400
400
200
200
0
0
0
0.5
1
1.5
2
Input Voltage
2.5
3
3.5
Output Voltage
4
4.5
0
D003
Figure 19. Recommended Continuous Operating Area for
VOUT = 1.8 V
1
1.5
2
2.5
3
Input Voltage Output Voltage
3.5
4
D004
2200
TA = 25°C
TA = 50°C
TA = 85°C
TA = 100°C
1800
1600
2000
1800
Output Current (mA)
2000
1400
1200
1000
800
600
1600
1400
1200
1000
800
600
400
400
200
200
0
0.00
0.5
Figure 20. Recommended Continuous Operating Area for
VOUT = 2.5 V
2200
Output Current (mA)
TA = 25°C
TA = 50°C
TA = 85°C
TA = 100°C
2000
TA = 50°C
TA = 25°C
TA = 85°C
TA = 100°C
0
0.50
1.00
1.50
2.00
Input Voltage Output Voltage
2.50
3.00
0
D005
Figure 21. Recommended Continuous Operating Area for
VOUT = 3.3 V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Voltage Output Voltage (V)
1
1.1 1.2
D006
Figure 22. Recommended Continuous Operating Area for
VOUT = 5 V
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8.2.3 Application Curves
10
3.5
IOUT = 0 A
IOUT= 0.1 A
IOUT = 0.5 A
IOUT = 2 A
3.25
3
2.75
1
2.5
IGND (mA)
Noise (PV/—Hz)
5
3
2
0.5
0.3
0.2
2.25
2
1.75
0.1
1.5
0.05
0.03
0.02
1.25
0.01
10 20
1
0.75
VIN = 3.3 V, VOUT = 2.8 V
0.5
50 100
1000
10000
Frequency (Hz)
100000
1000000
0
0.2
D016
Figure 23. Noise Density vs Frequency
0.4
0.6
0.8
1
1.2
IOUT (A)
1.4
1.6
1.8
2
D018
Figure 24. Ground Current vs Output Current
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.3 V to 6 V. The input supply should be
well regulated and free of spurious noise. To ensure that the LP5922 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 1 V. A minimum capacitor value of
22 μF is required to be within 1 cm of the IN pin.
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10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP5922 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5922.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5922 device, and
as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5922
GND pin using as wide and as short of a copper trace as is practical.
Avoid connections using long trace lengths, narrow trace widths, or connections through vias. These add
parasitic inductances and resistance that results in inferior performance especially during transient conditions
10.2 Layout Example
RUPPER
OUT
1
10
IN
OUT
2
9
IN
FB
3
8
GND
GND
4
7
SS/NR
PG
5
6
EN
CIN
COUT
GND
RLOWER
CSS/NR
RPG
Figure 25. LP5922 Typical Layout
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11 Device and Documentation Support
11.1 Related Documentation
For additional information, see the following:
• Using New Thermal Metrics
• Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP592201DSCR
PREVIEW
WSON
DSC
10
3000
TBD
Call TI
Call TI
-40 to 125
LP592201DSCT
PREVIEW
WSON
DSC
10
250
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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