AN10958 Fluorescent lamp driver with PFC using the UBA2015/16 family Rev. 2 — 9 August 2012 Application note Document information Info Content Keywords UBA2015, UBA2015A, UBA2016A fluorescent lamp driver, PFC Abstract This application note describes designs using IC family UBA2015, UBA2015A and UBA2016A for common ballast topologies. The IC is a controller used in electronic ballast for fluorescent lamps incorporating controllers and NMOST drivers for Power Factor Correction (PFC) and the half-bridge circuit. The high-voltage fluorescent lamp ballast controller drives a zero-voltage switching resonant topology. The lamp controller module includes a high-voltage level shift circuit and several protection features. The protection features include hard switching/capacitive mode protection, half-bridge overcurrent (coil saturation) protection, lamp overvoltage (lamp removal) protection and temperature protection. In addition to the lamp controller, the IC also contains a PFC controller. The quasi-resonant operation guarantees efficient operation of the PFC circuit. Overcurrent protection, overvoltage protection and demagnetization sensing ensure safe operation under all conditions. The brownout protection of the PFC controller reduces the half-bridge frequency to prevent excessive currents. The proprietary high-voltage BCD power logic process enables efficient, direct start-up from the rectified universal mains voltage. The IC can drive half-bridge circuits with a supply voltage up to 600 V (AC). The PFC and lamp controller combination makes the IC suitable for dimmable or fixed current output fluorescent ballasts with a PFC for AC mains voltages up to 390 V. AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family Revision history Rev Date Description v.2 20120809 second version v.1 20110620 first version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 2 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 1. Introduction 1.1 General IC description Today’s market demands high-quality, reliable, lightweight, small and efficient electronic High Frequency (HF) ballast with lamp end-of-life detection. The high-end market segment also requires dimming functionality. Electronic ballasts provide high efficiency performance because the lamp is operated at high frequencies above 10 kHz. At this frequency, the lamp is more efficient when compared to a magnetic ballast operating at 50 Hz to 60 Hz. High frequency operation enables smaller magnetic components in the electronic ballast to be smaller. This reduction makes electronic ballasts are approximately one fifth the weight of magnetic ballasts. The UBA2015, UBA2015A and UBA2016A combines Power Factor Correction (PFC) and half-bridge controller in one IC which reduces the component cost significantly and increases reliability. It has several protection mechanisms such as overvoltage/no ignition, coil saturation, overtemperature and on some pins, open/short protection to guarantee reliable and safe operation. The integrated dimming option allows control of the lamp current down to 1 % of the nominal lamp current. The integrated double-sided rectification of the lamp current feedback signal and a control loop compensation network pin allows stable lamp operation and achieves good dimming performance. The IC is intended for fluorescent lamp ballast with fixed or dimmable light output, with PFC for AC mains voltages up to 390 V. A feature list, block diagram and flow chart for the IC are provided in the IC data sheet. 1.2 Basic electronic ballast circuit Cs VAC EMI Ls Lpfc Lr PFC AND HALF-BRIDGE CONTROLLER/DRIVER Cr Ls Cs Cdc 019aaa610 The feedback signals are not shown. Fig 1. AN10958 Application note Basic electronic ballast circuit for inductive heating topology All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 3 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 1.2.1 Power factor correction Lighting applications above 25 W need a PFC circuit to fulfill the Total Harmonic Distortion (THD) and Power Factor (PF) requirements. The PFC circuit is actually a boost or step-up converter, therefore the output voltage must be higher than the peak AC mains voltage. The PFC provides a fixed DC output voltage which helps to create a better defined half-bridge circuit and therefore longer lamp life. A high DC voltage also results in more efficient ballasts for lamps operating at higher voltages. The PFC operates at a fixed on-time over one mains cycle. The PFC circuit inductor peak current follows the sinusoidal mains waveform. EMI filtering averages the PFC switching current and blocks common mode currents (see Figure 2). The frequency limit also reduces switching losses using valley skipping are reduced which is very effective at low AC mains input voltage and medium to low output load conditions. I I (1) (2) (3) (1) (2) t 0.5 × Tac t zero current switching on-time TPFC 019aaa608 a. Half AC mains cycle b. PFC switching cycle (1) ILPFC(peak). (1) IQPFC. (2) ILPFC. (2) IDPFC. 019aaa609 (3) Iac(avg). Fig 2. PFC circuit currents A fixed output voltage has the advantage that the half-bridge circuit can be designed for a high input voltage. The fixed bus voltage makes the half-bridge design more efficient for lamps with a high operating voltage such as T5 lamps. 1.2.2 Inductive heating half-bridge and ballast Refer to Figure 1. The capacitor (Cr) across the lamp is the resonant capacitor and inductor (Lr) is the resonant inductor. The capacitor in series with the lamp is the DC blocking capacitor (CDC). Before ignition, the electrodes are preheated at a predefined half-bridge current (UBA2016A) or frequency (UBA2015). After preheat, the lamp voltage increases while sweeping the half-bridge operating frequency down to the resonant frequency. Finally, the lamp ignites when the lamp ignition voltage is reached. When the lamp does not ignite, the switching frequency ramp down is stopped to avoid damage to components. Then a new ignition attempt is started. After a maximum of two ignition attempts, the IC enters a standby mode. Once the lamp is ignited, the resonant tank and switching frequency limit the amount of current through the lamp. The half-bridge operating frequency controls the lamp current. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 4 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 1.2.3 IC family overview This family of half-bridge controller ICs comprises three functionally different versions. All versions are available in both SO20 and DIP20 packages. The functional differences are explained in Table 1. Table 1. 1.2.3.1 IC family overview Function UBA2015 UBA2015A UBA2016A PFC controller yes yes yes Preheat operation current controlled and fixed frequency current controlled and fixed frequency current controlled Boost function no no yes Dim function no yes yes Preheat operation The current controlled preheat operation is intended for a series-resonant topology where the half-bridge current is equal to the filament currents. The accuracy is independent of the LC tank tolerances. Therefore, the preheat frequency is closer to the maximum preheat voltage allowed. As a result, the preheat current is higher than with fixed frequency preheat. The fixed frequency preheat operation is intended for multi-lamp ballasts where the total half-bridge current is not equal to the filament current. For example: the half-bridge current is reduced by a factor of two when a lamp is removed in a two-lamp ballast with conventional series-resonant topology. 1.2.3.2 Boost function The boost function is used for amalgam lamps or outdoor applications to provide a rapid light output run-up time. The run-up time is the time a discharged lamp takes to reach 80 % of the nominal light output. The boost function allows the lamp to be operated at 1.5 to 2.0 times its nominal current. As a result, the lamp reaches the optimum operating temperature sooner. The boost is applied at ballast power-on. A capacitor in the application determines the boost time. 1.2.3.3 Dim function The dim function is intended for energy harvesting or light reduction. 2. Basic circuit description This section describes the deep dimming ballast in the inductive series-resonant topology shown in Figure 1. The inductors Ls and Lr are coupled, therefore the current through the filaments is inductively coupled to the current through Lr in the LC tank. A complete electronic schematic of a ballast with dimming and boosting using the UBA2016A is shown in Figure 3. This application note uses this schematic as a guide. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 5 of 56 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors AN10958 Application note J3 2 1 C1 Chassis D6 2.2 nF X1/Y2 250 V AC CON4 J1 F1 fuse holder 2 + RV1 710 V 1 - C3 100 nF X2 275 V AC 2 4 1 3 PMBD914 C34 100 nF 1N4007 C6 150 nF 400 V 3 6 D2 1N4007 2 6 1 R31 100 Ω D4 1N4007 SHHB 10 kW 500 V R47 10 kΩ 10 pF 500 V C36 100 nF R33 reserved VCdc Q5 BFT46 R42 4.7 kΩ 1% reserved R41 200 kΩ R23 SHHB R39 1 kΩ C15 SHHB GLHB T3A 2.5 mH Np:Ns=30:1:1 3 Q2 2SK3767 6 5 WB1 VDD GLHB C18 470 nF C20 R11 R36 470 kΩ 10 kΩ GLHB SHHB FSHB 11 10 12 9 13 8 14 15 16 7 UBA2016AT 6 5 17 4 18 3 19 100 nF GHHB 20 50 V 2 1 BOOST DIM R24 CPT 3.3 kΩ D7 BAS101 CIFB C23 IREF 100 nF VFB VFB EOL EOL IFB R19 IFB SLHB SLHB R12 6.8 kΩ DIM CF 100 kΩ C16 1.5 nF C35 10 nF 2.2 kΩ C21 10 nF R21 33 kΩ 1% C19 100 pF J4 C25 220 pF C0G 1% C24 3.3 nF R22 1 kΩ C30 10 nF C26 82 nF C22 10 nF 4 3 2 C10 3.3 nF 2 kV C13 7 8 WB2 68 nF 100 V T3C 1 CON4 VCdc R7 5.1 MΩ SLHB R16 3.3 Ω 1% 0W25 GHHB C12 68 nF 100 V 2 GPFC GND VFB Q3 2SK3767 AUXPFC D8A BAV99 D8B BAV99 VBUS GHHB D11 PMBD914 R35 47 kΩ U1 FBPFC COMPPFC GPFC C8 330 pF 500 V SHHB T3B C28 47 pF FBPFC 470 nF 82 kΩ C27 100 nF reserved R25 470 kΩ 500 V C17 1 nF 100 pF 2 kV R29 3.3 kΩ 1% BOOST 10 μF 25 V BOOST C29 AUXPFC fuse holder cover C11 130 kΩ 470 nF 500 V 630 V DC reserved C5 FBPFC C37 Vbus R44 330 kΩ 500 V Q6 BC847C F4 R15 R28 PMBD914 3.9 Ω 1% 1W R27 3.9 Ω 1% 1W R5 2.2 MΩ R17 3.3 Ω 1% 0W25 R18 330 kΩ 500 V reserved OPTION R6 5.1 MΩ C14 68 nF 400 V DC 10 % VBUS EOL R4 1 MΩ 500 V reserved R20 180 kΩ 1% D9 PMBD6100 IFB R10 2.7 Ω 1W D15 PMBD7000 R37 R13 18 Ω 1% 0W25 R14 18 Ω 1% 0W25 BOOST 1Ω reserved R45 27 kΩ C31 100 nF R46 220 kΩ 1% Q4 BC847C reserved R3 75 kΩ reserved R38 100 kΩ reserved D12 PMBD914 reserved DIM 019aab530 Fig 3. Complete electronic ballast circuit for inductive series-resonant topology AN10958 6 of 56 © NXP B.V. 2012. All rights reserved. R9 2.7 Ω 1W Fluorescent lamp driver with PFC using the UBA2015/16 family Rev. 2 — 9 August 2012 All information provided in this document is subject to legal disclaimers. C32 10 nF D10 AUXPFC DIM F3 T1A R34 330 kΩ 1% 200 V VBUS R26 R40 C33 100 nF R32 390 kΩ 1% Q1 2SK3767 GPFC C7 10 μF 450 V 4.7 nF D13 PMBD914 1 MΩ R43 4.7 kΩ 8 C9 R8 UF4006 T2 5.0 mH Np:Ns=51:1 100 nF X2 275 V AC R30 390 kΩ 1% D5 2 D16 PMBD914 4 Q7 BC847C MMBZ15VAL VBUS D3 1N4007 C4 EFD15 10 mH N=1 T1 D14 DN2 D1 1N4007 L1 (2 ´ 47 mH B82731M) reserved L4 (2 ´ 47 mH B82731T) CON4 F2 thermal fuse R2 220 Ω 33 nF 400 V reserved reserved DN1 MMBZ15VAL reserved 4 Mains_L 3 Mains_N C2 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family The circuit diagram of the PFC section is shown in Figure 4. Signal FBPFC is the feedback to the controller. The bus voltage VBUS connects to the half-bridge circuit. The AUXPFC signal is fed to the controller. The GPFC is the gate drive signal from the controller. J1 2 1 D3 C1 Chassis D1 VBUS D2 R1 D4 J2 4 Mains_L 3 Mains_N 2 F1 2 1 RV1 1 C5 L1 4 C4 C3 3 T1 C2 2 R2 3 6 D5 D6 Q1 8 GPFC R4 R3 D7 AUXPFC R5 reserved FBPFC R6 R7 R8 C6 019aaa611 Fig 4. PFC section The inductive mode series-resonant topology is shown in Figure 5. An inductor coupled to the resonant inductor heats the electrodes. The bus voltage is from the PFC circuit output. GHHB and GLHB are the gate drive signals from the controller. SHHB is connected to the input of the controller and provides a supply for the controller during oscillation states. SLHB is connected to the input of the controller. The VFB signal is the lamp voltage feedback. IFB is the lamp current feedback. EOL is the feedback of the DC blocking capacitor C12. The VCDC signal provides the start-up current to the VDD pin. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 7 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family C7 R9 R10 VBUS VFB T2A C8 D8 R11 Q2 GHHB 3 T2B 2 C9 J3 4 SHHB 6 3 5 2 Q3 C11 C10 GLHB 7 1 8 VCdc T2C R12 R16 EOL SLHB R13 R15 R14 R17 C12 D9 IFB R18 R19 R20 R22 R23 C13 R21 D10 019aaa612 Fig 5. Half-bridge section inductive mode series-resonant topology The circuit diagram of the PFC and half-bridge controller is shown in Figure 6. AUXPFC, FBPFC and GPFC connect to the PFC circuit. The VDD pin receives the start-up current from VCDC (support relamp) or VBUS (no support for relamp). During oscillation states, the VDD pin is supplied by the dV/dt supply generated using the SHHB pin. The signals SHHB, GHHB, GLHB, and SLHB connect to the half-bridge NMOSTs. The boost signal is generated from the VBUS voltage. The dimming input circuit generates the DIM signal. The VFB signal is the lamp voltage feedback signal. IFB is the lamp current feedback signal. EOL is the voltage of the DC blocking capacitor used for lamp end-of-life detection. The start-up resistor R31 can be connected to the output of the bridge rectifier to reduce the power cycle time. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 8 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family AUXPFC D11 R24 VCdc C16 R25 C15 R26 C14 VBUS C17 VBUS C18 R29 R27 D12 R28 FBPFC U1 reserved R30 FBPFC C19 R31 COMPPFC AUXPFC SHHB AUXPFC GPFC GPFC GND C20 C22 D13A VDD C23 D13B GLHB C24 SHHB GLHB SHHB FSHB GHHB 11 10 12 9 13 8 14 7 15 16 UBA2016A 6 5 17 4 18 3 19 2 20 1 BOOST R32 DIM DIM CPT CF CIFB C21 IREF VFB VFB EOL EOL IFB R33 IFB SLHB GHHB C25 C26 C27 C28 SLHB C29 R34 R35 C30 C31 019aaa613 Fig 6. Controller section The dim control input circuit is described in Figure 7. An AC current from node SHHB of the half-bridge circuit is fed through the galvanic isolation transformer T3. The voltage from an external DC voltage source of 0 V to 10 V can be connected to the user side of T3. Due to the current through T3, the transformer voltage is clamped to the input voltage. The clamped voltage is sensed on the ballast side of T3 and filtered. The DIM signal is fed to the controller. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 9 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family J4 4 3 D14 F2 2 1 DN1 C33 C32 R36 T3 4 2 6 1 SHHB D15 Q4 R38 R37 Q5 C34 DIM Q6 C35 R39 R40 reserved R41 019aaa614 Fig 7. Dim control input section 3. Pin-to-pin component selection The functionality of the ballast circuit subblocks is described in Table 2 to Table 4 based on the functions assigned to each pin. Table 2. Symbol Pin Description FBPFC 11 PFC voltage feedback, overvoltage protection, overcurrent protection, open/short protection; see Section 3.12 on page 34 COMPPFC 12 PFC voltage control loop compensation network, input of on-time modulator; see Section 3.13 on page 36 AUXPFC 13 demagnetization detection, THD wave shaping, open pin protection; see Section 3.14 on page 37. GPFC 14 PFC gate drive; see Section 3.15 on page 38 Table 3. AN10958 Application note PFC function pins Half-bridge function pins Symbol Pin Description SLHB 1 preheat current regulation, coil saturation protection; see Section 3.1 on page 11 IFB 2 lamp current feedback input, lamp-on detection, internal lamp current rectifier, lamp overcurrent detection; see Section 3.2 on page 13 EOL 3 lamp end-of-life detection; see Section 3.3 on page 18 VFB 4 lamp voltage feedback, lamp overvoltage detection, open/short protection; see Section 3.4 on page 21 CIFB 6 input of the internal VCO, time constant of the lamp current control loop, ignition frequency ramp down speed after preheat; Section 3.6 on page 26 CF 7 timing capacitor of oscillator; Section 3.7 on page 27 CPT 8 preheat timer, fault timer, open/short protection; see Section 3.8 on page 28 All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 10 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family Table 3. Half-bridge function pins …continued Symbol Pin Description DIM 9 dimming input, reducing the lamp-on-detection threshold; see Section 3.9 on page 29 BOOST 10 lamp current boost input (UBA2016A); see Section 3.10 on page 30 PH/EN 10 preheat frequency setting and enable/disable (UBA2015/UBA2015A); see Section 3.11 on page 33 GLHB 17 low-side half-bridge gate driver; see Section 3.18 on page 43 SHHB 18 hard switching regulation and protection input, ground of high-side driver, source of the dV/dt supply; see Section 3.19 on page 43 FSHB 19 floating supply of the high-side driver; see Section 3.20 on page 43 GHHB 20 high-side half-bridge gate driver; see Section 3.21 on page 43 Table 4. Other function pins Symbol Pin Description IREF 5 IC reference current; see Section 3.5 on page 26 GND 15 IC ground reference; see Section 3.16 on page 39 VDD 16 IC supply, gate drive supply, restart after relamp; see Section 3.17 on page 39 3.1 SLHB pin: preheat current regulation, coil saturation protection Refer to Figure 8.The resistors R13 and R14 in parallel (R13//R14 = RSLHB) sense the half-bridge current. During preheat, the half-bridge controller with a preheat threshold Vth(ph)(SLHB) = 0.5 V regulates the half-bridge current. As a result, VSLHB(peak) = 500 mV. VBUS UBA2016 Q3 GHHB VDD Lres SHHB on GHHB GLHB off 8.5 μA VBUS preheat 480 mV Q2 V(SHHB) GLHB SLHB Rx 0V Ipeak saturation 2.5 V R13 I(Lres) 0A R14 I(R13//R14) t 019aaa616 019aaa615 a. The SLHB pin circuit diagram. Fig 8. b. Half-bridge current and voltage waveforms. The SLHB pin AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 11 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family The saturation protection is always active and it protects the circuit against: • coil saturation • overvoltage of the resonant tank and the lamp The IC has a fixed ratio of five between the preheat level and the saturation voltage level. The internal bias current source of 8.5 A allows the current ratio (saturation/preheat) to be increased by adding resistor Rx in series with the SLHB pin. Equation 1 results the value for resistor Rx: (1) V th ph SLHB I bias SLHB + V th ph SLHB I sat – V th sat SLHB I bias SLHB – V th sat SLHB I ph peak Rx = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------I bias SLHB I sat – I ph peak Vth(ph)(SLHB) = 0.5 V; Vth(sat)(SLHB) = 2.5 V; Ibias(SLHB) = 8.5 A. When Rx is known, Equation 2 calculates the R13 and R14 resistor values: V th ph SLHB – I bias SLHB Rx R 13//14 = ----------------------------------------------------------------------------I bias SLHB + I ph peak on GHHB GLHB off on GHHB GLHB off VBUS VBUS V(SHHB) V(SHHB) 0V 0V I(Lres) 0A I(Lres) 0A I(R13//R14) I(R13//R14) t t 019aaa617 a. Hard switching Fig 9. (2) 019aaa618 b. Coil saturation Simulated current through low-side sense resistor (R13//R14) The hard switching spikes on the SLHB are internally blanked with 300 ns (leading edge blanking) to prevent a false trigger of the coil saturation. During preheat and ignition, the saturation protection increases the HB operating frequency to reduce the HB inductor current. In preheat and ignition state the slow fault timer is used for saturation protection. In burn state, the saturation protection reacts very fast to detect lamp removal or broken lamp conditions. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 12 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.2 IFB pin: lamp current feedback, lamp-on detection, internal lamp current rectifier, overcurrent detection Ballasts that run at the minimum operating frequency do not require a lamp current sense resistor and lamp-on detection. The IFB pin can be left open or shorted to ground. If no lamp-on is detected, the controller sweeps the frequency down. When the minimum switching frequency is reached, the IC assumes that the lamp has ignited. The IC has an internal double-sided rectifier on the IFB pin which has no voltage drop. 3.2.1 Lamp-on detection (LOD) The LOD limits the visible flash when the ballast is switched on while the ballast control input is at a deep dim level. After LOD (also known as ignition detection) is triggered, the IC enters Burn state. The IFB and VFB pins on the IC trigger the LOD. The voltage on the IFB pin must exceed Vth(lod)(IFB) and the voltage on the VFB pin must be < Vth(lod)(VFB). Both pin conditions must apply for a continuous period of td(lod) = 3 ms. The delay is implemented to ensure that sufficient ionization energy is transferred to the lamp. This implementation ensures the ignition of multi-lamp applications while limiting the flash at start-up. ! ' &$* , #$& # ! " #$& DDD (1) See Figure 11. Fig 10. Lamp-on detection delay time The threshold Vth(lod)(IFB) is a function of the voltage on the DIM pin. The relationship between the LOD threshold and the DIM voltage is shown in Figure 11. The Vth(lod)(IFB) signal is filtered using a time constant of approximately 100 s. The threshold is therefore compared to the average double-sided rectified voltage on the IFB pin. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 13 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family Vth(lod)(IFB) (V) 1.12 0.35 0.00 0.5 VDIM (V) 1.27 019aaa619 Fig 11. Lamp on detection threshold on the IFB pin as function of the DIM pin voltage The voltage on the VFB pin must drop < Vth(lod)(VFB) = 1 V to trigger the LOD function. Remark: If controller reaches the minimum operating frequency of (VCIFB = 3 V) and the LOD condition is not met, the controller assumes that the lamps are ignited. In this case, the controller always enters the burn state. 3.2.2 Lamp current feedback Ballasts that require only lamp current control without deep dimming, a single sense resistor is sufficient. Applications that require deep dimming (below 10 %) are advised to use a non-linear sense circuit. The intention of the non-linear circuit is to guarantee a strong feedback signal for low lamp currents. Non-linear sensing has two advantages during deep dimming: • The circuit is less sensitive to tolerances • The circuit is less sensitive to low frequency ripples • The minimum lamp current setting via input the DIM pin is more accurate Place resistor R33 and C29 close to the IC (see Figure 12b). 3.2.3 Overcurrent lamp protection The IC enters Stop state when both of the following conditions are met: • The peak of the absolute voltage at the IFB pin exceeds Vth(ocd)(IFB) • The IC is oscillating at fhigh AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 14 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.0 V HALF-BRIDGE CONTROLLER LAMP-ON DETECTION Ilamp DIM R33 IFB R20 C29 VCO double-sided rectifier UBA2016A CIFB C21 R22 C26 R35 019aaa620 a. Normal application with basic IC Ilamp R33 R20 R18 R22 R19 IFB C29 D10 UBA2016A 019aaa621 b. Deep dimming R18, R19, D10 not mounted. Fig 12. Lamp current sense circuit and the IFB pin Typical values for lamps with nominal current of 300 mA: Figure 12a: R20 = R22 = 2.4 ; R33 = 1.0 k; C29 = 100 pF; R18 = R19 = reserved; D10 = reserved. Figure 12b: R20 = R22 = 18 ; R18 = R19 = 2.7 ; R33 = 1.0 k; C29 = 100 pF; D10 = PMBD7000. 3.2.3.1 Calculations for Figure 12a I lamp nom peak = I lamp nom SQRT 2 = 424 mA (3) After double-sided rectifying, Equation 4 gives the average lamp current. I lamp nom avg = I lamp nom peak 2 = 270 mA AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 (4) © NXP B.V. 2012. All rights reserved. 15 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family The internal regulation voltage Vreg(IFB) = 1.27 V when application does not pull-down the DIM voltage. Equation 5 calculates the value for R20 plus R22. V reg IFB R20 + R22 = ----------------------------------= 4.7 I lamp nom avg (5) Therefore R20 = R22 = 2.35 . 3.2.3.2 Calculations for Figure 12b Equation 6 calculates the parallel resistance value for R18 and R19. V reg IFB – V f avg R R18//R19 = ------------------------------------------- = 1.37 I lamp nom avg (6) The average forward voltage of the diode increases as a function of the current through the diode, the Vf(avg) = Vf 1.5 (based on measurements). The dimming target of the RMS lamp current is 2 % of nominal. Ilamp(dim)(rms) = 6 mA. Equation 7 calculates the average lamp dimming current. 2 I lamp dim avg = I lamp dim rms SQRT 2 --- = 5.4 mA (7) The IFB pin voltage level in deep dimming must be 150 mV or higher. The reason for this requirement is the accuracy of the internal double-sided rectifier. Equation 8 calculates the series resistance value of R20 plus R21. V reg IFB dim R 20 + 22 = ---------------------------------= 28 I lamp dim avg (8) Where Vreg(IFB)(dim) = 150 mV, therefore R20 = R22 = 14 . 3.2.3.3 Lamp at end-of-life and deep dimming sense circuit The IC tries to ignite the broken lamp, until the fault timer expires, while the voltage on VFB regulates the operating frequency. Current flows through the lamp current-sense circuit due to the parasitic capacitances inside the half-bridge transformer because of the high voltage across the resonant circuit. Take care to ensure that the lamp-on detection is not triggered. Therefore the R20 and R22 values in Figure 12b (deep dimming) must not be too high (see Figure 13). AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 16 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family T2 VBUS CBA C10 Q2 A C9 CAC B CBC C Cstray C11 Istray Q3 C12 C12 Vignition RSENSE RSENSE 019aaa622 019aaa623 a. Positions of stray capacitances in the half-bridge transformer b. Simplified model showing the stray current Fig 13. Stray capacitances of a half-bridge transformer for inductive topology Rsense = R20 + R22. The stray capacitance is the combination of all inter-winding capacitances (Equation 9). C stray = C BC C BA + C AC (9) C12 is much larger than Cstray, therefore C12 can be ignored. Equation 10 calculates the stray current. I stray = V ignition 2 f ignition C stray (10) Equation 11 calculates the average stray current. I stray avg = 4 V ignition peak f ignition C stray (11) A design requirement is applied to prevent false LOD triggering in deep dimming non-linear current sense circuits as shown in Equation 12. I stray avg R sense 150 mV (12) which is equal to Equation 13. 4 V ignition peak f ignition C stray R sense 150 mV (13) Some realistic values are: Vignition(peak) = 1.2 kV; fignition = 60 kHz; Cstray = 15 pF → Rsense < 35 . 3.2.3.4 Multiple lamp current sense The lamp current sense circuit for multiple lamps is very similar to the single lamp application; see Figure 14. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 17 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family lamp 1 lamp 1 lamp 2 lamp 2 R R IFB R C R UBA2016A IFB C UBA2016A 019aaa625 019aaa624 a. Lamps in series b. Lamps in parallel Fig 14. Lamp current sense for multiple lamps 3.3 e EOL: lamp end-of-life detection The voltage on the EOL pin is fed to the internal window comparator. The window lower limit equals the FBPFC voltage and the upper limit is equal to twice the FBPFC voltage. Asymmetric aging effects of the lamp (IEC rectifying and asymmetric pulse) can be sensed by sensing the voltage on DC blocking capacitor C12. The sensitivity and DC shift can be adjusted independently due to the internal current source Ibias(EOL) (see Figure 15). DIEC DIEC RIEC RIEC Ilamp C12 VBUS VC12 Ilamp C12 0V 019aaa628 a. Lamp end-of-life IEC test circuit (the diode can be connected in either polarity) RIEC 019aaa629 b. Relationship between DC blocking capacitor voltage and asymmetric power consumption Fig 15. Asymmetrical lamp end-of-life IEC test circuit and DC blocking voltage The power dissipated in the test resistor RIEC must be below the IEC requirement of PEOL(max) = 7.5 W for T5 and PEOL(max) = 5.0 W for T4 lamps. Practical measurement determines RIEC: RIEC is increased until the maximum power is reached. Equation 14 calculates the voltage on C12. VBUS P eol V C12 = --------------- -----------I lamp 2 (14) The voltage on C12 shifts as a function of the power dissipated in RIEC. The maximum EOL power PEOL(max) is an IEC requirement. PEOL(max) for T5 is 7.5 W and for T4 it is 5 W. Currently there are no IEC requirements for T8 lamps. The voltage shift of the DC blocking capacitor due to asymmetrical aging can fit into the IC end-of-life window by the application resistor divider. The resistor divider consists of REOL1 (R6 and R7 in Figure 3 on page 6) and REOL2. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 18 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family Ilamp FBPFC VCdc REOL1 EOL 1 C12 REOL2 HALF-BRIDGE CONTROLLER 16.2 μA 2× R20 R33 R22 IFB C29 UBA2016A 019aaa630 a. Fixed output and dimming down to 10 % Ilamp VCdc REOL1 EOL D9 R17 C25 C12 R21 R23 C13 R33 R20 R22 R18 R19 D10 IFB C29 UBA2016A 019aaa631 b. Deep dimming <10 % Fig 16. The EOL pin application with DC blocking capacitor C12 sensing In deep dimming application, the voltage on the DC blocking capacitor shifts if a DC current through the lamp is used for canceling striation. A compensation circuit (D9, R23, C13, R21) shown in Figure 16b can be used when VC12 rises when dimming is below 10 % of the nominal lamp current. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 19 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.3.1 Calculation of the resistor divider REOL1 and REOL2 See Figure 16a. The voltage at the EOL pin is shown in Equation 15. V C12 R EOL2 – I bias EOL R EOL1 R EOL2 V EOL = ---------------------------------------------------------------------------------------------------------R EOL1 + R EOL2 (15) Where Ibias(EOL) = 16.2 A. The EOL window threshold voltages are: Vth(low)(EOL) = 1 VFBPFC, Vth(high)(EOL) = 2 VFBPFC. Under normal operation, the VFBPFC voltage is 1.27 V as shown in Equation 16. V EOL window range = V th high EOL – V th low EOL = V FBPFC = 1.27 V (16) Equation 17 calculates the EOL window center voltage. V th high EOL + V th low EOL V EOL window center = ----------------------------------------------------------------------- = 1.91 V 2 (17) Equation 18 calculates the required ratio between REOL1 and REOL2. R EOL1 2 P EOL – V EOL window range I lamp --------------- = ---------------------------------------------------------------------------------------------R EOL2 V EOL window range I lamp (18) Where PEOL is the maximum power dissipated asymmetrically. The absolute values for REOL1 and REOL2 center the voltage in the EOL window, calculated with Equation 19 and Equation 20. V EOL window range I lamp VBUS R EOL1 = -----------------------------------------------------------------------------------------------2 – 2 V EOL window center -----------------------------------------------------------------------------------------------V EOL window range I lamp I bias EOL (19) V EOL window range I lamp VBUS R EOL2 = ----------------------------------------------------------------------------------------------------------------------------2 – 2 V EOL window center ----------------------------------------------------------------------------------------------------------------------------V EOL window range I lamp – 2 P EOL I bias EOL Table 5. AN10958 Application note (20) Calculated values for REOL1 and REOL2 for the EOL pin application Lamp VBUS (V) PEOL (W) Ilamp (mA) REOL1 (M) REOL2 (k) T5HE14W; T5HE21W; T5HE28W; T5HE35W 432 170 7.99 176 T5HO24W 300 10.4 411 T5HO39W 340 10.7 485 T5HO49W 260 9.90 338 T5HO54W 460 11.5 711 T5HO80W 555 11.8 896 7.5 All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 20 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family Use 1 % resistors such as the MRS type from Vishay BC Components for the EOL divider. The PFC output voltage must have 1 % accuracy because the voltage on the DC blocking capacitor is 0.5 times the bus voltage. 3.4 VFB pin: lamp voltage feedback, overvoltage detection, open/short protection The advantage of lamp voltage feedback is that it limits voltage stress on the half-bridge components such as NMOST, inductor and capacitors. The lamp voltage feedback signal can be derived from the LC tank voltage. The dedicated voltage feedback pin is advantageous in multilamp applications because the IC regulates on the maximum voltage of both lamps. When a lamp is removed or breaks in burn state, an immediate shutdown is activated when the shutdown threshold Vth(ovextra)(VFB) = 3.35 V is reached. As a result, the excessive voltage is only briefly on the half-bridge resonant node. 3.4.1 Lamp voltage regulation In preheat state and ignition state, when the VFB voltage is > Vth(ov)(VFB) = 2.5 V, the switching frequency is increased (lowering the voltage on the resonant tank) and the fault timer starts. This feature protects the ballast under no lamp conditions. The IC tries again to ignite the lamp. If after the second time the lamp still does not ignite, the IC enters the standby state. 3.4.2 Overvoltage protection In any state, when the VFB voltage is > Vth(ovextra)(VFB) = 3.35 V, the controller enters Stop state immediately. This mechanism prevents excessive component stress when the lamp is removed while the actual switching frequency is below the unloaded resonant frequency. 3.4.3 EOL protection symmetrical lamp aging Fluorescent lamps age over time and as a result the lamp voltage can increase. The VFB voltage is compared with threshold Vth(oveol)(VFB). When the threshold is exceeded, the slow fault timer is started. When designing the VFB circuit, remain below the minimum Vth(oveol)(VFB) value to ensure that the protection is not triggered. A dimmed lamp has a higher lamp voltage than nominal. However, the higher lamp voltage caused by dimming must not trigger the symmetrical EOL protection. Therefore, the threshold for symmetrical EOL detection increases when the DIM pin voltage is lowered. The relation between Vth(oveol)(VFB) and VDIM is shown in Figure 17. When VDIM < 250 mV the symmetrical EOL protection is disabled. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 21 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family aaa-001846 1.6 Vth(oveol)(VFB) 1.2 (1) 0.8 (2) (3) 0.4 0 0 0.5 1.0 1.5 VDIM (1) Maximum value. (2) Typical value. (3) Minimum value. Fig 17. Vth(oveol)(VFB) as a function of VDIM 3.4.4 Open/short-circuit protection When the VFB voltage is < Vth(osp)(VFB) = 80 mV, the switching frequency is increased and the fault timer is started. Ibias(VFB) pulls down the VFB pin when the pin is open. 3.4.5 Circuit diagrams for one and two LC tanks 3.4.5.1 Series resonant VFB circuit Refer to Figure 18. HV capacitor C7 senses the lamp voltage on the resonant node of the LC tank. The current through the HV capacitor C7 is fed through the capacitor C8 and the voltage is divided. The diode clamps the voltage to 600 mV. A 2nd divider made up with resistors R10 and R11 divide the voltage to the appropriate level at the VFB pin. The capacitor C31 at the VFB pin lowers the ripple on the VFB voltage. Do not make C31 too large or else the response time on overvoltage (Vth(ovextra)(VFB) = 3.35 V) is slow. Rbias is used to lift the VFB voltage slightly > Vth(OSP)(VFB) to enable start-up. Typical values for a the VFB pin application are: R10 = 100 k, R11 = 5.6 k, C7 = 100 pF, C8 = 1.5 nF, C31 = 10 nF and D8 = BAS101S. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 22 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family VBUS Cres Lres Cdc Rbias C7 3.35 V R10 VFB HALF-BRIDGE CONTROLLER 2.5 V R13//R14 D8 C8 R11 C31 80 mV 2.6 μA UBA2016A 019aaa635 Fig 18. Typical VFB pin circuit for series resonant topologies 3.4.5.2 Inductive heating VFB circuit In indicative heating topologies, the VFB circuit (with two LC tanks) shown in Figure 19 can be used. The resonance capacitors sense the lamp voltage and no additional HV capacitor is needed. The capacitor C2 in Figure 19 divides the lamp voltage to a lower level. R2 and R3 divided it to a lower level and provide an RC filter with capacitor C3. Cs Cs Lr1b Cdc Lr2b Lr2a Lr1a Cr1 Cr2 Lr1c Lr2c Cs Cs R1 R2 VFB UBA2015/6 C2 D1 R3 C3 aaa-001847 Fig 19. Typical VFB pin application for a topology with two LC tanks and lamp to ground configuration AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 23 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family Functionality of the VFB circuit components: • • • • • • 3.4.5.3 R1: offset for open/short protection Cr1/Cr2: resonance capacitors C2: capacitive divider capacitor D1: diode clamp to ground R2/R3: resistor divider and discharge time of capacitor C2 C3: Filter capacitor Constraints of the VFB circuit Start-up (and all other states): The voltage must be higher than 120 mV to satisfy the open/short protection. Set the voltage using resistor R1. Ignition: The maximum voltage on the resonant tank (lamp voltage) is regulated to 2.5 V on the VFB pin. Normal operation: The voltage on the VFB must remain under 800 mV to satisfy the symmetrical EOL protection. Table 6. VFB conditions Operating state VFB > 120 mV (Vth(osp)(VFB)max) VFB = 2.5 V (Vth(ov)(VFB)typ) VFB < 800 mV (Vth(oveol)(VFB)min) start-up yes yes - preheat yes yes - ignition yes yes - nominal yes yes yes When a large value capacitor for C2 is chosen, it is possible to make a DC shift with the clamping diode. The DC shift can help to find better matching of the voltage levels during ignition and operation. 3.4.5.4 Dimming constraints Make sure that the VFB voltage remains under the overvoltage EOL threshold Vth(oveol)(VFB) under all conditions. The Vth(oveol)(VFB) depends on the DIM pin voltage level as shown in Section 3.4.3. 3.4.5.5 Circuit definition and verification Starting point for the circuit design is that the divider capacitor C2 which must be at least 10x bigger than the Cr1 (+Cr2 if any). To minimize the costs of capacitor C2, keep the voltage < 100 V across the diode. To verify the solution by simulation, the circuit shown in Figure 20 can be used. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 24 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family R1 V2 Vbus/2 Cr1 Cr2 R2 V1 FREQ = 50 kΩ VAMPL = 1000 V C2 D1 VFB R3 C3 I1 DC = 2.6 u aaa-001848 Fig 20. Typical simulation configuration In Figure 20, VAMPL is the LC tank voltage. Check the Ignition state and operating states. During dimming, the lamp voltage increases while dimming and whether the VFB voltage remains under the dynamic Vth(oveol)(VFB) threshold. Cr2 is the resonant capacitor of the 2nd resonant tank; it can be omitted when verifying one LC tank circuits. 3.4.5.6 Calculation of the VFB pin components Equation 21 calculates the value of C8. The value of C7 is fixed C7 = 100 pF. 1 – m arg in 1 – V R ------------------------------------------- 2 V max – VBUS C8 = C7 ----------------------------------------------------------------- 2 V max – VBUS V R 1 – m arg in (21) The time constant = C8 (R10 + R11) determines the value of R10. Where margin = 0.3 and is a constant. Vmax is the worst case ignition voltage. VR is the maximum reverse voltage of the clamp diode. A diode with a VR of 300 V or higher requires sufficient voltage at start-up to satisfy Vth(osp)(VFB). Equation 22 calculates the value of R11. V reg C7 + C8 R11 = 2 R10 ------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------- (22) 2 V max – VBUS C7 V reg 1 – 2 ------------------------------------------------------------- C7 + C8 2 V max – VBUS C7 Capacitor C31 filters noise on the VFB PCB track. C31 must not be too high to enable the IC to react quickly on lamp removal when the switching frequency is near the resonant frequency of the LC tank. A time-constant of 100 ns is advised. The value of C31 is C21 R11 = 100 ns . AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 25 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.5 IREF pin: IC reference current A 33 k resistor (R34) connects the IREF pin to ground reference. 3.6 CIFB pin: input for the internal VCO, time-constant of the lamp current control loop, ignition frequency ramp-down speed after preheat 3.6.1 VCO input When the CIFB pin is 0 V, the half-bridge switching frequency is at fhigh. When CIFB is at Vhigh(CIFB) = 3.0 V, the half-bridge switching frequency is at flow. 3.6.2 Lamp current control The average voltage on the IFB pin controls the half-bridge frequency. If the IFB pin is not used, the switching frequency in Burn state is flow. Since the CIFB pin is the output of the error amplifier, the capacitance on the CIFB pin determines the speed/frequency response of the control loop. VBOOST VDIM VCIFB VBUS freq + 0 V to 1.27 V - error amp G1(s) VCO G2 power stage LC tank + lamp G3 G4(s) Ilamp feedback H 019aaa636 Fig 21. Small signal block diagram of the lamp current control loop Figure 22a shows the transfer of the error amplifier with the CIFB compensation network. This transfer is equal to G1(s) in Figure 21. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 26 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 019aaa638 1 G (%) 10−1 VCO (1) 10−2 UBA2016A (2) CIFB C21 C26 10−3 102 R35 103 104 f (Hz) 019aaa637 a. The CIFB pin application b. Small signal transfer (gain versus frequency) (1) C26, C21 and R35. (2) C26 (C21 and R35 not mounted). Fig 22. Frequency response of error amplifier plus CIFB network Typical values for the CIFB network are: Non-dimmable ballasts: C26 = 100 nF; C21 = reserved; R35 = reserved; Dimmable ballasts: C26 = 3.3 nF; C21 = 100 nF; R35 = 1 k. During deep dimming, the lamp discharge column is close to extinguishing and the time-constant of the lamp is small. The control loop has to be fast enough to prevent the lamp from extinguishing. Therefore, for a dimmable ballast, add C21 and R35 to increase the gain and speed of the control loop. 3.7 CF pin: timing capacitor of oscillator The oscillator frequency is twice the operating frequency of the half-bridge. To guarantee a 50 % duty cycle, the half-bridge operates at half the oscillator frequency. Capacitor C27 sets the frequency range of the half-bridge controller in the internal relaxation oscillator. Equation 23 calculates the value of C27. I cf C27 = --------------------------------------2 f low V th cf (23) Where Icf = 43 A; Vth(cf) = 2.5 V. The maximum switching frequency (fhigh) is a fixed ratio: f high = f low 2.4 . A typical value for C27 is 220 pF, results in an flow of 39 kHz and hence an fhigh of 94 kHz; see Figure 23. If C27 is a ceramic capacitor, use an NP0 or C0G dielectric, for high accuracy and temperature independency. Without lamp current control, use an accurate capacitor to obtain an accurate switching frequency. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 27 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family VCF fosc = 2 × fop = 2 × fhigh fop < fhigh 2.5 V t 0.0 V tph(start) 019aaa639 Fig 23. Voltage on the CF pin A current source charges capacitor C27 until the threshold of 2.5 V is reached then C27 is discharged during 300 ns. The IC regulates the amount of charge current and therefore the switching frequency. 3.8 CPT pin: preheat timer, fault timer, open/short protection The capacitor on the CPT pin sets the preheat and fault time duration. Equation 24 calculates the preheat time relation to CPT capacitor. t ph C30 = ---------------------------CPT cons tan t (24) Where CPTconstant = 10 106. A typical value for C30 is 100 nF which gives a preheat time tto(ph) of 1 s. When C30 is a ceramic capacitor, use an X7R dielectric. The X7R capacitance decreases when a DC voltage is applied, therefore the voltage rating must be 50 V even though a lower voltage is applied. 3.8.1 Preheat timer The preheat timer counts 8 times to charge capacitor C30 to 3.7 V with a current of 2.7 A. The discharge current of 11 A is applied until the voltage on C30 reaches 1.0 V (see Figure 24). The charge and discharge currents are unequal in the preheat state. The preheat-time/fault time ratio can be programmed (between 3.35 and 10.1) using an external resistor as described in the data sheet (Ref. 1). AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 28 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family VCPT 3.7 V 1V 0.7 V t 0V tph 019aaa640 Fig 24. Voltage on the CPT pin during preheat 3.8.1.1 Fault timer The fault timer provides a delay between fault detection and shutdown. The fault time duration is one fifth of the preheat time. The fault timer uses a charge and discharge time of 23.5 A. Since both timers use the same pin, the fault timer takes priority over the preheat timer. The preheat timer restarts after a fault has cleared. 3.8.1.2 Open/short protection When the CPT pin is < Vth(scp)(CPT) = 120 mV, the controller does not sweep the frequency down to the preheat frequency but continues switching at fhigh. This protection prevents endless preheating if a short or open circuit production fault occurs on this pin. When the CPT pin is < Vth(scp)(CPT) while the IC is in any oscillating state, the controller increases the switching frequency to fhigh with a time-constant of approximately 7 ms. The CIFB pin can be shorted to ground in case a shorter time-constant is needed. The open/short protection on the CPT pin allows an (optional) external protection circuit to switch the operating frequency to fhigh. At fhigh the power in the LC tank is minimal and the voltage stress on the half-bridge components is minimal. 3.9 DIM pin: reduces lamp current control set point, reduces the lamp-on-detection threshold 3.9.1 Lamp current regulation The controller regulates the frequency such that the average voltage on the IFB pin during Burn state equals the DC voltage on the DIM pin. The lamp current regulation level is equal to the voltage at the DIM pin. Internally the maximum regulation level is clamped to Vreg(IFB) = 1.27 V. During the start-up cycle (Preheat and Ignition state) the minimum regulation level is clamped to 500 mV. In Normal state, use a minimum level of 150 mV for better accuracy and also to prevent detection of false ignition (lamp-on detection) using the IFB pin. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 29 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.9.1.1 Lamp-on detection The lamp-on detection limits the visible flash when the ballast is switched on while the ballast control input is at a deep dim level. Section 3.2.1 describes how the DIM voltage is used for the lamp-on detection. 3.9.1.2 Chapter 3.9.1.2 Symmetrical aging Dimmable ballast only: the lamp voltage increases when the lamps are dimmed. The symmetrical aging threshold Vth(oveol)(VFB) is increased as function of the DIM voltage to avoid triggering the symmetrical aging function. In the burn state, the VFB pin senses the symmetrical aging. Section 3.4.3 describes the relationship between the DIM voltage and the symmetrical aging threshold. VDD 0.5 V start-up HALF-BRIDGE CONTROLLER 1.27 V Ilamp LOD 26 μA IFB DIM VCO RDIM C28 doublesided rectifier RIFB UBA2016A CIFB RMDL C21 C26 R35 019aaa641 Fig 25. The DIM pin application The DIM pin requires a capacitor C28 of 10 nF to ground. The internal current source Ibias(DIM) charges C28 to the maximum voltage (see Figure 25). If dimming is required, decreasing voltage on the DIM pin reduces the lamp current. A resistor or a voltage source that can sink at least 25 A of current is sufficient. RDIM in Figure 25 is used to set the voltage, RMDL is used to set an accurate minimum dim level. 3.10 BOOST pin: increase lamp current control set point The UBA2016A has a boost function that is intended to shorten the run-up time of the lamp. Boosting is useful for amalgam lamps or outdoor applications (see Figure 26). AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 30 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 019aaa644 Fig 26. Boost function of the lamp current at start-up The lamp current is increased as a function of the current that flows into the BOOST pin. Figure 27b shows the RMS lamp current versus the BOOST pin current; in this case a non-linear lamp current sense circuit Figure 12b is used. During the boost time, the minimum operating frequency flow is reduced to 50 %. The BOOST pin current increases the light output that is more than nominal. Control using the DIM pin does not reduce the minimum operating frequency. When not needed, connect the BOOST pin to ground. Consider using the UBA2015 which has a fixed frequency preheat function instead of the boost function. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 31 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family VBUS UBA2016A R26 C16 R28 R25 D12 R27 BOOST C18 1.4 V Iinternal 019aaa642 a. The BOOST pin components 019aaa643 220 Ilamp(rms) (%) 180 140 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IBOOST (μA) b. The BOOST pin current as a function of lamp current Fig 27. BOOST application Refer to Figure 27a. Typical values for the boost network are: R25 = 10 k; R26 = 2.2 M; R27 = 470 k; R28 = 47 k; C16 = 10 F; C18 = 10 nF; D12 = PMBD914. The boost time is equal to the discharge time of capacitor C16 minus the preheat time; R27 is in the circuit to discharge C16 completely. C18 makes the input less sensitive to noise. The boost voltage must not exceed the limiting value of +2.5 V: Calculate R26, R28. The BOOST pin current must not exceed 100 A when D12 is in forward mode: Calculate R25: 10 k is sufficient in most cases. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 32 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family The half-bridge circuit must support the boost function. Therefore the following two rules apply: V BUS 8 f bst L res SQRT 3 (25) 1 f low bst ----------------------------------------------------------pi SQRT L res Cdc (26) The first rule (Equation 25) ensures that the lamp current can be reached. The second rule (Equation 26) ensures that the half-bridge switching node is not operated in capacitive mode. 3.11 PH/EN: fixed frequency preheat, enable/disable, burn state indication output A resistor from the PH/EN pin to ground (UBA2015 sets the frequency during preheat. The preheat frequency is shown as a function of RPH/EN for CF = 180 pF, 200 pF and 220 pF. 019aac302 104 fsw(ph) (kHz) 88 (1) (2) (3) 72 56 40 35 105 175 245 315 385 RPH/EN (kΩ) (1) CF = 180 pF. (2) CF = 200 pF. (3) CF = 220 pF. Fig 28. Preheat frequency as a function of RPH/EN The controller can be disabled by pulling the PH/EN pin < 250 mV with a transistor. The sink current must be at least IO(clamp)max(PH/EN) = 160 A. The enable/disable feature is useful for power management or additional protection that needs a fast shutdown. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 33 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 250 mV FIXED FREQUENCY PREHEAT PH/EN QPH/EN TTL CONTROLLER VCO RPH/EN 10 kΩ UBA2015/UBA2015A 019aab531 Fig 29. The PH/EN pin application example with enable/disable transistor The PH/EN pin indicates when the burn state is entered. This function can be used to operate a switch in the half-bridge circuit to change the LC tank between preheat and burn state. In preheat and ignition state the output voltage is 1.84 V. In burn state the output voltage is 1.27 V. 3.12 FBPFC pin: PFC voltage feedback, overvoltage protection, overcurrent protection, open/short-circuit protection The brownout functionality is assigned to the COMPPFC pin (see Section 3.13). 3.12.1 PFC voltage feedback The PFC controller is always active when the half-bridge is active. The half-bridge switching frequency is kept at fhigh(HB) until the voltage on the FBPFC pin is > Vth(VPFCok)(FBPFC) = 1.0 V. The voltage on the FBPFC pin connects to the error amplifier of the PFC control loop. The FBPFC pin is connected to the PFC output voltage VBUS and it is compared with an internal voltage of Vreg(FBPFC) = 1.27 V. 3.12.1.1 Overvoltage protection The FBPFC voltage is compared with an internal voltage of Vth(ov)(FBPFC) = 1.39 V, internally, leading edge blanking is applied at the rise of GPFC. If VFBPFC > 1.39 V then, GPFC is immediately set to LOW and kept LOW while VFBPFC is > 1.39 V. 3.12.1.2 Overcurrent protection The PFC current sense is connected to the FBPFC pin using a diode to prevent damage to the PFC NMOST when coil saturation/overcurrent occurs. The negative temperature coefficient of the diode forward voltage (almost) compensates for the maximum flux density (Bmax) of the PFC inductor. Typically a diode such as PMBD914 or 1N4148 is preferred. Do not use a Schottky diode because of its high leakage current properties. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 34 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.12.1.3 Open/Short Protection (OSP) When the FBPFC pin voltage is < Vth(osp)(FBPFC) = 250 mV, the PFC gate drive is disabled. The internal bias current sink of Ibias(FBPFC) = 5 A ensures that VFBPFC is LOW when the pin is left open. D3 OV D4 VAC T1 1.39 V VBUS OK R1 C3 C2 1.0 V R2 PFC CONTROLLER OSP 0.25 V Q1 R4 D7 R6 R7 1.27 V FBPFC R8 PWM 5 μA C6 UBA2016A COMPPFC C17 C19 R29 019aaa645 Fig 30. The FBPFC pin and COMPPFC pin application Typical values for the pin applications: C6 = 47 pF; R8 = 3.3 k. There is a leading-edge blanking of tleb(FBPFC) = 330 ns on the FBPFC pin. t leb = C6 R8 330 ns . To prevent noise being injected into the feedback loop, ensure R8 ≤ 3.3 k. Calculate the sum of R1, R2, and R4 for the correct output voltage using Equation 27: V BUS – V reg FBPFC R1 + R2 + R4 = R8 ----------------------------------------------------------------------------------- V reg FBPFC + I bias FBPFC R8 (27) Use the same type of 1 % resistors for R1, R2, R4 and R8 for an accurate bus voltage and accurate voltage on the DC blocking capacitor. The voltage of the DC blocking capacitor is used for lamp end-of-life detection. Calculate the value of R6 and R7 in parallel for the correct PFC overcurrent protection using Equation 28. 1.27 + 0.6 R 6//7 = -------------------------------------I PFC peak 1.1 3.12.1.4 (28) Layout rules Place capacitor C6 close to transistor Q1 to keep the switching noise local to Q1. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 35 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.13 COMPPFC pin: PFC voltage control loop compensation network, input of on-time modulator A COMPPFC pin application is shown in Figure 30. The typical values are: C19 = 100 nF; C17 = 470 nF; R29 = 82 k. 3.13.1 Compensation network The compensation network has a unity gain in the PFC control loop at 20 Hz. It is a trade-off between Power Factor and transient behavior. A lower bandwidth leads to a better Power Factor but the transient behavior is less. A higher bandwidth leads to a better transient behavior but the Power Factor is less. The components C17 and R29 are added to have maximum phase margin at the unity gain frequency. 3.13.1.1 On-time modulator input The voltage on the COMPPFC pin determines the on-time of the PFC gate drive signal. A low voltage results in a low on-time, a high voltage (equal to Vhigh(COMPPFC) = 3.0 V) results in a maximum on-time of 28 s. 3.13.1.2 Brownout undervoltage If a brownout or undervoltage occurs, the COMPPFC voltage increases and therefore also the on-time. However, when the COMPPFC voltage reaches 3.0 V the on-time does not increase. Furthermore, a signal is sent to the lamp controller to reduce the lamp power by increasing the half-bridge switching frequency. Avoid the 3 V limit during the preheat and ignition states because the controller increases the half-bridge switching frequency. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 36 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.14 AUXPFC pin: demagnetization detection, THD waveshaper, open pin protection D3 D4 VAC T1 VBUS C3 C2 Q1 VDD 5 μA R3 AUXPFC 0.1 V PFC CONTROLLER UBA2016A D11 C14 COMPPFC C17 R5 R24 C15 C19 R29 019aaa646 Fig 31. Basic circuit diagram of the AUXPFC pin Typical values of the application shown in Figure 31: R3 = 10 k; R5 = reserved; R24 = 10 k; D11 = PMBD914; C15 = 100 nF; C14 = 4.7 nF. 3.14.1 PFC auxiliary winding Add a 10 k series resistor (R3) to AUXPFC to protect the IC against a too high voltage, for example during lightning surge events. The number of turns of the auxiliary winding on the PFC coil and the maximum voltage across the PFC inductor can be calculated. The PFC output voltage at overvoltage protection VBUS(ov) determines the maximum voltage across the PFC primary winding as shown in Equation 29. VBUS V th ov FBPFC VBUS ov = -------------------------------------------------------- = VBUS 1.1 V th reg FBPFC (29) It is important to maintain demagnetization detection even at low ringing amplitudes. The voltage at the AUXPFC pin to 8.1 V (absolute maximum rating minus 10 %). Ns VBUS ov Ns VBUS ov Np = -----------------------------------------------= -----------------------------------V AUXPFC max 0.9 0.81 (30) A resistor divider is placed when the number of auxiliary turns are too high. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 37 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.14.1.1 THD wave shaper circuit To reach a THD performance better than 25 % THD, the on-time of the PFC is modulated. With the waveshaper circuit, a THD < 8 % can be reached over a large input voltage range. The modulation increases the on-time when the absolute mains voltage decreases. The AUXPFC signal can be used as a signal source. After peak rectifying and filtering, the signal is injected into the COMPPFC pin capacitor. A short description of the THD waveshaper circuit: • D11 rectifies the negative peak of the VAUXPFC; • R24 and C15 buffer the rectified signal with the correct time-constant • C14 injects the compensation current into the COMPPFC pin. The capacitance determines the amount of compensation The time-constant of R24 and C15 is R24 C15 1 ms . Determine the best value for C14 by measurement. 3.15 GPFC pin: PFC gate driver Place a series resistor in track to the gate of the MOSFET. A typical value for this resistor is 22 . The strong switch-off capability ensures that the external MOSFETs are not switched on due to the current through the gate-drain capacitance of the external MOSFET. VDD ISOURCE RG LS GPFC VDRV CGS CISS ISINK UBA2016A 019aaa647 a. Sink and source currents 019aaa648 b. Gate drive resonant components Fig 32. PFC and half-bridge MOSFET driver diagram The IC MOSFET drivers capability is specified at the most interesting area (where the external MOSFETs are in the linear region). ISOURCE = 90 mA at VGS = 4 V RSINK = 16 at VGS = 2 V The sink resistance of 16 is useful for damping the oscillation that can occur at the NMOST gate when the NMOST is switched off. In Figure 32b, LS is the total inductance (track and source), CISS is the input capacitance of the NMOST as specified in the NMOST data sheet and RG is the total series resistance (of the driver and of the NMOST). Damping factor ξ of this series RGLSCISS circuit is shown in Equation 31. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 38 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family C ISS SQRT ---------- LS = R G -------------------------------------2 (31) ξ must be greater than 0.5 (ideally >1) for sufficient damping. 3.15.1 VDD supply load The major part of the power consumption from supply VDD is the gate drive. The amount of energy needed is linear to the switching frequency. Equation 32 the relationship between gate-charge and PFC switching and VDD supply current. I VDD PFC = Q g PFC f PFC (32) Where Qg(PFC) is the total gate charge as specified in the NMOST data sheet. There is also gate charge needed for the two half-bridge NMOSTs which are not synchronized to PFC switching. The GPFC track contains large current spikes; ensure that next to the GPFC track a low-ohmic return ground is present in the layout. The track width determines the inductance per cm, therefore use wide tracks for gate drive signals in case large NMOSTs are used. The ground track next to the signal track also reduces the inductance per cm. 3.16 GND pin: IC ground reference The GND pin is the reference ground for the IC. Isolate the small signal ground and the large signal (gate drive currents, half-bridge switching currents and PFC switching currents) in the PCB layout. 3.17 VDD pin: IC supply and gate-drive supply The application diagram for the VDD pin is shown in Figure 34. Refer to Figure 33. At power-on, the VDD supply determines when the IC starts oscillating. Initially, the start-up current is charging the VDD capacitor. The VDD voltage rises and passes the threshold Vrst(VDD) = 4.2 V. When the reset level is passed, the gate drive of the low side switch is equal to VDD. This voltage charges the floating supply capacitor via the internal bootstrap diode. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 39 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 1 2 3 8 CPT 0V VVDD GLHB 0V OFF RESET SUPPLY LOW PREHEAT IGNITION BURN Vclamp Vstartup state VVDD Vstop Vrestart Vrst 0V t0 t1 t2 t3 t4 t5 time 019aaa649 (1) Time t0: start charging VDD capacitor. (2) Time t3: start oscillation, VDD takeover supply active. (3) Time t4: preheat timer end. (4) Time t5: lamp-on detected, transition to burn state. Fig 33. Normal start-up behavior At the moment VVDD passes the threshold Vstartup(VDD) = 12.4 V, the gate drivers become active and Preheat state is entered. In Preheat state, capacitor C20 in the VDD takeover supply must deliver the energy to the IC and gate drivers. Capacitor C20 is part of the dV/dt supply that connects to the half-bridge switching node SHHB. On each rising edge of the SHHB node a current is fed through C20 and diode D13b to the buffer capacitor C23. C20 determines the amount of current. When C20 has a high value (> 470 pF), replace D13a by a 14 V Zener diode (1N5244) to keep within the VDD pin voltage limits. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 40 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family PFC driver IDRIVE(PFC) UBA2016A Q1 GPFC VBUS FSHB Istartup GHHB D13 C20 VDD SHHB Q2 SHHB b C22 C24 IDRIVE(HB) a Irestart(VDD) C23 IVDD GLHB Iclamp(VDD) 13.4 V SHHB Q3 OTHER CIRCUITS 019aaa650 Fig 34. The VDD pin application The VDD current consumption depends on the state of the IC. • Stop (standby), Reset and Supply LOW state: The current consumption is 240 Atyp. • Preheat, Ignition and Burn state: Both PFC and HBC are switching. The MOSFET drivers are dominant in current consumption. Initially the VDD current comes from the VDD buffer capacitor C23 but the dV/dt supply circuit takes over. The current consumption (excluding the MOSFET driver) is 1.7 mA (typ). For typical FETs in a 35 W application the VDD current is 10 mA. • Auto-restart state: The current consumption is 1.1 mA (typ). This current overrules the current Istartup and the VDD capacitor is discharged. This state is used for multiple ignition attempts. 3.17.1 dV/dt capacitor The VDD supply current is mostly determined by the NMOST types and internal drivers, a small part (only 1.7 mA) is needed for internal circuitry. Equation 33 calculates capacitor C20. 2 Q g HB + Q g PFC + I VDD f low HB C20 = 1.3 --------------------------------------------------------------------------------------------------VBUS (33) Factor 1.3 is a margin; Qg(HB) and Qg(PFC) are the total gate charges of the HB and PFC NMOST; VBUS is the bus voltage, IVDD = 1.7 mA and flow(HB) = 40 kHz or 20 kHz in case of boost. The calculated value is the minimum value for capacitor C20, a typical value is 330 pF. The margin in the formula depends on the tolerances in the design. Take care not to exceed maximum current Iclamp(VDD) = 25 mA of the internal clamp. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 41 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.17.1.1 Buffer capacitor A buffer capacitor C23 is required at the VDD pin. Current peaks can be localized by placing an SMD ceramic capacitor at position C23, close to the IC. The value of C23 is approximately 100 times larger than the total gate capacitance of all MOSFETs to prevent significant voltage drop during the discharge time of C23. Equation 34 calculates the value of C23. C23 100 2 C iss HB + C iss PFC (34) A typical capacitor for C23 is a 470 nF, 0805, 50 V, X7R ceramic type. 3.17.1.2 Start-up bleeder resistor This resistor connects to the PFC output bus voltage or the Double-Sided Rectified (DSR) mains. The bus capacitor holds the bus voltage and is only slowly discharged by the bleeder resistor, so DSR mains connection is preferred. The DSR mains connection results in a shorter off-time in a power-on-off-on cycle. The start-up current must be sufficient to supply the Istandby(VDD) = 240 A. The start-up current must be lower than Irestart(VDD)min = 850 A otherwise the IC cannot leave the Auto-restart state. Equation 35 calculates the start-up current. I startup = 1.2 I s tan dby VDD (35) The ballast mains start voltage Vac(start) must be < Vac(min) RMS as shown in Equation 36. V ac start = 0.9 V ac min (36) The start-up bleeder resistor R31 determines the start-up current (Istartup). SQRT 2 V ac start R31 = --------------------------------------------------I startup AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 (37) © NXP B.V. 2012. All rights reserved. 42 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 3.18 GLHB pin: Low-side half-bridge gate-driver The application for this pin is identical to the GPFC pin (see Section 3.15 on page 38). The GLHB is 12 V in standby state to pre-charge the floating supply capacitor on the FSHB pin. Note this when designing a ballast that must detect the hot-side filament of the lamp. Connect the gate of the lower half-bridge MOSFET to the GLHB pin using a small series resistor to prevent oscillation caused by parasitics. Oscillations increase stress on the MOSFETs. Do not use a too high resistor value to prevent switching the MOSFET on via its Miller capacitance. 3.19 SHHB pin: hard switching, capacitive mode, ground of high-side driver, source of the dV/dt supply In normal operation, the half-bridge is Zero-Voltage-Switching (ZVS), which means that the SHHB circuit node has commuted before the NMOST switches on. The SHHB node capacitance is charged or discharged by the current of the half-bridge inductance; the impedance of the half-bridge circuit is “inductive”. However, at low operating frequencies (overpower) or sudden removal/damage of the load (lamp) the impedance of the half-bridge circuit can become capacitive. Capacitive means that there is no commutation current to charge and discharge de SHHB node. 3.19.1 Hard switching ZVS is assumed if the voltage step on the SHHB node is below 30 V. When the voltage step on the SHHB node is above 100 V then hard switching is assumed. 3.19.2 Capacitive mode Capacitive mode protection is triggered when the voltage rise during the non-overlap time of the low-to-high transition of the SHHB node remains under Vth(cm)(SHHB) = 30 V/s. If the slope of the voltage rise is > 30 V/s, then hard switching or ZVS can be assumed. 3.20 FSHB pin: supply for high-side driver Connect the FSHB pin to the SHHB pin using capacitor C24. The capacitor must hold the charge for the internal high-side driver. The supply structure is shown in Figure 34 on page 41. When SHHB is switched to GND current flows via the bootstrap internal diode and high-voltage switch into C24. The high-side driver is supplied from this capacitor when SHHB is above GND. The voltage drop across the internal diode and high-voltage switch is VFd(bs) = 1.5 V. A typical value for C24 is 100 nF which is sufficient for most applications. 3.21 GHHB pin: High-side half-bridge gate driver The application for this pin is identical to the GPFC pin (see Section 3.15 on page 38). Connect the gate of the higher half-bridge MOSFET to the GHHB pin use a small series resistor to prevent oscillation caused by parasitics. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 43 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 4. Application description 4.1 Power supply The power supply to the IC includes several functions: • • • • Clamping by the internal clamping diode Restart internal current source Supply of the IC drivers function Supply of the IC controller function blocks 4.1.1 IC supply structure overview The VDD pin is the power supply pin. Internally the supply pin is clamped to 13.4 V by the integrated clamp and excessive VDD current (Iclamp(VDD)) is removed. The 13.4 V is used for the internal circuitry and for the integrated MOSFET drivers. An integrated bootstrap diode supplies the GHHB driver. The VDD pin connects to an external buffer capacitor which can be charged from one of several sources: • • • • Charge current Istartup from the bus voltage A dV/dt supply connected to the half-bridge Auxiliary supply from a winding on the half-bridge transformer External DC supply from a standby supply 4.1.2 Start-up It is possible to restart after a relamp action without a ballast power cycle of the ballast when the start-up current is fed through the lamp filament at restart. 4.1.3 Restart To provide multiple ignition attempts, the Auto-restart state is implemented. In the auto-restart state, the IC is not oscillating and there is an extra current (Irestart(VDD) = 1.1 mA) drawn from VDD. When Irestart(VDD) is larger than Istartup, a restart is triggered when the VDD < Vrestart(VDD) = 6.2 V. The restart timing also depends on C23. 4.1.4 Stop The IC stops operating when the VDD voltage < Vstop(VDD) to prevent unreliable switching of the half-bridge and PFC circuit. The IC enters Supply-low state. 4.2 Choice of the VBUS voltage In order for the PFC step-up converter to work correctly, the bus voltage must be higher than the maximum input voltage. V BUS 1.125 2 V ac max (38) At the lowest HB switching frequency the bus voltage must be sufficient to reach the required lamp current with an HB inductance. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 44 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family V BUS 3 8 f hb min L hb res I lamp max (39) At the nominal HB switching frequency, the bus voltage must be sufficiently high to support the required lamp voltage. V lamp nom pi V BUS ------------------------------------2 (40) Equation 38,Equation 39 and Equation 40 provide the minimum value requirements for VBUS. 4.3 PFC stage design The toff(low) parameter limits the maximum switching frequency fhigh(PFC). The minimum switching frequency flow(PFC) is a design parameter. Keep flow(PFC) above the audible range for humans and animals (30 kHz) during normal operation. Normal operating voltage range: Vac(rms)(min) to Vac(rms)(max). Nominal power: PF > 0.9 and flow(PFC) > 30 kHz. The inductance LPFC can be calculated for a certain flow(PFC) as shown in Equation 41. 2 V ac rms max VBUS – 2 V ac rms max L PFC = ---------------------------------------------------------------------------------------------------------------P lamp 2 f low PFC ------------- V BUS (41) Remark: If the boost function is used over the complete input voltage range, the Plamp must be the maximum lamp power during boost. Equation 42 shows the calculation of the maximum peak current Ipk(max)(PFC) of the PFC inductor operating in critical conduction mode. I pk max PFC P lamp 2 2 ------------ = -----------------------------------V ac rms min (42) Application requirements: Efficiency = 0.9; Plamp = 49 W; Vac(rms)(min) = 180 V to give: I pk max PFC = 856 mA Valley-detection needs additional ringing time within every switching-cycle. The ringing time adds short periods while no power is transferred to the PFC output. The PFC controller compensates for the ringing with a slightly higher peak current. A rule of thumb is that the peak current in a boundary condition mode, PFC with valley skipping is a maximum of 10 % higher than the calculated peak current in boundary conduction mode as shown in Equation 43. I LPFC sat = 1.1 I pk max PFC (43) The RMS current in the PFC inductor. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 45 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family P lamp I LPFC rms = 2 ----------------------------------------------------------SQRT 3 V ac min (44) Once the inductance LPFC and saturation current Ipk(max)(PFC) are known, the PFC inductor can be designed. The design requirements must include the following: • • • • • Inductance Saturation current at maximum operating temperature Maximum RMS current to determine the temperature increase Switching node close to core for low EMI Winding ratio primary: auxiliary The winding ratio calculation is described in Section 3.14 on page 37 and shown as: Np Ns = 0.11 V BUS . The low frequency output voltage peak-to-peak ripple: P lamp V BUS pk – pk = --------------------------------------------------------------2 f ac V BUS C BUS (45) Where VBUS(pk-pk) is chosen to be from 10 % to 15 % of VBUS. Once the ripple currents are measured in the application for certain capacitor values, the capacitor manufacturer can help support life-time calculations. Suggested capacitor series for ballast applications are: Rubycon BX series, Nippon KXG and Panasonic EB type A. 4.4 Half-bridge circuit The basic half-bridge circuit consists of an LC tank. Before the lamp is ignited, the LC tank is not damped and the voltage across the lamp strongly depends on the switching frequency. Electrode heating is applied while the lamp voltage is below the ignition voltage and the switching frequency is above the resonant frequency. After preheating, the lamp is ignited by sweeping the switching frequency down towards the resonant frequency. After ignition (Burn state), the lamp acts as a resistive load on the LC tank. The inductor limits the current though the lamp. There are several topologies for heating the lamp electrodes. The conventional and inductive heating is addressed in the following sections. 4.4.1 Conventional heating See Figure 35. In Preheat state, the half-bridge current flows through CDC, Cres and the electrodes of the lamp (except a small amount which flows through C electrode). Once the lamp is ignited, the half-bridge current also flows through the lamp and the resonant tank (Lres Cres) is damped. This type of circuit is used when lamp current control is not required. The half-bridge controller controls the switching frequency. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 46 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family VBUS Celectrode GHHB VDD Lres SHHB Cres 8.5 μA OCpreheat 480 mV HALF-BRIDGE CONTROLLER GLHB SLHB Celectrode saturation 2.5 V RSLHB Cdc UBA2016A 019aaa656 Lres: limits the lamp current in normal operation. Cres: generates the ignition voltage. Celectrode: reduces the electrode current in nominal operation. RSLHB: limits the half-bridge current during preheat and sets the saturation current. Fig 35. The SLHB pin and conventional heating 4.4.2 Inductive mode heating See Figure 36. In Preheat state, the half-bridge current flows through Lres and the electrodes of the lamp (no current flows through CDC). Once the lamp is ignited, the half-bridge current also flows through the lamp and the resonant tank (LresCres) is damped. The current though the CDC capacitor is equal to the lamp current, as a result the lamp current can easily be measured. This type of circuit is used if lamp current control is required, such as dimming. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 47 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family VBUS Lsec Celectrode Lsec Celectrode GHHB VDD Lres SHHB 8.5 μA OCpreheat 480 mV GLHB HALF-BRIDGE CONTROLLER SLHB saturation 2.5 V RSLHB Cres Cdc UBA2016A 019aaa659 Lres: inductor coupled to Lsec, limits the lamp current in normal operation. Cres: generates the ignition voltage. Celectrode: reduces the electrode current in nominal operation. Lsec: inductor coupled to Lres, determines the amount of electrode current. RSLHB: limits the half-bridge current during preheat and sets the saturation current. Fig 36. The SLHB pin and inductive heating 4.4.3 Half-bridge current control Saturation regulation level is a fixed ratio (5) to the preheat regulation level. The saturation level must support worst case (cold and old lamp) ignition voltages. If the default application (factor 5) is selected, the preheat current through the half-bridge is: Iworstcase(ignition) < 5 Iph; see Figure 37. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 48 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family coil saturation saturation threshold half-bridge current factor 5 preheat threshold extended by non-linear SLHB pin application f 019aaa660 Fig 37. Relationship between coil saturation and preheat current 4.5 Layout guide Figure 38 is an application example of a dual-layer PCB where the component-side layer tracks are Gray and the soldering-side tracks are Red, Blue and Cyan. The Blue track is the ground plane, a part of which is used as a small signal ground. This small signal ground is highlighted in Cyan. This ground is used for the components listed after Figure 38 to minimize the pickup of noise in case of deep dimming and ignition. Route the IFB track next to a ground plane or track for this reason. 019aac303 Fig 38. Top view of dual-layer PCB for an application example using UBA2016A in an SO20 package A separate small signal ground is recommended for the following: • • • • AN10958 Application note Pin 2, IFB: C19 Pin 3, EOL: C21 Pin 4, VFB: C22 Pin 5, IREF: R21 All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 49 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family • • • • • Pin 6, CIFB: R22, C24 Pin 7, CF: C25 Pin 8, CPT: C26 Pin 9, DIM: C30 Pin 10, BOOST, C30 Figure 39 is an example of an application of a single-layer PCB whose tracks are shown Red, Blue and Cyan. The Blue track is the ground plane, a part of which is used as a small signal ground. The small signal ground is highlighted in Cyan and is used for the following components to minimize the pickup of noise in case of ignition. IFB is connected to ground because the example is a non-dimmable application. 019aac304 Fig 39. Top view of a single-layer PCB for an application example using UBA2015 in a DIP20 package A separate small signal ground is recommended for: • • • • • • • • • AN10958 Application note Pin 3, EOL: C15 Pin 4, VFB: C14 Pin 5, IREF: R10 Pin 6, CIFB: C17 Pin 7, CF: C13 Pin 8, CPT: C16 Pin 10, PH/EN, R11 Pin 15, GND Pin 16, VDD: C7 All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 50 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 4.6 Tips and tricks 4.6.1 PFC disable The PFC controller can be disabled using the options shown in Table 7. Table 7. PFC disable options Shows the options for disabling the PFC controller for experimental purposes. Pin connection PFC mode PFC behavior AUXPFC COMPPFC FBPFC Open FBPFC COMPPFC disabled FBPFC regulates to approximate 1.1 V, disabled protection: brownout, FBPFC, OSP, FBPFC, overvoltage, EOL window changes because FBPFC voltage is lower Open GND 1.27 V disabled FBPFC must be set externally to 1.27 V from bus voltage for normal EOL window, disabled protection: brownout, FBPFC, OSP, FBPFC, overvoltage, EOL window does not change because FBPFC is set to 1.27 V If COMPFC and FBPFC are interconnected, then the FBPFC voltage regulates to 1.1 V. As a result the EOL pin thresholds change, the EOL bias current is also slight different at VEOL = 1.65 V. Table 8 the new values are shown. Table 8. EOL characteristics Vfb(PFC) = 1.1 V Symbol Parameter Conditions Vth(low)EOL low threshold voltage on pin EOL Vth(high)EOL high threshold voltage on pin EOL Ibias(EOL) bias current on pin EOL Min Typ Max Unit 1 1.1 1.2 V 2 VEOL = 1.65 V 15.4 2.25 2.5 V 16.2 17 A As the FBPFC/COMPFC node has a high–impedance, it could pick up noise. Therefore it connect a 10 nF to GND. A typical application is shown in Figure 40. SLHB SLHB IFB IFB BOL BOL VFB VFB 33 kΩ IREF 150 nF 22 kΩ 200 pF CF 68 nF DIM 68 kΩ CIFB CPT DIM FFPRHT 20 1 2 19 3 18 17 4 16 5 UBA2015AT 6 15 7 14 8 13 9 12 10 11 22 Ω GHHB FSHB GHHB 100 nF SHHB GLHB SHHB 22 Ω GLHB VDD VDD GND GPFC AUXPFC COMPFC FBPFC 10 nF aaa-001849 Fig 40. Typical PFC disabled application AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 51 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 4.7 Power-on of new ballast design 4.7.1 Test 1: check for short-circuits Apply voltage to the VDD pin via 330 resistor and 20 V laboratory supply. Start-up the supply from 0 V and monitor the current and voltage on the VDD pin. The VDD voltage clamps at about 13 V to 14 V. Do not increase VDD above 14 V or permanent damage occurs. 4.7.2 Test 2: check if oscillation stage is reached Switch VDD supply to 0 V. Apply 1.27 V to the FBPFC pin to enable switching of the MOSFETs. Increase VDD until clamping occurs, when using 330 in series, the laboratory supply can be increased to less than 20 V while keeping the internal clamp within specification. The gate drive signals (PFC and half-bridge) show some activity when the VDD passes the start-up threshold. 4.7.3 Test 3: check half-bridge functionality Switch VDD and FBPFC to 0 V. Connect diode to the CPT pin and connect its cathode to ground, to disable the preheat and fault timer. Apply 1.27 V to the FBPFC pin and 12.9 V to the VDD pin. Connect a 400 V laboratory supply to the bus capacitor and set the current limit to 200 mA. Slowly increase the bus voltage from 0 V to between 20 V and 30 V, and monitor the laboratory supply current. Monitor the bus voltage (PFC output voltage) and the source high-side of the half-bridge. Monitor the voltage across the resonant capacitor: the average voltage must be VBUS / 2. 4.7.4 Test 3: check half-bridge functionality Remove VDD, FBPFC and bus laboratory supply. Remove diode from the CPT pin. Connect 400 V, DC laboratory supply to the AC input, and set the current limit to 200 mA. Slowly increase the laboratory supply voltage from 0 V to between 20 V and 30 V, and monitor the laboratory supply current and the VDD voltage. Check if PFC starts regulating if the FBPFC voltage > 1.0 V. 4.7.5 VFB disable Connect a laboratory supply of 500 mV to the VFB pin. Make sure that the lamps are inserted because high voltage can occur in the LC tank. AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 52 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 4.7.6 EOL disable Connect a laboratory supply of 1.9 V to the EOL pin. 5. Abbreviations Table 9. Abbreviations Acronym Description EMI ElectroMagnetic Interference MOSFET Metal Oxide Semiconductor Field Effect Transistor NMOST N-channel Metal Oxide Semiconductor Transistor SMD Surface-Mounted Device VCO Voltage-Controlled Oscillator 6. References AN10958 Application note [1] UBA2016A/15/15A - 600 V fluorescent lamp driver with PFC, linear dimming and [2] UM10359 - UBA2016AT demo board 1 × 28 W dim and boost user manual [3] UM10466 - UBA2015P reference design 2 × 35 W T5 non-dimmable 230 V(AC) user manual. [4] UM10486 - UBA2015P reference design 2 × 35 W T5 non-dimmable 120 V (AC) user manual. [5] UM10438 - UBA2015AP evaluation board 1 × 35 W T5 dimmable 120 V (AC) user manual. [6] UM10440 - UBA2015AT reference design 2 × 35 W T5 dimmable 230 V (AC) user manual. [7] UM10513 - UBA2015AT reference design 2 × 35 W T5 dimmable 120 V (AC) user manual. All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 53 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 7. Legal information 7.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 7.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN10958 Application note design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 7.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 54 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 8. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 General IC description . . . . . . . . . . . . . . . . . . . 3 1.2 Basic electronic ballast circuit. . . . . . . . . . . . . . 3 1.2.1 Power factor correction. . . . . . . . . . . . . . . . . . . 4 1.2.2 Inductive heating half-bridge and ballast . . . . . 4 1.2.3 IC family overview . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3.1 Preheat operation . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3.2 Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3.3 Dim function . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Basic circuit description . . . . . . . . . . . . . . . . . . 5 3 Pin-to-pin component selection . . . . . . . . . . . 10 3.1 SLHB pin: preheat current regulation, coil saturation protection . . . . . . . . . . . . . . . . . . . . 11 3.2 IFB pin: lamp current feedback, lamp-on detection, internal lamp current rectifier, overcurrent detection . . . . . . . . . . . . . . . . . . . 13 3.2.1 Lamp-on detection (LOD) . . . . . . . . . . . . . . . . 13 3.2.2 Lamp current feedback . . . . . . . . . . . . . . . . . . 14 3.2.3 Overcurrent lamp protection . . . . . . . . . . . . . . 14 3.2.3.1 Calculations for Figure 12a. . . . . . . . . . . . . . . 15 3.2.3.2 Calculations for Figure 12b. . . . . . . . . . . . . . . 16 3.2.3.3 Lamp at end-of-life and deep dimming sense circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.3.4 Multiple lamp current sense . . . . . . . . . . . . . . 17 3.3 e EOL: lamp end-of-life detection . . . . . . . . . . 18 3.3.1 Calculation of the resistor divider REOL1 and REOL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 VFB pin: lamp voltage feedback, overvoltage detection, open/short protection . . . . . . . . . . . 21 3.4.1 Lamp voltage regulation . . . . . . . . . . . . . . . . . 21 3.4.2 Overvoltage protection . . . . . . . . . . . . . . . . . . 21 3.4.3 EOL protection symmetrical lamp aging . . . . . 21 3.4.4 Open/short-circuit protection . . . . . . . . . . . . . 22 3.4.5 Circuit diagrams for one and two LC tanks. . . 22 3.4.5.1 Series resonant VFB circuit . . . . . . . . . . . . . . 22 3.4.5.2 Inductive heating VFB circuit . . . . . . . . . . . . . 23 3.4.5.3 Constraints of the VFB circuit . . . . . . . . . . . . . 24 3.4.5.4 Dimming constraints . . . . . . . . . . . . . . . . . . . . 24 3.4.5.5 Circuit definition and verification . . . . . . . . . . . 24 3.4.5.6 Calculation of the VFB pin components . . . . . 25 3.5 IREF pin: IC reference current . . . . . . . . . . . . 26 3.6 CIFB pin: input for the internal VCO, time-constant of the lamp current control loop, ignitionfrequency ramp-down speed after preheat. . . . . . . . . . . . . . . . . . . . . 26 3.6.1 VCO input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6.2 Lamp current control. . . . . . . . . . . . . . . . . . . . 26 3.7 3.8 3.8.1 3.8.1.1 3.8.1.2 3.9 3.9.1 3.9.1.1 3.9.1.2 3.10 3.11 3.12 3.12.1 3.12.1.1 3.12.1.2 3.12.1.3 3.12.1.4 3.13 3.13.1 3.13.1.1 3.13.1.2 3.14 3.14.1 3.14.1.1 3.15 3.15.1 3.16 3.17 3.17.1 3.17.1.1 3.17.1.2 3.18 3.19 3.19.1 3.19.2 3.20 3.21 CF pin: timing capacitor of oscillator . . . . . . . 27 CPT pin: preheat timer, fault timer, open/short protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Preheat timer . . . . . . . . . . . . . . . . . . . . . . . . . 28 Fault timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Open/short protection . . . . . . . . . . . . . . . . . . 29 DIM pin: reduces lamp current control set point, reduces the lamp-on-detection threshold. . . . 29 Lamp current regulation . . . . . . . . . . . . . . . . . 29 Lamp-on detection . . . . . . . . . . . . . . . . . . . . . 30 Chapter 3.9.1.2 Symmetrical aging . . . . . . . . 30 BOOST pin: increase lamp current control set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PH/EN: fixed frequency preheat, enable/disable, burn state indication output . . . . . . . . . . . . . . 33 FBPFC pin: PFC voltage feedback, overvoltage protection, overcurrent protection, open/short-circuit protection. . . . . . . . . . . . . . 34 PFC voltage feedback . . . . . . . . . . . . . . . . . . 34 Overvoltage protection . . . . . . . . . . . . . . . . . . 34 Overcurrent protection . . . . . . . . . . . . . . . . . . 34 Open/Short Protection (OSP) . . . . . . . . . . . . 35 Layout rules . . . . . . . . . . . . . . . . . . . . . . . . . . 35 COMPPFC pin: PFC voltage control loop compensation network, input of on-time modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Compensation network . . . . . . . . . . . . . . . . . 36 On-time modulator input . . . . . . . . . . . . . . . . 36 Brownout undervoltage . . . . . . . . . . . . . . . . . 36 AUXPFC pin: demagnetization detection, THD waveshaper, open pin protection. . . . . . 37 PFC auxiliary winding . . . . . . . . . . . . . . . . . . 37 THD wave shaper circuit . . . . . . . . . . . . . . . . 38 GPFC pin: PFC gate driver . . . . . . . . . . . . . . 38 VDD supply load . . . . . . . . . . . . . . . . . . . . . . 39 GND pin: IC ground reference . . . . . . . . . . . . 39 VDD pin: IC supply and gate-drive supply . . . 39 dV/dt capacitor . . . . . . . . . . . . . . . . . . . . . . . . 41 Buffer capacitor . . . . . . . . . . . . . . . . . . . . . . . 42 Start-up bleeder resistor. . . . . . . . . . . . . . . . . 42 GLHB pin: Low-side half-bridge gate-driver. . 43 SHHB pin: hard switching, capacitive mode, ground of high-side driver, source of the dV/dt supply . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Hard switching . . . . . . . . . . . . . . . . . . . . . . . . 43 Capacitive mode . . . . . . . . . . . . . . . . . . . . . . 43 FSHB pin: supply for high-side driver . . . . . . 43 GHHB pin: High-side half-bridge gate driver . 43 continued >> AN10958 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 August 2012 © NXP B.V. 2012. All rights reserved. 55 of 56 AN10958 NXP Semiconductors Fluorescent lamp driver with PFC using the UBA2015/16 family 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.5 4.6 4.6.1 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 5 6 7 7.1 7.2 7.3 8 Application description . . . . . . . . . . . . . . . . . . Power supply . . . . . . . . . . . . . . . . . . . . . . . . . IC supply structure overview. . . . . . . . . . . . . . Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Choice of the VBUS voltage . . . . . . . . . . . . . . PFC stage design . . . . . . . . . . . . . . . . . . . . . . Half-bridge circuit . . . . . . . . . . . . . . . . . . . . . . Conventional heating . . . . . . . . . . . . . . . . . . . Inductive mode heating . . . . . . . . . . . . . . . . . Half-bridge current control . . . . . . . . . . . . . . . Layout guide . . . . . . . . . . . . . . . . . . . . . . . . . . Tips and tricks. . . . . . . . . . . . . . . . . . . . . . . . . PFC disable . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on of new ballast design . . . . . . . . . . . Test 1: check for short-circuits . . . . . . . . . . . . Test 2: check if oscillation stage is reached . . Test 3: check half-bridge functionality. . . . . . . Test 3: check half-bridge functionality. . . . . . . VFB disable . . . . . . . . . . . . . . . . . . . . . . . . . . EOL disable . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 44 44 44 44 44 45 46 46 47 48 49 51 51 52 52 52 52 52 52 53 53 53 54 54 54 54 55 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 August 2012 Document identifier: AN10958