Cypress CY7C346B-25JCJI 128-macrocell max epld Datasheet

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CY7C346B
128-Macrocell MAX® EPLD
Features
The 128 macrocells in the CY7C346B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
• 128 macrocells in eight logic array blocks (LABs)
• 20 dedicated inputs, up to 64 bidirectional I/O pins
Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the
chip.
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
Functional Description
The CY7C346B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
The speed and density of the CY7C346B allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346B allows the replacement of over
50 TTL CY7C346B. By replacing large amounts of logic, the
CY7C346B reduces board space, part count, and increases
system reliability.
Logic Block Diagram
. 1 (C7) [16]
. 78 (A10) [9]
. 79 (B9) [10]
80 (A9) [11]
. 83 (A8) [14]
. 84 (B7) [15]
. 2 (A7) [17]
. 5 (C6) [20]
. 6 (A5) [21]
. 7 (B5) [22]
INPUT [59]
INPUT [60]
INPUT [61]
INPUT [64]
INPUT [65]
INPUT [66]
INPUT [67]
INPUT [70]
INPUT [71]
INPUT [72]
. INPUT/CLK
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
(N4)
(M5)
(N5)
(N6)
(M7)
(L7)
(N7)
(L8)
(N9)
(M9)
.
.
.
.
.
.
.
.
.
.
36
37
38
41
42
43
44
47
48
49
SYSTEM CLOCK
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
LAB A
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
1
2
3
4
5
6
7
8
MACROCELL 121–128
MACROCELL 9–16
14 (A4)
15 (B4)
16 (A3)
17 (A2)
18 (B3)
21 (A1)
NC (B2)
NC (B1)
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
LAB B
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
17
18
19
20
21
22
23
24
MACROCELL 25–32
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2) [40]
LAB C
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
LAB F
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86–96
33
34
35
36
37
38
39
40
LAB D
(G12) NC
(H13) NC
(J13) 71
(J12) 70
(K13) 69
(K12) 68
(L13) 67
(L12) 64
[80]
[79]
[78]
[77]
[76]
[75]
[74]
[73]
(M13)
(M12)
(N13)
(M11)
(N12)
(N11)
(M10)
(N10)
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
(M4) NC
(N3) NC
(M3) 55
(N2) 54
(M2) 53
(N1) 52
(L2) 51
(M1) 50
NC
NC
63
60
59
58
57
56
LAB E
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
49
50
51
52
53
54
55
56
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
[18, 19, 43, 44, 68, 69, 93, 94]
VCC
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6)
[12, 13, 37, 38, 62, 63, 87, 88]
GND
•
72
71
70
69
68
67
66
65
MACROCELL 73– 80
MACROCELL 57– 64
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8)
Cypress Semiconductor Corporation
Document #: 38-03037 Rev. *C
[90]
[89]
[86]
[85]
[84]
[83]
[82]
[81]
MACROCELL 105–112
P
I
A
MACROCELL 41–48
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
3901 North First Street
() – PERTAIN TO 100-PIN PGA PACKAGE
[ ] – PERTAIN TO 100-PIN PQFP PACKAGE
•
San Jose, CA 95134
•
408-943-2600
Revised April 9, 2004
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CY7C346B
Selection Guide
7C346B-25
7C346B-35
Unit
25
35
ns
Maximum Access Time
Pin Configurations
11 10 9 8 7 6
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
GND
GND
PGA
Bottom View
INPUT
INPUT
INPUT/CLK
INPUT
INPUT
V
CC
V
CC
INPUT
INPUT
I/O
I/O
I/O
I/O
PLCC/CLCC
Top View
5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
I/O
I/O
12
13
73
I/O
I/O
I/O
14
15
72
I/O
I/O
I/O
16
I/O
I/O
GND
17
18
19
69
GND
20
21
66
65
22
I/O
I/O
VCC
23
VCC
I/O
24
25
26
I/O
71
70
68
INP GND INP VCC INP
I/O
I/O
I/O
I/O
L
I/O
I/O
I/O
I/O
K
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND INP
I/O GND GND
61
GND
I/O
E
I/O
I/O
D
I/O
I/O
I/O
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O
I/O
I/O
I/O
I/O
F
32
INPUT
I/O
I/O
GND
I/O
INPUT
I/O
63
62
56
INPUT
V
CC
V
CC
INPUT
I/O
I/O
55
INPUT
M
I/O
31
INPUT
I/O
G
30
INPUT
I/O
64
29
INPUT
GND
GND
I/O
I/O
I/O
I/O
INPUT
I/O
VCC VCC
I/O
I/O
INP INP INP VCC INP
H
58
57
INPUT
INP
VCC
I/O
27
I/O
I/O
I/O
I/O
I/O
I/O
Document #: 38-03037 Rev. *C
I/O
J
60
59
28
I/O
I/O
I/O
I/O
VCC
67
7C346B
I/O
N
I/O
I/O
I/O
INP
GND GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C
I/O
I/O
I/O
I/O
B
I/O
I/O
I/O
I/O
INP VCC INP GND INP
A
I/O
I/O
I/O
I/O
INP VCC INP
1
2
3
4
7C346B
INP
5
6
INP
GND
/CLK
7
I/O
I/O
I/O
I/O
INP INP INP
I/O
I/O
I/O
9
11
12
13
8
10
Page 2 of 15
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CY7C346B
Pin Configurations (continued)
87 86 85 84 83
I/O
I/O
I/O
I/O
I/O
I/O
GND
100 99 98 97 96 95 94 93 92 91 90 89 88
GND
I/O
I/O
I/O
CC
I/O
V
I/O
VCC
I/O
I/O
I/O
I/O
I/O
PQFP
Top View
82 81
I/O
I/O
1
I/O
2
80
79
I/O
I/O
3
78
I/O
I/O
4
I/O
I/O
5
77
76
I/O
6
75
I/O
I/O
7
74
I/O
I/O
8
73
I/O
INPUT
9
72
INPUT
INPUT
INPUT
VCC
INPUT
10
71
INPUT
11
70
GND
12
GND
13
69
68
INPUT
CY7C346B
I/O
VCC
14
67
INPUT
INPUT
15
66
INPUT
INPUT/CLK
16
65
INPUT
INPUT
17
64
INPUT
VCC
18
63
GND
VCC
19
62
INPUT
20
GND
INPUT
INPUT
21
61
60
INPUT
22
59
INPUT
I/O
23
58
I/O
I/O
24
57
I/O
I/O
25
56
I/O
I/O
26
55
I/O
I/O
27
54
I/O
I/O
28
I/O
29
I/O
30
53
INPUT
I/O
52
I/O
51
I/O
Document #: 38-03037 Rev. *C
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 15
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Logic Array Blocks
Externally, the CY7C346B provides 20 dedicated inputs, one
of which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirectional data flow.
There are eight logic array blocks in the CY7C346B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in
which they are situated.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
EXPANDER
DELAY
tEXP
REGISTER
LOGIC ARRAY
CONTROL DELAY tCLR
tLAC
tPRE
INPUT
INPUT
DELAY
tIN
LOGIC ARRAY
DELAY
tLAD
CY7C346B
tRSU
tRH
OUTPUT
DELAY
OUTPUT
tRD
tCOMB
tLATCH
tOD
tXZ
tZX
SYSTEM CLOCK DELAY tICS
PIA
DELAY
tPIA
CLOCK
DELAY
tIC
FEEDBACK
DELAY
tFD
I/O DELAY
tIO
C346B–9
Figure 1. CY7C346B Internal Timing Model
Design Recommendations
Operation of the devices described herein with conditions
above those listed in the “Maximum Ratings” section of this
datasheet may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure
to absolute maximum ratings conditions for extended periods
of time may affect device reliability. The CY7C346B contains
circuitry to protect device pins from high static voltages or
electric fields, but normal precautions should be taken to avoid
application of any voltage higher than the maximum rated
voltages.
For proper operation, input and output pins must be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level
(either VCC or GND). Each set of VCC and GND pins must
Document #: 38-03037 Rev. *C
be connected directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Design Security
The CY7C346B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
Page 4 of 15
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CY7C346B
program data, may be reset simply by erasing the entire
device.
Timing Considerations
The CY7C346B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsulated in non-windowed packages.
Typical ICC vs. fMAX
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on the dedicated input pins.
400
ICC ACTIVE (mA) Typ.
When calculating synchronous frequencies, use tSU if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1,
or 1/(tEXP + tSU) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
When expander logic is used in the data path, add the
appropriate maximum expander delay, tEXP to tAS1.
Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP +
tAS1) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
asynchronous configuration.
300
VCC = 5.0V
Room Temp.
200
100
0
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If tOH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
MAXIMUM FREQUENCY
IO OUTPUT CURRENT (mA) TYPICAL
Output Drive Current
250
IOL
200
VCC = 5.0V
Room Temp.
150
100
IOH
50
0
1
2
3
4
5
VO OUTPUT VOLTAGE (V)
Document #: 38-03037 Rev. *C
Page 5 of 15
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CY7C346B
DC Output Current per Pin[1] .................... –25 mA to+25 mA
Maximum Ratings
DC Input Voltage[1] ........................................–2.0V to + 7.0V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Operating Range[2]
Storage Temperature ................................. –65°C to+135°C
Range
Ambient Temperature with
Power Applied............................................. –65°C to+135°C
Ambient Temperature
VCC
0°C to +70°C
5V ± 5%
–40°C to +85°C
5V ± 10%
Commercial
Maximum Junction Temperature
(under bias).................................................................. 150°C
Industrial
Supply Voltage to Ground Potential[1] ............. –2.0V to+7.0V
Electrical Characteristics Over the Operating Range
Parameter
VCC
Description
Test Conditions
Supply Voltage
Maximum VCC rise time is 10 ms
[3]
VOH
Output HIGH Voltage
IOH = –4 mA DC
VOL
Output LOW Voltage
IOL = 8 mA DC[3]
Min.
Max.
Unit
4.75(4.5)
5.25(5.5)
V
0.45
V
2.4
V
VIH
Input HIGH Voltage
2.0
VCC +0.3
V
VIL
Input LOW Voltage
–0.3
0.8
V
IIX
Input Current
VI = VCC or ground
–10
+10
µA
IOZ
Output Leakage Current
VO = VCC or ground
–40
+40
µA
tR
Recommended Input Rise Time
100
ns
tF
Recommended Input Fall Time
100
ns
Capacitance
Max.
Unit
CIN
Parameter
Input Capacitance
Description
VIN = 0V, f = 1.0 MHz
Test Conditions
10
pF
COUT
Output Capacitance
VOUT = 0V, f = 1.0 MHz
20
pF
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
250Ω
50 pF
INCLUDING
JIG AND
SCOPE
(a)
3.0V
R2
250Ω
5 pF
INCLUDING
JIG AND
SCOPE
10%
GND
≤ 6 ns
90%
90%
10%
≤ 6 ns
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Document #: 38-03037 Rev. *C
Page 6 of 15
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CY7C346B
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C346B-25
Parameter
Description
Min.
Max.
Dedicated Input to Combinatorial Output Delay[4]
tPD1
7C346B-35
Min.
25
Delay[4]
Max.
Unit
35
ns
tPD2
I/O Input to Combinatorial Output
tSU
Global Clock Set-Up Time
tCO1
Synchronous Clock Input to Output Delay[4]
tH
Input Hold Time from Synchronous Clock Input
tWH
Synchronous Clock Input HIGH Time
8
12.5
ns
tWL
Synchronous Clock Input LOW Time
8
12.5
ns
fMAX
Maximum Register Toggle Frequency[5]
tCNT
Minimum Global Clock Period
tODH
Output Data Hold Time After Clock
2
2
ns
fCNT
Maximum Internal Global Clock Frequency[6]
50
33.3
MHz
40
15
55
ns
25
14
ns
20
0
ns
0
62.5
ns
40
20
MHz
30
ns
Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range
7C346B-25
Parameter
Description
Min.
Max.
Delay[4]
7C346B-35
Min.
Max.
Unit
35
ns
tACO1
Asynchronous Clock Input to Output
tAS1
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
5
25
10
ns
tAH
Input Hold Time from Asynchronous Clock Input
6
10
ns
tAWH
Asynchronous Clock Input HIGH
Time[7]
11
16
ns
tAWL
Asynchronous Clock Input LOW Time[7]
9
14
ns
tACNT
Minimum Internal Array Clock Frequency
fACNT
Maximum Internal Array Clock Frequency[6]
20
50
30
33.3
ns
MHz
Commercial and Industrial Internal Switching Characteristics Over Operating Range
7C346B-25
Parameter
Description
Min.
Max.
7C346B-35
Min.
Max.
Unit
11
ns
6
11
ns
12
20
ns
tIN
Dedicated Input Pad and Buffer Delay
5
tIO
I/O Input Pad and Buffer Delay
tEXP
Expander Array Delay
tLAD
Logic Array Data Delay
12
14
ns
tLAC
Logic Array Control Delay
10
13
ns
tOD
Output Buffer and Pad Delay[4]
5
6
ns
tZX
Output Buffer Enable Delay[4]
10
13
ns
tXZ
Output Buffer Disable Delay[8]
13
ns
tRSU
Register Set-Up Time Relative to Clock Signal
at Register
6
12
ns
tRH
Register Hold Time Relative to Clock Signal at
Register
4
8
ns
tLATCH
Flow Through Latch Delay
10
3
4
ns
tRD
Register Delay
1
2
ns
Notes:
4. C1 = 35 pF.
5. The fMAX values represent the highest frequency for pipeline data.
6. This parameter is measured with a 16-bit counter programmed into each LAB.
7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.
8. C1 = 5 pF.
Document #: 38-03037 Rev. *C
Page 7 of 15
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CY7C346B
Commercial and Industrial Internal Switching Characteristics Over Operating Range (continued)
7C346B-25
Parameter
Description
Min.
Max.
7C346B-35
Min.
Max.
Unit
tCOMB
Transparent Mode Delay
3
4
ns
tIC
Asynchronous Clock Logic Delay
14
16
ns
tICS
Synchronous Clock Delay
3
1
ns
tFD
Feedback Delay
1
2
ns
tPRE
Asynchronous Register Preset Time
5
7
ns
tCLR
Asynchronous Register Clear Time
5
7
ns
tPIA
Programmable Interconnect Array Delay Time
14
20
ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
tWH
External Synchronous
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
tAS1
tAH
tAWH
tAWL
ASYNCHRONOUS
CLOCK INPUT
Document #: 38-03037 Rev. *C
Page 8 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Switching Waveforms (continued)
Internal Combinatorial
tIN
INPUT PIN
t IO
I/O PIN
tEXP
EXPANDER
ARRAY DELAY
tLAC, tLAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Internal Asynchronous
tAWH
tIOtR
tAWL
tF
CLOCK PIN
tIN
CLOCK INTO
LOGIC ARRAY
CLOCK FROM
LOGIC ARRAY
tIC
tRSU
tRH
DATA FROM
LOGIC ARRAY
tRD,tLATCH
tFD
tCLR,tPRE
tFD
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
tPIA
REGISTER OUTPUT
TO ANOTHER LAB
Document #: 38-03037 Rev. *C
Page 9 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Switching Waveforms (continued)
Internal Synchronous
SYSTEM CLOCK PIN
SYSTEM CLOCK
AT REGISTER
tIN
tICS
tRSU
tRH
DATA FROM
LOGIC ARRAY
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
tRD
tOD
DATA FROM
LOGIC ARRAY
tXZ
OUTPUT PIN
tZX
HIGH IMPEDANCE
STATE
Ordering Information
Speed (ns)
25
35
Ordering Code
Package Name
Package Type
CY7C346B-25HC/HI
H84
84-pin Windowed Leaded Chip Carrier
CY7C346B-25JC/JI
J83
84-lead Plastic Leaded Chip Carrier
CY7C346B-25NC/NI
N100
100-lead Plastic Quad Flatpack
CY7C346B-25RC/RI
R100
100-pin Windowed Ceramic Pin Grid Array
CY7C346B-35HC/HI
H84
84-pin Windowed Leaded Chip Carrier
CY7C346B-35JC/JI
J83
84-lead Plastic Leaded Chip Carrier
CY7C346B-35NC/NI
N100
100-lead Plastic Quad Flatpack
CY7C346B-35RC/RI
R100
100-pin Windowed Ceramic Pin Grid Array
Document #: 38-03037 Rev. *C
Operating Range
Commercial/Industrial
Commercial/Industrial
Page 10 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams
84-leaded Windowed Leaded Chip Carrier H84
51-80081-**
Document #: 38-03037 Rev. *C
Page 11 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams (continued)
84-lead Plastic Leaded Chip Carrier J83
51-85006-*A
Document #: 38-03037 Rev. *C
Page 12 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
51-85052-*A
Document #: 38-03037 Rev. *C
Page 13 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams (continued)
100-pin
100-pin Windowed Ceramic Pin Grid Array R100
51-80010-*C
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-03037 Rev. *C
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Document History Page
Document Title: CY7C346B 128-Macrocell Max® EPLD
Document Number: 38-03037
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106460
07/11/01
SZV
Change from Spec Number: 38-00861 to 38-03037
*A
113615
04/11/02
OOR
PGA diagram dimensions were updated
*B
122236
12/28/02
RBI
Power up requirements added to Operating Range Information
*C
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03037 Rev. *C
Page 15 of 15
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