Order Now Product Folder Support & Community Tools & Software Technical Documents LM76002, LM76003 SNVSAK0 – OCTOBER 2017 LM76002/LM76003 3.5-V to 60-V, 2.5-A/3.5-A Synchronous Step-Down Voltage Regulator 1 Features 2 Applications • • • • • • • 1 • • • • • • • • Integrated Synchronous Rectification Input Voltage 3.5 V to 60 V (65 V Maximum) Output Current: – LM76002: 2.5 A – LM76003: 3.5 A Output Voltage 1 V to 95% VIN 15-µA Quiescent Current in Regulation Wide Voltage Conversion Range – tON-MIN = 65 ns (Typical) – tOFF-MIN = 95 ns (Typical) System-Level Features – Synchronization to External Clock – Power-Good Flag – Precision Enable – Adjustable Soft Start (6.3 ms Default) – Voltage Tracking Capability Pin-Selectable FPWM Operation High-Efficiency at Light-Load Architecture (PFM) Protection Features – Cycle-by-Cycle Current Limit – Short-Circuit Protection With Hiccup Mode – Overtemperature Thermal Shutdown Protection Create a Custom Design Using the LM76002/03 With the WEBENCH® Power Designer space Telecommunications Infrastructure Asset and Fleet Management Systems Video Surveillance Programmable Logic Controllers 3 Description The LM76002/LM76003 regulator is an easy-to-use synchronous step-down DC-DC converter capable of driving up to 2.5 A (LM76002) or 3.5 A (LM76003) of load current from an input up to 60 V. The LM76002/LM76003 provides exceptional efficiency and output accuracy in a very small solution size. Peak current-mode control is employed. Additional features such as adjustable switching frequency, synchronization, FPWM option, power-good flag, precision enable, adjustable soft start, and tracking provide both flexible and easy-to-use solutions for a wide range of applications. Automatic frequency foldback at light load and optional external bias improve efficiency. This device requires few external components and has a pinout designed for simple PCB layout with best-in-class EMI (CISPR22) and thermal performance. Protection features include thermal shutdown, input undervoltage lockout, cycleby-cycle current limit, and short-circuit protection. The LM76002/LM76003 device is available in the WQFN 30-pin leadless package with wettable flanks. Device Information(1) PART NUMBER LM76002 WQFN (30) LM76003 Simplified Schematic VIN EN VOUT SW 6.00 mm × 4.00 mm space CBOOT CIN BODY SIZE (NOM) (1) For all available packages, see the orderable addendum at the end of the data sheet. BOOT PVIN PACKAGE space L COUT PGND LM76003 Efficiency vs Output Current (VOUT = 5 V, fSW = 500 kHz, Auto Mode) 100 SS/TRK BIAS RT 90 80 RFBT SYNC/MODE VCC AGND RFBB CVCC Efficiency (%) 70 FB 60 50 40 30 20 Copyright © 2017, Texas Instruments Incorporated VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.01 0.1 Load Current (A) 1 5 D013 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 22 1 1 1 2 3 5 8 Application and Implementation ........................ 24 8.1 Application Information............................................ 24 8.2 Typical Applications ............................................... 24 9 Power Supply Recommendations...................... 42 10 Layout................................................................... 42 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics........................................... 6 Timing Characteristics............................................... 8 Switching Characteristics .......................................... 8 System Characteristics ............................................. 9 Typical Characteristics ............................................ 10 10.1 Layout Guidelines ................................................. 42 10.2 Layout Example .................................................... 45 10.3 Thermal Design..................................................... 46 11 Device and Documentation Support ................. 47 11.1 11.2 11.3 11.4 11.5 11.6 Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 47 47 12 Mechanical, Packaging, and Orderable Information ........................................................... 48 4 Revision History 2 DATE REVISION NOTES October 2017 * Initial release Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 5 Pin Configuration and Functions RNP Package 30-Pin WQFN Top View NC NC NC NC 30 29 28 27 SW 1 26 PGND SW 2 25 PGND SW 3 24 PGND SW 4 23 NC SW 5 22 PVIN BOOT 6 21 PVIN NC 7 20 PVIN VCC 8 19 NC BIAS 9 18 EN RT 10 17 SYNC/MODE SS/TRK 11 16 PGOOD DAP 12 13 14 15 FB AGND AGND AGND Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 3 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Pin Functions PIN I/O (1) DESCRIPTION SW P Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor and boot-strap capacitor. BOOT P Boot-strap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor from this pin to the SW pin. NC — Not internally connected. Connect to ground copper on PCB to improve heat-sinking of the device and board level reliability. 8 VCC P Output of internal bias supply. Used as supply to internal control circuits. Connect a highquality 2.2-µF capacitor from this pin to GND. TI does not recommended loading this pin by external circuitry. 9 BIAS P Optional BIAS LDO supply input. TI recommends tying this to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tying to an external 3.3-V or 5-V rail if available, to improve efficiency. When used, place a 1-µF capacitor from this terminal to ground. Tie to ground when not in use. 10 RT A Switching frequency setting pin. Place a resistor from this pin to ground to set the switching frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground. 11 SS/TRK A Soft-start-control pin. Leave this pin floating to use the 6.3-ms internal soft-start ramp. An external capacitor can be connected from this pin to ground to extend the soft-start time. A 2-µA current sourced from this pin can charge the capacitor to provide the ramp. Connect to external ramp for tracking. Do not short to ground. 12 FB A Feedback input for output voltage regulation. Connect a resistor divider to set the output voltage. Never short this terminal to ground during operation. 16 PGOOD A Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = Low when EN = Low. NO. NAME 1, 2, 3, 4, 5 6 7, 19, 23, 27, 28, 29, 30 17 SYNC/MODE A Synchronization input and mode setting pin. Do not float, tie to ground if not used. Tie to ground: DCM/PFM operation under light loads, improved efficiency; tie to logic high: forced PWM under light loads, constant switching frequency over load; tie to external clock source: synchronize switching action to the clock, forced PWM under light loads. Triggers on the rising edge of external clock. 18 EN A Precision-enable input to regulator. Do not float. High = on, Low = off. Can be tied to VIN. Precision-enable input allows adjustable UVLO by external resistor divider. 13, 14, 15 AGND G Analog ground. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. 20, 21, 22 PVIN P Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors CIN. CIN must be placed right next to this pin and PGND and connected with short traces. 24, 25, 26 PGND G Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP, AGND, ground side of CIN and COUT. Path to CIN must be as short as possible. DAP — Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation path for the die. Must be used for heat sinking by soldering to ground copper on PCB. Thermal vias are preferred. EP (1) 4 A = Analog, O = Output, I = Input, G = Ground, P = Power Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range of –40°C to +125°C (unless otherwise noted) (1) MIN MAX PVIN to PGND PARAMETER –0.3 65 EN to AGND –0.3 VIN + 0.3 FB, RT, SS/TRK to AGND –0.3 5 PGOOD to AGND –0.1 20 SYNC to AGND –0.3 5.5 BIAS to AGND –0.3 Lower of (VIN + 0.3) or 30 AGND to PGND –0.3 0.3 SW to PGND –0.3 VIN + 0.3 SW to PGND less than 10-ns transients –3.5 65 BOOT to SW –0.3 5.5 VCC to AGND –0.3 5.5 Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Input voltages Output voltages (1) UNIT V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX 3.5 60 EN 0 VIN FB 0 4.5 PGOOD 0 18 BIAS input not used 0 0.3 BIAS input used 0 Lower of (VIN + 0.3) or 24 AGND to PGND PVIN to PGND Input voltages UNIT V –0.1 0.1 Output voltage VOUT 1 95% of VIN V Output current IOUT, LM76002 0 2.5 A Output current IOUT, LM76003 0 3.5 A Temperature Operating junction temperature, TJ –40 125 °C (1) Recommended operating rating indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 5 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 6.4 Thermal Information LM76002/LM76003 THERMAL METRIC (1) RNP (WQFN) UNIT 30 PINS RθJA Junction-to-ambient thermal resistance 29 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 24.3 °C/W Junction-to-board thermal resistance 1.7 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 13.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (PVIN PINS) VIN Operating input voltage range ISD Shutdown quiescent current; measured at PVIN pin (1) VEN = 0 V TJ = 25℃ 3.5 IQ_NONSW Operating quiescent current from VIN (non-switching) VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external 60 V 1.2 10 µA 0.9 12 µA 1.2 V ENABLE (EN PIN) VEN_VCC_H Enable input high level for VCC output VEN_VCC_L Enable input low level for VCC VEN falling output VEN_VOUT_H Enable input high level for VOUT VEN rising VEN_VOUT_HYS Enable input hysteresis for VOUT VEN falling hysteresis ILKG_EN Enable input leakage current VEN = 2 V VEN rising 0.3 1.14 V 1.204 1.25 –150 1.4 V mV 200 nA INTERNAL LDO (VCC PIN, BIAS PIN) VCC Internal VCC voltage VCC_UVLO Internal VCC undervoltage lockout VBIAS_ON Input changeover IBIAS_NONSW Operating quiescent current from external VBIAS (nonswitching) PWM operation 3.29 PFM operation 3.1 VCC rising 2.96 3.14 VCC falling hysteresis –565 VBIAS rising 3.11 VBIAS falling hysteresis –63 VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external V V 3.27 V mV 3.25 V mV 21 50 µA 1.006 1.017 V 0.2 60 nA 2.2 2.7 V VOLTAGE REFERENCE (FB PIN) VFB Feedback voltage PWM mode ILKG_FB Input leakage current at FB pin VFB = 1 V 0.987 HIGH SIDE DRIVER (BOOT PIN) VBOOT_UVLO (1) 6 BOOT - SW undervoltage lockout 1.6 Shutdown current includes leakage current of the switching transistors. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. PARAMETER TEST CONDITIONS MIN TYP MAX LM76002 3.2 4.2 5.3 LM76003 4.35 5.5 6.8 LM76002 2.3 3.2 4.2 LM76003 3.4 4.2 5.3 UNIT CURRENT LIMITS AND HICCUP IHS_LIMIT (2) Short-circuit, high-side current limit ILS_LIMIT (2) Low-side current limit INEG_LIMIT Negative current limit VHICCUP Hiccup threshold on FB pin IL_ZC Zero cross-current limit LM76002 –2.5 LM76003 –3.3 0.38 0.42 A A A 0.46 0.05 V A SOFT START (SS/TRK PIN) ISSC Soft-start charge current RSSD Soft-start discharge resistance 1.8 UVLO, TSD, OCP; or EN = 0 V 2 2.2 2 µA kΩ POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION VPGOOD_OV Power-good overvoltage threshold % of FB voltage 106% 110% 113% VPGOOD_UV Power-good undervoltage threshold % of FB voltage 86% 90% 93% VPGOOD_HYS Power-good hysteresis % of FB voltage VPGOOD_VALID Minimum input voltage for proper PGOOD function 50-µA pullup to PGOOD pin, VEN = 0 V, TJ = 25°C 1.3 2 RPGOOD Power-good on-resistance VEN = 2.5 V 40 100 VEN = 0 V 30 90 2.5% V Ω MOSFETS RDS_ON_HS (3) High-side MOSFET onresistance IOUT = 1 A, VBIAS = VOUT = 3.3 V 95 150 mΩ RDS_ON_LS (3) Low-side MOSFET onresistance IOUT = 1 A, VBIAS = VOUT = 3.3 V 45 85 mΩ THERMAL SHUTDOWN TSD (4) (2) (3) (4) Thermal shutdown threshold Shutdown threshold Recovery threshold 160 °C 135 °C This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower. Measured at pins. Ensured by design. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 7 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 6.6 Timing Characteristics MIN NOM MAX UNIT CURRENT LIMITS AND HICCUP NOC (1) Number of switching cycles before hiccup is tripped tOC Overcurrent hiccup retry delay time 128 Cycles 46 ms 3.5 6.3 ms SOFT START (SS/TRK PIN) tSS CSS = OPEN, from EN rising edge to PGOOD rising edge Internal soft-start time POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION tPGOOD_RISE PGOOD rising edge deglitch delay 80 140 200 µs tPGOOD_FALL PGOOD falling edge deglitch delay 80 140 200 µs MIN TYP MAX UNIT 65 95 (1) Ensured by design. 6.7 Switching Characteristics PARAMETER TEST CONDITIONS PWM LIMITS (SW PINS) tON-MIN Minimum switch on-time tOFF-MIN Minimum switch off-time tON-MAX Maximum switch on-time ns 95 130 ns HS timeout in dropout 3.8 8 11.4 µs Internal oscillator frequency RT = open 440 500 560 kHz Minimum adjustable frequency by RT or SYNC RT =133 kΩ, 0.1% 270 300 330 kHz Maximum adjustable frequency by RT or SYNC RT = 17.4 kΩ, 0.1% 1980 2200 2420 kHz OSCILLATOR (RT and SYNC PINS) fOSC fADJ VSYNC_HIGH Sync input high level threshold VSYNC_LOW Sync input low level threshold VMODE_HIGH Mode input high level threshold for FPWM VMODE_LOW tSYNC_MIN 8 2 0.4 V V 0.42 V Mode input low level threshold for AUTO mode 0.4 V Sync input minimum on- and offtime 80 ns Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 6.8 System Characteristics The following specifications apply to the circuit found in the typical Simplified Schematic with appropriate modifications (see Table 2). These parameters are not tested in production and represent typical performance only. Unless otherwise stated the following conditions apply: TA = 25°C, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB_PFM Output voltage offset at no load VIN = 3.8 V to 36 V, VSYNC = 0 V, auto mode in auto mode IOUT = 0 A 2% Vdrop Minimum input to output voltage differential to maintain specified accuracy VOUT = 5 V, IOUT = 1.5 A, fSW = 2.2 MHz 0.4 V IQ_SW Operating quiescent current (switching) VEN = 3.3 V, IOUT = 0 A, RT = open, VBIAS = VOUT = 3.3 V, RFBT = 1 Meg 15 µA LM76002: VSYNC = 0 V, IOUT = 10 mA 0.5 LM76003: VSYNC = 0 V, IOUT = 10 mA 0.7 IPEAK_MIN Minimum inductor peak current A IBIAS_SW Operating quiescent current from external VBIAS (switching) fSW = 500 kHz, IOUT = 1 A 7 fSW = 2.2 MHz, IOUT = 1 A 25 DMAX Maximum switch duty cycle While in frequency foldback tDEAD Dead time between high-side and low-side MOSFETs 97.5% 4 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 mA ns 9 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 6.9 Typical Characteristics Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. Curves represent most likely parametric norm at specified condition. 140 130 120 Shutdown Current (nA) RDS-ON (m:) 110 100 90 80 70 60 50 40 HS Switch LS Switch 30 20 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 -40 0 20 40 60 80 Temperature (qC) 100 120 140 D002 Figure 2. Shutdown Quiescent Current 1.008 6 Temp = 40qC Temp = 25qC Temp = 125qC 1.007 HS Limit LS Limit 5.5 1.006 Current Limits (A) Feedback Voltage (V) -20 D001 Figure 1. High-Side and Low-Side Switch RDS-ON 1.005 1.004 1.003 5 4.5 4 1.002 3.5 1.001 1 0 6 12 18 24 30 36 Input Voltage (V) 42 48 54 3 -40 60 -20 0 D003 Figure 3. Feedback Voltage 20 40 60 80 Temperature (qC) 100 120 140 D004 Figure 4. LM76003 High-Side and Low-Side Current Limits 2500 5 HS Limit LS Limit 4.5 2250 2000 Frequency (kHz) Current Limits (A) VIN = 24 V VIN = 3.5 V VIN = 60 V 4 3.5 3 1750 FREQ = 300 kHz FREQ = 1 MHz FREQ = 2.2 MHz 1500 1250 1000 750 500 2.5 250 2 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 -20 D005 Figure 5. LM76002 High-Side and Low-Side Current Limits 10 0 -40 0 20 40 60 80 Temperature (qC) 100 120 140 D006 Figure 6. Switching Frequency Set by RT Resistor Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Typical Characteristics (continued) Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. Curves represent most likely parametric norm at specified condition. 1.4 540 1.2 530 Enable Thresholds (V) Switching Frequency RT open (kHz) 550 520 510 500 490 480 470 VIN = 12 V VIN = 3.5 V VIN = 60 V 460 450 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 1 0.8 0.6 0.4 140 0.2 -40 VEN_VOUT Rising VEN_VOUT Falling VEN_VCC Rising VEN_VCC Falling -20 0 20 D007 Figure 7. Switching Frequency With RT Open 40 60 80 Temperature (qC) 100 120 140 D008 Figure 8. Enable Threshold 115 PGOOD Threshold (%) 110 105 OV Tripping OV Recovery UV Recovery UV Tripping 100 95 90 85 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 D009 Figure 9. PGOOD Threshold Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 11 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 7 Detailed Description 7.1 Overview The LM76002/LM76003 regulator is an easy-to-use synchronous step-down DC-DC converter that operates from 3.5-V to 60-V supply voltage. The device is capable of delivering up to 2.5-A or 3.5-A DC load current with exceptional efficiency and thermal performance in a very small solution size. The LM76002/LM76003 employs fixed-frequency peak-current-mode control with configurable discontinuous conduction mode (DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load range. The device can also be configured as forced-PWM (FPWM) operation to keep constant switching frequency over the load range. The device is internally compensated, which reduces design time and requires fewer external components. The switching frequency is programmable from 300 kHz to 2.2 MHz by an external resistor. The LM76002/LM76003 is also capable of synchronization to an external clock operating within the 300-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to meet a wide range of design requirements. It can be optimized to very small solution size with higher frequency or to very high efficiency with lower switching frequency. It has very small minimum HS MOSFET on-time (tON-MIN) and minimum off-time (tOFF-MIN) to provide wide range of voltage conversion. Automated frequency foldback is employed under tON-MIN or tOFF-MIN condition to further extend the operation range. The LM76002/LM76003 also features a power-good (PGOOD) flag, precision enable, internal or adjustable softstart rate, start-up with pre-bias voltage, and output voltage tracking. It provides a both flexible and easy-to-use solution for wide range of applications. Protection features include thermal shutdown, VCC undervoltage lockout, cycle-by-cycle current limiting, and short-circuit hiccup protection. The family requires very few external components and has a pinout designed for simple, optimum PCB layout for EMI and thermal performance. The LM76002/LM76003 device is available in a 30-pin WQFN lead-less package. 7.2 Functional Block Diagram EN ISSC BIAS VCC LDO Internal SS VCC SS/TRK BOOT HS I Sense ICMD + EA REF + VBOOT ± RC FB FB ± + UVLO UVLO CC OV/UV Detector PFM Detector SW CONTROL LOGIC PGood HICCUP Detector Slope Comp Oscillator TSD ± + PGOOD PVIN VBOOT Precision Enable CLK ICMD AGND LS I Sense FPWM RT SYNC/ MODE PGND Copyright © 2017, Texas Instruments Incorporated 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 7.3 Feature Description 7.3.1 Fixed-Frequency, Peak-Current-Mode Control The following operation description of the LM76002/LM76003 refers to the Functional Block Diagram and to the waveforms in Figure 10. The LM76002/LM76003 supplies a regulated output voltage by turning on the internal high side (HS) and low side (LS) NMOS switches with varying duty cycle (D). During high-side switch on-time tON, the SW pin voltage VSW swings up to approximately VIN, and the inductor current iL increase with linear slope. The HS switch is off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. The control parameter of buck converter is defined as duty cycle D = tON / tSW. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. VSW SW Voltage D = tON/ TSW VIN tON tOFF t 0 -VD Inductor Current iL TSW ILPK IOUT ûiL t 0 Figure 10. SW Node and Inductor Current Waveforms in Continuous Conduction Mode The LM76002/LM76003 synchronous buck converter employs peak current-mode control topology. A voltagefeedback loop is used to get accurate DC-voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the on-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). At very light load, the LM76002/LM76003 operates in PFM to maintain high efficiency, and the switching frequency decreases with reduced load current. 7.3.2 Light Load Operation Modes — PFM and FPWM DCM operation is employed in the LM76002/LM76003 when the inductor current valley reaches zero. The LM76002/LM76003 is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET at zero current, and the conduction loss is lowered by not allowing negative current conduction. Power conversion efficiency is higher in DCM than CCM under the same conditions. In DCM, the HS switch on-time reduces with lower load current. When either the minimum HS switch on-time (tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency decreases to maintain regulation. At this point, the LM76002/LM76003 operates in PFM. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 13 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Feature Description (continued) In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The lower the frequency is in PFM, the more DC offset is needed at VOUT. See Typical Characteristics for typical DC offset at very light load. If the DC offset on VOUT is not acceptable for a given application, TI recommends a static load at output to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also serve as a static load. In conditions with low VIN and/or high frequency, the LM76002/LM76003 may not enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the LM76002/LM76003 is operating in PFM mode at higher VIN, it remains in PFM operation when VIN is reduced. Alternatively, the device can run in a forced pulse-width-modulation (FPWM) mode where the switching frequency does not lower with load, and no offset is added to affect the VOUT accuracy unless the minimum ontime of the converter is reached. 7.3.3 Adjustable Output Voltage The voltage regulation loop in the LM76002/LM76003 regulates the FB voltage to be the same as the internal reference voltage. The output voltage of the LM76002/LM76003 is set by a resistor divider to program the ratio from VOUT to VFB. The resistor divider is connected from the output node to ground with the mid-point connecting to the FB pin. VOUT RFBT FB RFBB Figure 11. Output Voltage Setting The voltage reference system produces a precise ±1% voltage reference over temperature. TI recommends using divider resistors with 1% tolerance or better with temperature coefficient of 100 ppm or lower. Selection of RFBT equal or lower than 100 kΩ is also recommended. RFBB can be calculated by Equation 1: VFB RFBT VOUT VFB RFBB (1) Larger RFBT and RFBB values reduce the current that goes through the divider, thus helping to increase light load efficiency. However, larger values also make the feedback path more susceptible to noise. If efficiency at very light load is not critical in a certain application, TI recommends RFBT = 10 kΩ to 100 kΩ. If the resistor divider is not connected properly, output voltage cannot be regulated because the feedback loop is broken. If the FB pin is shorted to ground or disconnected, the output voltage is driven close to VIN because the regulator detects very low voltage on the FB node. The load connected to VOUT could be damaged in this case. It is important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout. The minimum output voltage achievable equals VFB, with RFBB open. The maximum VOUT is limited by the maximum duty cycle at a given frequency: DMAX = 1 – (tOFF_MIN / TSW) where • • tOFF_MIN is the minimum off time of the HS switch TSW = 1 / fSW is the switching period (2) Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX Maximum output voltage with frequency foldback can be estimated using Equation 3: VOUT _ MAX 14 VIN_MIN u tON _ MAX tON _ MAX tOFF _ MIN IOUT u RDS _ ON _ HS DCR Submit Documentation Feedback (3) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Feature Description (continued) 7.3.4 Enable (EN Pin) and UVLO System UVLO by EN and VCC_UVLO voltage on the EN pin (VEN) controls the ON/OFF functionality of the LM76002/LM76003. Applying a voltage less than 0.3 V to the EN input shuts down the operation of the LM76002/LM76003. In shutdown mode the quiescent current drops to typically 1.2 µA at VIN = 24 V. The internal LDO output voltage VCC is turned on when VEN_VOUT_H is higher than 1.15 V. The LM76002/LM76003 switching action and output regulation are enabled when VEN is greater than 1.204 V (typical). The LM76002/LM76003 supplies regulated output voltage when enabled and output current up to 2.5 A/3.5 A. The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the LM76002/LM76003 is to connect the EN pin to PVIN pins directly. This allows self-start-up of the LM76002/LM76003 when VIN is within the operation range. Many applications may benefit from the employment of an enable divider RENT and RENB (see Figure 12) to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection. VIN RENT ENABLE RENB Figure 12. VIN UVLO With a selected RENT, the RENB can be calculated by: VEN _ VOUT _ H u RENT RENB VIN _ ON _ H VEN_VOUT_H where • • VIN_ON_H is the desired supply voltage threshold to turn on this device VEN_VOUT_H could be taken from device data sheet (4) Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the hundreds of kΩ range is a good starting point. 7.3.5 Internal LDO, VCC UVLO, and Bias Input The LM76002/LM76003 has an internal LDO generating VCC voltage for control circuitry and MOSFET drivers. The nominal voltage for VCC is 3.29 V. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and properly grounded. Do not load or short the VCC pin to ground during operation. Shorting the VCC pin to ground during operation may damage the device. An UVLO prevents the LM76002/LM76003 from operating until the VCC voltage exceeds VCC_UVLO. The VCC_UVLO threshold is 3.14 V and has approximately 575 mV of hysteresis, so the device operates until VCC drops below 2.575 V (typical). Hysteresis prevents the device from turning off during power up if VIN droops due to input current demands. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 15 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Feature Description (continued) The LDO can generate VCC from two inputs: the supply voltage VIN and the BIAS input. The LDO power loss is calculated by ILDO × (VINLDO – VOUTLDO). The higher the difference between the input and output voltages of the LDO, the more losses occur to supply the same LDO output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to improve efficiency, especially at light load. TI recommends tying the BIAS pin to VOUT when the output voltage is equal to or greater than 3.3 V. Tie the BIAS pin to ground for applications less than 3.3 V. BIAS can also tie to external voltage source if available to improve efficiency. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor be used to bypass the BIAS pin to ground. If there is high-frequency noise or voltage spikes present on VOUT (during transient events or fault conditions), TI recommends connecting a resistor (1 to 10 Ω) between VOUT and BIAS. The VCC voltage is typically 3.27 V. When the LM76302/3 is operating in PFM mode with frequency foldback, VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very light loads. Figure 13 shows an example of VCC voltage change with mode change. 3.5 Auto Mode FPWM Mode 3.4 3.3 VCC (V) 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 0.001 0.01 0.1 Load Current (A) 1 5 D010 Figure 13. VCC Voltage Change With Mode Change VCC voltage has an internal undervoltage lockout threshold, VCC_UVLO. When VCC voltage is higher than VCC_UVLO rising threshold, the device is active and in normal operation if VEN > VEN_VOUT_H. If VCC voltage droops below VCC_UVLO falling threshold, the VOUT is shut down. 7.3.6 Soft Start and Voltage Tracking (SS/TRK) The LM76002/LM76003 has a flexible and easy-to-use start-up rate control pin: SS/TRK. The soft-start feature is to prevent inrush current impacting the LM76002/LM76003, and its supply when power is first applied. Soft start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM76002/LM76003 employs the internal soft-start control ramp and starts up to the regulated output voltage in 6.3 ms typically. In applications with a large amount of output capacitors, higher VOUT, or other special requirements, the soft-start time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-start time further reduces the supply current required to charge up output capacitors and supply any output loading. An internal current source (ISSC = 2.2 μA) charges CSS and generates a ramp from 0 V to VFB to control the ramp-up rate of the output voltage. For a desired soft-start time tSS, the capacitance for CSS can be found by Equation 5: 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Feature Description (continued) CSS = ISSC × tSS where • • • CSS = soft-start capacitor value (µF) ISSC = soft-start charging current (µA) tSS = desired soft-start time (s) (5) The soft-start capacitor CSS is discharged by an internal FET when VOUT is shut down by hiccup protection or ENABLE = logic low. When a large CSS is applied, and EN is toggled low only for a short period of time, CSS may not be fully discharged. The next soft-start ramp follows internal soft-start ramp before reaching the leftover voltage on CSS and then follows the ramp programmed by CSS. If this is not acceptable for a certain application, an R-C low-pass filter can be added to EN to slow down the shutting down of VCC, allowing more time to discharge CSS. The LM76002/LM76003 is capable of start-up into pre-biased output conditions. When the inductor current reaches zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also called diode emulation mode. It is built in by the DCM operation in light loads. With a pre-biased output voltage, the LM76002/LM76003 waits until the soft-start ramp allows regulation above the pre-biased voltage and then follows the soft-start ramp to the regulation level. When an external voltage ramp is applied to the SS/TRK pin, the LM76002/LM76003 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage detected by the SS/TRK pin must not fall below 1.2 V to avoid abnormal operation VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 14 shows resistive divider connection if external ramp tracking is desired. EXT RAMP RTRT SS/TRK RTRB Figure 14. Soft-Start Tracking External Ramp Figure 15 shows the case when VOUT ramps more slowly than the internal ramp, while Figure 16 shows when VOUT ramps faster than the internal ramp. Faster start-up time may result in inductor current tripping current protection during start-up. Use with special care. Enable Internal SS Ramp Ext Tracking Signal to SS pin VOUT Figure 15. Tracking With Longer Start-up Time Than The Internal Ramp Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 17 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Feature Description (continued) Enable Internal SS Ramp Ext Tracking Signal to SS pin VOUT Figure 16. Tracking With Shorter Start-up Time Than The Internal Ramp The LM76002/LM76003 is capable of start-up into pre-biased output conditions. During start-up the device sets the minimum inductor current to zero to avoid discharging a pre-biased load. 7.3.7 Adjustable Switching Frequency (RT) and Frequency Synchronization The switching frequency of the LM76002/LM76003 can be programmed by the impedance RT from the RT pin to ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating, and the LM76002/LM76003 operates at 500-kHz default switching frequency. The RT pin is not designed to be shorted to ground. For an desired frequency, RT can be found by: RT (k:) = 38400 Frequency(kHz) 14.33 (6) 140 120 RT (k:) 100 80 60 40 20 0 0 500 1000 1500 Frequency (kHz) 2000 2500 D008 Figure 17. Switching Frequency vs RT Table 1. Switching Frequency vs RT 18 SWITCHING FREQUENCY (kHz) RT RESISTANCE (kΩ) 300 134.42 400 99.57 500 79.07 750 52.20 1000 38.96 1500 25.85 2000 19.34 2200 17.57 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 The LM76002/LM76003 switching action can also be synchronized to an external clock from 300 kHz to 2.2 MHz. TI recommends connecting an external clock to the SYNC pin with appropriate termination resistor. Ground the SYNC pin if not used. SYNC EXT CLOCK RTERM Figure 18. Frequency Synchronization The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM76002/LM76003 switches at the frequency programmed by the RT resistor after a time-out period. TI recommends connecting a resistor RT to the RT pin so that the internal oscillator frequency is the same as the target clock frequency when the LM76002/LM76003 is synchronized to an external clock. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails. The choice of switching frequency is usually a compromise between conversion efficiency and the size of the circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. It is related to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. The choice of switching frequency may also be limited if an operating condition triggers tON-MIN or tOFF-MIN. 7.3.8 Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions Minimum on-time, tON-MIN, is the smallest duration of time that the HS switch can be on. tON-MIN is typically 70 ns in the LM76002/LM76003. Minimum off-time, tOFF-MIN, is the smallest duration that the HS switch can be off. tOFFMIN is typically 100 ns in the LM76002/LM76003. In CCM operation, tON-MIN and tOFF-MIN limits the voltage conversion range given a selected switching frequency. The minimum duty cycle allowed is: DMIN = tON-MIN × fSW (7) And the maximum duty cycle allowed is: DMAX = 1 – tOFF-MIN × fSW (8) Given fixed tON-MIN and tOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty cycle. In the LM76002/LM76003, frequency foldback scheme is employed to extend the maximum duty cycle when tOFF-MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT or the synchronization clock. Such a wide range of frequency foldback allows the LM76002/LM76003 output voltage to stay in regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. See Typical Characteristics for more details. Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operational supply voltage can be found by: VIN_MAX = VOUT / (fSW × tON-MIN) (9) At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without frequency foldback can be approximated by: VIN_MIN = VOUT / (fSW × tOFF-MIN) (10) Considering power losses in the system with heavy load operation, VIN-MIN is higher than the result calculated in Equation 10. With frequency foldback, VIN-MIN is lowered by decreased fSW. When the device is operating in auto mode at voltages near maximum rated input voltage and light load conditions, an increased output voltage ripple during load transient may be observed. For this reason TI recommends that device operating point be calculated with sufficient operational margin so that minimum on-time condition is not triggered. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 19 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 7.3.9 Internal Compensation and CFF The LM76002/LM76003 is internally compensated with RC = 600 kΩ and CC = 35 pF as shown in the Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. TI recommends placing an external feed-forward cap CFF in parallel with the top resistor divider RFBT for optimum transient performance. VOUT RFBT CFF FB RFBB Figure 19. Feed-Forward Capacitor for Loop Compensation The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by Equation 11: fZ-CFF = 1 / (2π × RFBT × CFF) (11) An additional pole is also introduced with CFF at the frequency of Equation 12: fP-CFF = 1 / (2π × CFF × (RFBT // RFBB)) (12) Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover. Electrolytic capacitors have much larger ESR and the ESR zero frequency would be low enough to boost the phase up around the crossover frequency. fZ-ESR = 1 / (2π × ESR × COUT) (13) Designs using mostly electrolytic capacitors at the output may not need any CFF. The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See Feed-Forward Capacitor for the calculation of CFF. 7.3.10 Bootstrap Voltage and VBOOT UVLO (BOOT PIN) The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. The capacitor connected between CBOOT and SW works as a charge pump to boost voltage on the BOOT pin to (VSW + VCC). The boot diode is integrated on the LM76002/LM76003 die to minimize physical size. TI recommends a 0.47-µF, 6.3-V or higher capacitor for CBOOT. The VBOOT_UVLO threshold is typically 2.2 V. If the CBOOT capacitor is not charged above this voltage with respect to SW, the device initiates a charging sequence using the low-side FET. 7.3.11 Power-Good and Overvoltage Protection (PGOOD) The LM76002/LM76003 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 12 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical range of pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is within the power-good band, +6% above and –7% below the internal reference VREF typically, the PGOOD switch is turned off, and the PGOOD pin voltage is pulled to ground. When the FB is 2% (typical) closer to FB than the PGOOD threshold, the PGOOD switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. Both rising and falling edges of the power-good flag have a built-in 220-µs (typical) deglitch delay. To pull up PGOOD pin to a voltage higher than 15 V, a resistor divider can be used to divide the voltage down. 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 VPU RPGT PGOOD RPGB Figure 20. PGOOD Resistor Divider For given pullup voltage VPU and desired voltage on PGOOD pin is VPG and with RPGT chosen, value for RPGB can be calculated using Equation 14: RPGB = VPG RPGT VPU VPG (14) 7.3.12 Overcurrent and Short-Circuit Protection The LM76002/LM76003 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating. High-side MOSFET overcurrent protection is implemented by the nature of the peak current-mode control. The HS switch current is sensed when the HS is turned on after a blanking time. The HS switch current is compared to the either the minimum of a fixed current set point (ISC) or the output of the voltage regulation loop minus slope compensation every switching cycle. The slope compensation increases with duty cycle and tends to lower the HS current limit above 60% duty cycle as it lowers below ISC. See Typical Characteristics. When the LS switch is turned on, the current going through it is also sensed and monitored. Before turning off the LS switch at the end of every clock cycle, the LS current is compared to the LS current limit. If the LS current limit is exceeded, the LS MOSFET stays on, and the HS switch is not turned on. The LS switch is kept ON so that inductor current keeps ramping down, until the inductor current ramps below ILSLIMIT. The LS switch is turned off once the LS current falls below the limit, and the HS switch is turned on again after a dead time. If the current of the LS switch is higher than the LS current limit for 128 consecutive cycles, and the feedback voltage falls 60% below regulation, hiccup current-protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 40 ms typically before the LM76002/LM76003 tries to start again. If overcurrent or a short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, and prevents overheating and potential damage to the device. Under non-severe overcurrent conditions when the feedback voltage has not fallen 60% below regulation, the LM76002/LM76003 reduces the switching frequency and keeps the inductor current valley clamped at the LS current limit level. This operation mode allows slight overcurrent operation during load transients without tripping hiccup. If tracking was used for initial sequencing the device attempts to restart using the internal soft-start circuit until the tracking voltage is reached. 7.3.13 Thermal Shutdown Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 135°C. When the junction temperature falls below 135°C, the LM76002/LM76003 attempts to soft start. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 21 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 7.4 Device Functional Modes 7.4.1 Shutdown Mode The EN pin provides electrical on/off control for the LM76002/LM76003. When the EN pin voltage is below 0.3 V (typical), both the regulator and the internal LDO have no output voltages, and the device is in shutdown mode. In shutdown mode the quiescent current drops to typically 1.2 µA. The LM76002/LM76003 also employs UVLO protection. If VCC voltage is below the UVLO level, the output of the regulator is turned off. 7.4.2 Standby Mode The internal LDO has a lower EN threshold than the regulator. When the EN pin voltage is above below 1.1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCC voltage at 3.29 V typically. The precision enable circuitry is ON once VCC is above the UVLO. The internal MOSFETs remain in tri-state unless the voltage on EN pin goes above the precision enable threshold. The LM76002/LM76003 also employs UVLO protection. If VCC voltage is below the UVLO level, the output of the regulator is turned off. 7.4.3 Active Mode The LM76002/LM76003 is in active mode when the EN pin and UVLO high threshold levels are satisfied. The simplest way to enable the operation of the LM76002/LM76003 is to connect the EN pin to VIN, which allows self start-up of the LM76002/LM76003 when the input voltage is in the operation range: 3.5 V to 60 V. See Enable (EN Pin) and UVLO for details on setting these operating levels. In active mode, depending on the load current, the LM76002/LM76003 will be in one of five sub modes: 1. CCM with fixed switching frequency with load between half of IMINPK to full load. 2. DCM when the load current is lower than half of the inductor current ripple. 3. Light load mode where the device uses pulse frequency modulation (PFM) and lowers the switching frequency at load under half of IMINPK to improve efficiency. 4. Foldback mode when switching frequency is reduced to maintain output regulation with supply voltages that cause the minimum tON or tOFF to be exceeded. 5. Forced-pulse-width modulation (FPWM) is similar to CCM with fixed switching frequency, but extends the fixed frequency range of operation from full to no load. 7.4.4 CCM Mode CCM operation is employed in the LM76002/LM76003 when the load current is higher than ½ of the peak-topeak inductor current. If the load current is decreased, the device enters DCM mode. In CCM operation, the frequency of operation is constant and fixed unless the minimum tON or tOFF are exceeded which causes the part to enter fold back mode (refer to Internal LDO, VCC UVLO, and Bias Input for details). In these cases, PWM is still maintained, but the frequency of operation is folded back (reduced) to maintain proper regulation. 7.4.5 DCM Mode DCM operation is employed in the LM76002/LM76003 when the load current is lower than ½ of the peak-to-peak inductor current. In DCM operation (also known as diode emulation mode), the LS FET is turned off when the inductor current drops below 0 A to keep operation as efficient as possible by reducing switching losses and preventing negative current conduction. In PWM operation, the frequency of operation is constant and fixed unless the load current is reduced below IPEAK_MIN, which causes the part to enter light load mode, or if the minimum tON or tOFF are exceeded, which cause the device to enter foldback mode. 7.4.6 Light Load Mode At light output current loads, PFM is activated for the highest efficiency possible. When the inductor current does not reach IPEAK_MIN during a switching cycle, the on-time is increased, and the switching frequency reduces as needed to maintain proper regulation. The on-time has a maximum value of 8 µs to avoid large output voltage ripple in dropout conditions. Efficiency is greatly improved by reducing switching and gate-drive losses. During light-load mode of operation the LM76002/LM76003 operates with a minimum quiescent current of 10 to 15 µA (typical). 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Device Functional Modes (continued) 7.4.7 Foldback Mode Foldback protection modes are entered when the duty cycle exceeds the minimum on- and off-times of the device. At very high duty cycles, where the minimum off-time is not satisfied, the frequency folds back to allow more time for the peak current command to be reached. The maximum on-time is 8 µs, which limits the maximum duty cycle in dropout to 98%. At very low duty cycles when the minimum on-time is reached, the device maintains regulation by dropping the frequency to allow more time for the inductor current to discharge the output capacitor. Foldback mode is exited once the minimum on-time and off-times are satisfied. 7.4.8 Forced Pulse-Width-Modulation Mode FPWM is employed when the FPWM pin is pulled high, or the device is synchronized to an external clock. In this mode, diode emulation is turned off, and the device emains in CCM over the full load range. In FPWM operation, the frequency of operation is constant and fixed unless the minimum tON or tOFF are exceeded, which cause the device to enter foldback mode. In these cases, PWM operation is still maintained, but the frequency of operation is folded back (reduced) to maintain proper regulation. DC accuracy is at a minimum in FPWM mode. 7.4.9 Self-Bias Mode For highest efficiency of operation, TI recommends that the BIAS pin be connected directly to VOUT when 3.3 V ≤ VOUT ≤ 24 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal LDO are reduced, and therefore the total efficiency of the LM76002/LM76003 is improved. These efficiency gains are more evident during light load operation. During this mode of operation, the LM76002/LM76003 operates with a minimum quiescent current of 15 µA (typical). See Internal LDO, VCC UVLO, and Bias Input for more details. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 23 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM76002/LM76003 is a step-down DC-DC converter. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 3.5 A. The following design procedure can be used to select component values for the LM76002/LM76003. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design (see Custom Design With WEBENCH® Tools). 8.2 Typical Applications The LM76002/LM76003 only requires a few external components to convert from a wide range of supply voltage to output voltage, as shown in Figure 21: L VIN CIN VOUT SW PVIN PGND BOOT FB EN CBOOT VCC COUT RFBT CFF RFBB CVCC SS/TRK BIAS RT LM76003 SYNC AGND CBIAS PGOOD Tie BIAS to PGND when VOUT < 3.3 V Copyright © 2017, Texas Instruments Incorporated Figure 21. LM76002/LM76003 Basic Schematic The LM76002/LM76003 also integrates a full list of features to aid system design requirements, such as VCC UVLO, programmable soft start, start-up tracking, programmable switching frequency, clock synchronization, and a power-good indication. Each system can select the features needed in a specific application. A comprehensive schematic with all features utilized is shown in Figure 22: 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Typical Applications (continued) L VIN RENT VOUT SW PVIN CIN PGND COUT CBOOT RFBT BOOT EN RENB CFF FB VCC RFBB CVCC SS/TRK CSS RT BIAS LM76003 RT CBIAS SYNC PGOOD AGND PGND RPG RSYNC Tie BIAS to PGND when VOUT < 3.3 V Copyright © 2017, Texas Instruments Incorporated Figure 22. LM76002/LM76003 Comprehensive Schematic The external components must fulfill the requirements of the application, but also the stability criteria of the device control loop. The LM76002/LM76003 is optimized to work within a range of external components. Inductance and capacitance of the LC output filter each create poles that have to be considered in the control of the converter. Table 2 can be used to simplify the output filter component selection. Table 2. L, COUT, and CFF Typical Values fSW (kHz) VOUT (V) L (µH) COUT (µF) RFBT (kΩ) RFBB (kΩ) 300 1 2.5 680 100 OPEN 500 1 1.5 470 100 OPEN 1000 1 0.68 200 100 OPEN 2200 1 0.47 120 100 OPEN 300 3.3 6.8 200 100 43.5 500 3.3 4.7 150 100 43.5 1000 3.3 2.5 88 100 43.5 2200 3.3 1.2 44 100 43.5 300 5 10 150 100 25 500 5 6.8 100 100 25 1000 5 3.3 66 100 25 2200 5 1.5 44 100 25 300 12 22 66 100 9.09 500 12 15 44 100 9.09 1000 12 6.8 22 100 9.09 2200 12 3.3 22 100 9.09 300 24 47 40 100 4.37 500 24 27 33 100 4.37 1000 24 15 22 100 4.37 2200 24 6.8 22 100 4.37 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 25 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 8.2.1 Design Requirements Detailed Design Procedure is based on a design example. For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Example Parameters DESIGN PARAMETER VALUE Input voltage range 3.5 V to 60 V Output voltage 3.3 V Input ripple voltage 400 mV Output ripple voltage 30 mV Output current rating 3.5 A Operating frequency 500 kHz 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM76002/03 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.2.2 Output Voltage Setpoint The output voltage of the LM76002/LM76003 device is externally adjustable using a resistor divider network. In the application circuit of Figure 22, this divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 15 is used to determine the output voltage of the converter: RFBB VFB VOUT VFB RFBT (15) Choose the value of the RFBT to be around 1 MΩ to minimize quiescent current during light load operation or 100 kΩ to improve noise immunity. With the desired output voltage set to be 3.3 V and with a VFB = 1 V, the RFBB value can then be calculated using Equation 15. The formula yields a value of 434.78 kΩ. Choose the closest available value of 432 kΩ for the RFBB, or a combination of two resistors (432 kΩ + 2.74 kΩ) to increase initial accuracy. 8.2.2.3 Switching Frequency The default switching frequency of the LM76002/LM76003 device is set at 500 kHz. If the RT is left open, the LM76002/LM76003 switches at 500 kHz in CCM mode. Use Equation 16 to calculate the required value for RT in order to operate the LM76002/LM76003 at different frequencies. RT (k:) = 38400 Frequency(kHz) 14.33 (16) The unit for the result is kΩ. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 8.2.2.4 Input Capacitors The LM76002/LM76003 device requires an input decoupling and, depending on the application, a bulk input capacitor. The typical recommended value for the high frequency decoupling capacitor is 10 μF to 22 μF. TI recommends a high-quality ceramic type X5R or X7R with sufficiency voltage rating. The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LM76002/LM76003 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable. The optimum value for this capacitor is four times the ceramic input capacitance with ESR close to the characteristic impedance of the LC filter formed by the application input inductance and ceramic input capacitors. For this design, two 4.7-μF, X7R dielectric capacitors rated for 100 V are used for the input decoupling capacitance. A single capacitor has equivalent series resistance (ESR) of approximately 3 mΩ, and an RMS current rating of 3 A. Include a capacitor with a value of 47 nF for high-frequency filtering and place it as close as possible to the device pins. NOTE DC-Bias Effect: High capacitance ceramic capacitors have a DC-bias derating effect, which has a strong influence on the final effective capacitance. Therefore, choose the right capacitor value carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. 8.2.2.5 Inductor Selection The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is based on the desired peak-to-peak ripple current, ΔiL that flows in the inductor along with the load current. As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance means lower ripple current and hence lower output voltage ripple. Lower inductance results in smaller, less expensive devices. An inductance that gives a ripple current of 20% to 40% of the maximum output current is a good starting point. (ΔiL = (1/5 to 2/5) × IOUT). The peak-to-peak inductor current ripple can be found by Equation 17 and the range of inductance can be found by Equation 18 with the typical input voltage used as VIN. 'iL (VIN VOUT ) u D L u fSW (17) (VIN VOUT ) u D (V VOUT ) u D d L d IN 0.4 u fSW u IL-MAX 0.2 u fSW u IL-MAX (18) D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN, assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value comes out in micro henries. The inductor ripple current ratio is defined by: 'iL r IOUT (19) The second criterion is the inductor saturation-current rating. The inductor must be rated to handle the maximum load current plus the ripple current: IL-PEAK = ILOAD-MAX + Δ iL / 2 (20) The LM76002/LM76003 has both valley current limit and peak current limit. During an instantaneous short, the peak inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be higher than the HS current limit. TI recommends selection of an inductor with a larger core saturation margin and preferably a softer roll off of the inductance value over load current. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 27 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However, too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full load could be falsely triggered. It also generates more conduction loss because the RMS current is slightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak-current-mode control, it is not recommended to have an inductor current ripple that is too small. Enough inductor current ripple improves signalto-noise ratio on the current comparator and makes the control loop more immune to noise. Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. The hard saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate. For the design example, a standard 10-μH inductor from Wurth, Coiltronics, or Vishay can be used for the 3.3-V output with plenty of current rating margin. 8.2.2.6 Output Capacitor Selection The device is designed to be used with a wide variety of LC filters. TI generally recommends using as little output capacitance as possible to keep cost and size down. Choose the output capacitor(s), COUT, with care as it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load current transients. The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the equivalent series resistance (ESR) of the output capacitors: ΔVOUT-ESR = ΔiL × ESR (21) The other is caused by the inductor current ripple charging and discharging the output capacitors: ΔVOUT-C = ΔiL / (8 × fSW × COUT) (22) The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks. Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens, output capacitors provide the required charge before the inductor current can slew to the appropriate level. The initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until the control loop response increases or decreases the inductor current to supply the load. To maintain a small overshoot or undershoot during a transient, small ESR, and large capacitance are desired. But these also come with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage deviation. For a given input and output requirement, Equation 23 gives an approximation for an absolute minimum output cap required: COUT ! (fSW ª§ r 2 · 1 u «¨ u (1 Dc) ¸ ¨ ¸ u r u 'VOUT / IOUT ) ¬«© 12 ¹ º Dc u (1 r) » ¼» (23) Along with this for the same requirement, calculate the maximum ESR as per Equation 24 ESR < D' · §1 u ¨ + 0.5 ¸ fSW u COUT ©r ¹ where • • • • • 28 r = Ripple ratio of the inductor ripple current (ΔiL / IOUT) ΔVO = target output voltage undershoot D’ = 1 – duty cycle fSW = switching frequency IOUT = load current Submit Documentation Feedback (24) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 A general guideline for COUT range is that COUT should be larger than the minimum required output capacitance calculated by Equation 23, and smaller than 10 times the minimum required output capacitance or 1 mF. In applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits potential output voltage overshoots as the input voltage falls below the device normal operating range. To optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback resistor. For this design example, three 47-µF, 10-V, X7R ceramic capacitors are used in parallel. 8.2.2.7 Feed-Forward Capacitor The LM76002/LM76003 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively. Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 25, assuming COUT has very small ESR. fX 15.46 VOUT u COUT (25) The Equation 26 for CFF was tested: CFF 1 1 u 2Sfx RFBT u (RFBT / /RFBB ) (26) If capacitors with high ESR are used CFF is not required. The CFF capacitor creates a time constant with RFBT that couples the attenuated output voltage ripple to the FB node. Using a value that is too large for CFF may couple too much ripple to FB node and affect output voltage regulation. For capacitors with medium ESR (20 – 200 mΩ) Equation 26 can be used as quick starting point. For the application in this design example, a 47-pF COG capacitor is used. 8.2.2.8 Bootstrap Capacitors Every LM76002/LM76003 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47 μF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability. 8.2.2.9 VCC Capacitors The VCC pin is the output of an internal LDO for LM76002/LM76003. The input for this LDO comes from either VIN or BIAS (please refer to functional block diagram for LM76002/LM76003). To insure stability of the part, place a 1-µF to 2.2-µF, 10-V capacitor for this pin. Never short VCC pin to ground during operation. 8.2.2.10 BIAS Capacitors For an output voltage 3.3 V and greater, connect the BIAS pin to the output in order to increase light load efficiency. The BIAS pin is one of the two inputs for the VCC LDO. When BIAS voltage is below VBIAS-ON threshold, the input for the VCC LDO is internally connected to VIN. Because this is an LDO, the voltage differences between the input and output affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS pin as an input capacitor for the LDO. 8.2.2.11 Soft-Start Capacitors The SS pin can be left floating, and the LM76002/LM76003 implements a soft-start time of 6.3 ms. In order to use an external soft-start capacitor, the capacitor must be sized so that the soft-start time is greater than 6.3 ms. Use Equation 27 to calculate the soft-start capacitor value: CSS = ISSC × tSS (27) With a desired soft start time of 11 ms, a soft-start charging current of 2 µA, and an internal VREF of 1 V, Equation 27 yields a soft start capacitor value of 22 nF. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 29 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 8.2.2.12 Undervoltage Lockout Setpoint The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT is connected between the PVIN pin and the EN pin of the LM76002/LM76003. RENB is connected between the EN pin and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. Equation 28 can be used to determine the VIN UVLO level. VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB (28) The EN rising threshold (VENH) for LM76002/LM76003 is set to be 1.218 V (typical). Choose the value of RENB to be 1 MΩ to minimize input current from the supply. If the desired VIN UVLO level is at 5 V, then the value of RENT can be calculated using Equation 29: RENT = (VIN-UVLO-RISING / VENH – 1) × RENB (29) Equation 29 yields a value of 1.38 MΩ. The resulting falling UVLO threshold, can be calculated by Equation 30, where EN falling threshold (VENL) is 0.99 V (typical). VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB (30) 8.2.2.13 PGOOD A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 18 V. If it is desired to pull up the PGOOD pin to a voltage higher than 18 V, a resistor can be added from the PGOOD pin to ground to divide the voltage detected by the PGOOD pin to a value no higher than 18 V. 8.2.2.14 Synchronization The LM76002/LM76003 switching action can synchronize to an external clock from 300 kHz to 2.2 MHz. TI recommends connecting an external clock to the SYNC pin with a 50-Ω to 100-Ω termination resistor. Ground the SYNC pin if not used. 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 8.2.3 Application Curves 100 100 90 95 80 90 70 85 Efficiency (%) Efficiency (%) Unless otherwise specified the following conditions apply: 60 50 40 30 80 75 70 65 VIN = 8 V VIN = 12 V VIN = 18 V VIN = 24 V 20 10 0 0.001 VIN = 8 V VIN = 12 V VIN = 18 V VIN = 24 V 60 55 50 0.01 VOUT = 3.3 V 0.1 Load Current (A) 1 5 0 0.5 fSW = 500 kHz Auto Mode VOUT = 3.3 V 1.5 2 2.5 Load Current (A) 3 3.5 4 D011 fSW = 500 kHz FPWM Mode Figure 24. LM76003 Efficiency 100 100 90 95 80 90 70 85 Efficiency (%) Efficiency (%) Figure 23. LM76003 Efficiency 60 50 40 30 80 75 70 65 20 60 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 55 50 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 0.5 1 D014 fSW = 500 kHz Auto Mode VOUT = 5 V Figure 25. LM76003 Efficiency 1.5 2 2.5 Load Current (A) 3 3.5 4 D014 fSW = 500 kHz FPWM Mode Figure 26. LM76003 Efficiency 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 1 D011 60 50 40 30 60 50 40 30 20 20 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 0.5 1 D016 fSW = 1000 kHz Auto Mode VOUT = 5 V Figure 27. LM76003 Efficiency 1.5 2 2.5 Load Current (A) 3 fSW = 1000 kHz 3.5 D016 FPWM Mode Figure 28. LM76003 Efficiency Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 4 31 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Unless otherwise specified the following conditions apply: 60 50 40 30 60 50 40 30 20 20 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 0.5 fSW = 2200 kHz Auto Mode VOUT = 5 V 120 120 100 100 80 80 60 40 VIN = 24 V VIN = 48 V VIN = 60 V 0 0.001 3.5 4 D018 fSW = 2200 kHz FPWM Mode 60 40 VIN = 24 V VIN = 48 V VIN = 60 V 20 0.1 Load Current (A) 1 5 0 0.5 fSW = 500 kHz Auto Mode VOUT = 12 V 100 100 80 80 Efficiency (%) 120 60 40 VIN = 32 V VIN = 48 V VIN = 60 V 0 0.001 1.5 2 2.5 Load Current (A) 3 3.5 4 D020 fSW = 500 kHz FPWM Mode Figure 32. LM76003 Efficiency 120 20 1 D020 Figure 31. LM76003 Efficiency Efficiency (%) 3 0 0.01 VOUT = 12 V 60 40 VIN = 32 V VIN = 48 V VIN = 60 V 20 0 0.01 VOUT = 24 V 0.1 Load Current (A) 1 5 0 0.5 1 D022 fSW = 300 kHz Auto Mode VOUT = 24 V Figure 33. LM76003 Efficiency 32 1.5 2 2.5 Load Current (A) Figure 30. LM76003 Efficiency Efficiency (%) Efficiency (%) Figure 29. LM76003 Efficiency 20 1 D018 Submit Documentation Feedback 1.5 2 2.5 Load Current (A) 3 fSW = 300 kHz 3.5 4 D022 FPWM Mode Figure 34. LM76003 Efficiency Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Unless otherwise specified the following conditions apply: 60 50 40 30 60 50 40 30 20 20 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 10 0 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 0.5 fSW = 500 kHz Auto Mode VOUT = 5 V Figure 35. LM76002 Efficiency 2.5 3 D024 fSW = 500 kHz FPWM Mode 3.4 VIN = 8 V VIN = 12 V VIN = 18 V VIN = 24 V 3.38 3.36 3.36 3.34 3.32 3.3 3.28 3.26 3.34 3.32 3.3 3.28 3.26 3.24 3.24 3.22 3.22 3.2 0.01 VIN = 8 V VIN = 12 V VIN = 18 V VIN = 24 V 3.38 Output Voltage (V) Output Voltage (V) 1.5 2 Load Current (A) Figure 36. LM76002 Efficiency 3.4 3.2 0.1 Load Current (A) VOUT = 3.3 V 1 5 0 0.5 1 D012 fSW = 500 kHz Auto Mode VOUT = 3.3 V Figure 37. LM76003 Load and Line Regulation 1.5 2 2.5 Load Current (A) 3 3.5 4 D012 fSW = 500 kHz FPWM Mode Figure 38. LM76003 Load and Line Regulation 5.1 5.2 VIN = 12 V VIN = 24 V VIN = 48 V 5.16 5.12 5.06 5.08 5.04 5 4.96 4.92 5.04 5.02 5 4.98 4.96 4.88 4.94 4.84 4.92 4.8 0.001 VOUT = 5 V VIN = 12 V VIN = 24 V VIN = 48 V 5.08 Output Voltage (V) Output Voltage (V) 1 D024 4.9 0.01 0.1 Load Current (A) fSW = 500 kHz 1 5 0 0.5 D015 Auto Mode Figure 39. LM76003 Load and Line Regulation VOUT = 5 V 1 1.5 2 2.5 Load Current (A) fSW = 500 kHz 3 3.5 4 D015 FPWM Mode Figure 40. LM76003 Load and Line Regulation Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 33 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Unless otherwise specified the following conditions apply: 5.1 5.2 VIN = 12 V VIN = 24 V VIN = 48 V 5.16 5.06 5.08 Output Voltage (V) Output Voltage (V) 5.12 5.04 5 4.96 4.92 5.04 5.02 5 4.98 4.96 4.88 4.94 4.84 4.92 4.8 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 5.08 4.9 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 fSW = 1000 kHz Auto Mode 3 3.5 4 D017 fSW = 1000 kHz FPWM Mode 5.1 VIN = 12 V VIN = 24 V VIN = 48 V 5.16 5.12 5.06 5.08 5.04 5 4.96 4.92 5.04 5.02 5 4.98 4.96 4.88 4.94 4.84 4.92 4.8 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 5.08 Output Voltage (V) Output Voltage (V) 1.5 2 2.5 Load Current (A) Figure 42. LM76003 Load and Line Regulation 5.2 4.9 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 0.5 1 D019 fSW = 2200 kHz Auto Mode VOUT = 5 V Figure 43. LM76003 Load and Line Regulation 1.5 2 2.5 Load Current (A) 3 3.5 4 D019 fSW = 2200 kHz FPWM Mode Figure 44. LM76003 Load and Line Regulation 12.4 12.4 VIN = 24 V VIN = 48 V VIN = 60 V 12.35 12.3 VIN = 24 V VIN = 48 V VIN = 60 V 12.35 12.3 12.25 Output Voltage (V) 12.25 Output Voltage (V) 1 VOUT = 5 V Figure 41. LM76003 Load and Line Regulation 12.2 12.15 12.1 12.05 12 11.95 12.2 12.15 12.1 12.05 12 11.95 11.9 11.9 11.85 11.85 11.8 0.001 VOUT = 12 V 11.8 0.01 0.1 Load Current (A) fSW = 500 kHz 1 5 0 0.5 D021 Auto Mode Figure 45. LM76003 Load and Line Regulation 34 0.5 D017 VOUT = 12 V 1 1.5 2 2.5 Load Current (A) fSW = 500 kHz 3 3.5 4 D021 FPWM Mode Figure 46. LM76003 Load and Line Regulation Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Unless otherwise specified the following conditions apply: 24.5 24.5 VIN = 32 V VIN = 48 V VIN = 60 V 24.4 24.3 Output Voltage (V) Output Voltage (V) 24.3 VIN = 32 V VIN = 48 V VIN = 60 V 24.4 24.2 24.1 24 23.9 23.8 24.2 24.1 24 23.9 23.8 23.7 23.7 23.6 0.001 23.6 0.01 VOUT = 24 V 0.1 Load Current (A) 1 5 0 fSW = 300 kHz Auto Mode 1.5 2 2.5 Load Current (A) 3 3.5 4 D023 fSW = 300 kHz FPWM Mode Figure 48. LM76003 Load and Line Regulation 5.1 5.2 VIN = 12 V VIN = 24 V VIN = 48 V 5.16 5.12 5.06 5.08 5.04 5 4.96 4.92 5.04 5.02 5 4.98 4.96 4.88 4.94 4.84 4.92 4.8 0.001 VIN = 12 V VIN = 24 V VIN = 48 V 5.08 Output Voltage (V) Output Voltage (V) 1 VOUT = 24 V Figure 47. LM76003 Load and Line Regulation 4.9 0.01 VOUT = 5 V 0.1 Load Current (A) 1 5 0 fSW = 500 kHz Auto Mode 3.4 5.4 3.3 5.2 Output Voltage (V) 3.2 3.1 3 2.9 2.8 ILOAD = 10 mA ILOAD = 1 A ILOAD = 2.5 A ILOAD = 3.5 A 2.7 2.6 VOUT = 3.3 V 4.5 5 Input Voltage (V) 5.5 6 D025 FPWM Mode 4.8 4.6 4.4 ILOAD = 10 mA ILOAD = 1 A ILOAD = 2.5 A ILOAD = 3.5 A 4 6.5 Auto Mode Figure 51. LM76003 Dropout Curve 3 5 3.8 4.5 4.75 5 D026 fSW = 500 kHz 2.5 fSW = 500 kHz 4.2 2.5 4 1.5 2 Load Current (A) Figure 50. LM76002 Load and Line Regulation 5.6 3.5 1 VOUT = 5 V 3.5 3 0.5 D025 Figure 49. LM76002 Load and Line Regulation Output Voltage (V) 0.5 D023 VOUT = 5 V 5.25 5.5 5.75 Input Voltage (V) 6 6.25 fSW = 500 kHz 6.5 D027 Auto Mode Figure 52. LM76003 Dropout Curve Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 35 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 5.6 5.6 5.4 5.4 5.2 5.2 Output Voltage (V) Output Voltage (V) Unless otherwise specified the following conditions apply: 5 4.8 4.6 4.4 ILOAD = 10 mA ILOAD = 1 A ILOAD = 2.5 A ILOAD = 3.5 A 4.2 4 3.8 4.5 4.75 5 VOUT = 5 V 5.25 5.5 5.75 Input Voltage (V) 6 6.25 5 4.8 4.6 4.4 ILOAD = 10 mA ILOAD = 1 A ILOAD = 2.5 A ILOAD = 3.5 A 4.2 4 3.8 4.5 6.5 fSW = 1000 kHz Auto Mode 5 5.25 5.5 5.75 Input Voltage (V) VOUT = 5 V Figure 53. LM76003 Dropout Curve 6 6.25 6.5 D029 fSW = 2200 kHz Auto Mode Figure 54. LM76003 Dropout Curve 5.6 12.4 5.4 12.2 12 Output Voltage (V) 5.2 Output Voltage (V) 4.75 D028 5 4.8 4.6 4.4 4.2 3.8 4.5 4.75 5 VOUT = 5 V 5.25 5.5 5.75 Input Voltage (V) 6 6.25 11.6 11.4 11.2 ILOAD = 100 mA ILOAD = 1 A ILOAD = 2.5 A ILOAD = 3.5 A 11 ILOAD = 100 mA ILOAD = 1 A ILOAD = 2.5 A 4 11.8 10.8 6.5 10.6 11.5 12 D030 fSW = 500 kHz Auto Mode VOUT = 12 V Figure 55. LM76002 Dropout Curve 12.5 13 13.5 Input Voltage (V) 14 14.5 15 D031 fSW = 500 kHz Auto Mode Figure 56. LM76003 Dropout Curve 25 Output Voltage (V) 24.5 VSW (5 V/DIV) 24 23.5 IINDUCTOR (500 mA/ DIV) 23 22 23.5 24 VOUT = 24 V 24.5 25 25.5 Input Voltage (V) 26 26.5 Time (1 ms/DIV) 27 D032 fSW = 300 kHz Auto Mode Figure 57. LM76003 Dropout Curve 36 VOUT (20 mV/DIV) ILOAD = 100 mA ILOAD = 1 A ILOAD = 2.5 A ILOAD = 3.5 A 22.5 VIN = 12 V No Load VOUT = 5 V fSW = 500 kHz Auto Mode Figure 58. LM76003 Switching Waveform and Output Ripple Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Unless otherwise specified the following conditions apply: VSW (5 V/DIV) VSW (5 V/DIV) IINDUCTOR (500 mA/ DIV) IINDUCTOR (500 mA/ DIV) VOUT (20 mV/DIV) VOUT (20 mV/DIV) Time (2 µs/DIV) VIN = 12 V No Load VOUT = 5 V Time (2 µs/DIV) fSW = 500 kHz FPWM Mode Figure 59. LM76003 Switching Waveform and Output Ripple VIN = 12 V 100-mA Load VOUT = 5 V fSW = 500 kHz Auto Mode Figure 60. LM76003 Switching Waveform and Output Ripple Enable (2 V/DIV) VSW (5 V/DIV) VOUT (2 V/DIV) IINDUCTOR (500 mA/ DIV) PGOOD (2 V/DIV) VOUT (20 mV/DIV) IINDUCTOR (2 A/DIV) Time (2 µs/DIV) VIN = 12 V 100-mA Load VOUT = 5 V Time (5 ms/DIV) fSW = 500 kHz FPWM Mode VIN = 12 V No Load Figure 61. LM76003 Switching Waveform and Output Ripple Enable (2 V/DIV) VOUT (2 V/DIV) VOUT (2 V/DIV) PGOOD (2 V/DIV) PGOOD (2 V/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) Time (5 ms/DIV) VOUT = 3.3 V fSW = 500 kHz Auto Mode Figure 62. LM76003 Start-up Waveform Enable (2 V/DIV) VIN = 12 V No Load VOUT = 3.3 V Time (5 ms/DIV) fSW = 500 kHz FPWM Mode Figure 63. LM76003 Start-up Waveform VIN = 12 V No Load VOUT = 5 V fSW = 500 kHz Auto Mode Figure 64. LM76003 Start-up Waveform Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 37 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Unless otherwise specified the following conditions apply: Enable (2 V/DIV) Enable (2 V/DIV) VOUT (2 V/DIV) VOUT (2 V/DIV) PGOOD (2 V/DIV) PGOOD (2 V/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) Time (5 ms/DIV) VIN = 12 V No Load VOUT = 5 V Time (5 ms/DIV) fSW = 500 kHz FPWM Mode VIN = 12 V 3.5-A Load Figure 65. LM76003 Start-up Waveform Enable (2 V/DIV) VOUT (2 V/DIV) VOUT (2 V/DIV) PGOOD (2 V/DIV) PGOOD (2 V/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) Time (5 ms/DIV) VOUT = 5 V Time (5 ms/DIV) fSW = 500 kHz VIN = 12 V No Load Figure 67. LM76003 Start-up Waveform Enable (2 V/DIV) VOUT = 5 V fSW = 500 kHz Auto Mode Figure 68. LM76002 Start-up Waveform Enable (2 V/DIV) VOUT (2 V/DIV) VOUT (2 V/DIV) PGOOD (2 V/DIV) PGOOD (2 V/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) Time (5 ms/DIV) VIN = 12 V 2.5-A Load VOUT = 5 V Time (5 ms/DIV) fSW = 500 kHz Figure 69. LM76002 Start-up Waveform 38 fSW = 500 kHz Figure 66. LM76003 Start-up Waveform Enable (2 V/DIV) VIN = 12 V 3.5-A Load VOUT = 3.3 V VIN = 12 V No Load VOUT = 5 V fSW = 500 kHz Auto Mode Figure 70. LM76003 Start-up With Pre-Biased Output Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Unless otherwise specified the following conditions apply: VOUT (1 V/DIV) Enable (2 V/DIV) VOUT (2 V/DIV) IINDUCTOR (2 A/DIV) PGOOD (2 V/DIV) VSW (5 V/DIV) IINDUCTOR (2 A/DIV) Time (5 ms/DIV) VIN = 12 V No Load VOUT = 5 V Time (50 ms/DIV) fSW = 500 kHz FPWM Mode Figure 71. LM76002 Start-up With Pre-Biased Output ILOAD (2 A/DIV) VIN = 12 V VOUT = 5 V fSW = 500 kHz Auto Mode Figure 72. LM76003 Short-Circuit Behavior With Hiccup ILOAD (2 A/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) VOUT (200 mV/ DIV) VOUT (200 mV/ DIV) Time (100 µs/DIV) VIN = 12 V VOUT = 3.3 V 10 mA to 3.5 A to 10 mA Time (100 µs/DIV) fSW = 500 kHz Auto Mode VIN = 12 V VOUT = 3.3 V 10 mA to 3.5 A to 10 mA Figure 73. LM76003 Load Transient ILOAD (2 A/DIV) fSW = 500 kHz FPWM Mode Figure 74. LM76003 Load Transient ILOAD (2 A/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) VOUT (200 mV/ DIV) VOUT (200 mV/ DIV) Time (100 µs/DIV) VIN = 12 V VOUT = 5 V 10 mA to 3.5 A to 10 mA Time (100 µs/DIV) fSW = 500 kHz Auto Mode Figure 75. LM76003 Load Transient VIN = 12 V VOUT = 5 V 10 mA to 3.5 A to 10 mA fSW = 500 kHz FPWM Mode Figure 76. LM76003 Load Transient Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 39 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Unless otherwise specified the following conditions apply: ILOAD (2 A/DIV) ILOAD (2 A/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) VOUT (200 mV/ DIV) VOUT (200 mV/ DIV) Time (100 µs/DIV) VIN = 12 V VOUT = 5 V 10 mA to 3.5 A to 10 mA Time (100 µs/DIV) fSW = 1000 kHz Auto Mode VIN = 12 V VOUT = 5 V 10 mA to 3.5 A to 10 mA Figure 77. LM76003 Load Transient ILOAD (2 A/DIV) Figure 78. LM76003 Load Transient ILOAD (2 A/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) VOUT (200 mV/ DIV) VOUT (200 mV/ DIV) Time (100 µs/DIV) VIN = 12 V VOUT = 5 V 10 mA to 3.5 A to 10 mA Time (100 µs/DIV) fSW = 2200 kHz Auto Mode VIN = 12 V VOUT = 5 V 10 mA to 3.5 A to 10 mA Figure 79. LM76003 Load Transient ILOAD (2 A/DIV) fSW = 2200 kHz FPWM Mode Figure 80. LM76003 Load Transient ILOAD (2 A/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) VOUT (500 mV/ DIV) VOUT (500 mV/ DIV) Time (100 µs/DIV) VIN = 24 V VOUT = 12 V 10 mA to 3.5 A to 10 mA Time (100 µs/DIV) fSW = 500 kHz Auto Mode Figure 81. LM76003 Load Transient 40 fSW = 1000 kHz FPWM Mode VIN = 24 V VOUT = 12 V 10 mA to 3.5 A to 10 mA fSW = 500 kHz FPWM Mode Figure 82. LM76003 Load Transient Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Unless otherwise specified the following conditions apply: ILOAD (1 A/DIV) ILOAD (1 A/DIV) IINDUCTOR (2 A/DIV) IINDUCTOR (2 A/DIV) VOUT (200 mV/ DIV) VOUT (200 mV/ DIV) Time (100 µs/DIV) VIN = 12 V VOUT = 5 V 10 mA to 2.5 A to 10 mA Time (100 µs/DIV) fSW = 500 kHz Auto Mode Figure 83. LM76002 Load Transient VIN = 12 V VOUT = 5 V 10 mA to 2.5 A to 10 mA fSW = 500 kHz FPWM Mode Figure 84. LM76002 Load Transient Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 41 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 9 Power Supply Recommendations The LM76002/LM76003 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LM76002 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LM76002/LM76003 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF or 100-µF electrolytic capacitor is a typical choice. 10 Layout 10.1 Layout Guidelines The performance of any switching converter depends as much upon the layout of the PCB as the component selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and minimum generation of unwanted EMI. 1. Place ceramic high frequency bypass CIN as close as possible to the LM76002/LM76003 PVIN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pins and PAD. 2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device ground. 3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB must be located close to the FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielding layer. 4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. Have a single point ground connection to the plane. Route the ground connections for the feedback, soft start, and enable components to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 5. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 6. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. 10.1.1 Layout Highlights 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout as shown in the figure above. The high current loops that do not overlap have high di/dt content that causes observable high frequency noise on the output pin if the input capacitor CIN is placed at a distance away from the LM76002/LM76003. Therefore, place CIN as close as possible to the LM76002/LM76003 PVIN and PGND pins. This minimizes the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized topside plane that connects to the PGND pin. 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 3. Minimize trace length to the FB pin net. Place both feedback resistors, RFBT and RFBB, close to the FB pin. Because the FB node is high impedance, maintain the copper area as small as possible. Route the traces from RFBT, RFBB away from the body of the LM76002/LM76003 to minimize possible noise pickup. Place Cff directly in parallel with RFBT. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a 42 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Layout Guidelines (continued) separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array (or greater) with a minimum via diameter of 12 mil thermal vias spaced 46.8 mil apart. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. 10.1.2 Compact Layout for EMI Reduction Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch, and then return to the ground of the input capacitors, as shown in Figure 85. BUCK CONVERTER VIN PVIN SW L VOUT CIN COUT PGND High di/dt current PGND Figure 85. Buck Converter High di / dt Path High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the PVIN and PGND pins is the key to EMI reduction. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current condution path to minimize parasitic resistance. The output capacitors should be place close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely grounded to PGND and the exposed PAD. 10.1.3 Ground Plane and Thermal Considerations TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are connected to the source of the internal LS switch; connect the PGND pins directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to load variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the ground plane. The other side of the ground plane contains much less noise — use for sensitive routes. Provide adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat sinking. Distribute the vias evenly under the PAD. Use as much copper as possible for system ground plane on the top and bottom layers for the best heat dissipation. TI recommends using a four-layer board with the copper thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness and proper layout provides low current conduction impedance, proper shielding and lower thermal resistance. The thermal characteristics of the LM76002/LM76003 are specified using the parameter RθJA, which characterize the junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 43 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com Layout Guidelines (continued) TJ = PD × RθJA + TA where • • • • • TJ = junction temperature in °C PD = VIN × IIN × (1 − efficiency) − 1.1 × IOUT × DCR DCR = inductor DC parasitic resistance in Ω RθJA = junction-to-ambient thermal resistance of the device in °C/W TA = ambient temperature in °C. (31) The maximum operating junction temperature of the LM76002/LM76003 is 125°C. RθJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow. Figure 86 shows measured results of RθJA with different copper area on a 2-layer board and a 4-layer board. 30 1W @0 fpm - 2layer 1W @0 fpm - 4layer 2W @0 fpm - 2layer 2W @0 fpm - 4layer 28 R,JA (°C/W) 26 24 22 20 18 16 14 12 10 20 30mm 30 × 30mm 40mm 40 × 40mm 50mm 50 × 50mm 60 70mm 70 ×70mm 80 Copper Area Figure 86. Measured RθJA vs PCB Copper Area on a 2-Layer Board and a 4-Layer Board 10.1.4 Feedback Resistors To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to the feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high value resistors are used to set the output voltage. TI recommends routing the voltage sense trace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in between the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage feedback path from switching noises. 44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 10.2 Layout Example Figure 87. Layout Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 45 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 10.3 Thermal Design When calculating module dissipation use the maximum input voltage and the average output current for the application. Many common operating conditions are provided in the characteristic curves such that less common applications can be derived through interpolation. In all designs, the junction temperature must be kept below the rated maximum of 125°C. For the design case of VIN = 12 V, VOUT = 5 V, IOUT = 3.5 A, fSW = 2100 kHz, and TAMAX = 85°C, the part must see a thermal resistance from exposed pad (case) to ambient (RθCA) RTCA < TJ-MAX TA-MAX PIC _ LOSS RTCA (32) The typical thermal impedance from junction to case is 1.7°C/W. Use the 125°C power dissipation curves in Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 3 W. The inductor losses must be subtracted from this number and can be estimated as: RTCA < 125qC 85qC 2.75 W 1.7qC/W < 12.84qC/W (33) To reach RθCA = 12.84°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink, a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal layers is: Board Area_cm2 d 500 qC u cm2 u RTCA W (34) As a result, approximately 38.95 square cm of 2 oz. copper on top and bottom layers is the minimum required area for the example PCB design. This is a 6.25 cm (2.45 inch) square. The PCB copper heat sink must be connected to the pins of the device and to the exposed pad with multiple thermal vias to the bottom copper. For an example of a high thermal performance PCB layout refer to AN-2020 Thermal Design By Insight, Not Hindsight and the evaluation board documentation. 46 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM76002 or LM76003 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 47 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 48 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 LM76002, LM76003 www.ti.com SNVSAK0 – OCTOBER 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 49 LM76002, LM76003 SNVSAK0 – OCTOBER 2017 www.ti.com EXAMPLE STENCIL DESIGN RNP0030B WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 8X (0.8) 27 30 8X (0.6) 22X (0.75) 1 26 31 30X (0.25) 8X (0.94) 26X (0.5) (5.8) SYMM (0.57) TYP (1.14) TYP METAL TYP 16 11 (R0.05) TYP 12 SYMM 15 (0.5) TYP (3.65) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 31: 74.3% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4222784/A 02/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com 50 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LM76002 LM76003 PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM76002RNPR ACTIVE WQFN RNP 30 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LM76002R NP LM76002RNPT ACTIVE WQFN RNP 30 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LM76002R NP LM76003RNPR ACTIVE WQFN RNP 30 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LM76003R NP LM76003RNPT ACTIVE WQFN RNP 30 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LM76003R NP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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