LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 LM4308 Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display Interface Master/Slave Check for Samples: LM4308 FEATURES DESCRIPTION • • • • • • • • • • • • • The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level. 1 2 • • • 18-bit i80 CPU Display Interface Supports up to 640 x 480 VGA Formats Differential SLVS Interface Dual Displays Supported WRITE and READ Operations Supported Robust Differential Physical Layer 400mVpp Differential Signal Swing Internal 100 Ω Termination Resistor Low Power Consumption 5-bit CRC for Data Integrity Level Translation between Host and Display Low Power Sleep State 3.3V Tolerant Master Clock Input Regardless of VDDIO Fast Start Up Time - 1k CLK Cycles 1.6V to 2.0V Core / Analog Supply Voltage 1.6V to 3.0V I/O Supply Voltage Range SYSTEM BENEFITS • • • • The differential line drivers and receivers conform to the JEDEC SLVS Standard. When noise is picked up as common-mode, it is rejected by the receivers. This is further enhanced with the 50 Ohm output impedance of the drivers. The 100 Ohm termination is integrated into the receivers. Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ operations. An Error (ERR) pin reports the occurrence of an error. A Write Only mode is also provided. The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost. A low power sleep state entered when the PD* inputs are driven low. Small Interface Low Power Low EMI Intrinsic Level Translation Memory Port (Display) 1.8V Typical Application Diagram Apps Processor --Graphics Processor --Baseband Processor CLK Tree LM4308 Master D[17:0] AD WR* RD* CS2* CS1* D[17:0] AD WR* RD* CS2* CS1* DD (other devices) DC ERR CLK PLLCON[1:0] LM4308 Slave Sub Display (Buffered) Optional GND PD* 1.8V PD* PWR 2.8V 1.8V Config. RDS[1:0] M/S* TM WO PWR GND M/S* TM (Bypass Caps not shown) Config. Main Display (Buffered) ERR PLL GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com Pin Descriptions Pin Name No. of Pads uArray Description No. of Pins WQFN I/O, Type (1) CPU Master (MST) IO, slvs Differential Data - Positive, Transceiver CPU Slave (SLV) SLVS SERIAL BUS PINS DDP 1 1 DDN 1 1 IO, slvs Differential Data - Negative, Transceiver DCP 1 1 O, I, slvs Differential Clock - Positive, Line Driver Differential Clock - Positive, Receiver DCN 1 1 O, I, slvs Differential Clock - Negative, Line Driver Differential Clock - Clock, Receiver Low for Slave CONFIGURATION/PARALLEL BUS PINS M/S* 1 1 I, LVCMOS High for Master TM 1 1 I, LVCMOS Test Mode Control Input Tie Low L = Normal H = Test Mode (factory test only) PLLCON[1:0] 2 2 I, LVCMOS PLL Multiplier Input Pins See Table 1 NA RDS[1:0] 2 2 I, LVCMOS NA Receiver Drive Strength Control Input Pins, See Table 2 ERR 1 1 O, LVCMOS Error Output Signal Indicates a CRC error on the READ Payload Error Output Signal Reports a CRC error was detected on the WRITE Payload WO 1 1 I, LVCMOS NA WRITE Only Control Input L = Writes and reads enabled H = Write Only NA CLOCK / POWER DOWN SIGNALS CLK 1 1 I, LVCMOS CLK Input Input is 3.3V Tolerant regardless of VDDIO PD* 1 1 I, LVCMOS Power Down Input, L = Powered down, Low Power SLEEP state H = active state PARALLEL INTERFACE SIGNALS D[17:0] 18 18 IO, LVCMOS CPU Data Bus Inputs / Outputs CPU Data Bus Outputs / Inputs CS1* CS2* 2 2 I, O, LVCMOS Chip Select Input Pins Only one CS is allowed to be Low at a time. Chip Select Output Pins RD* 1 1 I, O, LVCMOS Read Enable Input, active Low Read Enable Output, active Low WR* 1 1 I, O, LVCMOS Write Enable Input, active Low Write Enable Output, active Low AD 1 1 I, O, LVCMOS Address / Data selector input Address / Data selector output POWER/GROUND PINS (1) 2 VDDA 1 1 Power Power Supply Pin for the PLL (MST) and SLVS Interface. 1.6V to 2.0V VSSA 1 1 Ground Ground Pin for the PLL (MST) and SLVS Interface. VDD 1 1 Power Power Supply Pin for the digital core. 1.6V to 2.0V VSS 1 * Ground Ground Pin for the digital core. VDDIO 2 2 Power Power Supply Pin for the parallel interface I/Os. 1.6V to 3.0V VSSIO 9 * Ground Ground Pin for the parallel interface I/Os. For the WQFN Package, VSSIO and VSS Note: I = Input, O = Output, IO = Input/Output. Do not float input pins. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 Pin Descriptions (continued) Pin Name No. of Pads uArray No. of Pins WQFN DAP NA * 1 Description I/O, Type (1) CPU Master (MST) CPU Slave (SLV) Connect to Ground - WQFN Package Ground pin for VSSIO and VSS Table 1. PLLCON[1:0] - PLL Multiplier Settings PLLCON1 PLLCON0 Multiplier L L 8X L H 10X H L 12X H H Reserved Table 2. RDS[1:0] - Receiver Output Drive Strength RDS1 RDS0 Result L L Use with High VDDIO operation L H Increased drive on DATA, AD, and CS1*/CS2* outputs H L Increased drive on WR* and RD* H H All outputs, use for Low VDDIO, Increased drive strength on all outputs These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VDDA) −0.3V to +2.2V Supply Voltage (VDD) −0.3V to +2.2V −0.3V to +3.6V Supply Voltage (VDDIO) −0.3V to (VDDIO +0.3V) LVCMOS Input/Output Voltage −0.3V to +3.3V CLK LVCMOS Input Voltage −0.3V to VDDA SLVS Input/Output Voltage Junction Temperature +150°C Storage Temperature −65°C to +150°C ESD Ratings: ≥±2 kV HBM, 1.5 kΩ, 100 pF ≥±200V EIAJ, 0Ω, 200 pF Maximum Package Power Dissipation Capacity at 25°C NYC Package 2.75 W Derate NYC Package above 25°C 22 mW/°C RSB Package 3.43 W Derate RSB Package above 25°C (1) (2) 27 mW/°C “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. RECOMMENDED OPERATING CONDITIONS Min Typ Max Units VDDA to VSSA and VDD to VSS 1.6 1.8 2.0 V VDDIO to VSSIO 1.6 3.0 V Clock Frequency 9.6 30 MHz DC (Serial) Clock Frequency 76.8 240 MHz Ambient Temperature −40 85 °C Supply Voltage 25 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 3 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions (1) (2) Min Typ Max Units 140 200 270 mV -10 0 10 mV 150 200 250 mV -5 0 5 mV SLVS 100 Ω Load VOD Differential Output Voltage ΔVOD Differential Output Voltage Match VOS Driver Offset Voltage ΔVOS Driver Offset Voltage Match ROUT Driver Output Impedance VOH High Level Output Voltage (Diff. Mode) RT Receiver Differential Termination Resistor DD (RX) Configuration or DC (SLV) VIDH Differential Input High Threshold RX, VCM = 35mV, 200mV and 365mV VIDL Differential Input Low Threshold VCM Receiver Common Mode Input RX with VID = |70mV| Range See (3) See (3) High Output 50 Low Output 50 Ω Ω 360 mV 100 125 Ω 10 70 mV (4) 80 (3) −70 -10 35 mV 365 mV V LVCMOS VIH Input Voltage High Level 0.7 VDDIO VDDIO VIL Input Voltage Low Level GND 0.3 VDDIO VHY Input Hysteresis IIH Input Current High Level IIL Input Current Low Level VOH Output Voltage High Level VOL Output Voltage Low Level 160 LVCMOS Inputs VIN = VDDIO CLK Input VIN = 3.3V VDDIO = 1.8V CLK Input VIN = 1.8V VDDIO = 1.8V −1 (5) 0 0 V mV +1 µA +8 µA −1 0 +1 µA −1 0 +1 µA IOH = −2 mA RDS = H VDD = 1.6 V , VDDIO = 2.0 V 0.75 VDDIO VDDIO V IOH = −2 mA RDS = L VDD = 2.0 V , VDDIO = 3.0 V 0.8 VDDIO VDDIO V IOL = 2 mA RDS = H VDD = 1.6V , VDDIO = 2.0 V VSSIO 0.2 VDDIO V IOL = 2 mA RDS = L VDD = 2.0 V , VDDIO = 3.0 V VSSIO 0.2 VDDIO V SUPPLY CURRENT (1) (2) (3) (4) (5) 4 Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C. Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise specified. Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. When clock input is in overdrive ( Vin = 3.3 V ) and then stop clock is applied, it is recommended to set input clock to a low state. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol IDD Parameter Conditions Total Supply Current—Enabled Conditions: CLK = 30MHx (8X mode), DC = 240MHz, DD = 480Mbps Worse Case Data Pattern, constant WRITE Master Supply Current—Enabled Bus Idle (WR* = H) Master Slave (6) (6) Supply Current—Disable Power Down Modes PD Power Dissipation Max Units VDDIO 64 µA VDD/VDDA 18 mA VDDIO 18 mA 7 mA VDDIO 10 µA VDD/VDDA 8.2 mA VDDIO >1 µA VDD/VDDA 2.9 mA Master PD* = L, or CLK stop VDDIO 8 µA VDD/VDDA 9 µA Slave PD* = L, or Auto Sleep VDDIO 8 µA VDD/VDDA 9 µA 25% Bus active Master 15 mW Slave 6 mW Master 14.8 mW Slave 5.2 mW Master 195 µW Slave 8 µW Master >0.1 µW Slave >0.1 µW Idle Bus QVGA (7) PD*=L (6) (7) Typ VDD/VDDA Slave IDDZ Min For IDD measurements a checkerboard pattern 2AAAA-15555 was used. Typical PD for QVGA application. Conditions: 1.8V, 25C, 19.2MHz CLK and 8X, 10% blanking, 1fps. Link is started up, 1 frame (240 x 320) is sent and link is powered down. SWITCHING CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min (1) Typ Max Units PARALLEL BUS TIMING See also Table 5 and Figure 9 tSET Set Up Time tHOLD Hold Time tRISE Rise Time tFALL Master Input, WRITE 5 ns 5 ns RD* and WR* Slave VDDIO = 1.6V Outputs (2) RDS = H CL = 15 pF, Figure 2 VDDIO = 3.0V RDS = L Fall Time 7 ns 7 ns VDDIO = 1.6V RDS = H 7 ns VDDIO = 3.0V RDS = L 6 ns SERIAL BUS TIMING tDVBC Data Valid before DC Clock tDVAC Data Valid after DC Clock tSset Serial Set Time tShold Serial Hold Time tT Transition Time (1) (2) (3) (4) Master Slave (3) (4) 26% 74% UI 26% 74% UI 400 ps 400 Master 20% to 80% ps 200 ps Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C. Rise and Fall Time tested on the following pins only: WR* and RD*. Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 5 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com SWITCHING CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units POWER UP TIMING ta DC ON High Delay tb DC Low Delay tc DC Active Delay td DD High Delay te DD Low Delay tf DD Differential ON tSU Start Up Delay Includes PLL Lock Time Link Start Up Sequence ta +tb + tc + td + te + tf 128 CLK cycles 128 CLK cycles 504 CLK cycles 128 CLK cycles 8 CLK cycles 128 CLK cycles 1,024 CLK cycles POWER OFF TIMING tO (5) Turn Off Delay See (5) 0.1 2 µs Typ Max Units 30 MHz 104.2 ns Specified functionally by the IDDZ parameter. See also Figure 7. RECOMMENDED INPUT TIMING REQUIREMENTS Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min (1) MASTER REFERENCE CLOCK (CLK) f Clock Frequency 9.6 tCP Clock Period 33.3 CLKDC Clock Duty Cycle tT Clock/Data Transition Times tCLKgap CLK Stop Gap (1) (2) 6 (Rise or Fall, 10%–90%) (2) 30 50 2 >2 4 70 % ns CLKcycles Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C. Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 TIMING DIAGRAMS Master Serial Out DC DD tDVBC tDVAC 50% tDVBC tDVAC 50% 1UI Slave Serial In DC DD tShold tSset tShold tSset Figure 1. Serial Data Valid & Set/Hold Times VDDIO 80% SLV Outputs 20% 0V tFALL tRISE Figure 2. Slave Output Rise and Fall Time (WR* and RD*) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 7 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION BUS OVERVIEW The LM4308 is a Master (SER) / Slave (DES) configurable part that supports a 18-bit (or less) i80 CPU Display interface. Both WRITE and READ transactions are supported. The SLVS physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termination is provided internal to the SLVS receiver. A maximum raw throughput of 480 Mbps (raw) is possible with this chipset. The SLVS interface is designed for use with 100Ω differential lines. LM4308 SLV LM4308 MST DD DC GND Figure 3. SLVS Point-to-Point Bus SERIAL BUS TIMING Data valid is relative to both edges for a CPU WRITE as shown in Figure 4. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps. DC (Diff.) DD (Diff.) Figure 4. Serial Link Timing (WRITE) Data is strobed out on the Rising edge by the Slave for a CPU READ as shown in Figure 5. The Master monitors for the start bit transition (High to Low) and then selects the best strobe to sample the incoming data on. This is done to account for the round trip delay of the interconnect and application data rate. Since READ data is sent on one edge only, the back channel rate (READ) is one quarter that of the WRITE rate. DC (Diff.) DD (Diff.) Figure 5. Serial Link Timing (READ) SERIAL BUS PHASES There are five bus phases on the serial bus. These are determined by the state of the DC and DD lines. The bus phases are shown in Table 3. 8 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 Table 3. Link Phases (1) DC State DD State OFF (O) Name GND GND IDLE (I) A H Idle, MD(s) = Logic Low A or LU A or O ACTIVE (A), Write A X Write Payloads LU, A, or I A, I, or O ACTIVE, Read Read Command A X (MST) Read Command A, or I TA’ A HUH MD Turn Around RC RD Read Data A X (SLV) Read Payload TA’ TA" TA" A HUH MD Turn Around RD I Master * * O A, I, or O LINK-UP (LU) (1) Phase Description Pre-Phase Post-Phase A, I or LU LU Link is Off Start Up Notes on DC/DD Line State: 0 = no current (off) SERIAL BUS START UP TIMING The DC and DD lines are held at a LVCMOS Low state in the Sleep state (PD* = L). When the PD* signal is switched to a High state the DC lines are pulsed. Next the DC lines are driven to the differential levels and the clock signal is active. The DD lines are then pulsed from a LVCMOS Low state, then driven to a valid differential static High state. Data transmission (WRITE) starts with a valid Low start bit on the DD signal. Bus Phase Link Off Link Up Idle Active Idle Power H PD* L H CLK L DCP (SE Waveform) DCN (SE Waveform) DC (DIFF) DDP (SE Waveform) DDN (SE Waveform) td ta DD (DIFF) tb tf te tc tSU Figure 6. Serial Bus Power Up Timing Actual start up time is clock rate dependant. The 1024 CLK counter encompasses both the SLVS start up delay and PLL Lock Time. At 19.2MHz operation, the link is ready for transmission after only 54 µs. Do not WRITE to either display before the serial link start up delay has expired. Table 4. Start Up Time vs. CLK Frequency CLK FREQ Start Up Delay 9.6MHz 106.7 µs 19.2MHz 53.3 µs 30MHz 34.13 µs Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 9 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com OFF PHASE In the OFF phase, differential transmitters are turned off and the lines are both driven to Ground. Figure 7 shows the transition of the serial bus into the OFF phase. The link may be powered down by asserting Master and Slave PD* pins, the Master PD* pin alone or stopping the clock . To avoid loss of data the clock input should only be asserted after the serial bus has been in the IDLE state for at least 100 DC clock cycles. This also applies to when Master’s PD* input is asserted. The 100 DC clock cycles give the Slave enough time to complete any write operations received from the serial bus. Do not asserted the Slave PD* pin alone, as this will not reset the link properly. If the Slave PD* pin is asserted, the Master’s PD* must also be asserted to generate a proper start up sequence. Bus Phase Idle Active Link Off Idle H PD* L DCP (SE Waveform) DCN (SE Waveform) DC (DIFF) DDP (SE Waveform) DDN (SE Waveform) DD (DIFF) tO Figure 7. Serial Bus Power Down Timing I80 CPU INTERFACE COMPATIBILITY The CPU Interface mode provides compatibility between an i80 CPU Interface and a small form factor (SFF) Display or other fixed I/O port application. Both WRITE and READ transactions are supported. READs require a dual access on the Master to complete the operation. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 DC DD L AD R/W* CS12 D15 D16 D0 D17 D1 C0 D2 C1 D3 C2 D4 C3 D5 C4 D6 D7 D8 D9 D10 D11 D12 D13 D14 H idle Figure 8. WRITE Transaction WRITE TRANSACTION The WRITE transaction consists of 14 DC cycles to send the control, data and CRC information on the DD signal. This includes the Start Bit, AD, R/W*, CS12, D[0:17], CRC bits C[0:4] and a reserved bit (High). See Figure 8. The data payload is sent least significant bit (LSB) first. The CS1/2 bit denotes which Chipset pin was active. CS1/2 = HIGH designates that CS1* is active (Low). CS1/2 = LOW designates that CS2* is active (Low). CS1* and CS2* Low is not allowed. The AD carries the information on the AD input signal. The R/W* will be Low for a Write transaction. Figure 9 illustrates a WRITE transaction showing Master Input, SLVS, and Slave output timing. Table 5 lists the WRITE timing parameters. On the Master input, an i80 style WRITE is shown. The ChipSelect (CS1* or CS2*) is Low. The WR* goes Low, and Data and AD signals are sampled on the rising edge of the WR* signal. A tight set and hold window is required as shown by T1 and T2. A Latency delay later (T4) the SLVS start bit will be transmitted on the DD signal. Since it takes 14 DC cycles to send the serial word, a maximum load rate on the Master input should be slower than this (16 DC cycles or longer). This is T3 in Figure 9. The Slave output timing is shown in the bottom of Figure 9. Note that the SLV output timing is different than the MST input timing, however the same information is conveyed. T5 is the latency delay of the Slave and also the serial payload length. Once the start bit is received, it will take this long for the SLV output to update. First, the Data[0:17], AD and CS* bits will update as required. One DC cycle later the WRITE signal will transition Low for 12 DC cycles. Then the WRITE signal will transition High and the Display will latch the data. There is a minimum hold time of one DC cycle (T9). This hold time can (will) be longer as the outputs hold their last state until the next transition is received. Also note that the CS1* and CS2* signals also hold their last state until they need to change. This would occur if a transaction is received for the other CS* signal, or if the Slave enters Power Down (PD*=L). Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 11 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com DATA[17:0] AD T1 T2 MASTER INPUT T3 WR* CS1* or CS2* other CS*=H RD* T4 T5 DC DD 14 DC DATA[17:0] AD SLAVE OUTPUT T6 WR* T7 RD* T8 T9 CS1* or CS2* other CS* = H Figure 9. WRITE Waveforms Table 5. i80 CPU WRITE Interface Parameters No. 12 Parameter Min Typ Max Units T1 MasterIN Data and address Setup Time before Low-High Edge 5 T2 MasterIN Data and address Hold after Low-High Edge 5 T3 MasterIN Bus Cycle Rate 16 DC Cycles T4 Master Master Latency 7 DC Cycles T5 Slave Slave Latency 15 DC Cycles T6 SlaveOUT Data Valid before WR* High-Low 1 DC Cycles T7 SlaveOUT WR* Low Pulse Width 12 DC Cycles T8 SlaveOUT Data Valid before WR* Low-High, 13 DC Cycles T9 SlaveOUT Data Valid after WR* Low-High 1 DC Cycles Submit Documentation Feedback ns ns Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 READ TRANSACTION The READ transaction is similar to the WRITE but longer. The full serial READ transaction is shown in Figure 10 . CRC bits protect both the READ command sent from the Master to the Slave (C[0:4] bits), and also the Data sent back from the Slave to the Master (RC[0:4] bits). The READ transaction consists of four sections. In the first section the Master sends a READ Command to the Slave. This command is the same as a WRITE, but the R/W serial bit is set High and the data payload is ignored. The CRC bits are used to ensure that the transaction is valid and prevents a false READ from being entered. The Control Input "Write Only - WO" on the Slave must be set to WRITE & READ mode (Low) to support READ transactions. In the second section (TA') the DD line is turned around, such that the Master becomes the DD Receiver and Slave becomes the DD Line Driver. The Slave will drive the DD line High after a fixed number of DC cycles. This ensures that the DD lines are a stable High state and that the High-to-Low transition of the "Start" bit is seen by the Master. The third section consists of the transfer of the read data from the Slave to the Master. Therefore the back channel data signaling rate is ¼ of the forward channel (Master-to-Slave direction). When the Slave transmits data back to the Master, it drives the DD line Low to indicate start of read data, followed by the actual read data and CRC payload. The fourth and final section (TA") occurs after the read data has been transferred from the Slave to the Master. In the fourth section the DD line is again turned around, such that the Master becomes the transmitter and the Slave becomes the receiver. The Slave drives the DD line High for 1 bit and then turns off. The DD lines are OFF momentarily to avoid driver contention. The Master then drives the DD line High for 1 bit time and then idles the bus until the next transaction is sent (WRITE or another READ). DC A a r DD c c c c c c h TA' Read Command A B h l l l l RD0 RD1 TA' RD2 RD3 RD4 RD5 Read Data B C RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RD16 RD17 RCRC0 Read Data C RCRC1 RCRC2 RCRC3 Read Data RCRC4 h TA" IDLE, Write or READ Figure 10. READ Transaction The READ transaction requires a dual cycle on the Master input to complete. Once the first READ is done (RDCycle1) the serial link is busy until the second READ (RDCycle2) is done. The Host may do transactions to other devices between the READs, just not to CS1* or CS2*. On the first READ, the CS1* or CS2* line is driven low and the RD* pulses low. A fixed Data Word of all Lows is returned and should be ignored by the Host. The requested data will be available at the Master after 480 DC cycles. The second READ should now be done to collect the requested data. Upon the READ from the host, the Master will turn ON its 18 data drivers and output the data to the Host and then turn them off. When the READ is received, the Data output buffers turn off to avoid contention. After 140 DC cycles the RD* signal switches Low. It then switches High after another 62 DC cycles and latches in the Data from the Display. The CRC is then calculated and sent to the Master. To avoid floating the inputs to the Display, the Slave data outputs are turned back on. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 13 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com DATA LOW DATA VALID DATA[17:0] AD T1 T2 T4 MASTER INPUT T3 RD* CS1* or CS2* other CS*=H WR* RDcycle1 RDcycle2 T5a T5 DC X SLV Outputs Update Data, AD, CS1*, CS2* as needed DD Figure 11. Master Input READ Timing SLV ON SLV ON Display Driver ON T8 DATA[17:0] T9 T10 AD SLAVE OUTPUT RD* T6 T7 WR* CS1* or CS2* other CS* = H Figure 12. Slave Output READ Timing Table 6. i80 CPU READ Interface Parameters No. 14 Parameter Min Typ Max Units T1 MasterOUT Data and address valid after RD* High-to-Low 15 ns T2 MasterOUT Data and address valid after RD* Low-to-High T3 MasterIN Delay Time Between READs 500 0 ns ns T4 MasterIN Delay Time Until Data Available (RDcyc2) 480 ns T5 Master Master Latency 7 DC Cycles T5a Slave Slave Latency, (not shown) 158 DC Cycles T6 Slave AD Set Time before RD* High-to-Low 140 DC Cycles T7 Slave RD* Pulse Low Width 62 DC Cycles T8 Slave Data Set Time 7 DC Cycles T9 Slave Data Hold Time 0 ns T10 Slave Slave Data Outputs 8 DC Cycles Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 SLAVE OUTPUT TIMING / DISPLAY COMPATIBILITY Compatibility of target device’s timing requirements should be checked. Check that the Slave WR* active low pulse is wide enough for the target display(s). If the Slave output is too fast, a slower DC rate should be chosen (PLL setting or CLK rate may be adjusted). See SYSTEM CONSIDERATION section also. Figure 13 illustrates the timing of two writes being sent to CS1*. Note that on the Slave output for Word N, that the DATA, AD, and CS signals hold their last state until the next transaction is received. This effectively extends the Hold time after Word N’s WRITE rise. The length of this period (idle) is determined by the time until the next transaction on the Master input. When the second write is received (Word N+1) the Data, AD, and CS signals update as needed. Note that the active CS signal stay low until a transaction to the other CS is received or the Slave is put into powerdown. MASTER INPUT Word N to CS1* Word N+1 to CS1* DATA[17:0] AD RD* WR* CS1* CS2* SERIAL DC DD L L SLAVE OUTPUT DATA[17:0] AD CS1* CS2* WR* RD* Word N idle Word N+1 idle Figure 13. Timing Example - Two WRITEs to CS1* CYCLIC REDUNDANCY CHECK (CRC) The CRC is used to detect errors in both WRITE and READ transactions on the serial link. The LM4308 uses a 5-bit CRC field to detect errors in the 22-bit payload. The Transmitting device calculates the CRC and appends it to the payload. The Receiver also calculates the CRC and compares it to the received CRC. If they are the same, the transmission is error free. If they are different, the ERR pin then flags the error. CRC provides a better coverage than a parity bit, which can only flag one half of the possible errors. The CRC is calculated by taking the payload and adding 5 zeros and then dividing by a fixed number. The remainder of the calculation is the 5-bit CRC field that is transmitted. If a CRC error handling is shown in the table below. See also Figure 14. Table 7. CRC Error Response Operation Direction Error Response Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 15 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com Table 7. CRC Error Response (continued) Write Master-to-Slave CRC error Slave Flags, ERR pins remains High until PD* cycle or Power cycle, Data is written to the display Read Command Master-to-Slave CRC error Slave Flags, ERR pins remains High until PD* cycle or Power cycle, Slave does nothing Write Master-to-Slave, Slave WO = H CRC error, Serial R/W* bit error (False Read) Slave Flags, ERR pins remains High until PD* cycle or Power cycle, Data is written to the display (write expected) Read Data Slave-to-Master CRC error Master Flags, ERR goes High, then Low after 2nd READ, Data = X Read Data Slave-to-Master Read Data not received by Master Master times out, drives all Low data, then on 2nd READ cycle ERR goes High DATA, AD, CS (SLV) ERR Slave WRITE WR*(SLV) ERR(SLV) RD*(Host) ERR Master READ DATA (MST) ERR(MST) 1 = CS1* active which is a High, and 2 = CS2* active which is a Low Figure 14. CRC - ERR Output Timing SLVS INTERFACE Scalable Low Voltage Signaling is the differential interface used for the physical layer of the serial (Data and Clock) signals. The differential signal is a 200mV (typ) swing with a 200mV offset from ground. This generates a ±200mV (400mVpp) across the integrated termination resistor for the receiver to recover. The receiver detects the differential signal and converts it to a LVCMOS signal. Noise picked up along the inteconnect is seen as common-mode by the receiver and rejected. The low output impedance of the line driver and of the termination network help to minimize couple noise also. 16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 mV P 300 Single-Ended 200 100 N +200 mV P-N 0V Differential -200 mV Figure 15. Single-ended and differential SLVS waveforms Noise that gets coupled onto both signals, is common-mode and is rejected by the receiver. Route the traces that form the pair together (coupled) to help ensure that noise picked up is common. Differential noise that causes a dip in the signal but does not enter the threshold region is also rejected. Differntial noise margin is the minimum VOD signal minus the MAX threshold voltage. 140mV - 70mV = 70mV minimum differential noise margin. mV 300 P 100 N Single-Ended 0V Differential (P-N) Figure 16. SLVS common-mode rejection waveform LM4308 Features and Operation POWER SUPPLIES The VDD and VDDA (MPL-2 and PLL) must be connected to the same potential between 1.6V and 2.0V. VDDIO powers the logic interface and may be powered between 1.6 and 3.0V to be compatible with a wide range of host and target devices. BYPASS RECOMMENDATIONS Bypass capacitors should be placed near the power supply pins of the device. Use high frequency ceramic (surface mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tantalum capacitor is recommended near the Master VDDA pin for PLL bypass. Connect bypass capacitors with wide traces and use dual or larger vias to reduce resistance and inductance of the feeds. Utilizing a thin spacing between power and ground planes will provide good high frequency bypass above the frequency range where most typical surface mount capacitors are less effective. To gain the maximum benefit from this, low inductance feed points are important. Also, adjacent signal layers can be filled to create additional capacitance. Minimize loops in the ground returns also for improved signal fidelity and lowest emissions. MASTER / SLAVE CONFIGURATION The LM4308 device can be configured to be a Master or a Slave with the M/S* pin. For normal modes, TM (Test Mode) input must also be Low, setting TM High enters a factory test mode. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 17 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com UNUSED/OPEN LVCMOS PINS Unused inputs must be tied to the proper input level — do not float them. Unused outputs should be left open to minimize power dissipation. LVCMOS MASTER INPUT PINS CPU Interface input pins (Data, AD, CS, WR, RD) accept voltages from -300mV to (VDDIO + 300mV). Inputs are not High-Z with power supplies OFF. If communication between the Host (i.e. BBP) and other devices (i.e. Memory) is required when the display is not ON; the power to the Master must be ON, and the Master should be in SLEEP mode (by CLK Stop or PD*=L). In this condition, Master inputs are High Z and will not load (or clamp) the shared bus signals. Master inputs are not in a High Z state when Master VDDIO = 0V. MASTER CLOCK INPUT The Master Clock input is a special 3.3V Tolerant input pin. This allows the clock tree to be powered from a different VDDIO than the CPU interface from the host device. PLLCON1 PLLCON0 Multiplier 0 0 8 CLK Range 9.6 to 30 MHz 0 1 10 9.6 to 24 MHz 1 0 12 9.6 to 20 MHz 1 1 Reserved Reserved PHASE-LOCKED LOOP When the LM4308 is configured as a Master, a PLL is enabled to generate the serial link clock. The Phaselocked loop system generates the serial data clock at several multiples of the input clock. The DC rate is limited to 240 MHz. The PLL multiplier is set via the PLLCON[1:0] pins. Multipliers of 8X, 10X and 12X are available. For example, if the input clock is 19.2MHz, and a 8X multiplier is selected, DC will be 153.6 MHz. and the DD line rate is 307.2 Mbps (raw bandwidth). POWER DOWN OUTPUT STATES When the device is in the SLEEP state (PD*=L) the output pins will be driven to the states shown in the table below. Device Signal State in Power Down Slave Data[17:0] Low Slave CS1*, CS2*, WR*, RD*, AD High Slave ERR Low Master ERR Low SLAVE Upon application of power to the SLV device, all outputs are turned on and held in their de-asserted states. MASTER Upon application of power to the MST device, the ERR output is ON, and is logic low (normal mode). SLEEP MODE OPTIONS The Master can enter sleep mode by three options. The PD* pin is driven low, the clock input is stopped, or if the power supplies are turned off. The simplest option is a control signal to drive the PD* input. When PD* input is driven low, the device enters a sleep mode and supply current is minimized. This mode also supports high-Z Master LVCMOS inputs. The second option is with Power ON, PD* = H, and the CLK input is stopped. The CLK stop state is recommend to be logic Low. The Master detects this state and enters the sleep state. The third option is to cut power to the device. In this configuration the LVCMOS inputs are not High-Z due to internal diodes for ESD protection. 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 There are also three options for the Slave to enter the sleep state. These are: based on the MPL-2 interface, the Slave PD* input pin, and by powering off the Slave device. With power ON, and the Slave PD* input = H, the Slave detects the state on the MPL-2 bus and powers up or enters sleep mode. Direct control of the Slave is also possible by the use of its PD* input pin (relative to the Slave’s VDDIO levels). The third option is to turn off power to the Slave. In this configuration, do not enable and activate the Master outputs without the Slave also being ON. SLAVE OUTPUT DRIVE STRENGTH CONTROL The Slave Outputs have two drive strength options to support a wide range of VDDIO operation. See Table 2. If the SLV VDDIO is 1.8V TYP, RDS0 and RDS1 should be set to a logic High. Depending upon application speed, RDS0 can be set to a logic Low to soften the edge rate on the Data signals for less noise. For high VDDIO operation (i.e. 2.8V), both RDS0 and RDS1 should be set to a logic Low. SLAVE WRITE ONLY MODE In some applications, only WRITE operations may be required. In this case, the Slave can be configured to only support WRITE transactions by setting the WO configuration input High. Application Information SYSTEM CONSIDERATIONS DUAL SMART DISPLAY APPLICATION A Dual Smart Display application is shown in Figure 17. The Master (MST) resides by the host and connects to a Memory Interface. VDDIO on the MST is set to be the same as the Host’s port. i80 CPU Bus signals are connected as shown (Data, AD, WR*, RD*, and CS* signals). The Master also has a SLEEP mode to save power when the display is not required. The Sleep state is entered when the PD* signal is driven Low. It is also entered if the PD* signal is High and the CLK input is gated off (held at a static state). In the Sleep state, supply current into the Master is >1µA typical. In this state, (Power ON, and Sleep state), the Master inputs will not load the shared bus, and communication between the host and other devices may occur. If power is OFF (VDDIO = 0V), Master input ESD diodes will clamp the bus, preventing communication on the bus. The Master requires a system clock reference which is typically 19.2MHz in CDMA applications. This signal is used to generate the serial DC clock. The CLK input is multiplied by the selected PLL multiplier to determine the serial clock rate. In the 19.2MHz CLK and 8X application, the DC rate will be 153.6MHz. Due to the serial transmission scheme using both clock edges, the raw bandwidth of a WRITE is 307.3 Mbps. The Master also provides a ERR pin that reports a CRC error on a READ transaction. The host may monitor this signal if desired, or it may be brought out to a test point only. Several configuration pins are also required to be set. For a Master, tie M/S* = H, TM = L, and PLLCON[1:0] to the desired setting. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 19 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com LM4308 (Master) E1 E2 F1 F2 G1 G2 F3 G3 G5 F5 G6 F6 G7 F7 E6 E7 D6 C7 BaseBand Processor VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 C1 A1 D2 C2 A2 WR* A/D RD* CS2 CS1 A3 PD* VDDA VDDIO DDP_M DDN_M DCP_M DCN_M ERR VSS VSSA VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O 1.8V CLK Tree B1 B7 B6 B2 MS* CLK PCON1 PCON0 TM Notes: 1. PCON1, PCON0 = Low = x 8 Mode 2. Bypass Capacitor Values : C1, C2 = 4.7 PF C3 = 2.2 PF C4 = 0.1 PF B5 C3 D7 D1 C4 C3 A7 A6 A4 A5 C6 F4 B4 C3 C4 C5 D3 D4 D5 E3 E4 E5 VDDA C2 D7 D1 VDD C1 B5 C2 VDDIO LM4308 (Slave) 1.8V G4 C1 (Other Devices) B3 1.8V G4 A4 A5 A7 A6 F4 B4 C3 C4 C5 D3 D4 D5 E3 E4 E5 VDDIO VDDIO DDP_S DDN_S DCP_S DCN_S VSS VSSA VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O VSSI/O D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 WR* A/D RD* CS1 CS2 E1 E2 F1 F2 G1 G2 F3 G3 G5 F5 G6 F6 G7 F7 E6 E7 D6 C7 Main Display (Buffered) C1 A1 D2 A2 C2 Sub Display (Buffered) Optional 1.8V RDS0 RDS1 WO ERR PD* TM MS* B6 B7 B1 C6 A3 B2 B3 Notes: 1. RDS0 and RDS1 are VDDIO dependent. If/When VDDIO = 3.0V, RDS0 and RDS1 should be strapped low. 2.Bypass Capacitor Values : C1,C2 = 4.7 PF C3 = 0.1 PF Figure 17. Dual SMART Display Application The Slave recovers the serial signals and generates the parallel bus for the Display(s). The Slave VDDIO is set to be compatible with the Displays employed. The Data bus signals are bidirectional to support both WRITEs and READs. The other signals. AD, WR*, RD*, and CS* signals are outputs only. The connection between the Slave device and the displays should be done such that long stubs are avoided. Extra care should be taken on the WR* and RD* signal layouts as these signals rely on the signal edges to latch the data. The Slave has user adjustable edge rate controls for the parallel bus outputs. This can be used to optimize the edge rate vs the required VDDIO magnitude. Also, independent control of the strobe (WR* and RD*) is supported. This allows for the strobe signal to retain sharp edges, while using softer edges on the wide parallel data bus signals. This aids in noise reduction. The Slave also provides a ERR pin to flag any CRC errors detected. This signal maybe routed back to the host for monitoring, or bought out to a test point. The Slave supports a WRITE ONLY mode (READ operation and serial bus turn around is prevented). This mode is obtained by setting the WO pin to a logic High. The Sleep state of the display may be entered by driving the PD* signal to a logic Low. Outputs are then set to their Power Down de-asserted states. Several configuration pins are also required to be set. For a Slave, tie M/S* = L, TM = L, and WO and RDS[1:0] to the desired setting. If only one display is required in the application, the unused CS output signal should be left un-connected. In this application, WRITEs and READs for the Displays are serialized and sent to the displays. Transaction to other devices on the shared bus (MST input) are ignored by the Master. SYSTEM TIMING CONSIDERATIONS When employing the SERDES chipset in place of a parallel bus, a few system considerations must be taken into account. Before sending commands (i.e. initialization commands) to the display, the SERDES must be ready to transmit data across the link. The serial link must be powered up, and the PLL must be locked. Also, a review of the Slave output timing should be completed to insure that the timing parameters provided by the Slave output meet the requirements of the LCD driver input. Specifically, pulse width on WR* and RD*, data valid time, and bus cycle rate should be reviewed and checked for display compatibility. Additional details are provided next: 20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 The serial link should be started up as follows: The chipset should be powered. During power up, the PD* inputs should be held Low and released once power is stable and within specification and link transmission is desired. Before data can be sent across the serial link, the link must be ready for transmission. The CLK needs to be applied to the MST, and the PLL locked. This is controlled by a keep-off counter set for 1024 CLK cycles. After the PLL has locked and the counter expired, transmission may now occur. For a 19.2MHz application is is less than 54µs delay. If a WRITE is done to the display during this time, it will be lost and the display may not be properly configured. Ensure that the FIRST WRITE to the display is done AFTER the link is ready for transmission. It takes 14 DC Cycles to send a 18-bit CPU Write including the serial overhead. The DC cycle time is calculated based on the PLL Multiplier setting and also the input clock frequency. For example, a 19.2 MHz input CLK and a 8X PLLCON[1:0] setting yields a DC frequency of 153.6 MHz. Thus it takes ∼100 ns to send the word in serial form. To allow some idle time between transmissions (this will force a bit sync per word if the gap is long enough in between), the load rate on the Master input should not be faster than 16 DC cycles, or every 105 ns (9.6 MT/s) in our example to support a data pipe line. This is sometimes referred to as the bus cycle time (time between commands). Thus the time between WRITEs on the Master Input MUST NOT be faster than 105 ns, otherwise the FIFO will overflow and data will be lost. The Slave output WR* and RD* timing is a function of DC cycles alone. The width of the WR* pulse low is TWELVE DC cycles regardless of the pulse width applied to the Master input. In the 19.2MHz & 8X application, the WR* pulse low will be 78 ns. System designers need to check compatibility with the display driver to ensure that this pulse width meets its requirement. If it is too fast, select a lower PLL Multiplier or apply a slower input clock. PCB LAYOUT – SERIAL SIGNALS The LM4308 provides a swap function of SLVS DD and DC lines depending upon the state of the M/S* pin. This facilitates a straight through via-less SLVS interface design eliminating the needs for via and crossovers as shown on Figure 18. It is recommended to use separate logic symbols for the Master and the Slave to avoid layout errors. NOTE THE PINOUT IS DIFFERENT FOR A MASTER AND SLAVE CONFIGURED DEVICE. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 21 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com PD* CS1* AD MASTER CLK CS2* WR* RD* SLAVE D0 ERR D1 D17 D2 A D3 D16 1 D4 D15 TOP VIEW D14 D5 D13 D6 D12 D7 D8 D11 7 DC D10 D9 D9 D10 D8 DD D11 D7 D12 D6 D13 7 D5 D4 D14 D15 D3 D16 D2 1 D17 ERR D1 A D0 WR* CS2* Notes: Static and Supply signals not shown. Inner row may also use via in escape. AD CS1* PD* Figure 18. SLVS Interface Layout FLEX CIRCUIT RECOMMENDATIONS A differential 100 Ohm transmission path will yield the best results and be matched to the integrated differential termination resistance. Also, the interconnect should employ a coupled lines to ensure that the majority of any noise pick up is common-(equal on both the P and N signals) so that it is rejected by the differential receiver. A GSSGSSG pinout is recommended. Depending on external noise sources, shielding maybe required. GROUNDING Even though the serial Data and Clock signals are differential, a common ground signal is still required. This provides a common ground reference between the devices and a current return path for the common mode current. GENERAL GUIDELINES and RECOMMENDATIONS FOR PCB DESIGN LVCOMS Signals: • To reduce EMI, avoid parallel runs with fast edge, large LVCMOS swings. • To reduce crosstalk allow enough space between traces. It is recommended to distance the centers of two adjacent traces at least four times the trace width. To improve design performance, lower the distance between the trace and the ground plane to under ~ 10 mils. • Keep clock trace as straight as possible. Use arc-shaped traces as an alternative to the right-angle bends. • Do not use multiple signal layers for clock signals. • Do not use vias in clock transmission lines, as vias can cause impedance change and reflection. SLVS Signals: • Floor plan, locate Master near the connector to limit chance of cross talk to high speed serial signals. • Use differential routing techniques. (i.e., match the lengths as well as the turns that each trace goes through) • Keep the length of the two differential traces the same to minimize the skew and phase difference. • Route serial traces together, minimize the number of layer changes to reduce loading. 22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com • • • • • • • SNLS225C – AUGUST 2007 – REVISED MAY 2013 Use ground lines are guards to minimize any noise coupling (specifies distance). Avoid using multiple vias to reduce impedance mismatch and inductance. Use a GSSGSSG pinout in connectors (Board to Board or ZIF). Bypass the device with MLC surface mount devices and thinly separated power and ground planes with low inductance feeds. High current returns should have a separate path with a width proportional to the amount of current carried to minimize any resulting IR effects. Slave device - follow similar guidelines. see AN-1126 (SNOA021) (BGA) and AN-1187 (SNOA401) (WQFN) also Connection Diagram csBGA Package Ball A1 A B C D E F G 1 2 3 4 5 6 7 Figure 19. TOP VIEW (not to scale) Note that the pinout of a MASTER configured device is DIFFERENT than a SLAVE configured device. The use of two logic symbols for PCB schematic is recommended. Table 8. CPU Master Pinout MST 1 2 3 4 5 6 7 A AD CS1* PD* DCP_M DCN_M DDN_M DDP_M B CLK TM M/S* VSSA VDDA PLLCON0 PLLCON1 C WR* CS2* VSSIO VSSIO VSSIO ERR D17 D VDDIO RD* VSSIO VSSIO VSSIO D16 VDDIO E D0 D1 VSSIO VSSIO VSSIO D14 D15 F D2 D3 D6 VSS D9 D11 D13 G D4 D5 D7 VDD D8 D10 D12 Table 9. CPU Slave Pinout SLV 1 2 3 4 5 6 7 A AD CS1* PD* DDP_S DDN_S DCN_S DCP_S RDS1 B WO TM M/S* VSSA VDDA RDS0 C WR* CS2* VSSIO VSSIO VSSIO ERR D17 D VDDIO RD* VSSIO VSSIO VSSIO D16 VDDIO E D0 D1 VSSIO VSSIO VSSIO D14 D15 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 23 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com Table 9. CPU Slave Pinout (continued) SLV 1 2 3 4 5 6 7 F D2 D3 D6 VSS D9 D11 D13 G D4 D5 D7 VDD D8 D10 D12 VDDIO RD* WR* CS2* WO AD 5 4 3 2 1 AD 1 6 CLK 2 D0 CS2* 3 7 WR* 4 D1 RD* 5 8 VDDIO 6 D2 D0 7 9 D1 8 D3 D2 9 10 D3 10 Connection Diagram - WQFN Package D4 11 40 TM D4 11 40 TM D5 12 39 CS1* D5 12 39 CS1* D6 13 38 M/S* D6 13 38 M/S* D7 14 37 PD* D7 14 PD* 15 36 DCP NC 15 36 DDP VDD 16 35 VSSA VDD 16 TOP VIEW 40 Lead WQFN 5mm x 5mm x 0.8mm 0.4mm pitch (not to scale) 37 NC TOP VIEW 40 Lead WQFN 5mm x 5mm x 0.8mm 0.4mm pitch (not to scale) 35 VSSA D8 17 M/S*=H, MASTER 34 DCN D8 17 M/S*=L, SLAVE 34 DDN D9 18 (DAP connection, center pad = GND) 33 VDDA D9 18 (DAP connection, center pad = GND) 33 VDDA D10 19 32 DDN D10 19 32 DCN D11 20 31 DDP D11 20 31 DCP 30 29 RDS1 RDS0 28 27 D17 ERR 26 24 D15 VDDIO 23 D14 25 22 D13 D16 21 LM4308SQ D12 27 D17 30 26 VDDIO PLLCON0 25 D16 29 24 D15 PLLCON1 23 D14 28 22 D13 ERR 21 D12 LM4308SQ Figure 20. TOP VIEW — (not to scale) Note that the pinout of a MASTER configured device is DIFFERENT than a SLAVE configured device. The use of two logic symbols for PCB schematic is recommended. Table 10. CPU Master - Slave Pad Assignments Pin # Master 1 2 24 Slave AD CLK WO Pad # Master Slave 21 D12 22 D13 3 CS2* 23 D14 4 WR* 24 D15 5 RD* 25 D16 6 VDDIO 26 VDDIO 7 D0 27 D17 8 D1 28 ERR 9 D2 29 PLLCON1 10 D3 30 PLLCON0 RDS0 11 D4 31 DDP_M DCP_S 12 D5 32 DDN_M 13 D6 33 14 D7 34 15 NC 35 Submit Documentation Feedback RDS1 DCN_S VDDA DCN_M DDN_S VSSA Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 LM4308 www.ti.com SNLS225C – AUGUST 2007 – REVISED MAY 2013 Table 10. CPU Master - Slave Pad Assignments (continued) Pin # Pad # Master Slave 16 Master VDD Slave 36 DCP_M DDP_S 17 D8 37 PD* 18 D9 38 M/S* 19 D10 39 CS1* 20 D11 40 TM DAP VSSIO / VSS DAP VSSIO / VSS Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 25 LM4308 SNLS225C – AUGUST 2007 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision B (May 2013) to Revision C • 26 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 25 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM4308 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM4308GR/NOPB ACTIVE csBGA NYC 49 1000 Green (RoHS & no Sb/Br) CU SNAGCU Level-1-260C-UNLIM L4308GR LM4308GRX/NOPB ACTIVE csBGA NYC 49 3500 Green (RoHS & no Sb/Br) CU SNAGCU Level-1-260C-UNLIM L4308GR LM4308SQ/NOPB ACTIVE WQFN RSB 40 1000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR L4308SQ LM4308SQX/NOPB ACTIVE WQFN RSB 40 4500 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR L4308SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM4308GR/NOPB csBGA NYC 49 1000 178.0 12.4 4.3 4.3 1.5 8.0 12.0 Q1 LM4308GRX/NOPB csBGA NYC 49 3500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q1 LM4308SQ/NOPB WQFN RSB 40 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LM4308SQX/NOPB WQFN RSB 40 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4308GR/NOPB csBGA NYC 49 1000 210.0 185.0 35.0 LM4308GRX/NOPB csBGA NYC 49 3500 367.0 367.0 35.0 LM4308SQ/NOPB WQFN RSB 40 1000 213.0 191.0 55.0 LM4308SQX/NOPB WQFN RSB 40 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NYC0049A GRA49A (Rev A) www.ti.com MECHANICAL DATA RSB0040A SQF40A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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