MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.1 Overview 1.1.1 Overview The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, fax machine, music instrument and other applications. This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a simple efficient instruction set. The MN101E30 series have an internal 928 KB (maximum) of ROM and 8 KB (maximum) of RAM. Peripheral functions include 6 external interrupts, 30 internal interrupts including NMI, 9 timer counters, 6 sets of serial interfaces, A/D converter, D/A converter, LCD driver, watchdog timer, 2 sets of automatic data transfer, synchronous output function and buzzer output. The configuration of this microcomputer is well suited for application as a system controller in camera, timer selector for VCR, CD player, or minicomponent, and also suited for audio reproduction with a high-precision D/A converter. With three oscillation system (high frequency: max. 20 MHz / low frequency: 32.768 kHz and PLL: frequency multiplier of high frequency) contained on the chip, the system clock can be switched to high frequency input (high speed mode), PLL input (PLL mode), or to low frequency input (low speed mode). The system clock is generated by dividing the oscillation clock. The best operation clock for the system can be selected by switching its frequency by software. High speed mode has the normal mode based on fpll/2 which is half clock generated from an original oscillation and PLL, and the double speed mode based on fpll which is clock generated from an original oscillation without dividing. A machine cycle (min. instructions execution) in the normal mode is 100 ns when fosc is 20 MHz (at the time that PLL is not used). A machine cycle in the double speed mode is 50 ns when fosc is 20 MHz. A machine cycle in the PLL mode is 50 ns (maximum).The package is 100-pin QFP, LQFP. Publication date: October 2015 1 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.1.2 Product Summary This manual describes the following models of the MN101E30 series. These products have identical functions, and their memory capacity and type are shown below. Table:1.1.1 Product Summary Model ROM Size RAM Size Classification Package MN101E30N 508 KB 8 KB Mask ROM version LQFP100-P-1414C QFP100-P-1818B MN101E30R 928 KB 8 KB Mask ROM version QFP100-P-1818B MN101EF30R 928 KB 8 KB Flash EEPROM version LQFP100-P-1414 QFP100-P-1818B This manual is described with a focus on MN101E30N. .. Publication date: October 2015 2 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.2 Hardware Functions Feature - ROM Capacity: 508/928 KB - RAM Capacity: 8 KB - Package: 100pin LQFP (14 mm square, 0.5 mm pitch) 100pin QFP (18 mm square, 0.65 mm pitch) - Machine Cycle: High speed mode 0.05 ms/ 20 MHz (2.2 V to 5.5 V) PLL mode 0.05 s/ 20 MHz (2.2 V to 5.5 V) Low speed mode 62.5 s/16 kHz (2.2 V to 5.5 V) - Clock Gear: Operation speed of system clock is variable by changing the frequency. - Multiplied Clock: High-speed frequency clock (fosc) can be multiplied by 2, 3, 4, 5, 6, 8 and 10. - Memory bank: Data memory space is expanded by the bank system. - Bank for the source address/Bank for the destination address. - ROM correction: Correcting address designation: up to 7 addresses possible - Operation Modes: NORMAL mode ( High speed mode) PLL mode SLOW mode ( Low speed mode) HALT mode STOP mode (The operation clock can be switched in each mode.) - Operating Voltage: Publication date: October 2015 2.2 V to 5.5 V 3 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E - Operating Temperature: - Interrupt: -40C to +85C 36 levels <Watchdog timer> - NMI-Watchdog timer overflow <Timer interrupts> - TM0IRQ-Timer 0 interrupt (8-bit timer) - TM1IRQ-Timer 1 interrupt (8-bit timer) - TM2IRQ-Timer 2 interrupt (8-bit timer) - TM3IRQ-Timer 3 interrupt (8-bit timer) - TM4IRQ-Timer 4 interrupt (8-bit timer) - TM6IRQ-Timer 6 interrupt (8-bit timer) - TBIRQ-Clock timer interrupt - TM7IRQ-Timer 7 interrupt (16-bit timer) - T7OC2IRQ- Timer 7 interrupt (16-bit timer) - TM8IRQ-Timer 8 interrupt (16-bit timer) - T8OC2IRQ- Timer 8 interrupt (16-bit timer) - TM9IRQ-Timer 9 interrupt (16-bit timer) - T9OC2IRQ- Timer 9 interrupt (16-bit timer) <Serial interrupts> - SC0TIRQ-Serial interface 0 interrupt - SC0RIRQ-Serial interface 0 UART reception interrupt (peripheral function group interrupt) - SC1TIRQ-Serial interface 1 interrupt - SC1RIRQ-Serial interface 1 UART reception interrupt (peripheral function group interrupt) - SC2TIRQ-Serial interface 2 interrupt - SC2RIRQ-Serial interface 2 UART reception interrupt - SC3TIRQ-Serial interface 3 interrupt - SC3RIRQ-Serial interface 3 UART reception interrupt (peripheral function group interrupt) - SC4TIRQ- Serial interface 4 interrupt - SC4SIRQ- Serial interface 4 stop condition interrupt (peripheral function group interrupt) - SC5TIRQ- Serial interface 5 interrupt (peripheral function group interrupt) <A/D conversion end> Publication date: October 2015 4 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E - ADIRQ-AD conversion end (peripheral function group interrupt) <Automatic Transfer Controller interrupts> - ATC0IRQ-ATC0 interrupt (peripheral function group interrupt) - ATC1IRQ-ATC1 interrupt (peripheral function group interrupt) <External interrupts> Edge selectable - IRQ0:External interrupt (AC zero-cross detector, With/Without noise filter) - IRQ1:External interrupt (AC zero-cross detector, With/Without noise filter) - IRQ2:External interrupt (Both edges interrupt) - IRQ3:External interrupt (Both edges interrupt) - IRQ4:External interrupt (Both edges interrupt) - IRQ5:External interrupt (Key scan interrupt only) <Audio interrupts> - Audio reproduction end interrupt - Audio phrase end interrupt - Timer Counter: 11 timers All timer counters generate interrupt (10 can be operated independently) - 8-bit timer for general use: 5 sets - 8-bit free-running timer: 1 set - Time base timer: 1 set - 16-bit timer for general use: 3 sets - Simple 8-bit timer: 1 set Timer 0 (8-bit timer for general use) - Square wave output (timer pulse output), added pulse(2-bit) system PWM output (can be output to large current pin TM0IOB), event count, remote control carrier output, simple pulse with measurement - Clock source fpll, fpll/4, fpll/16, fpll/32, fpll/64, fpll/128, fs/2, fs/4, fs/8, fx, external clock, TimerA output - Real timer output control Control the timer (PWM) output by the falling edge of external interrupt 0 (IRQ0) with the follow 3 value; “High”-fixed, “LOW”-fixed and “Hi-Z”-fixed Timer 1 (8-bit timer for general use) -Square wave output (timer pulse output), event count, 16-bit cascade connected (timer0, 1) timer synchronous output event Publication date: October 2015 5 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E -Clock source fpll, fpll/4, fpll/16, fpll/32, fpll/64, fpll/128, fs/2, fs/4, fs/8, fx, external clock, TimerA output Timer 2 (8-bit timer for general use) - Square wave output (timer pulse output), added pulse(2-bit) system PWM output (can be output to large current pin TM2IOB), event count, simple pulse with measurement, 24-bit cascade connected (timer0, 1) timer synchronous output event - Clock source fpll, fpll/4, fpll/16, fpll/32, fpll/64, fpll/128, fs/2, fs/4, fs/8, fx, external clock, TimerA output - Real timer output control Control the timer (PWM) output by the falling edge of external interrupt 0 (IRQ0) with the follow 3 value; “High”-fixed, “LOW”-fixed and “Hi-Z”-fixed Timer 3 (8-bit timer for general use) - Square wave output (timer pulse output), event count, remote control carrier output, 16bit cascade connected (timer2), 32-bit cascade connected (timer0, 1, 2) - Clock source fpll, fpll/4, fpll/16, fpll/32, fpll/64, fpll/128, fs/2, fs/4, fs/8, fx, external clock, TimerA output Timer 4 (8-bit timer for general use) - Square wave output (timer pulse output), added pulse(2-bit) system PWM output, event count, serial transfer clock, simple pulse measurement - Clock source fpll, fpll/4, fpll/16, fpll/32, fpll/64, fpll/128, fs/2, fs/4, fs/8, fx, external clock, TimerA output Timer 6 (8-bit free-running timer, Time base timer) 8-bit free-running timer - Clock source fpll, fpll/212, fpll/213, fs, fx, fx/212, fx/213 Time base timer - Interrupt generation cycle fpll/27, fpll/28, fpll/29, fpll/210, fpll/213, fpll/215, fx/27, fx/28, fx/29, fx/210, fx/213, fx/215 Timer 7 (16-bit timer for general use) - Clock source fpll, fpll/2, fpll/4, fpll/16, fs, fs/2, fs/4, fs/16 1/1, 1/2, 1/4, 1/16 of the external clock, TimerA output - Hardware organization Compare register with double buffer: 2 sets Publication date: October 2015 6 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Input capture register: Timer interrupt: 1 set 2 vectors - Timer functions Square wave output (Timer pulse output), High precision PWM output (Cycle/Duty continuous changeable), IGBT output (Cycle/Duty continuous changeable) can be output to large current pin TM7IOB Timer synchronous output, event count, Input capture function (Both edges can be operated) -Real timer output control Control the timer (PWM) output by the falling edge of external interrupt 0 (IRQ0) with the follow 3 value; “High”-fixed, “LOW”-fixed and “Hi-Z”-fixed Timer 8 (16-bit timer for general use) -Clock source fpll, fpll/2, fpll/4, fpll/16, fs, fs/2, fs/4, fs/16 1/1, 1/2, 1/4, 1/16 of the external clock, TimerA output -Hardware organization Compare register with double buffer: 2 sets Input capture register: 1 set Timer interrupt: 2 vectors -Timer functions Square wave output (Timer pulse output), High precision PWM output (Cycle/Duty continuous changeable) can be output to large current pin TM8IOB, event count, pulse width measurement, input capture (Both edge available), 32-bit cascade connected (Timer7, 8), 32-bit PWM output, Input capture is available at 32-bit cascade Timer 9 (16-bit timer for general use) -Clock source fpll, fpll/2, fpll/4, fpll/16, fs, fs/2, fs/4, fs/16, 1/1, 1/2, 1/4, 1/16 of the external clock TimerA output -Hardware organization Compare register with double buffer: 2 sets Input capture register: 1 set Timer interrupt: 2 vectors -Timer functions Square wave output (Timer pulse output), High precision PWM output (Cycle/Duty continuous changeable) can be output to large current pin TM9IOB, event count, pulse width measurement, input capture (Both edge available) -Real timer output control Control the timer (PWM) output by the falling edge of external interrupt 0 (IRQ0) with the follow 3 value; “High”-fixed, “LOW”-fixed and “Hi-Z”-fixed TimerA output (Simple timer counter A) Clock output for peripheral function Publication date: October 2015 7 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E - Watchdog timer - Time-out cycle can be selected from fs/216, fs/218, fs/220 - On detection of errors, hard reset is done inside LSI. - Synchronous output function - Timer synchronous output, interrupt synchronous output Port 8 outputs the latched data, on the event timing of the synchronous output signal of timer 1, 2, or 7, or of the external interrupt 2 (IRQ2). - Buzzer Output/Reverse Buzzer Ouput: - Output frequency can be selected from fpll/29,fpll/210,fpll/211,fpll/212,fpll/213, fpll/214,fx/ 23,fx/24. - Remote Control Carrier Output: - A remote control carrier output with duty cycle of 1/2 or 1/3 of timer 0 or timer 3 output are available. - A/D Converter: 10-bit x 12 channels - D/A Converter: 8-bit x 4 channels - Data automatic transfer:2 systems ATC0 Data is transferred automatically in all memory space - External request/internal event request/software request - Maximum transfer cycles are 255 - Support continuous serial transmission / reception. - Burst transfer function (Urgent stop of interrupts is contained.) ATC1 Data is transferred automatically in all memory space - External request/internal event request/software request - Maximum transfer cycles are 255 - Support continuous serial transmission / reception. - Burst transfer function (Urgent stop of interrupts is contained.) Publication date: October 2015 8 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E - Serial Interface: 6 channels Serial 0 (Full duplex UART / Synchronous serial interface) Synchronous serial interface - Transfer clock source fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output, external clock - MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1 to 8 bits can be selected. - Sequence transmission, reception or both are available. Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A) - Parity check, Overrun error / Framing error detection - Transfer size 7 to 8 bits can be selected. Serial 1 (Full duplex UART / Synchronous serial interface) Synchronous serial interface - Transfer clock source fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output, external clock - MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1 to 8 bits can be selected. - Sequence transmission, reception or both are available. Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A) - Parity check, Overrun error / Framing error detection - Transfer size 7 to 8 bits can be selected. Serial 2 (Full duplex UART / Synchronous serial interface) Synchronous serial interface - Transfer clock source fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output,external clock - MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1 to 8 bits can be selected. - Sequence transmission, reception or both are available. Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A) - Parity check, Overrun error / Framing error detection - Transfer size 7 to 8 bits can be selected. Serial 3 (Full duplex UART / Synchronous serial interface) Synchronous serial interface - Transfer clock source fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output ,external clock - MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1 to 8 bits can be selected. Publication date: October 2015 9 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E - Sequence transmission, reception or both are available. Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A) - Parity check, Overrun error / Framing error detection - Transfer size 7 to 8 bits can be selected. Serial 4 (multi master I2C / Synchronous serial interface) Synchronous serial interface - Transfer clock source fpll/2, fpll/4, fpll/8, fpll/32, fs/2, fs/4, Timer0,1,2,3,4 and A output, external clock - MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1 to 8 bits can be selected. - Sequence transmission, reception or both are available. Multi master I2C - 7-bit of slave address can be set. - General call communication mode handling Serial 5 - IIC slave interface - IIC high-speed transfer mode (communication speed: 400 kbps) - 7-bit or 10-bit of slave address can be set. - General call communication mode handling - LED Driver: 8 pins (Push-pull structure) - Automatic Reset - LCD Driver: LCD driver pins Segment output max. 55 pins (SEG0 to 54) SEG0 to 54 can be switched to I/O ports by 1 pin [Note:At reset, SEG0 to 54 are input ports.] Common output pins:4 pins COM0 to 3 can be switched to I/O ports by 1 pin Display mode selection Static 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/4 duty, 1/3 bias Publication date: October 2015 10 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E LCD driver clock - When the source clock is the main clock (fpll) 1/218, 1/217, 1/216, 1/215, 1/214, 1/213, 1/212, 1/211 - When the source clock is the sub clock (fx) 1/29, 1/28, 1/27, 1/26 - Timer0, 1, 2, 3, 4 and A output LCD power supply Use at VDD5 VLC1 External supply voltage is input from VLC1, VLC2, VLC3 pins or voltage applied to VLC1 is divided by internal resistance and supplied to VLC2 and VLC3 pins. - DAC for audio reproduction Analog DAC input PWM digital output Continuous reproduction function Repeat function (phrase repeat) Volume control (2048 tone) Sampling frequency: 8 to 44.1 kHz - Port: I/O ports : 85 pins LED (large current) driver pins : 8 pins LCD driver for segment : 55 pins LCD driver for common : 4 pins serial interface pin : 34 pins Timer I/O : 28 pins Buzzer output : 4 pins A/D input : 12 pins External interrupt pin : 5 pins LCD power : 3 pins XI/XO : 2 pins D/A output : 4 pins Audio output : 2 pins Publication date: October 2015 11 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Special pins : 10 pins Operation mode input pins : 3 pin Analog reference voltage input pins : 1 pin Reset input pin : 1 pin Oscillation pins : 2 pins Power pins : 6 pins Publication date: October 2015 12 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.3 Pin Description P72 / SEG9 / NWE / SBT2A P71 / SEG10 / A7 / SBI2A / RXD2A P70 / SEG11 / A6 / SBO2A / TXD2A P67 / SEG12 / A5 / SBT4A / SCL4A P66 / SEG13 / A4 / SBO4A / SDA4A P65 / SEG14 / A3 / SBI4A P64 / SEG15 / A2 / TM4IOB P63 / SEG16 / A1 / TM3IOB P62 / SEG17 / A0 / TM1IOB P61 / SEG18 / DA_B P60 / SEG19 P50 / SEG20 / KEY0 / D0 / SBO0A / TXD0A P51 / SEG21 / KEY1 / D1 / SBI0A / RXD0A P52 / SEG22 / KEY2 / D2 / SBT0A P53 / SEG23 / KEY3 / D3 / BUZZERA P54 / SEG24 / KEY4 / D4 / NBUZZERA P55 / SEG25 / KEY5 / D5 P56 / SEG26 / KEY6 / D6 P57 / SEG27 / KEY7 / D7 P47 / SEG28 / SCL5B P46 / SEG29 / SDA5B P45 / SEG30 / SBT0B P44 / SEG31 / SBI0B / RXD0B P43 / SEG32 / SBO0B / TXD0B P42 / SEG33 / SBT3B 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Pin configuration SDA5A / NRE / SEG8 / P73 76 50 P41 / SEG34 / SBI3B / RXD3B SCL5A / NCS / SEG7 / P74 77 49 P40 / SEG35 / SBO3B / TXD3B TXD1B / SBO1B / A8 / SEG6 / P75 78 48 P36 / SEG36 RXD1B / SBI1B / A9 / SEG5 / P76 79 47 P35 / SEG37 / SBI4B SBT1B / A10 / SEG4 / P77 80 46 P34 / SEG38 / SBT4B / SCL4B TM9OD0 / SDO0 / A11 / SEG3 / P80 81 45 P33 / SEG39 / SBO4B / SDA4B TM9OD1 / SDO1 / A12 / SEG2 / P81 82 44 P32 / SEG40 / SBT2B TM9OD2 / SDO2 / A13 / SEG1 / P82 83 43 P31 / SEG41 / SBI2B / RXD2B 42 P30 / SEG42 / SBO2B / TXD2B 41 P16 / SEG43 / TM8IOC / NBUZZERB 40 P15 / SEG44 / TM7IOC / BUZZERB 39 P14 / SEG45 / TM4IOC 38 P13 / SEG46 / TM3IOC 37 P12 / SEG47 / TM1IOC TM9OD3 / SDO3 / A14 / SEG0 / P83 84 TM9OD4 / SDO4 / A15 / COM0 / P84 85 TM9OD5 / SDO5 / A16 / COM1 / P85 86 SDO6 / A17 / COM2 / P86 87 SDO7 / A18 / COM3 / P87 88 A19 / VLC3 / P92 89 MN101E30N/E30R/EF30R 100 pin QFP/LQFP (Top View) NDK / VLC2 / P93 90 36 P11 / SEG48 / TM2IOC DA_C / VLC1 / P94 91 35 P10 / SEG49 / TM0IOC / RMOUTC DA_D / P95 92 34 P24 / SEG50 / IRQ4 AVDD 93 33 P23 / SEG51 / IRQ3 DAI-DOUT 94 32 P22 / SEG52 / IRQ2 DAI-AOUT 95 31 P21 / SEG53 / IRQ1 / ACZ1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TM8IOA / AN6 / PA6 TM9IOA / AN7 / PA7 Vref+ MMOD ATRST NRST / P27 XO / P91 XI / P90 VSS OSC1 OSC2 VDD5 VDD18 (1.8 V capacity) * VDD(3.3 V capacity) DMOD RXD1A / SBI1A / TM7IOB / LED0 / P00 TXD1A / SBO1A / TM8IOB / LED1 / P01 SBT1A / TM9IOB / LED2 / P02 RMOUTB / TM0IOB / TM2IOB / LED3 / P03 P04 / LED4 / SBO3A / TXD3A 5 P05 / LED5 / SBI3A / RXD3A 26 TM7IOA / AN5 / PA5 27 100 TM4IOA / AN4 / PA4 99 AN8 / PB0 4 P06 / LED6 / SBT3A AN9 / PB1 TM3IOA / AN3 / PA3 28 3 P07 / LED7 / DA_A 98 2 P20 / SEG54 / IRQ0/ ACZ0 29 AN10 / PB2 1 30 97 TM2IOA / AN2 / PA2 96 TM1IOA / AN1 / PA1 AVSS AN11 / PB3 RMOUTA / TM0IOA / AN0 / PA0 1.3.1 * N.C. (non-connection pin) in mask ROM version Figure:1.3.1 Pin Configuration (MN101E30N/MN101E30R/MN101EF30R) Mode Pin setting Object Activation microcontroller area NRST ATRST DMOD P01 P02 MMOD Register setting EXMEM flag Single chip mode FLASH-ROM MASK-ROM MAIN (1) L or H H Normal pin L 0 Memory extend mode FLASH-ROM MASK-ROM MAIN (1) L or H H Normal pin L 1 Micro controller rewriting mode (3) FLASH-ROM BOOT (1) L H Normal pin H 0 D-wire communication mode(3) FLASH-ROM - (2) L (2) Pull up(2) Pull up(2) L 0 Publication date: October 2015 13 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Pin setting Object Activation microcontroller area NRST ATRST DMOD P01 Mode P02 MMOD Register setting EXMEM flag (1)The mode becomes fixed from the pin state in releasing NRST(L to H). (2)This is controlled by a dedicated on-board programmer (3)This mode becomes the rewriting mode only for Flash microcontroller. Therefore does not exist in the Mask version (MN101E30N/E30R) 1.3.2 Pin Specification Table:1.3.1 Pin Specification Pins Special Functions P00 RXD1A SBI1A TM7IOB LED0 P01 TXD1A SBO1A P02 I/O Direction Control Pin Control Functions Description in/out P0DIR0 P0PLU0 RXD1A: UART1 reception data input SBI1A: Serial1 reception data output TM7IOB: Timer 7 input / output LED0: LED driver pin 0 in/out P0DIR1 P0PLUD1 TXD1A: UART1 transmission data output SBO1A: Serial1 transmission data output TM8IOB LED1 SBT1A TM9IOB in/out P0DIR2 P0PLUD2 P0DIR3 P0PLUD3 RMOUTB: Remote control carrier output TM2IOB: Timer 2 input / output LED3: LED driving pin 3 P0DIR4 P0PLUD4 LED4: LED driving pin 4 SBO3A: Serial3 transmission data output LED2 RMOUTB TM0IOB in/out TM2IOB LED3 P04 LED4 SBO3A in/out TXD3A LED5 P06 LED1: LED driving pin 1 SBT1A: Serial 1 clock input / output TM9IOB: Timer 9 input / output LED2: LED driving pin 2 P03 P05 TM8IOB: Timer 8 input / output TM0IOB: Timer 0 input / output TXD3A: UART3 transmission data output SBI3A in/out P0DIR5 P0PLUD5 LED5: LED driving pin 5 LED6 SBT3A in/out P0DIR6 P0PLUD6 LED6: LED driving pin 6 SBT3A: Serial3 clock input / output P07 LED7 DA_A in/out P0DIR7 P0PLUD7 LED7: LED driving pin 7 DA_A: Analog A output P10 SEG49 TM0IOC in/out P1DIR0 P1PLUD0 SEG49: Segment49 output TM0IOC: Timer0 input / output RXD3A SBI3A: Serial3 reception data output RXD3A: UART3 reception data input RMOUTC: Remote control carrier output RMOUTC P11 SEG48 TM2IOC in/out P1DIR1 P1PLUD1 SEG48: Segment48 output TM2IOC: Timer2 input / output P12 SEG47 TM1IOC in/out P1DIR2 P1PLUD2 SEG47: Segment47 output TM1IOC: Timer1 input / output P13 SEG46 TM3IOC in/out P1DIR3 P1PLUD3 SEG46: Segment46 output TM3IOC: Timer3 input / output P14 SEG45 TM4IOC in/out P1DIR4 P1PLUD4 SEG45: Segment45 output TM4IOC: Timer4 input / output P15 SEG44 TM7IOC in/out P1DIR5 P1PLUD5 SEG44: Segment44 output TM7IOC: Timer7 input / output BUZZERB: Buzzer output BUZZERB P16 SEG43 TM8IOC in/out P1DIR6 P1PLUD6 P20 SEG54 IRQ0 in/out P2DIR0 P2PLUD0 ACZ0 P21 SEG53 SEG43: Segment43 output TM8IOC: Timer8 input / output NBUZZERB: Buzzer inversion output NBUZZERB SEG54: Segment54 output IRQ0: External interrupt0 ACZ0: Zero-cross detection input IRQ1 in/out P2DIR1 P2PLUD1 ACZ1 SEG53: Segment53 output IRQ1: External interrupt1 ACZ1: Zero-cross detection input P22 SEG52 IRQ2 in/out P2DIR2 P2PLUD2 SEG52: Segment52 output IRQ2: External interrupt2 P23 SEG51 IRQ3 in/out P2DIR3 P2PLUD3 SEG51: Segment51 output IRQ3: External interrupt3 P24 SEG50 IRQ4 in/out P2DIR4 P2PLUD4 SEG50: Segment50 output IRQ4: External interrupt4 P27 NRST in - - NRST: Reset Publication date: October 2015 14 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Pins P30 Special Functions SEG42 SBO2B I/O in/out Direction Control P3DIR0 Pin Control P3PLUD0 TXD2B P31 SEG41 P32 Functions Description SEG42: Segment42 output SBO2B: Serial2 transmission data output TXD2B: UART2 transmission data output SBI2B in/out P3DIR1 P3PLUD1 SEG41: Segment41 output SEG40 SBT2B in/out P3DIR2 P3PLUD2 SEG40: Segment40 output SBT2B: Serial2 clock input / output P33 SEG39 SBO4B in/out P3DIR3 P3PLUD3 SEG39: Segment39 output SBO4B: Serial4 transmission data output P34 SEG38 SBT4B in/out P3DIR4 P3PLUD4 SEG38: Segment38 output RXD2B RXD2B: UART2 reception data input SDA4B SDA4B: IIC4 data input / output SCL4B P35 SEG37 P36 SEG36 P40 SEG35 SEG34 P42 P43 SBT4B: Serial4 clock input / output SCL4B: IIC4 clock input / output SBI4B in/out P3DIR5 P3PLUD5 in/out P3DIR6 P3PLUD6 SEG36: Segment36 output SBO3B in/out P4DIR0 P4PLUD0 SEG35: Segment35 output TXD3B P41 SBI2B: Serial2 reception data output SEG37: Segment37 output SBI4B:Serial4 reception data output SBO3B: Serial3 transmission data output TXD3B: UART3 transmission data output SBI3B in/out P4DIR1 P4PLUD1 SEG34: Segment34 output SEG33 SBT3B in/out P4DIR2 P4PLUD2 SEG33: Segment33 output SBT3B: Serial3 clock input / output SEG32 SBO0B in/out P4DIR3 P4PLUD3 SEG32: Segment32 output SBO0B: Serial0 transmission data output RXD3B RXD3B: UART3 reception data input TXD0B P44 SEG31 P45 SBI3B: Serial3 reception data output TXD0B: UART0 transmission data output SBI0B in/out P4DIR4 P4PLUD4 SEG31: Segment31 output SEG30 SBT0B in/out P4DIR5 P4PLUD5 SEG30: Segment30 output SBT0B: Serial0 clock input / output P46 SEG29 SDA5B in/out P4DIR6 P4PLUD6 SEG29: Segment29 output SDA5B: IIC5 data input / output P47 SEG28 SCL5B in/out P4DIR7 P4PLUD7 SEG28: Segment28 output SCL5B: IIC5 clock input / output P50 SEG20 KEY0 in/out P5DIR0 P5PLUD0 SEG20: Segment20 output KEY0: KEY interrupt input0 D0 SBO0A D0: Data input / output (bp0) SBO0A: Serial0 transmission data output RXD0B RXD0B: UART0 reception data input TXD0A P51 TXD0A: UART0 reception data input SEG21 KEY1 D1 SBI0A in/out P5DIR1 P5PLUD1 RXD0A P52 P53 P54 P55 SEG22 KEY2 D2 SBT0A SEG23 KEY3 D3 BUZZE RA SEG24 KEY4 D4 NBUZZE RA SEG25 KEY5 SEG26 in/out in/out in/out in/out P5DIR2 P5DIR3 P5DIR4 P5DIR5 P5PLUD2 P5PLUD3 P5PLUD4 P5PLUD5 SEG27 KEY1: KEY interrupt input1 D1:Data input / output (bp1) SBI0A: Serial0 reception data output SEG22: Segment22 output KEY2: KEY interrupt input2 D2: Data input / output (bp2) SBT0A: Serial0 clock input / output SEG23: Segment23 output KEY3: KEY nterrupt input3 D3: Data input / output (bp3) BUZZERA:Buzzer output SEG24: Segment24 output KEY4: KEY interrupt input4 D4:Data input / output (bp4) NBUZZERA: Buzzer inversion output SEG25: Segment25 output KEY5: KEY interrupt input5 D5: Data input / output (bp5) KEY6 in/out P5DIR6 P5PLUD6 D6 P57 SEG21: Segment21 output RXD0A: UART0 transmission data output D5 P56 SBI0B: Serial0 reception data output SEG26: Segment26 output KEY6:KEY interrupt input6 D6:Data input / output (bp6) KEY7 D7 Publication date: October 2015 in/out P5DIR7 P5PLUD7 SEG27: Segment27 output KEY7: KEY interrupt input7 D7: Data input / output (bp7) 15 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Pins Special Functions I/O Direction Control Pin Control Functions Description P60 SEG19 in/out P6DIR0 P6PLUD0 SEG19: Segment19 output P61 SEG18 DA_B in/out P6DIR1 P6PLUD1 SEG18: Segment18 output DA_B: Analog B output P62 SEG17 A0 in/out P6DIR2 P6PLUD2 SEG17: Segment17 output A0: Address output (bp0) P63 SEG16 A1 in/out P6DIR3 P6PLUD3 SEG16: Segment16 output TM1IOB TM1IOB: Timer1 input / output TM3IOB P64 SEG15 A2 in/out P6DIR4 P6PLUD4 TM4IOB P65 SEG14 P67 P70 P71 P72 A3 in/out P6DIR5 P6PLUD5 SEG13 A4 SBO4A SDA4A SEG12 A5 SBT4A SCL4A SEG11 A6 SBO2A TXD2A SEG10 A7 SBI2A RXD2A SEG9 NWE SDA5A in/out in/out in/out in/out in/out P6DIR6 P6DIR7 P7DIR0 P7DIR1 P7DIR2 P6PLUD6 P6PLUD7 P7PLUD0 P7PLUD1 P7PLUD2 SCL5A SEG14: Segment14 output A3: Address output (bp3) SEG13: Segment13 output A4: Address output (bp4) SBO4A: Serial4 transmission data output SDA4A: IIC4 data input / output SEG12: Segment12 output A5: Address output (bp5) SBT4A: Serial4 clockinput / output SCL4A: IIC4 clock input / output SEG11: Segment11 output A6: Address output (bp6) SBO2A: Serial2 transmission data output TXD2A: UART2 transmission data output SEG10: Segment10 output A7: Address output (bp7) SBI2A: Serial2 reception data output RXD2A: UART2 reception data input SEG9: Segment9 output NWE: Write enable signal SBT2A: Serial2 clock input / output NRE in/out P7DIR3 P7PLUD3 SEG8 P74 A2: Address output (bp2) SBI4A: Serial4 reception data output SBT2A P73 SEG15: Segment15 output TM4IOB: Timer4 input / output SBI4A P66 A1: Address output (bp1) TM3IOB: Timer3 input / output SDA5A: IIC5 data input / output NRE: Read enable signal SEG8: Segment8 output NCS in/out P7DIR4 P7PLUD4 SEG7 SCL5A: IIC5 clock input / output NCS: Chip selection signal SEG7: Segment7 output P75 TXD1B SBO1B in/out P7DIR5 P7PLUD5 TXD1B: UART1 transmission data output A8 SEG6 P76 RXD1B SBI1B A9 SEG5 P77 SBT1B P80 A8: Address output (bp8) SEG6: Segment6 output in/out P7DIR6 P7PLUD6 RXD1B: UART1 reception data input SBI1B: Serial1 reception data output A9: Address output (bp9) SEG5: Segment5 output A10 in/out P7DIR7 P7PLUD7 SBT1B: Serial1 clock input / output A10: Address output (bp10) TM9OD0 SDO0 in/out P8DIR0 P8PLU0 TM9OD0: Timer9 output A11 SEG3 P81 TM9OD1 SDO1 A12 SEG2 P82 TM9OD2 SDO2 A13 SEG1 P83 TM9OD3 SDO3 A14 SEG0 P84 TM9OD4 SDO4 A15 COM0 P85 TM9OD5 SDO5 A16 COM1 P86 SDO6 P87 SDO7 SEG4 SBO1B: Serial1 transmission data output SEG4: Segment4 output SDO0: Timer synchronous output0 A11: Address output (bp11) SEG3: Segment3 output SDO1: Timer synchronous output1 in/out P8DIR1 P8PLU1 TM9OD1: Timer9 output A12: Address output (bp12) SEG2: Segment2 output in/out P8DIR2 P8PLU2 TM9OD2: Timer9 output SDO2: Timer synchronous output2 A13: Address output (bp13) SEG1: Segment1 output in/out P8DIR3 P8PLU3 TM9OD3: Timer9 output SDO3: Timer synchronous output3 A14: Address output (bp14) SEG0: Segment0 output in/out P8DIR4 P8PLU4 TM9OD4: Timer9 output SDO4: Timersynchronou soutput4 A15: Address output (bp15) COM0: LCD common output in/out P8DIR5 P8PLU5 TM9OD5: Timer9 output SDO5: Timer synchronous output5 A16: Address output (bp16) COM1:LCD common output A17 in/out P8DIR6 P8PLU6 SDO6: Timer synchronous output6 A17: Address output (bp17) A18 in/out P8DIR7 P8PLU7 SDO7: Timer synchronous output7 COM2 COM2:LCD common output COM3 Publication date: October 2015 A18: Address output (bp18) COM3:LCD common output 16 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Pins Special Functions I/O Direction Control Pin Control Functions Description P90 XI in P9DIR0 P9PLU0 P91 XO out P9DIR1 P9PLU1 XO: Clock output pin P92 A19 VLC3 in/out P9DIR2 P9PLU2 A19: Address output (bp19) VLC3: LCD power supply P93 NDK VLC2 in/out P9DIR3 P9PLU3 NDK: Data acknowledge signal VLC2:LCD power supply P94 VLC1 DA_C in/out P9DIR4 P9PLU4 VLC1:LCD power supply DA_C: AnalogC output P95 DA_D in/out P9DIR5 P9PLU5 DA_D: AnalogD output PA0 RMOUTA TM0IOA in/out PADIR0 PAPLU0 RMOUTA:Remote control carrier output AN0 XI: Clock input pin TM0IOA: Timer0 input / output AN0: Analog0 input PA1 TM1IOA AN1 in/out PADIR1 PAPLU1 TM1IOA: Timer1 input / output AN1: Analog1 input PA2 TM2IOA AN2 in/out PADIR2 PAPLU2 TM2IOA: Timer2 input / output AN2: Analog2 input PA3 TM3IOA AN3 in/out PADIR3 PAPLU3 TM3IOA: Timer3 input / output AN3: Analog3 input PA4 TM4IOA AN4 in/out PADIR4 PAPLU4 TM4IOA: Timer4 input / output AN4: Analog4 input PA5 TM7IOA AN5 in/out PADIR5 PAPLU5 TM7IOA: Timer7 input / output AN5: Analog5 input PA6 TM8IOA AN6 in/out PADIR6 PAPLU6 TM8IOA: Timer8 input / output AN6: Analog6 input PA7 TM9IOA AN7 in/out PADIR7 PAPLU7 TM9IOA: Timer9 input / output AN7: Analog7 input PB0 AN8 in/out PBDIR0 PBPLU0 AN8: Analog8 input PB1 AN9 in/out PBDIR1 PBPLU1 AN9: Analog9 input PB2 AN10 in/out PBDIR2 PBPLU2 AN10: Analog10 input PB3 AN11 in/out PBDIR3 PBPLU3 AN11: Analog11 input DA1_ DOUT DA1_DOUT out - - Audio digital output DA1_ AOUT DA1_AOUT out - - Audio analog output Publication date: October 2015 17 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.3.3 Pin Functions Table:1.3.2 Pin Functions Name NO I/O Other Function Function Description VSS VDD5 AVDD AVSS 15 18 93 96 - Power connect pins Supply 2.2 V to 5.5 V to VDD5, 5.0 V to AVDD and 0 V to VSS and AVSS. VDD18 (Capacity 1.8 V) 19 - Capacity connect pins For internal power circuit output stability, connect at least one bypass capacitor of 1 uF or larger between VDD18 and Vss. VDD (Capacity 3.3 V) 20 - Capacity connect pins For internal power circuit output stability, connect at least one bypass capacitor of 1 uF or larger between VDD and Vss. (Only Flash version) OSC1 OSC2 16 17 Input Output Clock input pins Connect these oscillation pins to ceramic or crystal Clock output pins ocsillators for high-frequency clock operation. If the clock is an external input, connect it to OSC1 and leave OSC2 open. The chip will not operate with an external clock when using either the STOP or SLOW modes. XI XO 14 13 Input P90 Output P91 Clock input pins Connect these oscillation pins to crystal oscillators for Clock output pins low-frequency clock operation. If the clock is an external input, connect it to XI and leave XO open. the chip will not operate with an external clock when using the STOP mode. If these pins are not used, connect XI to VSS and leave XO open. NRST 12 Input Reset pin [Active low] ATRST 11 input P00 22 I/O P01 23 TXD1A,SBO1A,TM8IOB,LED1 P02 24 SBT1A,TM9IOB,LED2 P03 25 RMOUTB,TM0IOB, TM2IOB,LED3 P27 This pin resets the chip when power is turned on, is allocated as P27 and contains an internal pull-up resistor (Type. 50 k. Setting this pin low initialize the internal state of the device. Thereafter, setting the input to high releases the reset. The hardware waits for the system clock to stabilize, then processes the reset interrupt. Also, if “0” is written to P27 and the reset is initiated by software, a low level will be output. The output has an n-channel open-drain configuration. If a capacitor is to be inserted between NRST and VSS, it is recommended that a discharge diode be placed between NRST and VDD5. Auto reset setting Input “H” to enable auto reset function and “L” to dispins 2 able this function RXD1A,SBI1A,TM7IOB,LED0 P04 26 LED4,SBO3A,TXD3A P05 27 LED5,SBI3A,RXD3A P06 28 LED6,SBT3A P07 29 LED7,DA_A Publication date: October 2015 I/O port0 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P0DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P0PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. (However, pull-up and pull-down resistors cannot be mixed.) Direct LED drive available at output. At reset, the input mode is selected and pull-up resistors are disabled (high impedance). 18 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O I/O Other Function P10 35 P11 36 SEG48,TM2IOC P12 37 SEG47,TM1IOC P13 38 SEG46,TM3IOC P14 39 SEG45,TM4IOC P15 40 SEG44,TM7IOC,BUZZERB P16 41 SEG43,TM8IOC,NBUZZERB P20 30 P21 31 SEG53,IRQ1,ACZ1 P22 32 SEG52,IRQ2 P23 33 SEG51,IRQ3 P24 34 SEG50,IRQ4 P27 12 input P30 42 I/O P31 43 SEG41,SBI2B,RXD2B P32 44 SEG40,SBT2B P33 45 SEG39,SBO4B,SDA4B P34 46 SEG38,SBT4B,SCL4B P35 47 SEG37,SBI4B P36 48 SEG36 I/O I/O SEG49,TM0IOC,RMOUTC Function 7-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P1DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P1PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. A pullup/pull down can not be mixed. At reset, the input mode is selected and pull-up resistors are disabled (high impedance). I/O port2 5-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P2DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P2PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. (A pull-up/pull down can not be mixed.) At reset, the input mode is selected and pull-up resistors are disabled (high impedance) NRST I/O port2 Port P27 has an N-channel open-drain configuration. When “0” is written and the reset is initiated by software, a low level will be output. SEG42,SBO2B,TXD2B I/O port3 7-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P3DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P3PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. (A pull-up/pull down can not be mixed.) At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O port4 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P4DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P4PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. A pullup/pull down can not be mixed. At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O port5 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P5DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P5PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. (A pull-up/pull down can not be mixed.) At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O port6 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P6DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P6PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. (A pull-up/pull down can not be mixed.) At reset, the input mode is selected and pull-up resistors are disabled (high impedance) SEG54,IRQ0,ACZ0 P40 49 P41 50 SEG34,SBI3B,RXD3B P42 51 SEG33,SBT3B P43 52 SEG32,SBO0B,TXD0B P44 53 SEG31,SBI0B,RXD0B P45 54 SEG30,SBT0B P46 55 SEG29,SDA5B P47 56 P50 64 SEG35,SBO3B,TXD3B P51 63 SEG21,KEY1,D1,SBI0A, RXD0A P52 62 SEG22,KEY2,D2,SBT0A P53 61 SEG23,KEY3,D3,BUZZERA P54 60 SEG24,KEY4,D4,NBUZZERA P55 59 SEG25,KEY5,D5 P56 58 SEG26,KEY6,D6 P57 57 SEG27,KEY7,D7 P60 65 P61 66 SEG18,DA_B P62 67 SEG17,A0,TM1IOB P63 68 SEG16,A1,TM3IOB P64 69 SEG15,A2,TM4IOB P65 70 SEG14,A3,SBI4A P66 71 SEG13,A4,SBO4A,SDA4A P67 72 SEG12,A5,SBT4A,SCL4A SEG28,SCL5B I/O I/O Description I/O port1 SEG20,KEY0,D0,SBO0A, TXD0A SEG19 Publication date: October 2015 19 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O I/O Other Function P70 73 P71 74 SEG10,A7,SBI2A,RXD2A P72 75 SEG9,NWE,SBT2A P73 76 SEG8,SDA5A,NRE P74 77 SEG7,SCL5A,NCS P75 78 SEG6,TXD1B,SBO1B,A8 P76 79 SEG5,RXD1B,SBI1B,A9 P77 80 SEG4,SBT1B,A10 P80 81 P81 82 TM9OD1,SDO1,A12,SEG2 P82 83 TM9OD2,SDO2,A13,SEG1 P83 84 TM9OD3,SDO3,A14,SEG0 P84 85 TM9OD4,SDO4,A15,COM0 P85 86 TM9OD5,SDO5,A16,COM1 P86 87 SDO6,A17,COM2 I/O SEG11,A6,SBO2A,TXD2A TM9OD0,SDO0,A11,SEG3 P87 88 P90 14 P91 13 P92 89 A19,VLC3 P93 90 NDK,VLC2 Function Description I/O port7 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P7DIR register. A pull-up /pull-down resistor for each bit can be selected individually by the P7PLUD register. A pull-up/down resistor connection for each port can be selected individually by the SELUD register. (A pull-up/pull down can not be mixed.) At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O port8 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P8DIR register. A pull-up resistor for each bit can be selected individually by the P8PLUD register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O port9 7-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P9DIR register. A pull-up resistor for each bit can be selected individually by the P8PLUD register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O portA 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the PADIR register. A pull-up resistor for each bit can be selected individually by the PAPLUD register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance) I/O portB 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the PBDIR register. A pull-up resistor for each bit can be selected individually by the PBPLUD register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance) SDO7,A18,COM3 I/O XI XO P94 91 DA_C,VLC1 P95 92 DA_D PA0 1 PA1 2 TM1IOA,AN1 PA2 3 TM2IOA,AN2 PA3 4 TM3IOA,AN3 PA4 5 TM4IOA,AN4 PA5 6 TM7IOA,AN5 PA6 7 TM8IOA,AN6 PA7 8 TM9IOA,AN7 PB0 100 I/O AN8 PB1 99 AN9 PB2 98 AN10 PB3 97 AN11 DA1_DOUT DA1_AOUT 94 95 I/O SBO0A 64 I/O P50,SEG20,KEY0,D0 Serial interface SBO0B 52 P43,SEG32,TXD0B transmission SBO1A 23 TXD1A,TM8IOB,LED1,P01 data output pins SBO1B 78 TXD1B,A8,SEG6,P75 I/O RMOUTA,TM0IOA,AN0 Audio output pins Special output pins for audio production function These output “L” at reset. SBO2A 73 P70,SEG11,A6,TXD2A SBO2B 42 P30,SEG42,TXD2B SBO3A 26 P04,LED4,TXD3A SBO3B 49 P40,SEG35,TXD3B SBO4A 71 P66,SEG13,A4,SDA4A SBO4B 45 P33,SEG39,SDA4B Publication date: October 2015 Transmission data output pins for serial interface 0 to 4. The output configuration, either CMOS push-pull or nchannel open-drain can be selected with the P0ODC, P3ODC, P4ODC, P5ODC, P6ODC, P7ODC registers. Pull-up resistor can be selected by the P0PLUD, P3PLUD, P4PLUD, P5PLUD, P6PLUD and P7PLUD registers. Select the output mode at the P0DIR, P3DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and serial data output mode by serial mode register 1 (SC0MD1 to SC4MD1). These can be used as normal I/O pins when the serial interface is not used. 20 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O input Other Function P51,SEG21,KEY1,D1 Function SBI0A 63 SBI0B 53 P44,SEG31,RXD0B reception SBI1A 22 RXD1A,TM7IOB,LED0,P00 data input pins SBI1B 79 RXD1B,A9,SEG5,P76 SBI2A 74 P71,SEG10,A7,RXD2A SBI2B 43 P31,SEG41,RXD2B SBI3A 27 P05,LED5,RXD3A SBI3B 50 P41,SEG34,RXD3B SBI4A 70 P65,SEG14,A3 SBI4B 47 SBT0A 62 SBT0B 54 P52,SEG22,KEY2,D2 Serial interface P45,SEG30 clock I/O pins 24 TM9IOB,LED2,P02 SBT1B 80 A10,SEG4,P77 SBT2A 75 P72,SEG9,NWE SBT2B 44 P32,SEG40 SBT3A 28 P06,LED6 SBT3B 51 P42,SEG33 SBT4A 72 P67,SEG12,A5,SCL4A 46 TXD0A 64 TXD0B 52 Description Reception data output pins for serial interface 0 to 4. A pull-up resistor can be selected with the P0ODC, P3ODC, P4ODC, P5ODC, P6ODC, P7ODC registers. Select the output mode at the P0DIR, P3DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and serial data output mode by serial mode register 1 (SC0MD1 to SC4MD1). These can be used as normal I/O pins when the serial interface is not used. P35,SEG37 I/O SBT1A SBT4B Serial interface Clock I/O pins for serial interface 0 to 4. The output configuration, either CMOS push-pull or nchannel open-drain can be selected with the P0ODC, P3ODC, P4ODC, P5ODC, P6ODC, P7ODC registers. Pull-up resistor can be selected by the P0PLUD, P3PLUD, P4PLUD, P5PLUD, P6PLUD and P7PLUD registers. Select the clock I/O with the P0DIR, P3DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and serial data output mode by serial mode register 1 (SC0MD1 to SC4MD1) according to the communication. These can be used as normal I/O pins when the serial interface is not used. P34,SEG38,SCL4B output P50,SEG20,KEY0,D0,SBO0A P43,SEG32,SBO0B TXD1A 23 SBO1A,TM8IOB,LED1,P01 TXD1B 78 SBO1B,A8,SEG6,P75 TXD2A 73 P70,SEG11,A6,SBO2A TXD2B 42 P30,SEG42,SBO2B TXD3A 26 P04,LED4,SBO3A TXD3B 49 P40,SEG35,SBO3B RXD0A 63 RXD0B 53 P44,SEG31,SBI0B RXD1A 22 SBI1A,TM7IOB,LED0,P00 input P51,SEG21,KEY1,D1,SBI0A RXD1B 79 SBI1B,A9,SEG5,P76 RXD2A 74 P71,SEG10,A7,SBI2A RXD2B 43 P31,SEG41,SBI2B RXD3A 27 P05,LED5,SBI3A RXD3B 50 P41,SEG34,SBI3B SDA4A 71 SDA4B 45 P33,SEG39,SBO4B SDA5A 76 NRE,SEG8,P73 SDA5B 55 P46,SEG29 I/O P66,SEG13,A4,SBO4A Publication date: October 2015 UART transmission data output pins In the serial interface0 to 3 in UART mode, this pin is configured as the transmission data output pin. The output configuration, either CMOS push-pull or nchannel open-drain can be selected with the P0ODC, P3ODC, P4ODC, P5ODC, P7ODC registers. Pull-up resistor can be selected by the P0PLUD, P3PLUD, P4PLUD, P5PLUD and P7PLUD registers. Select the output mode at the P0DIR, P3DIR, P4DIR, P5DIR and P7DIR registers and serial data output mode by serial mode register 1 (SC0MD1 to SC3MD1). These can be used as normal I/O pins when the serial interface is not used. UART reception data input pins In the serial interface0 to 3 in UART mode, this pin is configured as the reception data output pin. Pull-up resistor can be selected by the P0PLUD, P3PLUD, P4PLUD, P5PLUD and P7PLUD registers. Select the output mode at the P0DIR, P3DIR, P4DIR, P5DIR and P7DIR registers and serial data output mode by serial mode register 1 (SC0MD1 to SC3MD1). These can be used as normal I/O pins when the serial interface is not used. IIC data I/O pins In the serial interface4, 5 in IIC mode, this pin is configured as the data input / output pin. For the output configuration, select n-channel opendrain with the P3ODC, P4ODC, P6ODC and P7ODC registers and pull-up resistors by the P3PLUD, P4PLUD, P6PLUD and P7PLUD registers. Select the output mode at the P3DIR, P4DIR, P6DIR and P7DIR registers and serial data input / output mode by serial mode register 1 (SC4MD1, SC5MD1). These can be used as normal I/O pins when the serial interface is not used. 21 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O I/O Other Function SCL4A 72 SCL4B 46 P34,SEG38,SBT4B SCL5A 77 NCS,SEG7,P74 SCL5B 56 P47,SEG28 TM0IOA 1 TM0IOB 25 RMOUTB,TM2IOB,LED3,P03 TM0IOC 35 P10,SEG49,RMOUTC TM1IOA 2 AN1,PA1 TM1IOB 67 P62,SEG17,A0 TM1IOC 37 P12,SEG47 TM2IOA 3 AN2,PA2 TM2IOB 25 RMOUTB,TM0IOB,LED3,P03 TM2IOC 36 P11,SEG48 TM3IOA 4 AN3,PA3 I/O P67,SEG12,A5,SBT4A RMOUTA,AN0,PA0 TM3IOB 68 P63,SEG16,A1 TM3IOC 38 P13,SEG46 TM4IOA 5 AN4,PA4 TM4IOB 69 P64,SEG15,A2 TM4IOC 39 RMOUTA 1 RMOUTB 25 TM0IOB,TM2IOB,LED3,P03 RMOUTC 35 P10,SEG49,TM0IOC BUZZERA 61 BUZZERB 40 Function Description IIC clock I/O pins In the serial interface4, 5 in IIC mode, this pin is configured as the clock input / output pin. For the output configuration, select n-channel opendrain with the P3ODC, P4ODC, P6ODC and P7ODC registers and pull-up resistors by the P3PLUD, P4PLUD, P6PLUD and P7PLUD registers. Select the output mode at the P3DIR, P4DIR, P6DIR and P7DIR registers and serial data input / output mode by serial mode register 1 (SC4MD1, SC5MD1). These can be used as normal I/O pins when the serial interface is not used Timer I/O pins Event counter clock input pin, timer output and PWM signal output pin for 8-bit timer 0 to 4. To use this pin as event clock input, configure this as input by P0DIR register, P1DIR register, P6DIR register and PADIR register. In the input mode, pull-up resistors can be selected by the P0PLUD register, P1PLUD register, P6PLUD register and PAPLU register. For timer output, PWM signal output, select the special function pin by port 0 output mode register, port 1 output mode register, port 6 output mode register and port A output mode register ((P0OMD, P1OMD, P6OMD and PAOMD), and set to the output mode at P0DIR register, P1DIR register and PADIR register. These can be used as normal I/O pins when the timer I/O is not used. P14,SEG45 I/O I/O TM0IOA,AN0,PA0 P53,SEG23,KEY3,D3 P15,SEG44,TM7IOC NBUZZERA 60 P54,SEG24,KEY4,D4 NBUZZERB 41 P16,SEG43,TM8IOC Publication date: October 2015 Remote control Output pin for remote control transmission with a carrier signal. For remote control carrier output, select the special signal output pins function pin by the port 0 output mode register, port 1 output mode register and port A output mode register (P0OMD, P1OMD and PAOMD), and set to the output mode by the P0DIR register, P1DIR register and PADIR register. At the same time, select remote control carrier output by the remote control carrier output register. These can be used as normal I/O pins when the buzzer output is not used. transmission Buzzer output Piezoelectric buzzer driving pin. Buzzer output available to port1, port5. The driving frequency can be selected with the DLYCTR register. To select buzzer output for porrt1, port5, select the special function pin by the port 1 output mode register and port 5 output mode register (P1OMD and P5OMD), and set to the output mode by the P1DIR register and P5DIR register. At the same time, select buzzer output by the oscillation stabilization wait control register (DLYCTR). These can be used as normal I/O pins when the buzzer output is not used. 22 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O I/O Other Function 6 TM7IOB 22 RXD1A,SBI1A,LED0,P00 TM7IOC 40 P15,SEG44,BUZZERB TM8IOA 7 AN6,PA6 TM8IOB 23 TXD1A,SBO1A,LED1,P01 TM8IOC 41 P16,SEG43,NBUZZERB TM9IOA 8 AN7,PA7 TM9IOB 24 SBT1A,LED2,P02 TM9OD0 81 TM9OD1 82 SDO1,A12,SEG2,P81 TM9OD2 83 SDO2,A13,SEG1,P82 TM9OD3 84 SDO3,A14,SEG0,P83 TM9OD4 85 SDO4,A15,COM0,P84 TM9OD5 86 SDO0 81 TM9OD0,A11,SEG3,P80 Synchronous SDO1 82 TM9OD1,A12,SEG2,P81 output pins SDO2 83 TM9OD2,A13,SEG1,P82 SDO3 84 TM9OD3,A14,SEG0,P83 SDO4 85 TM9OD4,A15,COM0,P84 output AN5,PA5 Function TM7IOA SDO0,A11,SEG3,P80 SDO5,A16,COM1,P85 output SDO5 86 TM9OD5,A16,COM1,P85 SDO6 87 A17,COM2,P86 SDO7 88 A18,COM3,P87 VREF+ 100 - AN0 1 AN1 2 TM1IOA,PA1 AN2 3 TM2IOA,PA2 AN3 4 TM3IOA,PA3 AN4 5 TM4IOA,PA4 AN5 6 TM7IOA,PA5 AN6 7 TM8IOA,PA6 AN7 8 TM9IOA,PA7 AN8 100 PB0 input Description Event counter clock input pin, timer output and PWM signal output pin for 16-bit timer7 and 8. To use this pin as event clock input, configure this as input with the PADIR register. In the input mode, pullup resistors can be selected by P0PLU register, P1PLU register and PAPLU register. For timer output, PWM signal output, select the special function pin by the port 0 output mode register, port 1 output mode register and port A output mode register (P0OMD, P1OMD and PAOMD), and set to the output mode at P0DIR register, P1DIR register and PADIR register. These can be used as normal I/O pins when not used as timer I/O pins. Timer output pins Timer output and PWM signal output pin for 16-bit timer. To select timer output and PWM signal output, select the special function pin by the P8OMD1 register, and set to the output mode at the P8DIR register. These can be used as normal I/O pins when not used as timer I/O pins. 8-bit synchronous output pins. Synchronous output for each bit can be selected individually by the port 8 synchronous output control register (P8SYO). Set to the output mode by the P8DIR register. These pins can be used as a normal I/O pins when not used for synchronous output pin. + power supply Reference power supply pins for the A/D converter. for A/D converter Use this under the condition: 2.0 V VREF+ VDD5 RMOUTA,TM0IOA,PA0 AN9 99 PB1 AN10 98 PB2 AN11 97 PB3 DA_A 29 DA_B 66 P61,SEG18 DA_C 91 VLC1,P94 DA_D 92 IRQ0 30 IRQ1 31 IRQ2 32 P22,SEG52 IRQ3 33 P23,SEG51 IRQ4 34 P24,SEG50 output Timer I/O pins P07,LED7 Analog input pins Analog input pins for an 16-channel, 10-bit A/D converter. When not used for analog input, these pins can be used as normal input pins. Analog output pins Analog output pins for an 4-channel, 8-bit A/D converter. When not used for analog output, these pins can be used as normal I/O pins. P20,SEG54 External interrupt P21,SEG53,ACZ1 input pins External interrupt input pins. The valid edge for IRQ0 to 4 can be selected with the IRQnICR register. IRQ1 has AC zero-cross detection function. IRQ1 can be set at both edges at pin voltage level. When not used for interrupts, these can be used as normal input pins. P95 input Publication date: October 2015 23 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O input Other Function ACZ1 31 P21,SEG53,IRQ1 ACZ0 30 KEY0 64 KEY1 63 P51,SEG21,D1,SBI0A, RXD0A KEY2 62 P52,SEG22,D2,SBT0A KEY3 61 P53,SEG23,D3,BUZZERA KEY4 60 P54,SEG24,D4,NBUZZERA KEY5 59 P55,SEG25,D5 KEY6 58 P56,SEG26,D6 KEY7 57 P57,SEG27,D7 LED0 22 LED1 23 TXD1A,SBO1A,TM8IOB,P01 LED2 24 SBT1A,TM9IOB,P02 LED3 25 RMOUTB,TM0IOB,TM2IOB, P03 LED4 26 P04,SBO3A,TXD3A Function AC zero-cross detection input pin. AC zero-cross detection output “H” when input level is mid-level and “L” otherwise. ACZ input signal is connected to P20 input and IRQ0 interrupt circuit or P21 input and IRQ1 interrupt circuit. When not used for AC zero-cross detection, these can be used as normal input pins. Key interrupt input pins Input pins for interrupt based on OR result of pin inputs. These can be set to key input pins by 1-bit with the key interrupt control register (KEYT3_1IMD, KEYT3_2IMD) and by 2-bit with the key interrupt control register (KEYT3_1IMD). When not used for KEY input, these pins can be used as normal I/O pins. LED drive pins Large current output pins. When not used for LED output, these pins can be used as normal I/O pins. P20,SEG54,IRQ0 input I/O P50,SEG20,D0,SBO0A, TXD0A RXD1A,SBI1A,TM7IOB,P00 LED5 27 P05,SBI3A,RXD3A LED6 28 P06,SBT3A LED7 29 NWE 75 NRE 76 SDA5A,SEG8,P73 NCS 77 SCL5A,SEG7,P74 NDK 90 input VLC2,P93 A0 67 output P62,SEG17,TM1IOB A1 68 Description AC zero-cross detection input pins P07,DA_A output P72,SEG9,SBT2A P63,SEG16,TM3IOB A2 69 P64,SEG15,TM4IOB A3 70 P65,SEG14,SBI4A A4 71 P66,SEG13,SBO4A,SDA4A A5 72 P67,SEG12,SBT4A,SCL4A A6 73 P70,SEG11,SBO2A,TXD2A A7 74 P71,SEG10,SBI2A,RXD2A A8 78 TXD1B,SBO1B,SEG6,P75 A9 79 RXD1B,SBI1B,SEG5,P76 A10 80 SBT1B,SEG4,P77 A11 81 TM9OD0,SDO0,SEG3,P80 A12 82 TM9OD1,SDO1,SEG2,P81 A13 83 TM9OD2,SDO2,SEG1,P82 A14 84 TM9OD3,SDO3,SEG0,P83 A15 85 TM9OD4,SDO4,COM0,P84 A16 86 TM9OD5,SDO5,COM1,P85 A17 87 SDO6,COM2,P86 A18 88 SDO7,COM3,P87 A19 89 VLC3,P92 Publication date: October 2015 Write enable pins [Active low] Memory control signal used when the memory area is expanded to the external of this LSI. Read enable pins NWE is the strobe signal output for the write operation of the external memory and NRE is the strobe signal [Active low output for the read operation of the external memory Chip select pins NCS is the chip selection signal outputs the external [Active low] memory at the access. Data acknowlNDK is the acknowledge signal that indicates close of edge pins [Active access to the external memory. low] Address pin A0-A19 is the address signal to the external memory. D0-D7 is the data I/O signal to the external memory. (Continue to next page) 24 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O I/O Other Function D0 64 P50,SEG20,KEY0,SBO0A, TXD0A D1 63 P51,SEG21,KEY1,SBI0A, RXD0A D2 62 P52,SEG22,KEY2,SBT0A D3 61 P53,SEG23,KEY3,BUZZERA D4 60 P54,SEG24,KEY4,NBUZZERA D5 59 P55,SEG25,KEY5 D6 58 P56,SEG26,KEY6 D7 57 COM0 85 Output TM9OD4,SDO4,A15,P84 COM1 86 TM9OD5,SDO5,A16,P85 COM2 87 SDO6,A17,P86 COM3 88 VLC1 91 VLC2 90 NDK,P93 VLC3 89 A19,P92 SEG0 84 SEG1 83 Function Data pin Description (Continued from previous page) P57,SEG27,KEY7 LCD common output pins These pins output common signal of required timing for LCD display. Connect to the common pins of LCD display panel. When the LCD functions are not used, these pins can be used as normal I/O port by the setting the LCD output control register LCCTR0. LCD power supply pins Supply for LCD power. Apply 5.5 VVLC1VLC2VLC30 V. When the internal voltage divider resistor is used, VLC1=VDD5 pin is selected as the reference voltage input pin. When LCD is not used, VLC1 to VLC3 can be used as normal I/O pins with the setting of LCD output control register0 (LCCTR0). TM9OD3,SDO3,A14,P83 LCD segment TM9OD2,SDO2,A13,P82 output pinas These pins output segment signal of required timing for LCD display. Connect to the segment pins of the LCD display panel. When LCD display is turned off, Vss level is output. These pins can be used as normal I/O pins with the setting of LCD output control register LCCTR1 to 7. SEG can exchange segment pins and normal port by each bit. SDO7,A18,P87 - output SYSCLK,DA_C,P94 SEG2 82 TM9OD1,SDO1,A12,P81 SEG3 81 TM9OD0,SDO0,A11,P80 SEG4 80 SBT1B,A10,P77 SEG5 79 RXD1B,SBI1B,A9,P76 SEG6 78 TXD1B,SBO1B,A8,P75 SEG7 77 SCL5A,NCS,P74 SEG8 76 SDA5A,NRE,P73 SEG9 75 P72,NWE,SBT2A SEG10 74 P71,A7,SBI2A,RXD2A SEG11 73 P70,A6,SBO2A,TXD2A SEG12 72 P67,A5,SBT4A,SCL4A SEG13 71 P66,A4,SBO4A,SDA4A SEG14 70 P65,A3,SBI4A SEG15 69 P64,A2,TM4IOB SEG16 68 P63,A1,TM3IOB SEG17 67 P62,A0,TM1IOB SEG18 66 P61,DA_B SEG19 65 P60 SEG20 64 P50,KEY0,D0,SBO0A,TXD0A SEG21 63 P51,KEY1,D1,SBI0A,RXD0A SEG22 62 P52,KEY2,D2,SBT0A SEG23 61 P53,KEY3,D3,BUZZERA SEG24 60 P54,KEY4,D4,NBUZZERA SEG25 59 P55,KEY5,D5 SEG26 58 P56,KEY6,D6 SEG27 57 P57,KEY7,D7 SEG28 56 P47,SCL5B SEG29 55 P46,SDA5B SEG30 54 P45,SBT0B SEG31 53 P44,SBI0B,RXD0B Publication date: October 2015 (Continue to next page) 25 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Name NO I/O Other Function SEG32 52 P43,SBO0B,TXD0B SEG33 51 P42,SBT3B Function Description (Continued from previous page) SEG34 50 P41,SBI3B,RXD3B SEG35 49 P40,SBO3B,TXD3B SEG36 48 P36 SEG37 47 P35,SBI4B SEG38 46 P34,SBT4B,SCL4B SEG39 45 P33,SBO4B,SDA4B SEG40 44 P32,SBT2B SEG41 43 P31,SBI2B,RXD2B SEG42 42 P30,SBO2B,TXD2B SEG43 41 P16,TM8IOC,NBUZZERB SEG44 40 P15,TM7IOC,BUZZERB SEG45 39 P14,TM4IOC SEG46 38 P13,TM3IOC SEG47 37 P12,TM1IOC SEG48 36 P11,TM2IOC SEG49 35 P10,TM0IOC,RMOUTC SEG50 34 P24,IRQ4 SEG51 33 P23,IRQ3 SEG52 32 P22,IRQ2 SEG53 31 P21,IRQ1,ACZ1 SEG54 30 MMOD 10 input Memory mode switch input pins Set always to VSS. DMOD 21 input Mode switch input pins Set always to VDD5. P20,IRQ0 Publication date: October 2015 26 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.4 Block Diagram Serial Interface 1 8-bit Timer 2 Serial Interface 2 8-bit Timer 3 Serial Interface 3 8-bit Timer A Serial Interface 4 Time base timer6 Serial Interface 5 AVDD LCD 16-bit Timer 8 Watchdog Timer 16-bit Timer 9 BUZZER D/A converter TXD0A, SBO0A, D0, KEY0, SEG20, P50 RXD0A, SBI0A, D1, KEY1, SEG21, P51 SBT0A, D2, KEY2, SEG22, P52 BUZZERA, D3, KEY3, SEG23, P53 NBUZZERA, D4, KEY4, SEG24, P54 D5, KEY5, SEG25, P55 D6, KEY6, SEG26, P56 D7, KEY7, SEG27, P57 PORT 6 PORT 7 TXD2A, SBO2A, A6, SEG11, P70 RXD2A, SBI2A, A7, SEG10, P71 SBT2A, NWE, SEG9, P72 SEG8, NRE, SDA5A, P73 SEG7, NCS, SCL5A, P74 SEG6, A8, SBO1B, TXD1B, P75 SEG5, A9, SBI1B, RXD1B, P76 SEG4, A10, SBT1B, P77 Data Automatic Transfer0, 1 A/D Converter SEG19, P60 DA_B, SEG18, P61 TM1IOB, A0, SEG17, P62 TM3IOB, A1, SEG16, P63 TM4IOB, A2, SEG15, P64 SBI4A, A3, SEG14, P65 SDA4A, SBO4A, A4, SEG13, P66 SCL4A, SBT4A, A5, SEG12, P67 PORT 4 External Interrupt PA7, TM9IOA, A9 PA6, TM8IOA, A8 PA5, TM7IOA, A7 PA4, TM4IOA, A4 PA3, TM3IOA, A3 PA2, TM2IOA, A2 PA1, TM1IOA, A1 PA0, RMOUTA, TM0IOA P95, DA_D P94, DA_C, VLC1 P93, NDKK, VLC2 P92, A19, VLC3 P91, XO P90, XI PORT 8 8-bit Timer 1 PB3, AN11 PB2, AN10 PB1, AN9 PB0, AN8 PORT 9 Serial Interface 0 DA1_AOUT DA1_DOUT PORT A Audio Reproduction 8-bit Timer 0 AVSS DMOD High-precision DAC PORT B RAM 8 KB PORT 5 VREF+ MMOD OSC2 OSC1 VDD18 VDD VDD5 VSS CPU MN101E PLL 16-bit Timer 7 PORT 3 TXD3B, SBO3B, SEG35, P40 RXD3B, SBI3B, SEG34, P41 SBT3B, SEG33, P42 TXD0B, SBO0B, SEG32, P43 RXD0B, SBI0B, SEG31, P44 SBT0B, SEG30, P45 SDA5B, SEG29, P46 SCL5B, SEG28, P47 High-speed Oscillator Circuit ROM 508 KB PORT 2 ACZ0, IRQ0, SEG54, P20 ACZ1, IRQ1, SEG53, P21 IRQ2, SEG52, P22 IRQ3, SEG51, P23 IRQ4, SEG50, P24 NRST, P27 TXD2B, SBO2B, SEG42, P30 RXD2B, SBI2B, SEG41, P31 SBT2B, SEG40, P32 SDA4B, SBO4B, SEG39, P33 SCL4B, SBT4B, SEG38, P34 SCL4B, SBI4B, SEG37, P35 SEG36, P36 Low-speed Oscillator Circuit PORT 1 RMOUTC, TM0IOC, SEG49, P10 TM2IOC, SEG48, P11 TM1IOC, SEG47, P12 TM3IOC, SEG46, P13 TM4IOC, SEG45, P14 BUZZERB, TM7IOC, SEG44, P15 NBUZZERB, TM8IOC, SEG43, P16 PORT 0 LED0, TM7IOB, SBI1A, RXD1A, P00 LED1, TM8IOB, SBO1A, TXD1A, P01 LED2, TM9IOB, SBT1A, P02 LED3, TM2IOB, TM0IOB, RMOUTB, P03 TXD3A, SBO3A, LED4, P04 RXD3A, SBI3A, LED5, P05 SBT3A, LED6, P06 DA_A, LED7, P07 XO/P91 Block Diagram XI/P90 1.4.1 P87, SDO7, A18, COM3 P86, SDO6, A17, COM2 P85, TM9OD5, SDO5, A16, COM1 P84, TM9OD4, SDO4, A15, COM0 P83, TM9OD3, SDO3, A14, SEG0 P82, TM9OD2, SDO2, A13, SEG1 P81, TM9OD1, SDO1, A12, SEG2 P80, TM9OD0, SDO0, A11, SEG3 Figure:1.4.1 Block Diagram * Depending on the models. See [[1.1.2 Product Summary]] Publication date: October 2015 27 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5 Electrical Characteristics This LSI manual describes the standard specification. Please ask our sales offices for the product specifications. Model Contents MN101E30 Structure CMOS integrated circuit Application General purpose Function CMOS, 8-bit, single chip micro controller Publication date: October 2015 28 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.1 Absolute Maximum Ratings *2 *3 VSS = 0 V Parameter Symbol Rating 1 Power supply voltage VDD5 -0.3 to +7.0 2 Capacity connection pin VDD18 -0.3 to +2.5 3 *4 VDD -0.3 to +4.6 4 Input clamp current (ACZ) IC -500 to +500 5 Input pin voltage VI -0.3 to VDD5 + 0.3 6 Output pin voltage VO -0.3 to VDD5 + 0.3 7 I/O pin voltage VIO1 -0.3 to VDD5 + 0.3 P0 IOL1 (peak) 30 Other than P0 IOL2 (peak) 20 10 All pins IOH (peak) -10 11 P0 IOL1 (avg) 20 Other than P0 IOL2 (avg) 15 All pins IOH (avg) -5 8 9 12 Peak power current Average output current *1 13 Unit V A V mA 14 Power dissipation PT 400 15 Operating ambient temperature Topr -40 to +85 16 Storage temperature Tstg -55 to +125 mW C *1 Applied to any 100 ms period. *2 Connect approximate 1F capacitor between VDD18/VDD power supply pin and the ground, and approximate 10-times capacitor connect to VDD18/VDD between VDD5 power supply pin and the ground for the internal power supply stabilization. *3 The absolute maximum ratings are the limit values beyond which the LSI may be damaged. *4 Applied only in Flash version. Publication date: October 2015 29 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.2 Operating Conditions VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Condition Unit MIN TYP MAX Power supply voltage *4 1 2 Power supply voltage In not using PLL VDD5-1 fosc 20 MHz [Double speed mode: fs 20 MHz] 2.2 5.5 In using PLL VDD5-2 4.0 MHz fosc 10 MHz [Multiplied by 2 to 10: fs 20 MHz] 2.2 5.5 VDD5-3 fx=32.768 kHz [Normal mode: fsfx/2] 2.2 5.5 VDD5-4 [During STOP mode] 1.8 5.5 tc1 VDD5=2.2 V to 5.5 V 0.05 tc2 VDD5=2.2 V to 5.5 V 61 3 4 Voltage to maintain RAM data V Operating speed *5 5 Instruction execution time 6 *4 fosc: Input clock frequency to OSC1 pin. fx: Input clock frequency to XI pin *5 tc1: In the case of OSC1 as CPU clock, or OSC1 multiplied by PLL as CPU clock. tc2: In the case of XI as CPU clock. s Use LCD power supply voltage with VLC1 VDD5. .. .. Publication date: October 2015 30 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Condition Unit MIN TYP MAX Crystal oscillator 1 Figure:1.5.1 [NORMAL mode] 7 8 fxtal1 Crystal frequency External capacitors 9 10 Internal feedback resistor VDD5 = within the operation power supply voltage (Refer to the reference value of power supply voltage 1 to 3.) 2.0 20 C11 10 C12 10 Rf10 MHz pF VDD5=5.0 V 950 k 32.768 kHz Crystal oscillator 2 Figure:1.5.2 [SLOW mode] 11 12 fxtal2 Crystal frequency External capacitors 13 14 Internal feedback resistor VDD5=2.2 V to 5.5 V C21 4 C22 4 Rf20 pF VDD5=5.0 V 6 M XI OSC1 fxtal2 fxtal1 Rf10 Rf20 OSC2 XO MN101E30N MN101E30N C12 C11 Instruction cycle becomes clock frequency divided by 1/2 Built-in feedback resistor Figure:1.5.1 Crystal oscillator 1 C22 C21 Instruction cycle becomes clock frequency divided by 1/2 Built-in feedback resistor Figure:1.5.2 Crystal oscillator 2 Connect external capacitors that suits the used pin. When crystal oscillator or ceramic oscillator is used, the frequency is changed depending on the condenser rate. Therefore, consult the manufacturer of the pin for the appropriate external capacitor. .. .. Publication date: October 2015 31 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E VDD5 = 2.2 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Condition Unit MIN TYP MAX External clock input 1 OSC1 (OSC2 is unconnected) 15 Clock frequency 16 High level pulse width *6 fOSC1 1.0 twh1 17 Low level pulse width *6 twl1 18 Rising time *7 twr1 19 Falling time *7 twf1 20.0 MHz 22.5 Figure:1.5.3 22.5 ns Figure:1.5.3 0 5.0 0 5.0 External clock input 2 XI (XO is unconnected) 20 Clock frequency 21 High level pulse width *6 fOSC2 32.768 twh2 22 Low level pulse width *6 twl2 23 Rising time *7 twr2 twf2 4.5 Figure:1.5.4 Figure:1.5.4 s 4.5 0 20 0 20 ns 24 Falling time *7 *6 The clock duty rate in the standard mode should be 45 % to 55 % *7 Rising time and falling time differ depending on oscillation frequency. This is noted that the maximum value is a rough value, not a specified value. Consult the oscillator manufacturer and perform matching tests for determining appropriate values. Publication date: October 2015 kHz 32 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 0.9VDD5 0.1VDD5 twh1 twl1 twr1 twf1 twc1 Figure:1.5.3 OSC1 Timing Chart 0.9VDD5 0.1VDD5 twh2 twl2 twr2 twf2 twc2 Figure:1.5.4 XI Timing Chart Publication date: October 2015 33 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.3 DC Characteristics VSS=0 V Ta=-40 C to +85 C Parameter Symbol Power supply current *8 Conditions (NORMAL mode: fs=fosc/2 Rating MIN TYP MAX 4 (9) 8 (18) SLOW mode: fs=fx/2) 1 IDD1 fosc=20 MHz [Double-speed mode: fs=fosc] VDD5=5 V (In not using PLL) 2 IDD2 fosc=4 MHz [Multiplied by 5: fs=20 MHz] VDD5=5 V (In using PLL) 4 (10) 8 (20) 3 IDD fosc=8 MHz [Double-speed mode: fs=fosc] VDD5=5 V (In not using PLL) 1.5 (5) 3 (9) IDD4 fosc=4 MHz [Double-speed mode: fs=fosc] VDD5=5 V (In not using PLL) 1 (3) 2 (6) 5 IDD5 fx=32.768 MHz, [fs=fx/2] VDD5=3 V Ta=25 C 5 (60) 20 (120) 6 IDD6 fx=32.768 MHz, [fs=fx/2] VDD5=3 V Ta=85 C IDD7 fx=32.768 MHz VDD5=3 V Ta=25 C IDD8 fx=32.768 kHz VDD5=3 V Ta=85 C IDD9 VDD5=5 V Ta=25 C IDD10 VDD5=5 V Ta=85 C 4 7 8 Power supply current Supply current during HALT1 mode 9 Supply current 10 during STOP mode Publication date: October 2015 Unit mA 75 (200) 4 (6) 13 (18) A 70 (80) 1 (2) 6 (7) 60 (60) 34 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E *8 Measured under condition without load. (pull-up / pull-down resistors are unconnected.) • The supply current during operation, IDD1 to IDD4 are measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <NORMAL mode>, the MMOD pin is at VSS level, the input pins are at VDD5 level, and a 20 MHz square wave of VDD5 and VSS amplitudes is input to the OSC1 pin. • The supply current during operation, IDD5 and IDD6 are measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <SLOW mode>, the MMOD pin is at VSS level, the input pins are at VDD5 level, and a 32.768 kHz square wave of VDD5 and VSS amplitudes is input to the XI pin. • The supply current during HALT1 mode, IDD7 and IDD8 are measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <HALT1 mode>, the input pins are at VDD5 level, and an 32.768 kHz square wave of VDD5 and VSS amplitudes is input to the XI pin. • The supply current during STOP mode, IDD9 and IDD10 are measured under the following conditions: After the oscillation is set to <STOP mode>, the MMOD pin is at VSS level, the input pins are at VDD5 level, and the OSC1 and XI pins are unconnected. • The values in parentheses are for Flash version. Publication date: October 2015 35 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E VDD5=2.2 V to 5.5 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 1 MMOD, DMOD, ATRST VIH1 0.8VDD5 VDD 12 Input low voltage VIL1 0 0.2VDD5 13 Input leakage current ILK1 11 Input high voltage 2 VIN=0 V to VDD5 V A I/O pin 2 P27 (NRST) 14 Input high voltage VIH2 0.8VDD5 VDD5 15 Input low voltage VIL2 0 0.15VDD5 16 Pull-up resistor RRH1 VDD5=5.0V VIN=VSS Pull-up resistor ON 10 50 100 V k I/O pin 3 P10 to P16, P20 to P24, P30 to P36, P40 to P47, P50 to P57, P60 to P67, P70 to P77 17 Input high voltage VIH3 0.8VDD5 VDD5 18 Input low voltage VIL3 0 0.2VDD5 19 Input leakage current ILK2 2 VIN=0 V to VDD5 20 Pull-up resistor RRH2 VDD5=5.0 V VIN=VSS Pull-up resistor ON 10 50 100 21 Pull-down resistor RRH1 VDD5=5.0 V VIN=VSS Pull-down resistor ON 10 50 100 22 Output high voltage VOH1 VDD5=5.0 V IOH=-0.5 mA 4.5 23 Output low voltage VOL1 VDD5=5.0 V IOL=1.0 mA Publication date: October 2015 V A k V 0.5 36 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E VDD5=2.2 V to 5.5 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN I/O pin 4 TYP MAX P80 to P87, P90 to P95, PA0 to PA7, PB0 to PB3 24 Input high voltage VIH4 0.8VDD5 VDD5 25 Input low voltage VIL4 0 0.2VDD5 26 Input leak current ILK3 27 Pull-up resistor RRH3 VDD5=5.0 V VIN=VSS Pull-up resistor ON 10 28 Output high voltage VOH2 VDD5=5.0 V IOH=0.5 mA 4.5 29 Output low voltage VOL2 VDD5=5.0 V IOL=1.0 mA I/O pin 5 VIN=0 V to VDD5 50 V 2 A 100 k V 0.5 P00 to P07 30 Input high voltage1 VIH5 0.8VDD5 VDD5 31 Input low voltage1 VIL5 0 0.2VDD5 32 Input leak current ILK4 33 Pull-up resistor 2 VIN=0 V to VDD5 RRH4 VDD5=5.0 V VIN=VSS Pull-up resistor ON 10 10 4.5 50 k 34 Pull-down resistor RRL2 35 Output high voltage VOH3 VDD5=5.0 V 36 Output low voltage1 VOL3 VDD5=5.0 V IOL=1.0 mA LED output OFF 0.5 37 Output low voltage2 VOL4 VDD5=5.0 V IOL=15 mA LED output ON 1.0 Publication date: October 2015 A 100 VDD5=5.0 V VIN=VSS Pull-down resistor ON IOH=0.5 mA V 50 100 V 37 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E VDD5=2.2 V to 5.5 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN I/O pin 6 TYP MAX P20 (during used as ACZ) and P21 (during used as ACZ) are regulated at 5.0 V 38 Input high voltage1 VDHH 39 Input high voltage2 VDHL 40 Input low voltage1 VDLH 41 Input low voltage2 VDLL 42 Input clamp current IC3 4.5 1.5 Figure:1.5.5 V 3.5 0.5 500 VIN > VDD5, VIN < 0 V A Display output pin 1 COM0 to COM3 (At VLC1, VSS Voltage output) *9 43 Output high voltage (In VLC1 voltage output) Output low voltage 44 (In VSS voltage output) VOCOMH VDD5=VLC1=5.0 V ICOM= -10 A 4.4 V VOCOML VDD5=VLC1=5.0 V ICOM=10 A 0.6 Display output pin 2 SEG0 to SEG54 (At VLC1, VSS Voltage output) *10 45 Output high voltage (In VLC1 voltage output) VOSEGH VDD5=VLC1=5.0 V ISEG= -2 A 46 Output low voltage (In VSS voltage output) VOSEGL VDD5=VLC1=5.0 V ISEG=2 A 4.4 V 0.6 Display power pin 1 VLC1, VLC2, VLC3 RVL1 47 Internal dividing resistor 48 RVL2 Ta=25 C *11 (Impedance between VLC1 and VSS) 142.5 300 570 15 30 60 k *9 However, COM0 to COM3 are also used as P84 to P87. *10 However, SEG0 to SEG54 are also used as P10 to P16, P20 to P24, P30 to P36, P40 to P47, P50 to P57, P60 to P67, P70 to P77and P80 to 83. *11 Summation of 3 resistors among VLC1 and VLC2, VLC2 and VLC3, VLC3 and VSS Publication date: October 2015 38 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.4 A/C Converter Characteristics VDD5=5.0 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX ACZ1 pin 1 2 trs Rising time 30 tfs Falling time s Figure:1.5.5 30 trs tfs Input 2 VDD5 VDHH VDLH ( Input ) VDHL VDLL VSS Output 1 ( Output ) Figure:1.5.5 Operation of AC Zero-Cross Detection Circuit Publication date: October 2015 39 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.5 A/D Converter Characteristics VDD5=5.0 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN 1 Resolution 2 Non-linearity error 1 3 Differential linearity error 1 4 Zero transition voltage 5 Full-scale transition voltage TYP MAX 10 VDD5=5.0 V, VSS=0 V Vref+=5.0 V TAD=800 ns *12 VDD5=5.0 V, VSS=0 V Vref+=5.0 V TAD=800 ns *12 ±3 ±3 -30 10 30 4970 4990 5030 TAD=800 ns *12 12.93 7 fx=32.768 kHz TAD=15.2 s *12 427.25 8 TAD=800 ns *12 1.6 fx=32.768 kHz TAD=15.2 s *12 30.52 6 A/D conversion time Sampling time 9 Vref+ Note) 2.0 VDD5 VSS Vref+ Reference voltage 11 Analog input voltage 12 Analog input leakage current When channel is OFF VADIN=0 V to 5.0 V 2 13 Reference voltage pin input leakage current When VREF+ is OFF Vss VREF+ VDD5 5 14 Ladder resistance *12 VDD5=5.0 V LSB mV s 10 RLADD Bits V A 15 40 80 k TAD is A/D conversion clock cycle. The values of 2 to 5 are guaranteed on the condition that VDD5=Vref+=5 V, VSS=0 V. Note) The voltage difference between VREF+ and VSS should be set to more than 2 V. The reference voltage input to VREF+ pin should be used on the condition of 2.0 V VREF+ VDD5 to avoid the malfunctions of microcomputer. .. .. Publication date: October 2015 40 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.6 D/A Converter Characteristics VDD5=5.0 V VSS=0 V Ta=25 C Rating Parameter Symbol Conditions 1 Resolution 2 Reference voltage low level DAVSS 3 Reference voltage high level DAVDD 4 Zero scale output voltage VZS VDD5=5.0 V, VSS=0 V D7 to D0=ALL "L" 5 Full scale output voltage VFS VDD5=5.0 V, VSS=0 V D7 to D0=ALL "H" 6 Analog output resistance (Minimum reference resistance) ROAT 7 Non-linearity error NLE 8 Differential non-linearity error 9 Settling time Publication date: October 2015 Unit MIN TYP MAX - - 8 VSS - VDD5 -0.05 0 0.05 4.93 4.98 5.03 5 10 15 VDD5=5.0 V, VSS=0 V - ± 2.0 ± 3.0 DNLE VDD5=5.0 V, VSS=0 V - ± 2.0 ± 3.0 TSET External capacitor CL=15 pF All bits are set to ON or OFF - 1.5 3.0 Bits V k LSB s 41 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.7 Auto Reset Characteristics VDD5=VRST to 5.5 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 1 Operation voltage VDD7 Auto reset is used VRST 5.5 V 4.5 V Power supply voltage 2 Power supply detection level VRST 3.7 3 Supply voltage change rate t/V 250 s/V Power supply current 4 Auto reset power consumption Publication date: October 2015 IDD7 VDD5=5 V 220 330 A 42 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.8 Audio Output Characteristics VDD5=AVDD=5.5 V VSS=0 V Ta=-40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Output pin 7 DA1_AOUT AVDD=VDD5 4.5 S/N AVDD=5 V (Note1) 80 88 dB D.R. AVDD=5 V (Note1) 70 78 dB AVDD 1 Power supply voltage 2 Signal-to-noise ratio 3 Dynamic range 4 Total harmonic distortion ratio THD+N AVDD=5 V (Note1) 5 Output impedance RAOUT 5.5 0.16 AVDD=5 V 0.25 4.5 V 0.26 % 2.0 k Output pin 8 DA1_DOUT 6 Output voltage high level VOH2 VDD5=5.0 V IOH=-2 mA 7 Output voltage low level VOL2 VDD5=5.0 V IOL=2.0 mA V 0.5 (Note1) This is the value sampling 1kHz SIN wave at 20kHz and recording with 16bit-PCM. (Note2) H2,H3 and H4 are the output level at the measuring point on the audio charactoristic measuring curcuit(Figure:1.5.6). Measuring point DA1_AOUT HPM Amplifier circuit AVDD AVSS Figure:1.5.6 Audio Characteristic Measuring Circuit (a) AVDD and VDD5 should be at the same electric potential regardless of whether or not the audio production function is used. .. .. Publication date: October 2015 43 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E HPM + 220 οF 96 ADACR HPOUTL 100 οϑ 3.5 Ω 0.22 οF 32 Ω 93 ADACL Amplifier circuit HPOUTR 2.2 kΩ 1.5 kΩ 10 kΩ Measuring point - 2.7 kΩ 1 kΩ + + 1000 pF 1 MΩ HPOUTR 10 kΩ HPOUTL 1 οF 47 kΩ 47 kΩ + 100 pF 1000 pF 100 pF Figure:1.5.7 Audio Characteristic Measuring Circuit (b) Publication date: October 2015 44 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.5.9 Flash EEPROM Program Condition Item Symbol 1 Programming voltage level VDD5-6 2 Data retention period Thold 3 Programming guarantee number times EMAX Publication date: October 2015 Condition MIN 2.7 Rating TYP MAX 5.5 10 Unit V Years 1000 Times 45 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E 1.6 Package Dimension Units: mm Figure:1.6.1 Package Dimension (QFP100-P-1818B) Sealing material: EPOXY resin Lead material : Cu alloy Lead surface processing : Pd plating The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales offices. .. Publication date: October 2015 46 MN101E30N/E30R/EF30R 8-bit Single-chip Microcontroller PubNo. 2163001-019E Units: mm Figure:1.6.2 Package Dimension (LQFP100) The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales offices. .. Publication date: October 2015 47 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. 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