MD1730 8-Channel Ultra-Low Phase Noise Continuous Waveform Transmitter with Beamformer Features General Description • 8-Channel Ultrasound Continuous Waveform (CW) Transmitter with Integrated Beamformer • CW Output ±1V to ±6Vp-p with Low RON • -160 dbc/Hz Ultra-Low Phase Noise at 1 kHz Offset and 5 MHz • 8-Bit Programmable Per-Channel Beamforming Phase Delay • 8-Bit Programmable Dividers for CW Frequency with Input Clock Frequency up to 250 Mhz • Input Clock Compatible with LVDS/SSTL or Single-Ended LVCMOS • LVCMOS 2.5V Logic for the Control I/O pins • Fast SPI Interface Supports up to 200 MHz • SPI Interface Supports Daisy Chaining and Broadcasting Mode The MD1730 is an 8-channel ultra-low phase noise CW transmitter with integrated beamformer. It is designed for medical ultrasound imaging systems requiring high-performance CW Doppler mode. The MD1730 has a dedicated signal path designed to minimize phase noise to the output. In addition, it has a high-speed SPI interface that enables CW beamforming features. The outputs of the MD1730 can swing up to ±6V and each output has a separate programmable phase delay. Additionally, by programming the internal frequency divider register, the MD1730 can output different CW frequencies from a single clock source. For instance, when the input clock frequency is 160 MHz and the frequency divider is set to 16, an output CW frequency of 5 MHz can be obtained with a phase delay step size of 6.25 ns, which translates to an angular resolution of 11.25 degrees. Package Type • Medical Ultrasound Imaging System for Cardiovascular Application • Ultrasound Fetal Heart Monitoring Device • Ultrasound Flow Meter • Programmable Array Pattern Generator VCW+ CPF VCW- VGP CNF GND CKB0 SPIB MD1730 6x6x0.9 mm 36-lead VQFN* CBE0 Applications 36 35 34 33 32 31 30 29 28 EN 1 27 CW0 CLKP 2 26 CW1 CLKN 3 25 CW2 VLL 4 24 CW3 EP 37 GND 5 VDD 6 23 VGN 22 CW4 SCK 7 21 CW5 CSN 8 20 CW6 SDI 9 19 CW7 VCW+ CPF CNF VCW- VGN TXRW CKB1 CBE1 SDO 10 11 12 13 14 15 16 17 18 * Includes Exposed Thermal Pad (EP); see Table 3-1. 2016 Microchip Technology Inc. DS20005586B-page 1 MD1730 Block Diagram +2.5V +5V +10V 1uF VLL 1uF 2.2uF V DD VGP CBE0 CBE1 VLL CLK CLKP CLKN SCK VLL SCK SPI & R egis ters CSN S DI D0 S DO Q MS B S P IB CKB0 LV DS / S S T L C loc k Input CKB1 CLK HIZ[7: 0] P HD7~0[7: 0] C W F D[7: 0] VC W+ 8 64 EN 1uF P HD0[7: 0] E NA CLK Q C W F D[7: 0] E NA CLK VPF 0 to + 6V 1uF VC W+ CPF VPF Q C W0 V NF T XR W C W1 P HD1[7: 0] E NA CLK Q C W2 C W F D[7: 0] E NA CLK Q V C W- C W3 VC W+ C W4 C W5 C W6 P HD7[7: 0] E NA CLK Q C W F D[7: 0] E NA CLK VPF Q V NF CLK 1uF MD1730 T hermal P ad C NF 1uF V C WS UB G ND C W7 V NF V C W- 0 to - 6V VGN 2.2uF -10V DS20005586B-page 2 2016 Microchip Technology Inc. MD1730 MD1730 CW Output via HV2201 Application Block Diagram +10V +10V AVDD VDD1 +10V TC8020 +90V 6 of 12-FET VDD2 V DD2 SP1 GP1 OP1 DP1 DN1 V DD2 GN1 ON1 -90V SN1 SP2 High Speed Gate Buffers V DD1 LVL[1:0] POS[1:0] NEG[1:0] B/CW SEL GP2 ON2 GN2 +50V TX0 DP2 Control Logic and Level Translation POS NEG OP2 DN2 V DD1 EN XDCR -50V GND SN2 High Speed Gate Buffers OP3 SP3 GP3 DP3 V SS V DD1 GN3 ON3 DN3 MD1715 1 of 2-ch PAD GND SN3 AVSS -10V +10V PAD VSUB -10V +10V AVDD VSS VDD1 +10V TC8020 +90V 6 of 12-FET VDD2 V DD2 SP1 GP1 OP1 DP1 DN1 V DD2 GN1 ON1 -90V SN1 SP2 High Speed Gate Buffers B/CW LVL[3:2] POS[3:2] NEG[3:2] V DD1 EN SEL GP2 ON2 GN2 +50V TX7 DP2 Control Logic and Level Translation POS NEG OP2 DN2 V DD1 -50V XDCR GND SN2 High Speed Gate Buffers OP3 SP3 GP3 DP3 V SS V DD1 GN3 ON3 GND PAD HV2201 8-ch HV Analog Switch DN3 MD1715 1 of 2-ch SN3 OUTPUT SWITCHES LEVEL SHIFTERS SW0 AVSS -10V VSS PAD VSUB -10V +5V +2.5V V LL SW1 D LE CL SW2 D LE CL +10V V DD LATCHES D LE CL CLK 8-BIT SHIFT REGISTER DIN FPGA V GP DOUT CBE0 CBE1 SW6 D LE CL SW7 D LE CL VLL CLKP CLK CKB0 LVDS / SSLT Clock Input CLKN FPGA SCK VLL SCK CSN SDI SPI & Registers D0 PHD7~0[7:0] CW/ B CLR LE B/CW LE GND VDD +3.3V +2 to +6V CWFD[7:0] VCW+ 8 64 VCW+ EN CPF PHD0[7:0] ENA CW_START VPP -100V +100V HIZ[7:0] Q MSB SDO SPIB VNN CKB1 CLK CLK TXRW CWFD[7:0] Q ENA CLK VPF VPF Q VNF PHD1[7:0] ENA CLK CW0 CW1 CWFD[7:0] Q ENA CLK Q VCWVCW+ PHD7[7:0] ENA CLK CWFD[7:0] Q ENA CLK VNF MD1730 VCWSUB Thermal Pad VNF CNF CLK GND CW7 VPF Q VCWV GN -2 to -6V -10V 2016 Microchip Technology Inc. DS20005586B-page 3 MD1730 NOTES: DS20005586B-page 4 2016 Microchip Technology Inc. MD1730 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Positive Logic Supply (VLL) ........................................................................................................................ -0.5V to +3.0V Positive Supply Voltage (VDD).................................................................................................................... -0.5V to +6.0V Positive Supply Voltage (VGP).................................................................................................................. -0.5V to +13.5V Negative Supply Voltage (VGN)................................................................................................................ +0.5V to -13.5V CW Output Positive Supply Voltage (VCW+) ............................................................................................... -0.5V to +12V CW Output Negative Supply Voltage (VCW-)............................................................................................... +0.5V to -12V All Digital Inputs (VIN)................................................................................................................................. -0.5V to +3.0V CW Outputs (VOUT)...................................................................................................................................... -12V to +12V Operating Ambient Temperature ................................................................................................................. 0°C to +85°C Maximum Junction Temperature ................................................................................................................. 0°C to +85°C Storage Temperature ............................................................................................................................................ +125°C Thermal Resistance Junction to Ambient (ƟJA, JESD51-5)..................................................................................25°C/W Thermal Resistance Junction to Bottom Cu Pad (ƟJB, JESD51-5) ....................................................................6.4°C/W Thermal Resistance Junction to Package Top (ƟJC, JESD51-5).......................................................................13.5°C/W ESD Rating All Pins ............................................................................................................................................. ±1.0 kV † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: INPUT/OUTPUT PIN DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Parameters Sym. Min. Typ. Max. Units Logic Supply Voltage VLL 2.35 2.50 2.65 V VDD Supply Voltage VDD 4.75 5.0 5.25 V Positive Supply Voltage VGP 8.0 10 12 V Negative Supply Voltage VGN -12 -10 -8.0 V CW Output Positive Supply VCW+ 1.0 — 6.0 V CW Output Negative Supply VCW- -6.0 — -1.0 V VLL Quiescent Current ILLQ — 0.02 0.1 mA mA Conditions Operating Supply VDD Quiescent Current IDDQ — 0.15 0.2 VGP Quiescent Current IGPQ — 1.0 2.0 µA VGN Quiescent Current IGNQ — 33 45 µA VCW+ Quiescent Current ICW+Q — 26 45 µA VCW- Quiescent Current ICW-Q — 6 10 µA VLL Enabled Current ILLEN — 6.0 9.0 mA VDD Enabled Current IDDEN — 0.2 0.3 mA VGP Enabled Current IGPEN — 2.0 3.0 mA VGN Enabled Current IGNEN — 2.0 3.0 mA VCW+ Enabled Current ICW+EN — 2.0 3.0 mA VCW- Enabled Current ICW-EN — 2.0 3.0 mA Note 1: 2: (VGP+|VCW-|) ≥ 10V (VGN+|VCW+|) ≥ 10V TA= 0 to +85°C, Note 2 EN = 0, fCLK = fSCK = 0 All logic input no transit EN = 1, fSCK = 120 MHz TXRW = 0, SDI = 0, SDO no load. Characterized only; not 100% tested in production. Design Guidance Only (DGO). 2016 Microchip Technology Inc. DS20005586B-page 5 MD1730 TABLE 1-1: INPUT/OUTPUT PIN DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Sym. Min. Typ. Max. Units VLL Current at CW 5MHz Parameters ILL5 — 2.5 3.0 mA VDD Current at CW 5MHz IDD5 — 1.0 2.0 mA VGP Current at CW 5MHz IGP5 — 6.0 10 mA VGN Current at CW 5MHz IGN5 — 12 18 mA VCW+ Current at CW 5MHz ICW+5 — 26 35 mA VCW- Current at CW 5MHz ICW-5 — 21 30 mA Conditions EN = 1, fCLK = 80 MHz, TXRW = 1, CW 5 MHz, no load 8-channel SPI & Logic Input Logic High Voltage VIH 0.8 VLL — VLL V Input Logic Low Voltage VIL 0 — 0.2 VLL V Input Logic High Current IIH — — 1.0 µA Input Logic Low Current IIL — — µA SPI and Logic Input Capacitance CIN — 4.5 — pF Note 1 Output Logic High Current IOH — — mA 2.5V LVCMOS Output Logic Low Current IOL — — mA SDO Output Logic High Voltage VOH — — V SDO Output Logic Low Voltage VOL — 0.35 V Note 1: 2: — 2.5V LVCMOS with 5 pF load Characterized only; not 100% tested in production. Design Guidance Only (DGO). TABLE 1-2: SPI AND LOGIC AC ELECTRICAL SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Parameters Sym. Min. Typ. Max. Units tr — 0.65 — ns 1.5 pF load, Note 1 Output Fall Time tf — 0.65 — Output Rise Propagation Delay tdr — 2.8 — ns Output Fall Propagation Delay tdf — 3.0 — CLK rise 50% to output 50%, after latency. Note 1 Delay Time Matching tdm — ±0.5 ±1.0 ns Channel to channel, Note 1, fCLK = 80 MHz Note 1 Output Rise Time Conditions SDI Valid to SCK, Setup Time t1 0.6 1.0 — ns SCK To SDI Data Hold Time t2 2.0 — — ns SCK High Time % of 1/fCLK t3 45 — 55 % SCK Low Time % of 1/fCLK t4 45 — 55 % CSN Hi-Time t5 2-cycle — — SCK Note 2 SCK Rise to CSN Rise t6 — 2.0 — ns Note 1 CSN Low to SCK Rise t7 — 0.8 — ns SDO Valid from SCK Rise t8 — 3.1 4.0 ns CSN Rise to SCK Rise t9 — 2.0 — CSN Rise to TXRW or SPIB Rise t10 9-cycle TXRW or SPIB Fall to CSN Fall t11 1-cycle Note 1: 2: Note 2 SPIB = 0, 1.5 pF Load, Note 1 ns Note 1 SCK Note 2 Characterized only; not 100% tested in production. Design Guidance Only (DGO). DS20005586B-page 6 2016 Microchip Technology Inc. MD1730 TABLE 1-2: SPI AND LOGIC AC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Sym. Min. Typ. Max. Units SDO to SDI Valid Delay Parameters t12 — 2.3 3.0 ns TXRW Rise to CLKP Rise t13 — 2.5 — Latency to CW Wave Rise t14 Latency CSN Rise to TXRW Fall t15 2-cycle — — SCK Clock Frequency Conditions SPIB = 1, 1.5 pF Load, Note 1 ns 2-cycle Note 1 CLK After TXRW = 1, PHD=0, Note 2 — CLK Note 2 200 MHz Note 1 fSCK — EN Off Time tEN-Off — 20 30 ns Note 2 EN On Time tEN-On — 150 300 µs 2.0 µF on CPF/CNF, Note 2 Note 1: 2: Characterized only; not 100% tested in production. Design Guidance Only (DGO). TABLE 1-3: CLOCK BUFFER OUTPUTS AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Parameters Sym. Min. Typ. Max. Units Conditions Clock Output Frequency Range fCKB 40 160 250 MHz Note 1 Clock Output Duty Cycle D% 45 — 55 % Note 2 CKB0,1 Rise Time trb — 0.6 1.0 ns CKB0,1 Fall Time tfb — 0.5 1.0 fCLK = 80 Mhz, 1.5 pF load, Note 1 Output Rise Propagation Delay tdrb — 2.0 3.0 ns CLK rise to CKB, 50%, Note 1 Output Fall Propagation Delay tdfb — 2.0 3.0 CBE Enable Time tcbe — 2.1 3.0 CKB0,1 Output logic high VOHCKB — VLL — V Note 2 CKB0,1 Output Logic low VOLCKB — GND — V Note 2 Note 1: 2: CBE to CLK rise, 50%, Note 1 Characterized only; not 100% tested in production. Design Guidance Only (DGO). TABLE 1-4: CW OUTPUTS DC/AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Parameters CW Output Peak to Peak Voltage Sym. Min. Typ. Max. Units Conditions VCWOUT -6.0 - +6.0 V CW Output Rise Propagation Delay tdrCW — 4.0 6.0 ns CW Output Fall Propagation Delay tdfCW — 4.0 6.0 TxCLK 50% to CWx 10%, after latency, Note 1 CW Output Maximum Current ICW± ±250 ±300 — mA VCW± = ±5.0V, 0.1Ω load, Note 1 Note 1: 2: Characterized only; not 100% tested in production. Design Guidance Only (DGO). 2016 Microchip Technology Inc. DS20005586B-page 7 MD1730 TABLE 1-4: CW OUTPUTS DC/AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Parameters Static Output Resistance PFET Sym. Min. Typ. Max. Units Conditions RONCW — 7.5 12 Ω — 6.5 11 RON at VCW± = ±5.0V, ICW± = ±100 mA load, Note 1 — 1.0 %/C VCW± = ±5.0V, Note 2 Note 2 Static Output Resistance NFET Change in RDS(ON) with Temperature ∆RONCW — CW Phase Resolution REPhase — 1 — CLK NPhase — -160 — dBC/ CW 5 MHz, Hz 1 kHz Offset, Note 1 CW Phase Noise Note 1: 2: Characterized only; not 100% tested in production. Design Guidance Only (DGO). TABLE 1-5: LVDS / SSTL CLOCK INPUTS AC / DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V, VCW- = -6.0V, VDD = +5V, TA = 25°C. Parameters Sym. Min. Typ. Max. Units Conditions CLKP/CLKN Clock Frequency fCLK 40 160 250 MHz Note 1 Clock Input Slew Rate tCSR 1.0 — — V/ns Note 2 Control/Data Input Slew Rate tDSR 1.0 — — V/ns SSTL Reference Voltage VREFS 1.13 1.25 1.38 V Note 1 DC Input Logic High VIH(DC) VREFS +0.15 — VLL +0.3 V Note 1 DC Input Logic Low VIL(DC) -0.3 — VREFS -0.15 V Note 1 AC Input Logic High VIH(AC) VREFS +0.31 — — V AC Input Logic Low VIL(AC) - — VREFS -0.31 V VREF = 0.5VLL, Slew rate 1.0 V/ns, Note 1 VX(AC) 0.5VLL -0.2 — 0.5VLL+0.2 V CLK and CLK, Note 1 Single Ended Clock Input Differential Clock Input AC Differential Cross Point DC Input Max Swing Voltage VSWING(DC) 0.3 — VLL +0.6 V Note 1 AC Differential Input Voltage VSWING(AC) 0.62 — VLL +0.6 V Note 1 DC Input Signal Voltage VIN(DC) -0.3 — VLL +0.3 V Note 1 CLKP/CLKN Slew Rate SLEW 1.0 — — V/ns Note 2 Note 1: 2: Characterized only; not 100% tested in production. Design Guidance Only (DGO). DS20005586B-page 8 2016 Microchip Technology Inc. MD1730 NOTES: 2016 Microchip Technology Inc. DS20005586B-page 9 MD1730 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Current (mA) Note: 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 VDD = 5.0V, fCLK= 80 MHz, fCW = 5 MHz, 8-ch, no-load 2.5 Current (mA) 2.0 2 1.5 VDD = 2.5V, fCLK= 80 MHz, fCW = 5 MHz, 8-ch, no-load 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 Temperature (°C) FIGURE 2-1: IDD vs. Temperature. 5 4 3 VGP = 10V, fCLK= 80 MHz, fCW = 5 MHz, 8-ch, no-load 2 1 Current (mA) Current (mA) 6 0 20 30 40 50 60 70 80 90 100 80 90 100 VGN = -10V, fCLK= 80 MHz, fCW = 5 MHz, 8-ch, no-load 0 10 20 IVGP vs. Temperature. 25 20 20 15 VCW+ = 5V, fCLK= 80 MHz, fCW = 5 MHz, 8-ch, no-load 5 40 50 60 70 80 90 100 IVGN vs. Temperature. FIGURE 2-5: 25 10 30 Temperature (°C) Current (mA) Current (mA) 70 10 9 8 7 6 5 4 3 2 1 0 Temperature (°C) FIGURE 2-2: 60 IVLL vs. Temperature. FIGURE 2-4: 7 10 50 Temperature (°C) 8 0 40 VCW- = -5V, fCLK= 80 MHz, fCW = 5 MHz, 8-ch, no-load 15 10 5 0 0 0 10 20 30 40 50 60 70 80 90 100 0 10 DS20005586B-page 10 IVCW+ vs. Temperature. 30 40 50 60 70 80 90 100 Temperature (°C) Temperature (°C) FIGURE 2-3: 20 FIGURE 2-6: IVCW- vs. Temperature. 2016 Microchip Technology Inc. MD1730 3 VDD = 5V, 8-ch, 220 pF, 1 kȍ 2 Current (mA) Current (mA) 2.5 1.5 1 0.5 0 0 2 4 6 8 10 12 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 VLL = 10V, 8-ch, 220 pF, 1 kȍ 0 2 CW Frequency (MHz) FIGURE 2-7: Frequency. 200 150 100 50 12 IVLL vs. CW Output 9 7 5 3 1 0 2 4 6 8 10 -1 0 12 2 4 CW Frequency (MHz) 400 Current (mA) 300 250 200 150 100 50 0 2 4 6 8 10 12 10 9 8 7 6 5 4 3 2 1 0 IVCW- vs. CW Output 2016 Microchip Technology Inc. 10 12 VGP = 10V, 8-ch, 220 pF, 1 kȍ 0 2 CW Frequency (MHz) FIGURE 2-9: Frequency. 8 IVGN vs. CW Output FIGURE 2-11: Frequency. VCW- = -5V, 8-ch, 220 pF, 1 kȍ 350 6 CW Frequency (MHz) IVCW+ vs. CW Output FIGURE 2-8: Frequency. Current (mA) 10 11 250 0 8 13 Current (mA) 300 0 6 15 VCW+ = 5V, 8-ch, 220 pF, 1 kȍ 350 Current (mA) FIGURE 2-10: Frequency. IVDD vs. CW Output 400 4 CW Frequency (MHz) 4 6 8 10 12 CW Frequency (MHz) FIGURE 2-12: Frequency. IVGP vs. CW Output DS20005586B-page 11 MD1730 -100 MD1730 CW Output Phase Noise at 5 MHz, Offset 10 Hz to 100 kHz Mixer + Lowpass + HP4195A with ATR -20 dB, RBW 10 Hz Phase Noise (dBc/Hz) -110 -120 -130 -140 -150 -160 -170 -180 0.01 0.1 1 10 100 Offset Frequency (kHz) FIGURE 2-13: DS20005586B-page 12 Typical CW Output Phase Noise Curves. 2016 Microchip Technology Inc. MD1730 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE 6x6 VQFN Symbol Pin Function 1 EN Device Enable Input. When EN = 0, the SPI and the internal regulator are disabled. The device is enabled when EN = 1. Note that the EN pin has no control over the clock buffers, as the clock buffers have their dedicated enable pins. 2 CLKP Positive Input of the Internal System Clock and is compatible with LVDS/SSTL. For LVCMOS 2.5V input refer to Figure 4-8. 3 CLKN Negative Input of the Internal System Clock and is compatible with LVDS/SSTL. For LVCMOS 2.5V input refer to Figure 4-8. 4 VLL 5, 33 GND Ground, 0V 6 VDD +5V Positive Voltage Power Supply, it requires a 1.0 µF decoupling capacitor to GND 7 SCK Serial Peripheral Interface (SPI) clock input 8 CSN Serial Peripheral Interface (SPI) chip-select. CSN is an active-low signal. Serial Peripheral Interface (SPI) data input +2.5V Positive Voltage Power Supply, it requires a 1.0 µF decoupling capacitor to GND 9 SDI 10 SDO 11, 35 CBE0-1 The clock buffer enable pin. When CBEn = 0, the corresponding clock buffer is disabled. The clock buffer is enabled otherwise. 12, 34 CKB0-1 2.5V Single-ended Clock Buffer output pins 13 TXRW CW Transmission Control pin. When TXRW = 0, the SPI is enabled for read/write. When TXRW = 1, the SPI is disabled and the CW transmission is started. 14, 23 VGN -10V Negative Voltage Power Supply, it requires a 2.2 µF capacitor to GND. The VGN supply is also the substrate and should be the most negative supply to the chip. 15, 31 CNF Negative Floating Supply Bypass Capacitor pin. Connects 1 µF/10V capacitor between this pin and the VCW- pin. 16, 30 VCW- -1V to -6V Negative Voltage Power Supply for the CW output, it requires a 1.0 µF decoupling capacitor per pin to GND 17, 29 CPF Positive Floating Supply Bypass Capacitor pin. Connects 1 µF/10V capacitor between this pin and the VCW+ pin. 18, 28 VCW+ +1V to +6V Positive Voltage Power Supply for the CW output. It requires a 1.0 µF decoupling capacitor per pin to GND. 19, 20, 21, 22, 24, 25, 26, 27 CW0-7 Serial Peripheral Interface (SPI) data output Channel 0-7 CW Waveform Output 32 VGP +10V Positive Voltage Power Supply, it requires a 2.2 µF decoupling capacitor to GND 36 SPIB SPI Broadcasting Mode pin. When SPIB = 1, the broadcast mode is enabled. 37 EP Exposed Thermal Pad (EP); must be connected to GND 2016 Microchip Technology Inc. DS20005586B-page 13 MD1730 NOTES: DS20005586B-page 14 2016 Microchip Technology Inc. MD1730 4.0 DEVICE DESCRIPTION 4.1 Operation Description The MD1730 is an 8-channel ultra-low phase noise monolithic CW transmitter. It consists of an SPI interface to program internal phase delay registers and frequency dividers to facilitate CW beamforming. It supports differential LVDS/SSTL and single-ended 2.5V LVCMOS clock inputs. The MD1730's output path is designed to provide ultra-low phase noise and can swing up to ±6V. The following sections provide a detailed overview of MD1730's feature set and operation. 4.2 Using The Built-in Clock Buffers The MD1730 has two built-in single ended clock output buffers. The MD1730 can accept LVDS, SSTL25 and LVCMOS 2.5V clock at its input and provide a single-ended output buffered clock. The clock buffers are independent of the chip's main EN pin and each output clock buffer can be enabled or disabled separately using the CBE0 or CBE1 pin. The maximum clock frequency of the buffers is 250 MHz. The output timing diagram for the clock buffers is shown in Figure 4-5. As shown in the diagram CKB0 and CKB1, clock outputs are only dependent on CBE0 and CBE1 respectively. This feature makes it convenient to drive the TX pulser retiming clock input, such as the HV7321. Using the built in clock buffers will save the cost of additional buffers, reduce PCB area, simplify the system clock distribution design and improve power savings as well. 4.3 SPI Registers Description REGISTER 4-1: SPI CONTROL REGISTER DESCRIPTION Data Bits Description W/R The W/R is the read write control bit. When W/R = 1, the SPI writes the data provided at the addressed register. When W/R = 0, the SPI reads the data stored from the appropriate register. The read operation is disabled when SPIB = 1. CWFD<7:0> The CWFD<7:0> register stores the divisor value for setting the CW output frequency. The CW output frequency is set by using the equation (fCW = fCLK/(2*CWFD)) except CWFD = 0. For CWFD = 0 the CW output frequency is fCW = fCLK/2*512. The CW output frequency ranges from (fCLK /512) ≤ fCW ≤ (fCLK /2). The register's initial value is 0. PHDCH<7:0> PHDCH<7:0> sets the phase delay for each individual channel. The equation for the output delay time is PHD<7:0>/fCLK + 2/fCLK once TXRW goes high. The register initial value is 0. Refer to Figure 4-4 for further details. HIZCH HIZCH bit enables the channel output when the corresponding bit is 0. The channel is disabled and its’ output becomes high Z when the corresponding bit is 1. The default register value is 0. Note: CH denotes channel number 0 to 7. 2016 Microchip Technology Inc. DS20005586B-page 15 MD1730 REGISTER 4-2: SPI REGISTER ADDRESS AND CONTROL BITS W/R SPI Register ADD<3:0> D12 Write or Read Data <7:0> D11 D10 D9 D8 0 0 0 0 Channel 0 phase delay PHD0<7:0> 1 = Write 0 = Read MSB first. 0 0 0 1 Channel 1 phase delay PHD1<7:0> 0 0 1 0 Channel 2 phase delay PHD2<7:0> 0 0 1 1 Channel 3 phase delay PHD3<7:0> (See Section 4.3 and Section 4.4) 0 1 0 0 Channel 4 phase delay PHD4<7:0> 0 1 0 1 Channel 5 phase delay PHD5<7:0> 0 1 1 0 Channel 6 phase delay PHD6<7:0> 0 1 1 1 1 0 0 0 1 0 0 1 Note: TABLE 4-2: 4.4 D6 D5 D4 D3 D2 D1 D0 HIZ1 HIZ0 Channel 7 phase delay PHD7<7:0> HIZ7 HIZ6 HIZ5 HIZ4 HIZ3 HIZ2 CW frequency divisor number CWFD<7:0> Power-On or EN = 0 sets all the registers to 0. TABLE 4-1: Note: D7 PHD<7:0> PHASE DELAY TIME REGISTER DESCRIPTION PHD<7:0> Delay Time to Start Transmitting 00000000 0/fCLK (Power-on default) 00000001 1/fCLK 00000010 2/fCLK ......... ........ 11111110 254/fCLK 11111111 255/fCLK CWFD<7:0> CW FREQUENCY DIVIDER REGISTER DESCRIPTION CWFD[7:0] Transmit CW Frequency fCW 00000000 fCLK/512 (Power-on default) 00000001 fCLK/2 00000010 fCLK/4 00000011 fCLK/6 ......... ........ 11111110 fCLK/508 11111111 fCLK/510 The selected CW frequency is same for all the CW0~7 outputs: fCW = fCLK/2*CWFD. The CW frequency applies to all channels. Serial Peripheral Interface (SPI) The MD1730’s SPI is used to program the phase delay and frequency divider registers. The SPI supports writing at speed up to 200 MHz and the MSB is shifted in first. SPI interface supports two operating modes: daisy chain mode and broadcasting mode. When SPIB = 0, the MD1730 is in daisy chain mode. In this mode, it supports both read and write operations. When SPIB = 1 the chip enters the “Broadcasting” mode. In this mode, the SDI data shifts into the shift register as well as to the SDO output. In this mode, the user can write the same register of different daisy chained chips with the same value in a single write DS20005586B-page 16 transaction. However, when SPIB = 1 the read operation is disabled. To verify the written data for each chip, the user can revert SPIB = 0 and perform a normal read operation. 4.4.1 SPI WRITE OPERATION EXAMPLES The following is a 1-byte writing example for the register at ADD = 0011b with the data D<7:0> = 01010101 when SPIB = TXRW = 0. 1. 2. The Write operation starts with setting CSN to low. The SCK clock is used to shift in the following SDI data: 2016 Microchip Technology Inc. MD1730 D12 = 1, W/R bit set equal to high for write operation. ADD<11:8> = 0011b, address for channel-3’s phase delay register. 3. 1. The SDI data is shifted in at the rising edge of SCK. 2. 2. The write operation starts with setting CSN to low with TXRW = 0 and SPIB = 1. The SCK clock is used to shift in the following SDI data to the first MD1730 chip: D12 = 1, W/R bit set equal to high for write operation. ADD<11:8> = 0011b, address channel-3’s phase delay register. for the The read operation starts with setting CSN to low. The SCK clock is used to shift in the following SDI data: D12 = 0, W/R bit set equal to high for read operation. Once the complete data has been shifted in, the CSN should be taken high to finish the writing operation. The SDI data is latched into channel-3’s phase delay register on the rising edge of the CSN signal. CSN has to be kept high for a minimum of 2-SCK cycles for the data to be written into the appropriate register. The MD1730 can also be used in the Broadcasting mode to write several daisy chained chips with the same data. The Broadcasting mode can be used to reduce the time required to write the SPI if several MD1730 chips need the same data. The following is a 1-byte writing example for the register at the address location ADD = 0011b with data D<7:0> =01010101b while the MD1730 is set to broadcasting mode. SPI READ OPERATION EXAMPLES The following is a 2-byte reading example from the register at ADD = 0011b (Channel-3’s phase delay register) when SPIB = TXRW = 0. D<7:0> = 01010101b, data to be written into channel-3’s phase delay register. In the case of eight chips daisy chained together as shown in Figure 4-3, there should be 13 x 8 = 104 cycles of SCK before the CSN is taken high. 1. 4.4.2 ADD<11:8> = 0011b, address for channel-3’s phase delay register. D<7:0> = X, for a Read operation the data field is don’t’ care. The SDI data is shifted in at the rising edge of SCK. 3. 4. 5. Once the complete data has been shifted into the SPI the CSN is taken high. While CSN is high the MD1730 fetches the data located at ADD<11:9> = 0011b and places it in its internal shift register. Once the complete data has been shifted in, the CSN should be taken high to finish the reading operation. While CSN is high the MD1730 fetches the data located at ADD<11:9> = 0011b and places it in its internal shift register. CSN has to be kept high for a minimum of 2-SCK cycles for the data to be fetched and placed into the internal shift register. The CSN is taken low and during the next 13 SCK clock cycles, the fetched data in the internal shift register is clocked out on the rising edge of SCK from the SDO of the MD1730. D<7:0> = 01010101, data to be written into the channel-3’s phase delay register. The SDI data is shifted in at the rising edge of SCK. In Broadcasting mode, the same set of data shifted into the first chip’s SDI is sent to all the MD1730 chips along the daisy chain. As shown is Figure 4-3 when SPIB = 1 an internal switch connects the SDI and SDO directly. 3. Once the complete data has been shifted in, the CSN should be taken high to finish the writing operation. The SDI data is latched into each chip’s channel-3 phase delay register on the rising edge of the CSN signal. CSN has to be kept high for a minimum of 2-SCK cycles for the data to be written into the appropriate register. 2016 Microchip Technology Inc. DS20005586B-page 17 MD1730 t3 t4 t1 t6 SCK t2 t9 D12 SDI D11 D0 D1 t7 t5 CSN t11 t10 t8 SDO SPIB TXRW FIGURE 4-1: SPI Register Read/Write Timing with SPIB = 0, TXRW = 0. t3 t4 t1 t6 SCK t2 D12 SDI t9 D11 D1 D0 t7 t5 CSN t11 SDO t10 t12 D12 D11 D1 D0 SPIB TXRW FIGURE 4-2: Note: SPI Register Broadcasting Write Timing with SPIB = 1, TXRW = 0. When in SPIB = 1 mode, the SPI register READ operations are not available. DS20005586B-page 18 2016 Microchip Technology Inc. MD1730 SPIB TXRW 7TXXRRWW SPIB SPIB TXRW TXRW FPGA SDI SDI 13bit Shift Shift Reg. 13bit Reg. SCK SCK D0 D0 SDO SDO Q12 Q12 13bit Shift Shift Reg. 13bit Reg. SCK SCK CS CSN SPIB SPIB SDI SDI SDO SDO Q12 Q12 Q12 Q12 D0 D0 7TXXRRWW SPIB SPIB SDI SDI SDO SDO SDO U8 0' U2 0' U1 0' D0 D0 13bit Shift Shift Reg. 13bit Reg. SCK SCK CS CSN CS CSN SCK CSN SDI FIGURE 4-3: 4.5 Multiple MD1730 Devices SPI Daisy Chain Connections. TXRW high. The phase delay counter starts counting down after a two CLK cycle latency. This is illustrated in Figure 4-4 for channel 0 and channel 1. In channel 0’s case, the phase delay starts counting down from 2 to 0 after the latency and once the delay reaches 0 on the next rising edge of CLK, the positive output appears on the pin CW0. Based on the value of the CWFD<7:0> register, after 4-CLK cycles the CW0 output toggles to the negative supply rail. Subsequently, after 4-CLK cycles at the negative rail, the output switches back again to the positive supply rail, completing one full CW output wave cycle. This process continues until the TXRW pin deasserts low, which shuts the transmission off and forces the channel into a high impedance state. This same procedure applies to channel 1, which is also depicted in Figure 4-4. CW0~7 Output Timing The CW output waveform transmission timing is crucial to an ultrasound imaging system. Any small timing variations on the output can degrade the phase noise performance. The MD1730’s internal circuitry is designed to ensure ultra-low phase noise. Figure 4-4 shows an example of the output waveform timing diagram. The chip is enabled by taking the EN pin high. Then using the SPI, channel-0’s and channel-1’s phase delay registers (PHD0<7:0> and PHD1<7:0>) are programmed with delays of 2 and 3 respectively. The rest of the channels are set to a high impedance state by programming the HIZ<7:0> register with data 11111100b. Furthermore, the frequency divider register (CWFD<7:0>) is set to 4. After completing the SPI operation the transmission starts by asserting EN=1 EN tEN_ON TXRW TXRW t13 PHD07:0! (Phase Delay Time for Ch0) PHD17:0! (Phase Delay Time for Ch1) (if PHD0=2) 2 (if PHD1=3) 3 1 2 -1 0 1 -1 0 PHD7:0!Start Count Down CLKP (fCLK) t14 (3-cycle CLK) CW0 Hi Z tdfCW tdrCW tdrCW CW end VCW+ CW CH = HiZ (if CWFD[7:0]=4) tdfCW tdrCW VCW+ CW1 VCW- tdrCW CW CH = HiZ Hi Z VCW- FIGURE 4-4: CW0~7 Output Timing Diagram. 2016 Microchip Technology Inc. DS20005586B-page 19 MD1730 CBE0 CBE1 tcbe CLKP (fCLK) tdrb tdfb CKB0 trb trb CKB1 FIGURE 4-5: 4.6 Clock Buffers CKB0/1 Output Timing Diagram. MD1730 Working with Two HV7321 The diagrams shown in Figure 4-6 and Figure 4-7 illustrate the MD1730 driving two HV7321s. 11. Once the system is ready to perform CW Doppler measurement, assert TXRW high to start the CW transmission on the selected channels. When the HV7321 is operated in the specific mode, CW MODE = 1, along with the MD1730, the following steps should be taken to ensure the combination settings work correctly: 6. Apply all power supply rails to both chips and set HV7321’s OEN = REN = PWS = 1 along with MD1730’s EN = 1 to enable both chips. Set all other control logic pins to zero. 7. Adjust the VCW+ and VCW- power supplies to the required peak-to-peak voltage levels for CW output transmission. Please note that a higher peak-to-peak transmission voltage will result in the MD1730 dissipating more power. The power dissipation on the MD1730 is proportional to the square of the peak-to-peak voltage. 8. Assert HV7321’s MODE pin high. 9. Program the MD1730 with the desired CW frequency divider and delay settings for CW transmission. 10. To place a channel in receive mode, set the corresponding pins SEL, NEG, POS = 011b on the HV7321. To place a channel to CW Transmit mode, set the corresponding pins SEL, NEG, POS to any other combination other than 011b on HV7321. This will put that channel of the HV7321 high voltage Tx output in High Z mode, but turn the channel’s CWSW on. In the case user wants a channel not in High Z or CW Transmit mode, then similarly, to set the channel of HV7321 to High Z and also set the MD1730’s corresponding bit in the HIZ register to 1. DS20005586B-page 20 2016 Microchip Technology Inc. MD1730 +2.5V +5V V LL C T R N[3:0] +10V V DD VGP 0 to+80V OE N 1 of 4 C hannels REN +2.5V T x F P G A I/Os VPP0 MODE PWS VPF0 V NF 0 OT P 0 to-80V OT P N DT [63:0] V NN0 VPP1 S E L0 0 to+80V NE G 0 VPF1 V NF 1 -0 to-80V P OS 0 S E L3 +2.5V +5V +1 to +6V +10V Decode & Level S hift V NN1 T X0 NE G 3 X0 R T ZS W TR S W P OS 3 V LL V DD VGP CPF VCW+ C B E 0,1 C LK P C LK N V LL R X0 TR S W CBE 1 R x0 CKB0 C LK LV DS C LK C LK C LK R XDMP C W IN0 SCK V LL S DI CBE 0 SPI C W IN1 CKB1 S DO CWSW R G ND C W IN2 CSN HIZ[7:0] C W IN3 VCW+ R G ND U2 HV 7321 T X1-3 R X1-3 T XR W CW F re.Dvdr & P has e Delay VPF CW0 V NF CW1 C h0 S UB G ND VCW- C h1~6 V LL CW7 V DD VGP 0 to+80V OE N 1 of 4 C hannels REN C h7 VPP0 MODE U1 MD1730 VCW- PWS VPF0 V NF 0 OT P N S UB T her. V G N PAD +10V CW5 V NF G ND +5V -10V +2.5V CW6 VPF EN VGN CW3 CW4 VCW+ S P IB V S UB CW2 C NF -10V VCW- To Other IC s 0 to-80V To Other IC s V NN0 VPP1 S E L0 -1 to -6V 0 to+80V NE G 0 VPF1 V NF 1 -0 to-80V P OS 0 S E L3 Decode & Level S hift V NN1 T X0 NE G 3 X4 R T ZS W TR S W P OS 3 To Other IC s R X0 TR S W R x4 C LK R XDMP C W IN0 C W IN1 CWSW C W IN2 C W IN3 R G ND R G ND U3 HV 7321 T X1-3 R X1-3 S UB G ND V S UB VGN -10V FIGURE 4-6: MD1730 & 2x HV 7321 Diagram MD1730 Works with Two HV7321 4-Channel ±80V 2.6A 5-Level Ultrasound Pulsers. 2016 Microchip Technology Inc. DS20005586B-page 21 CNF1 VNN2 VNN0 VNN1 VNN0 CPF0 CNF0 VGN VPP0 GDN VPP0 SEL0 VDD1 MODE POS0 NEG0 MD1730 CWIN0 CPF1 SEL1 VPP1 NEG1 TX3 POS1 RXO3 CWIN1 RGN D OEN RXO1 ,sϳϯϮϭ 9x9mm QFN-64 PWS CLK GND VLL TX1 CPOS CNEG TX2 REN RXO2 SEL2 RGN D NEG2 RXO3 TX3 CNF1 VNN1 VNN2 VNN0 VNN0 VNF0 CFP0 VPP0 VPP0 VGP GND VDD1 OTP1 CPF1 CWIN3 CW0 CW1 CLKE VPP1 SEL3 POS3 EN CLKW CWIN2 NEG3 VCW+ VCW- CP F GND CN F VGP CBE0 CK B0 SPIB POS2 CW2 DϭϳϯϬ 6x6mm QFN-36 To Probe & Rx LNA CW3 VGN CNF1 VNN1 VNN2 VNN0 CPF0 CNF0 VNN0 VPP0 VGN GDN CW7 VPP0 CW6 VDD1 CW5 SDI MODE SCK CSE SEL0 CW4 POS0 VDD NEG0 VLL GN D CP F VCW- VCW+ CN F VGN TXRW SDO CBE1 CK B1 CWIN0 CPF1 SEL1 VPP1 NEG1 TX3 POS1 RXO3 CWIN1 RGN D OEN RXO1 ,sϳϯϮϭ 9x9mm QFN-64 PWS CLK GND VLL TX1 CPOS CNEG TX2 REN RXO2 SEL2 RGN D NEG2 RXO3 TX3 POS2 FIGURE 4-7: 4.7 CNF1 VNN1 VNN2 VNN0 VNN0 VNF0 CFP0 VPP0 VPP0 VGP GND VDD1 MD1730 Working with Two HV7321 Pulsers Pinout and Package. CW Transmission Clock The input clock of the MD1730, used for CW transmission, can be connected either differentially or single-ended. Figure 4-8 shows the LVDS differential implementation for the transmission clock. Here the CLKP and the CLKN pins are directly driven by a LVDS clock buffer. It is highly recommended that a multiple-output LVDS clock buffer IC is used, such as the SY89832U, and that a 100Ω termination resistor is placed very close to the CLKP and CLKN pins. For successful transmission of the LVDS signal over differential traces, the following guidelines should be followed while laying out the PCB board: • To ensure minimal reflections and to maintain the receiver’s common-mode noise rejection, keep the differential traces as short as possible between the clock buffer IC and the CLKP/CLKN pins of the MD1730. • To reduce skew, the electrical lengths between differential LVDS traces should be identical. The arrival of one differential signal before the other will create a phase difference between the signal pairs, which would create clock skew and impair the system performance. • Minimize the number of vias or other DS20005586B-page 22 OTP1 CWIN3 CPF1 POS3 VPP1 SEL3 NEG3 CWIN2 discontinuities in the signal path. To avoid discontinuities, arcs or 45-degree traces are recommended instead of 90-degree turns. • Any parasitic loading, such as capacitance, must be present in equal amounts on each differential line. Figure 4-9 illustrates the two cases for the MD1730 used in a single-ended configuration. In these cases, one of the clock input pins, CLKP or CLKN, is connected to the VLL/2 voltage level and bypassed to ground with a 0.1 uF bypass capacitor. Each bypass capacitor must be placed very close to the MD1730. The other clock input pin connects to the main clock line. The PCB traces on the clock line must be designed for a 50Ω impedance with respect to the PCB ground place. Also, the clock pin must be terminated with a small 50Ω SMT resistor. Generally, the LVCMOS input configuration provides better CW phase noise performance due to its higher amplitude swing as compared to the LVDS configuration. However, if the user needs a very high frequency clock transmission, such as 160 MHz240 MHz range for a higher phase delay resolution, then LVDS should be used because it provides a better PCB clock trace distribution. 2016 Microchip Technology Inc. MD1730 TXRW EN 2.5V (from FPGA) 2.5V VLL TXRW VCC CLKP CLKN 100 TXRW VLL EN EN U4 0' U2 0' GND CLKP CLKN TXRW VLL U1 0' 2.5V EN EN 2.5V GND 100 GND CLKP CLKN DifferHQtialLVDS ClockLine-Pair 100 Q0 Clock Source IN GND Q1 ... ... Q3 SY89832U CLK Buffer FIGURE 4-8: LVDS Differential Transmission Clock. TXRW EN VLL 2.5V 80-150MHz Clock OSC. 2.5V 2.5V (from FPGA) GND VLL CLKPCLKN TXRW GND CLKP CLKN CLKP CLKN GND GND 33ohm 0.1F 0.1F 1.25V DC 2.5V 2.5V (from FPGA) VLL 2.5V EN TXRW U1 0' CLKPCLKN EN GND VLL 2.5V TXRW VLL EN U2 0' CLKP CLKN TXRW EN U4 0' CLKP CLKN GND GND Single-Ended LVCMOS Clock Line CLK0 CLK1 CLK3 33ohm 0.1F PL133-47 CLK Buffer FIGURE 4-9: 0' CLK3 TXRW EN GND EN Single-Ended LVCMOS Clock Line 0.1F REF TXRW VLL U4 CLK0 CLK1 PL133-47 CLK Buffer 80-150MHz Clock OSC. EN U2 0' U1 0' EN REF EN TXRW 2.5V 0.1F 0.1F 1.25V DC LVCMOS Single-Ended Transmission Clock. 2016 Microchip Technology Inc. DS20005586B-page 23 MD1730 NOTES: DS20005586B-page 24 2016 Microchip Technology Inc. MD1730 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 36-Lead VQFN (6x6x0.9 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: MD1730 e3 1624256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2016 Microchip Technology Inc. DS20005586B-page 25 MD1730 36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN] SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]" Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 A B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C C SEATING PLANE 0.10 C A1 A 36X SIDE VIEW (A3) 0.08 C 0.10 D2 C A B 0.10 C A B E2 2 1 NOTE 1 K N L e BOTTOM VIEW 36X b 0.10 0.05 C A B C Microchip Technology Drawing C04-272B-M2 Sheet 1 of 2 DS20005586B-page 26 2016 Microchip Technology Inc. MD1730 36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN] SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]" Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Notes: Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 Terminal Thickness A3 Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 Terminal Width b Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 3.60 3.60 0.18 0.50 0.45 MILLIMETERS NOM 36 0.50 BSC 0.90 0.02 0.20 REF 6.00 BSC 3.70 6.00 BSC 3.70 0.25 0.60 0.55 MAX 1.00 0.05 3.80 3.80 0.30 0.75 - 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-272B-M2 Sheet 2 of 2 2016 Microchip Technology Inc. DS20005586B-page 27 MD1730 36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x0.9 mm Body [VQFN] SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]" Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 36 G2 1 2 Y2 C2 ØV EV G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X36) X1 Contact Pad Length (X36) Y1 Contact Pad to Center Pad (X36) G1 Space Between Contact Pads (X32) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 3.80 3.80 5.60 5.60 0.30 1.10 0.35 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2272B-M2 DS20005586B-page 28 2016 Microchip Technology Inc. MD1730 APPENDIX A: REVISION HISTORY Revision B (November 2016) The following is the list of modifications: • Updated Section “Product Identification System”. • Minor typographical corrections. Revision A (September 2016) • Original Release of this Document. 2016 Microchip Technology Inc. DS20005586B-page 29 MD1730 NOTES: DS20005586B-page 30 2016 Microchip Technology Inc. MD1730 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip sales office. PART NO. Device [X](1) - X /XX Tape and Reel Temperature Package Option Range Device: MD1730: MD1730T: Programmable High-Voltage, Ultrasound-Transmit Beamformer Programmable High-Voltage, Ultrasound-Transmit Beamformer (Tape and Reel) Temperature Range: V = Package: M2 = Very Thin Plastic Quad Flat Pack, No-Lead Package – 6x6x1.0 mm Body, 36-Lead (VQFN) 2016 Microchip Technology Inc. 0C to +85C Examples: a) b) MD1730-V/M2: Programmable High-Voltage Ultrasound-Transmit Beamformer, 36LD 6x6 mm VQFN package MD1730T-V/M2: Tape and Reel, Programmable High-Voltage Ultrasound-Transmit Beamformer, 36LD 6x6 mm VQFN package Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20005586B-page 31 MD1730 NOTES: DS20005586B-page 32 2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. 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ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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