LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Revised TEST CONDITION of Average Operating Power Supply Current(Icc1) on page 3, “CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2V” Add “Green package available” on page 1 1. Revised TEST CONDITION of VOH, VOL on page 4 IOH = -8mA revised as -4mA IOL =4mA revised as 8mA 2. Revised VIH(max) & VIL(min) Notes on page 4 VIH(max) = VCC + 2.0V for pulse width less than 6ns. VIL(min) = VSS - 2.0V for pulse width less than 6ns. Revised the address pin sequence of TSOP-II pin configuration on page 2 to be compatible with industrial convention. (No function specifications and applications changed and all characteristics kept same as Rev 1.3 ) Deleted Commercial Grade Added PKG type : 36-ball 6mm x 8mm TFBGA Deleted WRITE CYCLE Notes : 1.WE#,CE# must be high during all address transitions. In page 6. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Issue Date Jul.12.2012 Jul.19.2012 Nov.02.2012 Jun.04.2013 Oct.30.2013 Jun.22.2016 LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 FEATURES GENERAL DESCRIPTION Fast access time : 8/10/12ns Low power consumption: Operating current: 50/40/35mA(TYP.) Standby current: 2mA(TYP.) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Green package available Data retention voltage : 1.5V (MIN.) Package : 44-pin 400 mil TSOP-II 36-ball 6mm x 8mm TFBGA The LY61L5128A is a 4,194,304-bit high speed CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L5128A operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family Operating Temperature VCC Range Speed -40 ~ 85℃ 2.7 ~ 3.6V 3.0 ~ 3.6V 10/12ns 8ns LY61L5128A(I) FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL A0 - A18 DQ0 – D7 CE# WE# OE# VCC VSS NC Vcc Vss A0-A18 DECODER 512Kx8 MEMORY ARRAY DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# WE# OE# CONTROL CIRCUIT Power Dissipation Standby(ISB1,TYP.) Operating(ICC1,TYP.) 2mA 40/35mA 2mA 50mA DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 LY61L5128A Rev. 1.5 512K X 8 BIT HIGH SPEED CMOS SRAM PIN CONFIGURATION Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 I/O OPERATION High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage VCC Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH*1 VIL*2 ILI ILO VOH VOL ICC Average Operating Power Supply Current ICC1 Standby Power Supply Current ISB ISB1 TEST CONDITION -8 -10/-12 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -4mA IOL = 8mA -8 Cycle time = Min. CE# = VIL, II/O = 0mA, -10 Others at VIL or VIH -12 -8 CE# ≦0.2, Others at 0.2V or Vcc-0.2V -10 II/O = 0mA;f=max -12 CE# =VIH, Others at VIL or VIH CE# ≧VCC - 0.2V, Others at 0.2V or VCC - 0.2V MIN. 3.0 2.7 2.2 - 0.3 -1 MAX. TYP. *4 3.3 3.6 3.3 3.6 VCC+0.3 0.8 1 -1 - 1 µA 2.4 - 65 50 45 50 40 35 - 0.4 80 70 60 60 55 50 30 V V mA mA mA mA mA mA mA - 2 10 mA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 UNIT V V V V µA LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 8 10 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 8/10/12ns 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY61L5128A-8 MIN. MAX. 8 8 8 4.5 2 0 3 3 2 - LY61L5128A-10 LY61L5128A-12 MIN. MAX. MIN. MAX. 10 12 10 12 10 12 4.5 5 2 3 0 0 4 5 4 5 2 2 - LY61L5128A-8 MIN. MAX. 8 6.5 6.5 0 6.5 0 5 0 2 3 LY61L5128A-10 LY61L5128A-12 MIN. MAX. MIN. MAX. 10 12 8 10 8 10 0 0 8 10 0 0 6 7 0 0 2 2 4 5 UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 UNIT ns ns ns ns ns ns ns ns ns ns LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 High-Z LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, low WE#. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V CE# ≧ VCC - 0.2V IDR Others at 0.2V or Vcc – 0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 2 10 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 3o 6o 0o DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 0o 3o 6o Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 LY61L5128A Rev. 1.5 512K X 8 BIT HIGH SPEED CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 LY61L5128A 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 ORDERING INFORMATION Package Type Access Time (Speed/ns) 44Pin 400mil TSOP-II 8 10 36Ball 6mm x 8mm TFBGA 8 10 Temperature Range(℃) -40℃~85℃ -40℃~85℃ -40℃~85℃ -40℃~85℃ Packing Type Tray LY61L5128AML-8I Tape Reel LY61L5128AML-8IT Tray LY61L5128AML-10I Tape Reel LY61L5128AML-10IT Tray LY61L5128AGL-8I Tape Reel LY61L5128AGL-8IT Tray LY61L5128AGL-10I Tape Reel LY61L5128AGL-10IT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 Lyontek Item No. LY61L5128A Rev. 1.5 512K X 8 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11