CGD15HB62LP VDrive IG RG Dual Channel Differential Isolated Gate Driver Cree CAS325M12HM2 C2M SiC Half Bridge Module Optimized Features • • • • • • • • +18/-5 V ±14 A 5Ω Package Optimized for Cree’s High Performance CAS325M12HM2 Half Bridge Power Modules High-Frequency, Ultra-Fast Switching Operation On Board 3 W or 6 W Isolated Power Supplies Configurable UVLO with Hysteresis Direct Mount Low Inductance Design On-Board Overcurrent, Overlap, and Reverse Polarity Protection Differential Inputs for Increased Noise Immunity Differential to Single-Ended Daughter Board Available Upon Request For Use with Cree Module • CAS325M12HM2, 1200 V, 325 A Module Half Bridge CPM2 Variants for Module Junction Temperatures up to 175 °C Part Number Package Marking CGD15HB62LP PCBA CGD15HB62LP V3 Applications • DC Bus Voltages up to 1000 V Maximum Ratings Symbol VDC 1 Parameter Value Supply Voltage -0.5 to 18 VI Logic Level Inputs -0.5 to 5.5 IO Output Peak Current ±14 IO(avg) Output Average Current ±4 Fmax Maximum Switching Frequency 115 Top Ambient Operating Temperature -50 to 95 Tstg Storage Temperature -50 to 125 CGD15HB62LP Rev. A, 07-2016 Unit Test Conditions V A kHz °C TA = 25 °C 3 W Power Supply + CAS325M12HM2 Gate Driver Electrical Characterization Symbol VDC VUVLO Parameter Min. Typ. Max. 9 12 18 Secondary UVLO Inactive Level +13.5 +14 +14.5 Secondary UVLO Active Level +11.2 +12 +12.7 Supply Voltage Secondary UVLO Hysteresis High Level Logic Input Voltage 3.5 5.5 VIL Low Level Logic Input Voltage 0 1.5 VIDTH Differential Input Common Mode Range Differential Input Threshold Voltage VODH Differential Output High Level VODL Differential Output Low Level VOD Differential Output Magnitude -7 - +12 -200 -125 -50 2.2 3.4 0.2 2 High Level Output Voltage +18 VGATE,LOW Low Level Output Voltage -5 VIOWM Working Isolation Voltage 1500 CISO Isolation Capacitance IOD = 20 mA pF RGIC-ON Output Resistance 1 0.4 1.5 RGIC-OFF Output Resistance1 0.3 1.2 RGEXT-ON External Output Resistance 2 4.99 RGEXT-OFF External Output Resistance2 4.99 100 0.67 Ω External SMD Resistor 0.82 V 250 tOFF Output Fall Time 140 Propagation Delay 75 tPD Over-current Propagation Delay to FAULT Signal Low 40 RSS Soft-Shutdown Resistance 3 30.1 Ω Output Fall Time Soft-Shutdown 1.5 µs Output resistance of totem pole IC Per Channel Gate Drive IC Output Rise Time tOFF-SS RL=100 Ω kV/µs tON tPHL/PLH VID = VPos-Line – VNeg-Line VRMS 17 0.62 mV V Common Mode Transient Immunity Turn-off Diode Forward Voltage Differential Inputs 0.4 CMTI DVF-OFF Single-Ended Inputs IOD = -20 mA 3.1 VGATE,HIGH Test Conditions V VIH VIDCM 1 2 Unit CLoad = 19 nF From 10% to 90% ns Does Not Include Blanking Output pulled low through RSS Additional output resistance is added with SMD resistors. A diode is provided to allow control of turn-off separately. The diode makes the effective turn-off resistance be the parallel combination of the RGEXT-ON and RGEXT-OFF while the turn-on effective resistance is RGEXT-ON. Standard value is 4.99 Ω for both turn-on and turn-off. See Figure 1 for configuration. 3 Soft-Shutdown Resistor will safely turn off the Gate in the event an over-current is detected by the Desaturation Protection circuit. 2 2 CGD15HB62LP Rev. A, 07-2016 Input Connector Information Pin Number Name 1 VDC 2 Common 3 HS-P (*) 4 HS-N (*) 5 LS-P (*) 6 LS-N (*) 7 FAULT - P (*) 8 FAULT - N (*) 9 RTD-P (*) 10 RTD-N (*) 11 PS-Dis 12 Common Common 13 PWM-EN Pull Down to Disable PWM Input Logic. Pull Up/Leave floating to enable. Gatesource will be held low through gate resistor if power supplies are enabled. 14 Common Common 15 OC-EN 16 Common Description Power Supply Input Pin Common Positive Line of 5 V Differential High Side PWM Signal Pair. Terminated Into 250 Ω. Negative Line of 5 V Differential High Side PWM Signal Pair. Terminated Into 250 Ω. Positive Line of 5 V Differential Low Side PWM Signal Pair. Terminated Into 250 Ω. Negative Line of 5 V Differential Low Side PWM Signal Pair. Terminated Into 250 Ω. Positive Line of 5 V Differential Fault Condition Signal Pair. Drive Strength 20 mA. Negative Line of 5 V Differential Fault Condition Signal Pair. Drive Strength 20 mA. Positive Line of 5 V Temperature Dependent Resistor Output Signal Pair. Drive Strength 20 mA. Temperature Measurement is Encoded Via PWM. Negative Line of 5 V Temperature Dependent Resistor Output Signal Pair. Drive Strength 20mA. Temperature Measurement is Encoded Via PWM. Pull Down to Disable Power Supply. Pull Up, or Leave Floating to Enable. GateSource will be Connected with 10 kΩ when disabled. Over-current Protection Enable. Pull down to disable detection of over-current fault. PWM and UVLO will continue to function. Pull up or leave floating to enable detection of over-current fault. Common (*) Inputs 3 – 10 are differential pairs. 3 CGD15HB62LP Rev. A, 07-2016 Block Diagram 12 V 18 V DC DC PS-Disable -5V MGJ3T12150505 VDS Measure PWM Enable DC + Over-current Enable IXDD614YI HS – PWM ISO7842 HS - Fault Fault LS - Fault 18 V DC DC PS-Disable -5V MGJ3T12150505 PWM Enable VDS Measure LS - RTD Over-current Enable IXDD614YI LS – PWM ISO7842 Fig 1. Block Diagram 4 CGD15HB62LP Rev. A, 07-2016 Midpoint Driver Interface JT 1 Pin 1 JB1 CGD15HB62LP JT 3 JB 2 JT 2 Fig 2. Top View 5 Connector Name JT2 Signal Input JT1 HS-Drain JT3 LS-Drain JB1 HS-GS JB2 LS-GS Description Description in Input Connection Information High Side Over-current protection connector Connect to DC + Low Side Over-current protection connector Connect to the Midpoint or populate RT19 with a 0 Ω resistor Red – Gate Green – Source Red – Gate Green – Source Blue – RTD CGD15HB62LP Rev. A, 07-2016 Signal Description • PWM Signals: High side and low side PWM must be differential signals 4. The termination impedance of the differential receiver is 250 Ω. A reference single-ended to differential converter is available as an optimized companion product. Overlap protection is provided to prevent both the high side and low side gates from turning on simultaneously. The overlap protection should not be used as a dead time generator. • FAULT Signal: The fault signal is a differential output4 with a maximum drive strength of 20mA. A high signal (positive line > negative line) means there are no fault conditions for either gate driver channel. This signal will be low if a UVLO or over-current fault is detected on either channel. See below for further description for what the individual faults indicate. • UVLO Fault: The UVLO circuit detects when the output rails of the isolated DC/DC converter falls below safe operating conditions for the gate driver. A UVLO fault indicates that the potential between the split output rails has fallen below the UVLO active level. The gate for the channel where the fault occurred will be pulled low through RG for the duration of the fault regardless of the PWM input signal. The fault will automatically clear once the potential has risen above the UVLO inactive level. There is hysteresis for this fault to ensure safe operating conditions, and the inactive and active regions can be configured through on-board resistors. The UVLO faults for both channels are combined along with the over-current fault in the FAULT output signal. • Over-Current Fault: An over-current fault is an indication of an over-current event in the SiC power module. The over-current protection circuit measures the drain-source voltage, and the fault will indicate if this voltage has risen above a level corresponding to the safe current limit. A drain sense connection is provided by quick-connect spade connectors for both high side and low side. The low side drain connection can optionally be connected on-board to the high side source through jumper RT19. When a fault has occurred the corresponding gate driver channel will be disabled, and the gate will be pulled down through a soft-shutdown resistor, RSS3. The drain-source limit can be configured through on-board resistors. The over-current protection is enabled by default, but it can be disabled by pulling the OC-EN pin low. The gate driver will operate correctly with this protection disabled. The over-current fault is latched upon detection and must be cleared by the user with a low pulse of at least 2.5 ns on the OC-EN signal. • RTD Signal: RTD output is a differential signal4 that measures the resistance of the RTD integrated into XAS325M12HM2 modules. The signal is a 50 kHz PWM that encodes the resistance of the RTD. The minimum and maximum duty cycles are 5% and 95% respectively to guarantee a signal is always present. The approximate temperature of the module can be determined from this resistance 5. The module temperature can be calculated using the formula, 𝑇𝑇𝑅𝑅𝑅𝑅𝑅𝑅 = 5.42 ∗ (𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷) − 244 °𝐶𝐶 . • PS-Dis Signal: PS-DIS signal disables the output of the isolated DC/DC converters for the two channels. It is a single-ended input that must be pulled low to turn off the power supplies. This can be used for startup sequencing. 4 5 A single-ended to differential converter for both input and output is available as an optimized companion product. See CAS325M12HM2 with Optional RTD Application Note for further description of the RTD measurements. 6 CGD15HB62LP Rev. A, 07-2016 • PWM-EN Signal: This is a single-ended input that enables the PWM inputs for both channels. When this signal is pulled down the differential receivers for both channels are disabled and the gates will both be pulled low through RG. All protection circuitry and power supplies will continue to operate including FAULT and RTD outputs. • Over-Voltage and Reverse Polarity Protection: Power input on pin 1 of connector JT2 features a Zener diode to protect the gate driver from damage by connecting a power source that exceeds the voltage rating of the gate driver. If over-voltage protection has occurred power should be removed to allow the PTC fuse to reset. There is also a diode in-line with the power input to protect against connecting a power source with positive and negative polarity reversed. Input Connector • SBH11-PBPC-D08-ST-BK • Drain connector for Overcurrent Protection: TE Connectivity 735187-2 Suggested Mating Parts • SFH210-PPPC-D08-ID-BK • SFH11-PBPC-D08-ST-BK • SFH11-PBPC-D08-RA-BK • Drain connector for Overcurrent: TE Connectivity 2-520272-2 Power Estimates The gate driver power required is calculated using the formula below. The gate charge is dependent on the datasheets of the module being driven. The gate driver voltage (VGD) is 23V for this gate driver. Once the required gate driver power is calculated the required input power can be calculated from the MGJ3T12150505MC and MGJ6T12150505MC efficiency curves on the power supplies datasheet. This calculation is for one channel of the gate driver. 𝑃𝑃𝑠𝑠𝑠𝑠 : 𝑄𝑄𝐺𝐺 : 𝐹𝐹𝑆𝑆𝑆𝑆 : Δ𝑉𝑉𝐺𝐺𝐺𝐺 : 7 𝑃𝑃𝑠𝑠𝑠𝑠 = 𝑄𝑄𝐺𝐺 ∗ 𝐹𝐹𝑆𝑆𝑆𝑆 ∗ Δ𝑉𝑉𝐺𝐺𝐺𝐺 gate driver power total gate charge switching frequency total gate drive voltage (VGATE,HIGH - VGATE,LOW) CGD15HB62LP Rev. A, 07-2016 Dimensions [in(mm)] CGD15HB62LP Important Notes Fig 3. Dimensions Suitability of this product for any application may depend on product parameters not specified in this document. Accordingly, buyers are cautioned to evaluate actual products against their needs and not to rely solely on the data and information presented in this document. The product described has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body or in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, vehicle navigation, communication or control systems, or air traffic control systems. The product described is not eligible for Distributor Stock Rotation or Inventory Price Protection. Copyright © 2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo, and Zero recovery are registered trademarks of Cree, Inc. 8 CGD15HB62LP Rev. A, 07-2016 Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5451 www.cree.com/power