Fairchild NC7WZ16FHX Tinylogicâ® uhs dual buffer Datasheet

NC7WZ16
TinyLogic® UHS Dual Buffer
Features
Description
ƒ
Ultra-High Speed: tPD 2.4ns (Typical) into 50pF at
5V VCC
ƒ
ƒ
ƒ
High Output Drive: ±24mA at 3V VCC
ƒ
ƒ
Power Down High-Impedance Inputs/Outputs
The NC7WZ16 is a dual buffer from Fairchild’s Ultra®
High Speed Series of TinyLogic . The device is
fabricated with advanced CMOS technology to achieve
ultra-high speed with high output drive while maintaining
low static power dissipation over a very broad VCC
operating range. The device is specified to operate over
the 1.65V to 5.5V VCC range. The inputs and outputs are
high impedance when VCC is 0V. Inputs tolerate
voltages up to 7V independent of VCC operating voltage.
ƒ
ƒ
ƒ
Proprietary Noise/EMI Reduction Circuitry
Broad VCC Operating Range: 1.65V to 5.5V
Matches Performance of LCX when Operated at
3.3V VCC
Over-Voltage Tolerance Inputs Facilitate 5V to 3V
Translation
Ultra-Small MicroPak™ Packages
Space-Saving SC70 Package
Ordering Information
Part Number
Top Mark
Package
Packing Method
NC7WZ16P6X
Z16
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
3000 Units on Tape & Reel
NC7WZ16L6X
C7
6-Lead MicroPak™, 1.00mm Wide
5000 Units on Tape & Reel
NC7WZ16FHX
C7
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
5000 Units on Tape & Reel
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
www.fairchildsemi.com
NC7WZ16 — TinyLogic® UHS Dual Buffer
December 2010
NC7WZ16 — TinyLogic® UHS Dual Buffer
Connection Diagrams
IEEC/IEC
Figure 1. Logic Symbol
Pin Configurations
Figure 2. SC70 (Top View)
Figure 3. MicroPak™ (Top Through View)
Notes:
1. AAA represents Product Code Top Mark (see ordering code).
2. Orientation of Top Mark determines Pin One location. Read the top product code mark left to right.
Pin One is the lower left pin.
Figure 4. Pin 1 Orientation
Pin Definitions
Pin # SC70
Pin # MicroPak™
Name
Description
1
1
A1
2
2
GND
3
3
A2
Input
4
4
Y2
Output
5
5
VCC
6
6
Y1
Input
Ground
Supply Voltage
Output
Function Table
Y= A
Inputs
Output
A
Y
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
VOUT
IIK
Parameter
Min.
Max.
Unit
Supply Voltage
-0.5
7.0
V
DC Input Voltage
-0.5
7.0
V
DC Output Voltage
-0.5
7.0
V
-50
mA
DC Input Diode Current
VIN < 0V
IOK
DC Output Diode Current
VOUT < 0V
-50
mA
IOUT
DC Output Source / Sink Current
±50
mA
DC VCC or Ground Current
±100
mA
+150
°C
ICC or IGND
TSTG
Storage Temperature Range
-65
TJ
Junction Temperature Under Bias
+150
°C
TL
Junction Lead Temperature (Soldering, 10 Seconds)
+260
°C
SC70-6
PD
ESD
Power Dissipation
NC7WZ16 — TinyLogic® UHS Dual Buffer
Absolute Maximum Ratings
180
MicroPak™-6
130
MicroPak2™-6
120
Human Body Model, JEDEC:JESD22-A114
4000
Charge Device Model, JEDEC:JESD22-C101
2000
mW
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
VIN
VOUT
tr,tf
TA
Parameter
Conditions
Min.
Max.
Supply Voltage Operating
1.65
5.50
Supply Voltage Data Retention
1.50
5.50
V
Input Voltage
0
5.5
V
Output Voltage
0
VCC
V
VCC=1.8V, 2.5V ±0.2V
0
20
VCC=3.3V ±0.3V
0
10
VCC=5.5V ±0.5V
0
5
-40
+125
Input Rise and Fall Times
Operating Temperature
SC70-6
θJA
Unit
Thermal Resistance
ns/V
°C
425
MicroPak™-6
500
MicroPak2™-6
560
°C/W
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
www.fairchildsemi.com
3
Symbol
Parameter
VCC (V)
TA=25°C
Conditions
Min.
Typ.
TA=-40 to +85°C
Max.
Min.
VIH
HIGH Level Control
Input Voltage
1.65 to 1.95
0.75VCC
0.75VCC
2.3 to 5.5
0.70VCC
0.70 VCC
VIL
LOW Level Control
Input Voltage
1.65 to 1.95
0.25VCC
0.25VCC
2.3 to 5.5
0.30VCC
0.30VCC
1.65
1.55
1.65
1.55
1.80
1.70
1.80
1.70
2.20
2.30
2.20
2.90
3.00
2.90
IOH=-100µA
2.30
3.00
VOH
HIGH Level Output
Voltage
4.50
4.40
4.50
4.40
IOH=-4mA
1.29
1.52
1.21
2.30
IOH=-8mA
1.90
2.14
1.90
3.00
IOH=-16mA
2.40
2.75
2.40
3.00
IOH=-24mA
2.30
2.62
2.30
4.50
IOH=-32mA
3.80
4.13
1.65
VIN=VIH
1.65
IIN
Input Leakage
Current
IOFF
Power Off Leakage
Current
ICC
Quiescent Supply
Current
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
V
V
3.80
0.10
0.10
0.00
0.10
0.10
0.00
0.10
0.10
3.00
0.00
0.10
0.10
4.50
0.00
0.10
0.10
IOL=4mA
0.08
0.24
0.24
2.30
IOL=8mA
0.10
0.30
0.30
3.00
IOL=16mA
0.16
0.40
0.40
3.00
IOL=24mA
0.24
0.55
0.55
4.50
IOL=32mA
0.25
0.55
0.55
0 ≥ VIN ≥ 5.5V
±0.1
±1.0
µA
VIN or VOUT=5.5V
1.0
10
µA
VIN=5.5V, GND
1.0
10
µA
IOL=100µA
2.30
LOW Level Output
Voltage
V
0.00
1.80
VOL
Units
Max.
1.65
0 to 5.5
0
1.65 to 5.50
VIN=VIL
NC7WZ16 — TinyLogic® UHS Dual Buffer
DC Electrical Characteristics
V
www.fairchildsemi.com
4
Symbol
Parameter
VCC (V)
Min.
1.65
Typ. Max.
Min.
Max.
5.5
9.6
1.8
10.6
1.8
4.6
8.0
1.8
8.8
1.0
3.0
5.2
1.0
5.8
3.30 ± 0.30
0.8
2.3
3.6
0.8
4.0
5.00 ± 0.50
0.5
1.8
2.9
0.5
3.2
1.2
3.0
4.6
1.2
5.1
0.8
2.4
3.8
0.8
4.2
1.80
Propagation Delay
TA=-40 to +85°C
1.8
2.50 ± 0.20
tPLH, tPHL
TA=25°C
Conditions
3.30 ± 0.30
5.00 ± 0.50
CL=15pF,
RL=1MΩ
CL=50pF,
RL=500Ω
CIN
Input Capacitance
0.00
2.5
CPD
Power Dissipation
Capacitance(4)
3.30
10
5.00
12
Units
Figure
Figure 5
Figure 6
ns
Figure 5
Figure 6
pF
pF
Figure 7
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic
operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).
NC7WZ16 — TinyLogic® UHS Dual Buffer
AC Electrical Characteristics
Note:
5. CL includes load and stray capacitance;
Input PRR=1.0MHz; tW =500ns
Figure 5. AC Test Circuit
Figure 6. AC Waveforms
Note:
6. Input=AC Waveform; tr=tf=1.8ns; PRR=10 MHz Duty Cycle=50%.
Figure 7. ICCD Test Circuit
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
www.fairchildsemi.com
5
NC7WZ16 — TinyLogic® UHS Dual Buffer
Physical Dimensions
SYMM
CL
2.00±0.20
0.65
A
0.50 MIN
6
4
B
PIN ONE
1.25±0.10
1
1.90
3
0.30
0.15
(0.25)
0.40 MIN
0.10
0.65
A B
1.30
LAND PATTERN RECOMMENDATION
1.30
1.00
0.80
SEE DETAIL A
1.10
0.80
0.10 C
0.10
0.00
C
2.10±0.30
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE
PLANE
(R0.10)
0.25
0.10
0.20
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH.
D) DRAWING FILENAME: MKT-MAA06AREV6
30°
0°
0.46
0.26
DETAIL A
SCALE: 60X
Figure 8.
6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf.
Package Designator
P6X
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
6
NC7WZ16 — TinyLogic® UHS Dual Buffer
Physical Dimensions
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.25
0.15 6X
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
(0.13)
4X
BOTTOM VIEW
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 9.
6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
L6X
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
7
NC7WZ16 — TinyLogic® UHS Dual Buffer
Physical Dimensions
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
6
5
4
0.35
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 10.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
8
NC7WZ16 — TinyLogic® UHS Dual Buffer
© 1999 Fairchild Semiconductor Corporation
NC7WZ16 • Rev. 1.0.4
www.fairchildsemi.com
9
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