TI1 OPT3001IDNPRQ1 Ambient light sensor (als) Datasheet

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OPT3001-Q1
SBOS853 – MARCH 2017
OPT3001-Q1 Ambient Light Sensor (ALS)
1 Features
3 Description
•
The OPT3001-Q1 device is an optical sensor that
measures the intensity of visible light. The spectral
response of the sensor tightly matches the photopic
response of the human eye and includes significant
infrared rejection.
1
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Devices
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4A
Precision Optical Filtering to Match Human Eye:
– Rejects > 99% (Typical) of IR
Automatic Full-Scale Setting Feature Simplifies
Software and Ensures Proper Configuration
Measurements: 0.01 Lux to 83k Lux
23-Bit Effective Dynamic Range With
Automatic Gain Ranging
12 Binary-Weighted Full-Scale Range Settings:
< 0.2% (Typical) Matching Between Ranges
Low Operating Current: 1.8 µA (Typical)
Operating Temperature Range: –40°C to 85°C
Functional Temperature Range: –40°C to 105°C
Wide Power-Supply Range: 1.6 V to 3.6 V
5.5-V Tolerant I/O
Flexible Interrupt System
Small-Form Factor: 2 mm × 2 mm × 0.65 mm
Measurements can be made from 0.01 lux up to 83k
lux, without manually selecting full-scale ranges, by
using the built-in, full-scale setting feature. This
capability allows light measurement over a 23-bit
effective dynamic range.
The digital operation is flexible for system integration.
Measurements can be either continuous or singleshot. The control and interrupt system features
autonomous operation, allowing the processor to
sleep while the sensor searches for appropriate
wake-up events to report through the interrupt pin.
The digital output is reported over an I2C- and
SMBus-compatible, two-wire serial interface.
2 Applications
•
•
•
•
•
•
•
•
•
The OPT3001-Q1 device is a single-chip lux meter,
measuring the intensity of light as visible by the
human eye. The precision spectral response and
strong IR rejection of the device enables the
OPT3001-Q1 device to accurately meter the intensity
of light as seen by the human eye, regardless of light
source. The strong IR rejection also aids in
maintaining high accuracy when industrial design
calls for mounting the sensor under dark glass for
aesthetics. The OPT3001-Q1 device is designed for
systems that create light-based experiences for
humans, and an ideal preferred replacement for
photodiodes, photoresistors, or other ambient light
sensors with less human eye matching and IR
rejection.
Automotive Lighting
Infotainment and Cluster
Display Backlight Controls
Lighting Control Systems
Personal Electronics
Electronic Point-of-Sale
Outdoor Traffic and Street Lights
Home Lighting
Cameras
The low-power consumption and low-power supply
voltage capability of the OPT3001-Q1 device
enhance the battery life of battery-powered systems.
Device Information(1)
PART NUMBER
Spectral Response: OPT3001-Q1 and the Human
Eye
1
OPT3001
Human Eye
0.9
OPT3001-Q1
USON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
0.8
Normalized Response
PACKAGE
Block Diagram
0.7
VDD
0.6
0.5
VDD
0.4
OPT3001
0.3
Ambient
Light
0.2
Optical
Filter
ADC
I2C
Interface
SCL
SDA
INT
ADDR
0.1
0
300
GND
400
500
600
700
Wavelength (nm)
800
900
1000
D001
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPT3001-Q1
SBOS853 – MARCH 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.6 Register Maps ......................................................... 19
8
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 28
8.3 Do's and Don'ts ...................................................... 31
9 Power-Supply Recommendations...................... 32
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram ......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Application and Implementation ........................ 27
10
10
11
13
16
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
12.1 Soldering and Handling Recommendations.......... 33
12.2 DNP (S-PDSO-N6) Mechanical Drawings ............ 34
4 Revision History
2
DATE
REVISION
NOTES
March 2017
*
Initial release.
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5 Pin Configuration and Functions
DNP Package
6-Pin USON
Top View
VDD
1
ADDR
2
GND
3
Thermal
Pad
6
SDA
5
INT
4
SCL
Not to scale
Pin Functions
PIN
NO.
DESCRIPTION
NAME
I/O
1
VDD
I
Device power. Connect to a 1.6-V to 3.6-V supply.
2
ADDR
I
Address pin. This pin sets the LSBs of the I2C address.
3
GND
Power
4
SCL
I
I2C clock. Connect with a 10-kΩ resistor to a 1.6-V to 5.5-V supply.
Ground
5
INT
O
Interrupt output, open-drain. Connect with a 10-kΩ resistor to a 1.6-V to 5.5-V supply.
6
SDA
I/O
I2C data. Connect with a 10-kΩ resistor to a 1.6-V to 5.5-V supply.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Voltage
MIN
MAX
UNIT
VDD to GND
–0.5
6
V
SDA, SCL, INT, and ADDR to GND
–0.5
6
V
10
mA
150
°C
150 (2)
°C
Current into any pin
Junction
Temperature
(1)
(2)
Storage, Tstg
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long exposure to temperatures higher than 105°C can cause package discoloration, spectral distortion, and measurement inaccuracy.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Operating temperature
–40
85
°C
Operating power-supply voltage
1.6
3.6
V
6.4 Thermal Information
OPT3001-Q1
THERMAL METRIC (1)
DNP (USON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
71.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.7
°C/W
RθJB
Junction-to-board thermal resistance
42.2
°C/W
ψJT
Junction-to-top characterization parameter
2.4
°C/W
ψJB
Junction-to-board characterization parameter
42.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
17.0
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics
At TA = 25°C, VDD = 3.3 V, (1), automatic full-scale range (RN[3:0] = 1100b (1)), white LED, and normal-angle incidence of light,
unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPTICAL
Peak irradiance spectral responsivity
Resolution (LSB)
550
Lowest full-scale range, RN[3:0] = 0000b at
800 ms conversion time (1)
0.01
Lowest full-scale range, RN[3:0] = 0000b(1) at
100 ms conversion time
0.08
lux
Full-scale illuminance
83 865.6
0.64 lux per ADC code, 2620.80 lux full-scale
(RN[3:0] = 0110) (1), 2000 lux input (2)
Measurement output result
3125
3437
ADC codes
1800
2000
2200
lux
Linearity
Measurement drift across temperature
Dark condition, ADC output
PSRR
0.2%
(2)
Light source variation
(incandescent, halogen, fluorescent)
lux
2812
Relative accuracy between gain
ranges (3)
Infrared response (850 nm)
nm
0.2%
Bare device, no cover glass
4%
Input illuminance > 40 lux
2%
Input illuminance < 40 lux
5%
Input illuminance = 2000 lux
0.01
%/°C
For Conversion Time = 800 ms
0
3
For Conversion Time = 100 ms
0
1
ADC codes
Half-power angle
50% of full-power reading
47
degrees
Power-supply rejection ratio
VDD at 3.6 V and 1.6 V
0.1
%/V (4)
POWER SUPPLY
VDD
Operating range
VI²C
Operating range of I2C pull-up resistor
I2C pull-up resistor, VDD ≤ VI²C
Dark
IQ
Quiescent current
Full-scale lux
POR
Power-on-reset threshold
1.6
3.6
1.6
5.5
V
V
Active, VDD = 3.6 V
1.8
2.5
µA
Shutdown (M[1:0] = 00) (1),
VDD = 3.6 V
0.3
0.47
µA
Active, VDD = 3.6 V
3.7
µA
Shutdown,
(M[1:0] = 00) (1)
0.4
µA
0.8
V
TA = 25°C
DIGITAL
I/O pin capacitance
Total integration time (5)
3
pF
(CT = 1) (1), 800-ms mode, fixed lux range
720
800
880
ms
(CT = 0) (1), 100-ms mode, fixed lux range
90
100
110
ms
VIL
Low-level input voltage
(SDA, SCL, and ADDR)
0
0.3 × VDD
V
VIH
High-level input voltage
(SDA, SCL, and ADDR)
0.7 × VDD
5.5
V
IIL
Low-level input current
(SDA, SCL, and ADDR)
0.25 (6)
µA
VOL
Low-level output voltage
(SDA and INT)
IOL= 3 mA
0.32
V
IZH
Output logic high, high-Z leakage
current (SDA, INT)
Pin at VDD
0.25 (6)
µA
85
°C
0.01
0.01
TEMPERATURE
Specified temperature range
(1)
(2)
(3)
(4)
(5)
(6)
–40
Refers to a control field within the configuration register.
Tested with the white LED calibrated to 2k lux and an 850-nm LED.
Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.
PSRR is the percent change of the measured lux output from its current value, divided by the change in power supply voltage, as
characterized by results from 3.6-V and 1.6-V power supplies.
The conversion time, from start of conversion until the data are ready to be read, is the integration time plus 3 ms.
The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller.
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6.6 Timing Requirements (1)
MIN
TYP
MAX
UNIT
0.4
MHz
I2C FAST MODE
fSCL
SCL operating frequency
0.01
tBUF
Bus free time between stop and start
1300
ns
tHDSTA
Hold time after repeated start
600
ns
tSUSTA
Setup time for repeated start
600
ns
tSUSTO
Setup time for stop
600
ns
tHDDAT
Data hold time
20
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
tRC and tFC
Clock rise and fall time
300
ns
tRD and tFD
Data rise and fall time
300
ns
tTIMEO
Bus timeout period. If the SCL line is held low for this duration of time, the bus
state machine is reset.
900
ns
ns
28
ms
2
I C HIGH-SPEED MODE
fSCL
SCL operating frequency
0.01
tBUF
Bus free time between stop and start
160
ns
tHDSTA
Hold time after repeated start
160
ns
tSUSTA
Setup time for repeated start
160
ns
tSUSTO
Setup time for stop
160
tHDDAT
Data hold time
20
tSUDAT
Data setup time
20
ns
tLOW
SCL clock low period
240
ns
tHIGH
SCL clock high period
60
tRC and tFC
Clock rise and fall time
40
ns
tRD and tFD
Data rise and fall time
80
ns
tTIMEO
Bus timeout period. If the SCL line is held low for this duration of time, the bus
state machine is reset.
(1)
2.6
MHz
ns
140
ns
ns
28
ms
All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.
1/fSCL
tRC
tFC
70%
30%
SCL
tLOW
tHDDAT tHIGH
tSUDAT
tSUSTA
tHDSTA
tSUSTO
70%
30%
SDA
tBUF
Stop
Start
tRD
tFD
Start
Stop
Figure 1. I2C Detailed Timing Diagram
6
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6.7 Typical Characteristics
At TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and
normal-angle incidence of light, unless otherwise specified.
500
1
OPT3001
Human Eye
0.9
400
Output Response (Lux)
0.8
Normalized Response
Fluorescent
Halogen
Incandescent
450
0.7
0.6
0.5
0.4
0.3
350
300
250
200
150
0.2
100
0.1
50
0
300
0
400
500
600
700
Wavelength (nm)
800
900
0
1000
50
100
D001
Figure 2. Spectral Response vs Wavelength
150 200 250 300 350
Input Illuminance (Lux)
400
450
500
D002
Figure 3. Output Response vs Input Illuminance, Multiple
Light Sources (Fluorescent, Halogen, Incandescent)
100
80000
800ms
100ms
800ms
100ms
70000
Output Response (Lux)
Output Response (Lux)
80
60000
50000
40000
30000
20000
60
40
20
10000
0
0
0
0
10000 20000 30000 40000 50000 60000 70000 80000
Input Illuminance (Lux)
D003
Figure 4. Output Response vs Input Illuminance
(Entire Range = 0 lux to 83k lux)
20
40
60
Input Illuminance (Lux)
80
100
D004
Figure 5. Output Response vs Input Illuminance
(Mid Range = 0 lux to 100 lux)
5
1.020
800ms
100ms
1.010
Relative Response
Output Response (Lux)
4
3
2
1.000
1.000
1.001
1.002
1.001
0.997
0.997
327.6
655.2
1.002
0.990
1
0
0
1
2
3
Input Illuminance (Lux)
4
5
0.980
40.95
D005
81.9
163.8
1310.4 2620.8
Full-Scale Range (Lux)
D006
Input illuminance = 33 lux,
normalized to response of 40.95 lux full-scale
Figure 6. Output Response vs Input Illuminance
(Low Range = 0 lux to 5 lux)
Figure 7. Full-Scale-Range Matching (Lowest 7 Ranges)
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Typical Characteristics (continued)
At TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and
normal-angle incidence of light, unless otherwise specified.
0.1
1.020
Dark Output Response (Lux)
0.09
Relative Response
1.010
1.000
1.000
1.002
1.003
1.004
1.002
1.000
0.990
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
-40
0.980
2620.8
5241.6
10483.2 20966.4 41932.8 83865.6
Full-Scale Range (Lux)
-20
0
D007
20
40
Temperature (qC)
60
80
100
D0016
Average of 30 devices
Input illuminance = 2490 lux,
normalized to response of 2560 lux full-scale
Figure 9. Dark Response vs Temperature
Figure 8. Full-Scale-Range Matching (Highest 6 Ranges)
1.02
1000
Conversion Time (ms)
Normalized Response
1.01
1
0.99
900
800
700
0.98
0.97
-40
-20
0
20
40
60
Temperature ( qC)
80
100
600
1.6
120
2
D008
Figure 10. Normalized Response vs Temperature
2.4
2.8
Power Supply (V)
3.2
3.6
D017
Figure 11. Conversion Time vs Power Supply
1
1.002
0.9
Normalized Response
Normalized Response
0.8
1.001
1
0.999
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.998
1.6
2
2.4
2.8
Power Supply (V)
3.2
3.6
-70
D009
Figure 12. Normalized Response vs Power-Supply Voltage
8
0
-90
-50
-30
-10
10
30
50
Illuminance Angle (Degrees)
70
90
D010
Figure 13. Normalized Response vs Illuminance Angle
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Typical Characteristics (continued)
4
0.5
3.5
0.45
Supply Current (PA)
Supply Current (PA)
At TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and
normal-angle incidence of light, unless otherwise specified.
3
2.5
2
0.4
0.35
0.3
0.25
1.5
0.2
1
100
1000
10000
Input Illuminance (Lux)
0
100000
20000
D011
M[1:0] = 10b
Figure 14. Supply Current vs Input Illuminance
D011
D012
Figure 15. Shutdown Current vs Input Illuminance
1.6
Shutdown Supply Current (PA)
Vdd = 3.3V
Vdd = 1.6V
3
Supply Current (PA)
80000
M[1:0] = 00b
3.5
2.5
2
1.5
1
-40
40000
60000
Input Illuminance (Lux)
-20
0
20
40
Temperature (qC)
60
80
100
1.4
Vdd = 3.3V
Vdd = 1.6V
1.2
1
0.8
0.6
0.4
0.2
-40
-20
D013
M[1:0] = 10b
0
20
40
Temperature (qC)
60
80
100
D014
M[1:0] = 00b, input illuminance = 0 lux
Figure 16. Supply Current vs Temperature
Figure 17. Shutdown Current vs Temperature
100
Shutdown Current (PA)
Vdd = 3.3V
Vdd = 1.6V
10
1
0.1
0.01
0.1
1
10
100
1000
Continuous I2C Frequency (KHz)
10000
D015
Input illuminance = 80 lux, SCL = SDA,
continuously toggled at I2C frequency
Note: A typical application runs at a lower duty cycle and thus consumes a lower current.
Figure 18. Supply Current vs Continuous I2C Frequency
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7 Detailed Description
7.1 Overview
The OPT3001-Q1 device measures the ambient light that illuminates the device. This device measures light with
a spectral response very closely matched to the human eye, and with very good infrared rejection.
Matching the sensor spectral response to that of the human eye response is vital because ambient light sensors
are used to measure and help create ideal human lighting experiences. Strong rejection of infrared light, which a
human does not see, is a crucial component of this matching. This matching makes the OPT3001-Q1 device
especially good for operation underneath windows that are visibly dark, but infrared transmissive.
The OPT3001-Q1 device is fully self-contained to measure the ambient light and report the result in lux digitally
over the I2C bus. The result can also be used to alert a system and interrupt a processor with the INT pin. The
result can also be summarized with a programmable window comparison and communicated with the INT pin.
The OPT3001-Q1 device can be configured into an automatic full-scale, range-setting mode that always selects
the optimal full-scale range setting for the lighting conditions. This mode frees the user from having to program
their software for potential iterative cycles of measurement and readjustment of the full-scale range until optimal
for any given measurement. The device can be commanded to operate continuously or in single-shot
measurement modes.
The device integrates its result over either 100 ms or 800 ms, so the effects of 50-Hz and 60-Hz noise sources
from typical light bulbs are nominally reduced to a minimum.
The device starts up in a low-power shutdown state, such that the OPT3001-Q1 device only consumes activeoperation power after being programmed into an active state.
The OPT3001-Q1 optical filtering system is not excessively sensitive to non-ideal particles and micro-shadows
on the optical surface. This reduced sensitivity is a result of the relatively minor device dependency on uniformdensity optical illumination of the sensor area for infrared rejection. Proper optical surface cleanliness is always
recommended for best results on all optical devices.
7.2 Functional Block Diagram
VDD
VDD
OPT3001
Ambient
Light
Optical
Filter
ADC
I2C
Interface
SCL
SDA
INT
ADDR
GND
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7.3 Feature Description
7.3.1 Human Eye Matching
The OPT3001-Q1 spectral response closely matches that of the human eye. If the ambient light sensor
measurement is used to help create a good human experience, or create optical conditions that are optimal for a
human, the sensor must measure the same spectrum of light that a human sees.
The device also has excellent infrared light (IR) rejection. This IR rejection is especially important because many
real-world lighting sources have significant infrared content that humans do not see. If the sensor measures
infrared light that the human eye does not see, then a true human experience is not accurately represented.
Furthermore, if the ambient light sensor is hidden underneath a dark window (such that the end-product user
cannot see the sensor) the infrared rejection of the OPT3001-Q1 device becomes significantly more important
because many dark windows attenuate visible light but transmit infrared light. This attenuation of visible light and
lack of attenuation of IR light amplifies the ratio of the infrared light to visible light that illuminates the sensor.
Results can still be well matched to the human eye under this condition because of the high infrared rejection of
the OPT3001-Q1 device.
7.3.2 Automatic Full-Scale Range Setting
The OPT3001-Q1 device has an automatic full-scale range setting feature that eliminates the need to predict and
set the optimal range for the device. In this mode, the OPT3001-Q1 device automatically selects the optimal fullscale range for the given lighting condition. The OPT3001-Q1 device has a high degree of result matching
between the full-scale range settings. This matching eliminates the problem of varying results or the need for
range-specific, user-calibrated gain factors when different full-scale ranges are chosen. For further details, see
the Automatic Full-Scale Setting Mode section.
7.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
The device has an interrupt reporting system that allows the processor connected to the I2C bus to go to sleep,
or otherwise ignore the device results, until a user-defined event occurs that requires possible action.
Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital
signal that indicates whether the light is above or below levels of interest.
The interrupt event conditions are controlled by the high-limit and low-limit registers, as well as the configuration
register latch and fault count fields. The results of comparing the result register with the high-limit register and
low-limit register are referred to as fault events. The fault count register dictates how many consecutive sameresult fault events are required to trigger an interrupt event and subsequently change the state of the interrupt
reporting mechanisms, which are the INT pin, the flag high field, and the flag low field. The latch field allows a
choice between a latched window-style comparison and a transparent hysteresis-style comparison.
The INT pin has an open-drain output, which requires the use of a pull-up resistor. This open-drain output allows
multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND
function between the devices. The polarity of the INT pin can be controlled with the polarity of interrupt field in
the configuration register. When the POL field is set to 0, the pin operates in an active low behavior that pulls the
pin low when the INT pin becomes active. When the POL field is set to 1, the pin operates in an active high
behavior and becomes high impedance, thus allowing the pin to go high when the INT pin becomes active.
Additional details of the interrupt reporting registers are described in the Interrupt Reporting Mechanism Modes
and Internal Registers sections.
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Feature Description (continued)
7.3.4 I2C Bus Overview
The OPT3001-Q1 device offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols
are essentially compatible with one another. The I2C interface is used throughout this document as the primary
example with the SMBus protocol specified only when a difference between the two protocols is discussed.
The OPT3001-Q1 device is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain
bidirectional data pin. The bus must be controlled by a master device that generates the serial clock (SCL),
controls the bus access, and generates start and stop conditions. To address a specific device, the master
initiates a start condition by pulling the data signal line (SDA) from a high logic level to a low logic level while
SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an acknowledge bit by pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition. When all data are transferred, the master generates a stop condition, indicated by pulling
SDA from low to high while SCL is high. The OPT3001-Q1 device includes a 28-ms timeout on the I2C interface
to prevent locking up the bus. If the SCL line is held low for this duration of time, the bus state machine is reset.
7.3.4.1 Serial Bus Address
To communicate with the OPT3001-Q1 device, the master must first initiate an I2C start command. Then, the
master must address slave devices via a slave address byte. The slave address byte consists of seven address
bits and a direction bit that indicates whether the action is to be a read or write operation.
Four I2C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL.
Table 1 summarizes the possible addresses with the corresponding ADDR pin configuration. The state of the
ADDR pin is sampled on every bus communication and must be driven or connected to the desired level before
any activity on the interface occurs.
Table 1. Possible I2C Addresses with Corresponding ADDR Configuration
DEVICE I2C ADDRESS
ADDR PIN
1000 100
GND
1000 101
VDD
1000 110
SDA
1000 111
SCL
7.3.4.2 Serial Interface
The OPT3001-Q1 device operates as a slave device on both the I2C bus and SMBus. Connections to the bus
are made via the SCL clock input line and the SDA open-drain I/O line. The OPT3001-Q1 device supports the
transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up
to 2.6 MHz). All data bytes are transmitted most-significant bits first.
The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of
input spikes and bus noise. See the Electrical Interface section for further details of the I2C bus noise immunity.
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7.4 Device Functional Modes
7.4.1 Automatic Full-Scale Setting Mode
The OPT3001-Q1 device has an automatic full-scale-range setting mode that eliminates the need for a user to
predict and set the optimal range for the device. This mode is entered when the configuration register range
number field (RN[3:0]) is set to 1100b.
The first measurement that the device takes in auto-range mode is a 10-ms range assessment measurement.
The device then determines the appropriate full-scale range to take its first full measurement.
For subsequent measurements, the full-scale range is set by the result of the previous measurement. If a
measurement is towards the low side of full-scale, the full-scale range is decreased by one or two settings for the
next measurement. If a measurement is towards the upper side of full-scale, the full-scale range is increased by
one setting for the next measurement.
If the measurement exceeds the full-scale range, resulting from a fast increasing optical transient event, the
current measurement is aborted. This invalid measurement is not reported. A 10-ms measurement is taken to
assess and properly reset the full-scale range. Then, a new measurement is taken with this proper full-scale
range. Therefore, during a fast increasing optical transient in this mode, a measurement can possibly take longer
to complete and report than indicated by the configuration register conversion time field (CT).
7.4.2 Interrupt Reporting Mechanism Modes
There are two major types of interrupt reporting mechanism modes: latched window-style comparison mode and
transparent hysteresis-style comparison mode. The configuration register latch field (L) (see the configuration
register, bit 4) controls which of these two modes is used. An end-of-conversion mode is also associated with
each major mode type. The end-of-conversion mode is active when the two most significant bits of the threshold
low register are set to 11b. The mechanisms report via the flag high and flag low fields, the conversion ready
field, and the INT pin.
7.4.2.1 Latched Window-Style Comparison Mode
The latched window-style comparison mode is typically selected when using the OPT3001-Q1 device to interrupt
an external processor. In this mode, a fault is recognized when the input signal is above the high-limit register or
below the low-limit register. When the consecutive fault events trigger the interrupt reporting mechanisms, these
mechanisms are latched, thus reporting whether the fault is the result of a high or low comparison. These
mechanisms remain latched until the configuration register is read, which clears the INT pin and flag high and
flag low fields. The SMBus alert response protocol, described in detail in the SMBus Alert Response section,
clears the pin but does not clear the flag high and flag low fields. The behavior of this mode, along with the
conversion ready flag, is summarized in Table 2. Note that Table 2 does not apply when the two threshold low
register MSBs (see the Transparent Hysteresis-Style Comparison Mode section for clarification on the MSBs) are
set to 11b.
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Device Functional Modes (continued)
Table 2. Latched Window-Style Comparison Mode: Flag Setting and Clearing Summary (1) (2)
FLAG HIGH
FIELD
FLAG LOW
FIELD
INT PIN (3)
CONVERSION
READY FIELD
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
X
Active
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
X
1
Active
1
The conversion is complete with fault count criterion not met
X
X
X
1
OPERATION
Configuration register read
(4)
0
0
Inactive
0
Configuration register write, M[1:0] = 00b (shutdown)
X
X
X
X
Configuration register write, M[1:0] > 00b (not shutdown)
X
X
X
0
SMBus alert response protocol
X
X
Inactive
X
(1)
(2)
(3)
(4)
X = no change from the previous state.
The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low
field can take on different behaviors.
The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two
configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
7.4.2.2 Transparent Hysteresis-Style Comparison Mode
The transparent hysteresis-style comparison mode is typically used when a single digital signal is desired that
indicates whether the input light is higher than or lower than a light level of interest. If the result register is higher
than the high-limit register for a consecutive number of events set by the fault count field, the INT line is set to
active, the flag high field is set to 1, and the flag low field is set to 0. If the result register is lower than the lowlimit register for a consecutive number of events set by the fault count field, the INT line is set to inactive, the flag
low field is set to 1, and the flag high field is set to 0. The INT pin and flag high and flag low fields do not change
state with configuration reads and writes. The INT pin and flag fields continually report the appropriate
comparison of the light to the low-limit and high-limit registers. The device does not respond to the SMBus alert
response protocol while in either of the two transparent comparison modes (configuration register, latch field =
0). The behavior of this mode, along with the conversion ready is summarized in Table 3. Note that Table 3 does
not apply when the two threshold low register MSBs (LE[3:2] from Table 11) are set to 11.
Table 3. Transparent Hysteresis-Style Comparison Mode: Flag Setting and Clearing Summary (1) (2)
FLAG HIGH
FIELD
FLAG LOW
FIELD
INT PIN (3)
CONVERSION
READY FIELD
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
0
Active
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
0
1
Inactive
1
The conversion is complete with fault count criterion not met
X
X
X
1
OPERATION
Configuration register read
(4)
X
X
X
0
Configuration register write, M[1:0] = 00b (shutdown)
X
X
X
X
Configuration register write, M[1:0] > 00b (not shutdown)
X
X
X
0
SMBus alert response protocol
X
X
X
X
(1)
(2)
(3)
(4)
14
X = no change from the previous state.
The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low
field can take on different behaviors.
The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two
configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
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7.4.2.3 End-of-Conversion Mode
An end-of-conversion indicator mode can be used when every measurement is desired to be read by the
processor, prompted by the INT pin going active on every measurement completion. This mode is entered by
setting the most significant two bits of the low-limit register (LE[3:2] from the Low-Limit Register) to 11b. This
end-of-conversion mode is typically used in conjunction with the latched window-style comparison mode. The INT
pin becomes inactive when the configuration register is read or the configuration register is written with a nonshutdown parameter or in response to an SMBus alert response. Table 4 summarizes the interrupt reporting
mechanisms as a result of various operations.
Table 4. End-of-Conversion Mode while in Latched Window-Style Comparison Mode:
Flag Setting and Clearing Summary (1)
FLAG HIGH
FIELD
FLAG LOW
FIELD
INT PIN (2)
CONVERSION
READY FIELD
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
X
Active
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
X
1
Active
1
The conversion is complete with fault count criterion not met
X
X
Active
1
OPERATION
Configuration register read
(3)
0
0
Inactive
0
Configuration register write, M[1:0] = 00b (shutdown)
X
X
X
X
Configuration register write, M[1:0] > 00b (not shutdown)
X
X
X
0
SMBus alert response protocol
X
X
Inactive
X
(1)
(2)
(3)
X = no change from the previous state.
The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two
configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
Note that when transitioning from end-of-conversion mode to the standard comparison modes (that is,
programming LE[3:2] from 11b to 00b) while the configuration register latch field (L) is 1, a subsequent write to
the configuration register latch field (L) to 0 is necessary in order to properly clear the INT pin. The latch field can
then be set back to 1 if desired.
7.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
The combination of end-of-conversion mode and transparent hysteresis-style comparison mode can also be
programmed simultaneously. The behavior of this combination is shown in Table 5.
Table 5. End-Of-Conversion Mode while in Transparent Hysteresis-Style Comparison Mode:
Flag Setting and Clearing Summary (1)
FLAG HIGH
FIELD
FLAG LOW
FIELD
INT PIN (2)
CONVERSION
READY FIELD
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
0
Active
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
0
1
Active
1
The conversion is complete with fault count criterion not met
X
X
Active
1
Configuration register read (3)
X
X
Inactive
0
Configuration register write, M[1:0] = 00b (shutdown)
X
X
X
X
Configuration register write, M[1:0] > 00b (not shutdown)
X
X
Inactive
0
SMBus alert response protocol
X
X
X
X
OPERATION
(1)
(2)
(3)
X = no change from the previous state.
The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two
configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
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7.5 Programming
The OPT3001-Q1 device supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to
400 kHz), and high-speed mode (up to 2.6 MHz). Fast and standard modes are described as the default
protocol, referred to as F/S. High-speed mode is described in the High-Speed I2C Mode section.
7.5.1 Writing and Reading
Accessing a specific register on the OPT3001-Q1 device is accomplished by writing the appropriate register
address during the I2C transaction sequence. Refer to Table 6 for a complete list of registers and their
corresponding register addresses. The value for the register address (as shown in Figure 19) is the first byte
transferred after the slave address byte with the R/W bit low.
1
9
1
9
SCL
SDA
1
0
0
0
1
Start by
Master
A1
A0
R/W
RA
7
RA
6
RA
5
RA
4
RA
3
ACK by
OPT3001
Frame 1: Two-Wire Slave Address Byte (1)
RA
2
RA
1
RA
0
ACK by
OPT3001
Stop by
Master
(optional)
Frame 2: Register Address Byte
(1) The value of the slave address byte is determined by the ADDR pin setting; see Table 1.
Figure 19. Setting the I2C Register Address
Writing to a register begins with the first byte transmitted by the master. This byte is the slave address with the
R/W bit low. The OPT3001-Q1 device then acknowledges receipt of a valid address. The next byte transmitted
by the master is the address of the register that data are to be written to. The next two bytes are written to the
register addressed by the register address. The OPT3001-Q1 device acknowledges receipt of each data byte.
The master may terminate the data transfer by generating a start or stop condition.
When reading from the OPT3001-Q1 device, the last value stored in the register address by a write operation
determines which register is read during a read operation. To change the register address for a read operation, a
new partial I2C write transaction must be initiated. This partial write is accomplished by issuing a slave address
byte with the R/W bit low, followed by the register address byte and a stop command. The master then generates
a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next
byte is transmitted by the slave and is the most significant byte of the register indicated by the register address.
This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The
master acknowledges receipt of the data byte. The master may terminate the data transfer by generating a notacknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the
same register are desired, continually sending the register address bytes is not necessary; the OPT3001-Q1
device retains the register address until that number is changed by the next write operation.
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Programming (continued)
Figure 20 and Figure 21 show the write and read operation timing diagrams, respectively. Note that register
bytes are sent most significant byte first, followed by the least significant byte.
1
9
9
1
1
9
1
9
SCL
SDA
1
0
0
0
1
A1
A0
Start by
Master
RA
7
R/W
RA
6
RA
5
RA
4
RA
3
RA
2
RA
1
RA
0
ACK by
OPT3001
Frame 1 Two-Wire Slave Address Byte (1)
D15 D14 D13 D12 D11 D10 D9
Frame 2 Register Address Byte
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACK by
OPT3001
ACK by
OPT3001
ACK by
OPT3001
Frame 3 Data MSByte
Stop by
Master
Frame 4 Data LSByte
(1) The value of the slave address byte is determined by the setting of the ADDR pin; see Table 1.
Figure 20. I2C Write Example
1
9
1
9
1
9
SCL
SDA
1
0
0
0
1
A1
A0 R/W
Start by
Master
D15 D14 D13 D12 D11 D10 D9
ACK by
OPT3001
Frame 1 Two-Wire Slave Address Byte (1)
From
OPT3001
D8
D7
ACK by
Master
Frame 2 Data MSByte
D6
D5
D4
D3
D2
D1
From
OPT3001
D0
No ACK Stop by
by
Master
Master(2)
Frame 3 Data LSByte
(1) The value of the slave address byte is determined by the ADDR pin setting; see Table 1.
(2) An ACK by the master can also be sent.
Figure 21. I2C Read Example
7.5.1.1 High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up resistors or active pull-up
devices. The master generates a start condition followed by a valid serial byte containing the high-speed (HS)
master code 0000 1XXXb. This transmission is made in either standard mode or fast mode (up to 400 kHz). The
OPT3001-Q1 device does not acknowledge the HS master code but does recognize the code and switches its
internal filters to support a 2.6-MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 2.6 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the
bus in HS mode. A stop condition ends the HS mode and switches all internal filters of the OPT3001-Q1 device
to support the F/S mode.
7.5.1.2 General-Call Reset Command
The I2C general-call reset allows the host controller in one command to reset all devices on the bus that respond
to the general-call reset command. The general call is initiated by writing to the I2C address 0 (0000 0000b). The
reset command is initiated when the subsequent second address byte is 06h (0000 0110b). With this transaction,
the device issues an acknowledge bit and sets all of its registers to the power-on-reset default condition.
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Programming (continued)
7.5.1.3 SMBus Alert Response
The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert
response capability, the processor does not know which device pulled the interrupt line when there are multiple
slave devices connected.
The OPT3001-Q1 device is designed to respond to the SMBus alert response address, when in the latched
window-style comparison mode (configuration register, latch field = 1). The OPT3001-Q1 device does not
respond to the SMBus alert response when in transparent mode (configuration register, latch field = 0).
The response behavior of the OPT3001-Q1 device to the SMBus alert response is shown in Figure 22. When the
interrupt line to the processor is pulled to active, the master can broadcast the alert response slave address
(0001 1001b). Following this alert response, any slave devices that generated an alert identify themselves by
acknowledging the alert response and sending their respective I2C address on the bus. The alert response can
activate several different slave devices simultaneously. If more than one slave attempts to respond, bus
arbitration rules apply. The device with the lowest address wins the arbitration. If the OPT3001-Q1 device loses
the arbitration, the device does not acknowledge the I2C transaction and its INT pin remains in an active state,
prompting the I2C master processor to issue a subsequent SMBus alert response. When the OPT3001-Q1
device wins the arbitration, the device acknowledges the transaction and sets its INT pin to inactive. The master
can issue that same command again, as many times as necessary to clear the INT pin. See the Interrupt
Reporting Mechanism Modes section for additional details of how the flags and INT pin are controlled. The
master can obtain information about the source of the OPT3001-Q1 interrupt from the address broadcast in the
above process. The flag high field (configuration register, bit 6) is sent as the final LSB of the address to provide
the master additional information about the cause of the OPT3001-Q1 interrupt. If the master requires additional
information, the result register or the configuration register can be queried. The flag high and flag low fields are
not cleared upon an SMBus alert response.
INT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
Start By
Master
R/W
1
0
0
ACK By
Device
Frame 1 SMBus ALERT Response Address Byte
0
1
A1
A0
From
Device
FH(1)
NACK By
Master
Stop By
Master
(2)
Frame 2 Slave Address Byte
(1) FH is the flag high field (FH) in the configuration register (see Table 10).
(2) A1 and A0 are determined by the ADDR pin; see Table 1.
Figure 22. Timing Diagram for SMBus Alert Response
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7.6 Register Maps
7.6.1 Internal Registers
The device is operated over the I2C bus with registers that contain configuration, status, and result information. All registers are 16 bits long.
There are four main registers: result, configuration, low-limit, and high-limit. There are also two ID registers: manufacturer ID and device ID. Table 6 lists
these registers.
Table 6. Register Map
REGISTER
ADDRESS
(Hex) (1)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Result
00h
E3
E2
E1
E0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Configuration
01h
RN3
RN2
RN1
RN0
CT
M1
M0
OVF
CRF
FH
FL
L
POL
ME
FC1
FC0
Low Limit
02h
LE3
LE2
LE1
LE0
TL11
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
High Limit
03h
HE3
HE2
HE1
HE0
TH11
TH10
TH9
TH8
TH7
TH6
TH5
TH4
TH3
TH2
TH1
TH0
Manufacturer ID
7Eh
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Device ID
7Fh
DID15
DID14
DID13
DID12
DID11
DID10
DID9
DID8
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
(1)
Register offset and register address are used interchangeably.
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7.6.1.1 Register Descriptions
NOTE
Register offset and register address are used interchangeably.
7.6.1.1.1 Result Register (offset = 00h)
This register contains the result of the most recent light to digital conversion. This 16-bit register has two fields: a
4-bit exponent and a 12-bit mantissa.
Figure 23. Result Register (Read-Only)
15
E3
R
14
E2
R
13
E1
R
12
E0
R
11
R11
R
10
R10
R
9
R9
R
8
R8
R
7
R7
R
6
R6
R
5
R5
R
4
R4
R
3
R3
R
2
R2
R
1
R1
R
0
R0
R
LEGEND: R = Read only
Table 7. Result Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
E[3:0]
R
0h
Exponent.
These bits are the exponent bits. Table 8 provides further details.
11:0
R[11:0]
R
000h
Fractional result.
These bits are the result in straight binary coding (zero to full-scale).
Table 8. Full-Scale Range and LSB Size as a Function of Exponent Level
E3
E2
E1
E0
FULL-SCALE RANGE (lux)
LSB SIZE (lux per LSB)
0
0
0
0
40.95
0.01
0
0
0
1
81.90
0.02
0
0
1
0
163.80
0.04
0
0
1
1
327.60
0.08
0
1
0
0
655.20
0.16
0
1
0
1
1310.40
0.32
0
1
1
0
2620.80
0.64
0
1
1
1
5241.60
1.28
1
0
0
0
10483.20
2.56
1
0
0
1
20966.40
5.12
1
0
1
0
41932.80
10.24
1
0
1
1
83865.60
20.48
The formula to translate this register into lux is given in Equation 1:
lux = LSB_Size × R[11:0]
(1)
where:
LSB_Size = 0.01 × 2E[3:0]
(2)
LSB_Size can also be taken from Table 8. The complete lux equation is shown in Equation 3:
lux = 0.01 × (2E[3:0]) × R[11:0]
(3)
A series of result register output examples with the corresponding LSB weight and resulting lux are given in
Table 9. Note that many combinations of exponents (E[3:0]) and fractional results (R[11:0]) can map onto the
same lux result, as shown in the examples of Table 9.
20
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Table 9. Examples of Decoding the Result Register into lux
FRACTIONAL
RESULT
(R[11:0], Hex)
LSB WEIGHT
(lux, Decimal)
00h
001h
0.01
0.01
00h
FFFh
0.01
40.95
0011 0100 0101 0110b
03h
456h
0.08
88.80
0111 1000 1001 1010b
07h
89Ah
1.28
2818.56
1000 1000 0000 0000b
08h
800h
2.56
5242.88
1001 0100 0000 0000b
09h
400h
5.12
5242.88
1010 0010 0000 0000b
0Ah
200h
10.24
5242.88
1011 0001 0000 0000b
0Bh
100h
20.48
5242.88
1011 0000 0000 0001b
0Bh
001h
20.48
20.48
1011 1111 1111 1111b
0Bh
FFFh
20.48
83865.60
RESULT REGISTER
(Bits 15:0, Binary)
EXPONENT
(E[3:0], Hex)
0000 0000 0000 0001b
0000 1111 1111 1111b
RESULTING LUX
(Decimal)
Note that the exponent field can be disabled (set to zero) by enabling the exponent mask (configuration register,
ME field = 1) and manually programming the full-scale range (configuration register, RN[3:0] < 1100b (0Ch)),
allowing for simpler operation in a manually-programmed, full-scale mode. Calculating lux from the result register
contents only requires multiplying the result register by the LSB weight (in lux) associated with the specific
programmed full-scale range (see Table 8). See the Low-Limit Register for details.
See the configuration register conversion time field (CT, bit 11) description for more information on lux resolution
as a function of conversion time.
7.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
This register controls the major operational modes of the device. This register has 11 fields, which are
documented below. If a measurement conversion is in progress when the configuration register is written, the
active measurement conversion immediately aborts. If the new configuration register directs a new conversion,
that conversion is subsequently started.
Figure 24. Configuration Register
15
RN3
R/W
14
RN2
R/W
13
RN1
R/W
12
RN0
R/W
11
CT
R/W
10
M1
R/W
9
M0
R/W
8
OVF
R
7
CRF
R
6
FH
R
5
FL
R
4
L
R/W
3
POL
R/W
2
ME
R/W
1
FC1
R/W
0
FC0
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 10. Configuration Register Field Descriptions
Bit
15:12
Field
RN[3:0]
Type
R/W
Reset
Description
1100b
Range number field (read or write).
The range number field selects the full-scale lux range of the device. The format of this field is
the same as the result register exponent field (E[3:0]); see Table 8. When RN[3:0] is set to
1100b (0Ch), the device operates in automatic full-scale setting mode, as described in the
Automatic Full-Scale Setting Mode section. In this mode, the automatically chosen range is
reported in the result exponent (register 00h, E[3:0]).
The device powers up as 1100 in automatic full-scale setting mode. Codes 1101b, 1110b, and
1111b (0Dh, 0Eh, and 0Fh) are reserved for future use.
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Table 10. Configuration Register Field Descriptions (continued)
Bit
11
10:9
8
7
6
5
22
Field
CT
M[1:0]
OVF
CRF
FH
FL
Type
R/W
R/W
R
R
R
R
Reset
Description
1b
Conversion time field (read or write).
The conversion time field determines the length of the light to digital conversion process. The
choices are 100 ms and 800 ms. A longer integration time allows for a lower noise
measurement.
The conversion time also relates to the effective resolution of the data conversion process. The
800-ms conversion time allows for the fully specified lux resolution. The 100-ms conversion
time with full-scale ranges above 0101b for E[3:0] in the result and configuration registers also
allows for the fully specified lux resolution. The 100-ms conversion time with full-scale ranges
below and including 0101b for E[3:0] can reduce the effective result resolution by up to three
bits, as a function of the selected full-scale range. Range 0101b reduces by one bit. Ranges
0100b, 0011b, 0010b, and 0001b reduces by two bits. Range 0000b reduces by three bits.
The result register format and associated LSB weight does not change as a function of the
conversion time.
0 = 100 ms
1 = 800 ms
00b
Mode of conversion operation field (read or write).
The mode of conversion operation field controls whether the device is operating in continuous
conversion, single-shot, or low-power shutdown mode. The default is 00b (shutdown mode),
such that upon power-up, the device only consumes operational level power after appropriately
programming the device.
When single-shot mode is selected by writing 01b to this field, the field continues to read 01b
while the device is actively converting. When the single-shot conversion is complete, the mode
of conversion operation field is automatically set to 00b and the device is shut down.
When the device enters shutdown mode, either by completing a single-shot conversion or by a
manual write to the configuration register, there is no change to the state of the reporting flags
(conversion ready, flag high, flag low) or the INT pin. These signals are retained for
subsequent read operations while the device is in shutdown mode.
00 = Shutdown (default)
01 = Single-shot
10, 11 = Continuous conversions
0b
Overflow flag field (read-only).
The overflow flag field indicates when an overflow condition occurs in the data conversion
process, typically because the light illuminating the device exceeds the programmed full-scale
range of the device. Under this condition OVF is set to 1, otherwise OVF remains at 0. The
field is reevaluated on every measurement.
If the full-scale range is manually set (RN[3:0] field < 1100b), the overflow flag field can be set
while the result register reports a value less than full-scale. This result occurs if the input light
has a temporary high spike level that temporarily overloads the integrating ADC converter
circuitry but returns to a level within range before the conversion is complete. Thus, the
overflow flag reports a possible error in the conversion process. This behavior is common to
integrating-style converters.
If the full-scale range is automatically set (RN[3:0] field = 1100b), the only condition that sets
the overflow flag field is if the input light is beyond the full-scale level of the entire device.
When there is an overflow condition and the full-scale range is not at maximum, the OPT3001Q1 device aborts its current conversion, sets the full-scale range to a higher level, and starts a
new conversion. The flag is set at the end of the process. This process repeats until there is
either no overflow condition or until the full-scale range is set to its maximum range.
0b
Conversion ready field (read-only).
The conversion ready field indicates when a conversion completes. The field is set to 1 at the
end of a conversion and is cleared (set to 0) when the configuration register is subsequently
read or written with any value except one containing the shutdown mode (mode of operation
field, M[1:0] = 00b). Writing a shutdown mode does not affect the state of this field; see the
Interrupt Reporting Mechanism Modes section for more details.
0b
Flag high field (read-only).
The flag high field (FH) identifies that the result of a conversion is larger than a specified level
of interest. FH is set to 1 when the result is larger than the level in the high-limit register
(register address 03h) for a consecutive number of measurements defined by the fault count
field (FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on
clearing and other behaviors of this field.
0b
Flag low field (read-only).
The flag low field (FL) identifies that the result of a conversion is smaller than a specified level
of interest. FL is set to 1 when the result is smaller than the level in the low-limit register
(register address 02h) for a consecutive number of measurements defined by the fault count
field (FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on
clearing and other behaviors of this field.
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Table 10. Configuration Register Field Descriptions (continued)
Bit
4
3
2
1:0
Field
L
POL
ME
FC[1:0]
Type
R/W
R/W
R/W
R/W
Reset
Description
1b
Latch field (read or write).
The latch field controls the functionality of the interrupt reporting mechanisms: the INT pin, the
flag high field (FH), and flag low field (FL). This bit selects the reporting style between a
latched window-style comparison and a transparent hysteresis-style comparison.
0 = The device functions in transparent hysteresis-style comparison operation, where the three
interrupt reporting mechanisms directly reflect the comparison of the result register with the
high- and low-limit registers with no user-controlled clearing event. See the Interrupt Operation,
INT Pin, and Interrupt Reporting Mechanisms section for further details.
1 = The device functions in latched window-style comparison operation, latching the interrupt
reporting mechanisms until a user-controlled clearing event.
0b
Polarity field (read or write).
The polarity field controls the polarity or active state of the INT pin.
0 = The INT pin reports active low, pulling the pin low upon an interrupt event.
1 = Operation of the INT pin is inverted, where the INT pin reports active high, becoming high
impedance and allowing the INT pin to be pulled high upon an interrupt event.
0b
Mask exponent field (read or write).
The mask exponent field forces the result register exponent field (register 00h, bits E[3:0]) to
0000b when the full-scale range is manually set, which can simplify the processing of the
result register when the full-scale range is manually programmed. This behavior occurs when
the mask exponent field is set to 1 and the range number field (RN[3:0]) is set to less than
1100b. Note that the masking is only performed to the result register. When using the interrupt
reporting mechanisms, the result comparison with the low-limit and high-limit registers is
unaffected by the ME field.
00b
Fault count field (read or write).
The fault count field instructs the device as to how many consecutive fault events are required
to trigger the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low
field (FL). The fault events are described in the latch field (L), flag high field (FH), and flag low
field (FL) descriptions.
00 = One fault count (default)
01 = Two fault counts
10 = Four fault counts
11 = Eight fault counts
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7.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
This register sets the lower comparison limit for the interrupt reporting mechanisms: the INT pin, the flag high
field (FH), and flag low field (FL), as described in the Interrupt Reporting Mechanism Modes section.
Figure 25. Low-Limit Register
15
LE3
R/W
14
LE2
R/W
13
LE1
R/W
12
LE0
R/W
11
TL11
R/W
10
TL10
R/W
9
TL9
R/W
8
TL8
R/W
7
TL7
R/W
6
TL6
R/W
5
TL5
R/W
4
TL4
R/W
3
TL3
R/W
2
TL2
R/W
1
TL1
R/W
0
TL0
R/W
LEGEND: R/W = Read/Write
Table 11. Low-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
LE[3:0]
R/W
0h
Exponent.
These bits are the exponent bits. Table 12 provides further details.
11:0
TL[11:0]
R/W
000h
Result.
These bits are the result in straight binary coding (zero to full-scale).
The format of this register is nearly identical to the format of the result register described in the Result Register.
The low-limit register exponent (LE[3:0]) is similar to the result register exponent (E[3:0]). The low-limit register
result (TL[11:0]) is similar to result register result (R[11:0]).
The equation to translate this register into the lux threshold is given in Equation 4, which is similar to the
equation for the result register, Equation 3.
lux = 0.01 × (2LE[3:0]) × TL[11:0]
(4)
Table 12 gives the full-scale range and LSB size as it applies to the low-limit register. The detailed discussion
and examples given in for the Result Register apply to the low-limit register as well.
Table 12. Full-Scale Range and LSB Size as a Function of Exponent Level
LE3
LE2
LE1
LE0
FULL-SCALE RANGE (lux)
LSB SIZE (lux per LSB)
0
0
0
0
40.95
0.01
0
0
0
1
81.90
0.02
0
0
1
0
163.80
0.04
0
0
1
1
327.60
0.08
0
1
0
0
655.20
0.16
0
1
0
1
1310.40
0.32
0
1
1
0
2620.80
0.64
0
1
1
1
5241.60
1.28
1
0
0
0
10483.20
2.56
1
0
0
1
20966.40
5.12
1
0
1
0
41932.80
10.24
1
0
1
1
83865.60
20.48
NOTE
The result and limit registers are all converted into lux values internally for comparison.
These registers can have different exponent fields. However, when using a manually-set
full-scale range (configuration register, RN < 0Ch, with mask enable (ME) active),
programming the manually-set full-scale range into the LE[3:0] and HE[3:0] fields can
simplify the choice of programming the register. This simplification results in the user only
having to think about the fractional result and not the exponent part of the result.
24
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7.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
The high-limit register sets the upper comparison limit for the interrupt reporting mechanisms: the INT pin, the
flag high field (FH), and flag low field (FL), as described in the Interrupt Operation, INT Pin, and Interrupt
Reporting Mechanisms section. The format of this register is almost identical to the format of the low-limit register
(described in the Low-Limit Register) and the result register (described in the Result Register). To explain the
similarity in more detail, the high-limit register exponent (HE[3:0]) is similar to the low-limit register exponent
(LE[3:0]) and the result register exponent (E[3:0]). The high-limit register result (TH[11:0]) is similar to the lowlimit result (TH[11:0]) and the result register result (R[11:0]). Note that the comparison of the high-limit register
with the result register is unaffected by the ME bit.
When using a manually-set, full-scale range with the mask enable (ME) active, programming the manually-set,
full-scale range into the HE[3:0] bits can simplify the choice of values required to program into this register. The
formula to translate this register into lux is similar to Equation 4. The full-scale values are similar to Table 8.
Figure 26. High-Limit Register
15
HE3
R/W
14
HE2
R/W
13
HE1
R/W
12
HE0
R/W
11
TH11
R/W
10
TH10
R/W
9
TH9
R/W
8
TH8
R/W
7
TH7
R/W
6
TH6
R/W
5
TH5
R/W
4
TH4
R/W
3
TH3
R/W
2
TH2
R/W
1
TH1
R/W
0
TH0
R/W
LEGEND: R/W = Read/Write
Table 13. High-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
HE[3:0]
R/W
Bh
Exponent.
These bits are the exponent bits.
11:0
TH[11:0]
R/W
FFFh
Result.
These bits are the result in straight binary coding (zero to full-scale).
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7.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
This register is intended to help uniquely identify the device.
Figure 27. Manufacturer ID Register
15
ID15
R
14
ID14
R
13
ID13
R
12
ID12
R
11
ID11
R
10
ID10
R
9
ID9
R
8
ID8
R
7
ID7
R
6
ID6
R
5
ID5
R
4
ID4
R
3
ID3
R
2
ID2
R
1
ID1
R
0
ID0
R
LEGEND: R = Read only
Table 14. Manufacturer ID Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
ID[15:0]
R
5449h
Manufacturer ID.
The manufacturer ID reads 5449h. In ASCII code, this register reads TI.
7.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
This register is also intended to help uniquely identify the device.
Figure 28. Device ID Register
15
DID15
R
14
DID14
R
13
DID13
R
12
DID12
R
11
DID11
R
10
DID10
R
9
DID9
R
8
DID8
R
7
DID7
R
6
DID6
R
5
DID5
R
4
DID4
R
3
DID3
R
2
DID2
R
1
DID1
R
0
DID0
R
LEGEND: R = Read only
Table 15. Device ID Register Field Descriptions
Bit
15:0
26
Field
Type
Reset
Description
DID[15:0]
R
3001h
Device ID.
The device ID reads 3001h.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Ambient light sensors are used in a wide variety of applications that require control as a function of ambient light.
Because ambient light sensors nominally match the human eye spectral response, they are superior to
photodiodes when the goal is to create an experience for human beings. Very common applications include
display optical-intensity control and industrial or home lighting control.
There are two categories of interface to the OPT3001-Q1 device: electrical and optical.
8.1.1 Electrical Interface
The electrical interface is quite simple, as illustrated in Figure 29. Connect the OPT3001-Q1 I2C SDA and SCL
pins to the same pins of an applications processor, microcontroller, or other digital processor. If that digital
processor requires an interrupt resulting from an event of interest from the OPT3001-Q1 device, then connect the
INT pin to either an interrupt or general-purpose I/O pin of the processor. There are multiple uses for this
interrupt, including signaling the system to wake up from low-power mode, processing other tasks while waiting
for an ambient light event of interest, or alerting the processor that a sample is ready to be read. Connect pullup
resistors between a power supply appropriate for digital communication and the SDA and SCL pins (because
they have open-drain output structures). If the INT pin is used, connect a pullup resistor to the INT pin. A typical
value for these pullup resistors is 10 kΩ. The resistor choice can be optimized in conjunction to the bus
capacitance to balance the system speed, power, noise immunity, and other requirements.
The power supply and grounding considerations are discussed in the Power-Supply Recommendations section.
Although spike suppression is integrated in the SDA and SCL pin circuits, use proper layout practices to
minimize the amount of coupling into the communication lines. One possible introduction of noise occurs from
capacitively coupling signal edges between the two communication lines themselves. Another possible noise
introduction comes from other switching noise sources present in the system, especially for long communication
lines. In noisy environments, shield communication lines to reduce the possibility of unintended noise coupling
into the digital I/O lines that could be incorrectly interpreted.
8.1.2 Optical Interface
The optical interface is physically located within the package, facing away from the PCB, as specified by the
Sensor Area in Figure 37.
Physical components, such as a plastic housing and a window that allows light from outside of the design to
illuminate the sensor (see Figure 30), can help protect the OPT3001-Q1 device and neighboring circuitry.
Sometimes, a dark or opaque window is used to further enhance the visual appeal of the design by hiding the
sensor from view. This window material is typically transparent plastic or glass.
Any physical component that affects the light that illuminates the sensing area of a light sensor also affects the
performance of that light sensor. Therefore, for optimal performance, make sure to understand and control the
effect of these components. Design a window width and height to permit light from a sufficient field of view to
illuminate the sensor. For best performance, use a field of view of at least ±35°, or ideally ±45° or more.
Understanding and designing the field of view is discussed further in application report SBEA002, OPT3001:
Ambient Light Sensor Application Guide.
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Application Information (continued)
The visible-spectrum transmission for dark windows typically ranges between 5% to 30%, but can be less than
1%. Specify a visible-spectrum transmission as low as, but no more than, necessary to achieve sufficient visual
appeal because decreased transmission decreases the available light for the sensor to measure. The windows
are made dark by either applying an ink to a transparent window material, or including a dye or other optical
substance within the window material itself. This attenuating transmission in the visible spectrum of the window
creates a ratio between the light on the outside of the design and the light that is measured by the OPT3001-Q1
device. To accurately measure the light outside of the design, compensate the OPT3001-Q1 measurement for
this ratio; an example is given in Dark Window Selection and Compensation.
Ambient light sensors are used to help create ideal lighting experiences for humans; therefore, the matching of
the sensor spectral response to that of the human eye response is vital. Infrared light is not visible to the human
eye, and can interfere with the measurement of visible light when sensors lack infrared rejection. Therefore, the
ratio of visible light to interfering infrared light affects the accuracy of any practical system that represents the
human eye. The strong rejection of infrared light by the OPT3001-Q1 device allows measurements consistent
with human perception under high-infrared lighting conditions, such as from incandescent, halogen, or sunlight
sources.
Although the inks and dyes of dark windows serve their primary purpose of being minimally transmissive to
visible light, some inks and dyes can also be very transmissive to infrared light. The use of these inks and dyes
further decreases the ratio of visible to infrared light, and thus decreases sensor measurement accuracy.
However, because of the excellent infrared rejection of the OPT3001-Q1 device, this effect is minimized, and
good results are achieved under a dark window with similar spectral responses to those shown in Figure 31.
For best accuracy, avoid grill-like window structures, unless the designer understands the optical effects
sufficiently. These grill-like window structures create a nonuniform illumination pattern at the sensor that make
light measurement results vary with placement tolerances and angle of incidence of the light. If a grill-like
structure is desired, the OPT3001-Q1 device is an excellent sensor choice because it is minimally sensitive to
illumination uniformity issues disrupting the measurement process.
Light pipes can appear attractive for aiding in the optomechanical design that brings light to the sensor; however,
do not use light pipes with any ambient light sensor unless the system designer fully understands the
ramifications of the optical physics of light pipes within the full context of his design and objectives.
8.2 Typical Application
Measuring the ambient light with the OPT3001-Q1 device in a product case and under a dark window is
described in this section. The schematic for this design is shown in Figure 29.
VDD
VDD
Digital Processor
OPT3001
Ambient
Light
Optical
Filter
SCL
ADC
I2C
Interface
SDA
INT
SCL
SDA
INT or GPIO
ADDR
GND
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Figure 29. Measuring Ambient Light in a Product Case Behind a Dark Window
28
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Typical Application (continued)
8.2.1 Design Requirements
The basic requirements of this design are:
• Sensor is hidden under dark glass so that sensor is not obviously visible. Note that this requirement is
subjective to designer preference.
• Accuracy of measurement of fluorescent light is 15%
• Variation in measurement between fluorescent, halogen, and incandescent bulbs (also known as light source
variation) is as small as possible.
8.2.2 Detailed Design Procedure
8.2.2.1 Optomechanical Design
After completing the electrical design, the next task is the optomechancial design. Design a product case that
includes a window to transmit the light from outside the product to the sensor, as shown in Figure 30. Design the
window width and window height to give a ±45° field of view. A rigorous design of the field of view takes into
account the location of the sensor area, as shown in Figure 37. The OPT3001-Q1 active sensor area is centered
along one axis of the package top view, but has a minor offset on the other axis of the top view. Window sizing
and placement is discussed in more rigorous detail in application report SBEA002, OPT3001: Ambient Light
Sensor Application Guide.
Window Width
Window
Product Case
Field of View
Window Height
OPT3001
Side View
Active Sensor Area
PCB
Figure 30. Product Case and Window Over the OPT3001-Q1 Device
8.2.2.2 Dark Window Selection and Compensation
There are several approaches to selecting and compensating for a dark window. One of many approaches is the
method described here.
Sample several different windows with various levels of darkness. Choose a window that is dark enough to
optimize the balance between the aesthetics of the device and sensor performance. Note that the aesthetic
evaluation is the subjective opinion of the designer; therefore, it is more important to see the window on the
physical design rather than refer to window transmission specifications on paper. Make sure that the chosen
window is not darker than absolutely necessary because a darker window allows less light to illuminate the
sensor and therefore impedes sensor accuracy.
The window chosen for this application example is dark and has less than 7% transmission at 550 nm.Figure 31
shows the normalized response of the spectrum. Note that the equipment used to measure the transmission
spectrum is not capable of measuring the absolute accuracy (non-normalized) of the dark window sample, but
only the relative normalized spectrum. Also note that the window is much more transmissive to infrared
wavelengths longer than 700 nm than to visible wavelengths between 400 nm and 650 nm. This imbalance
between infrared and visible light decreases the ratio of visible light to infrared light at the sensor. Although it is
preferable to have the window decrease this ratio as little as possible (by having a window with a close ratio of
visible transmission to infrared transmission), the OPT3001-Q1 device still performs well as shown in Figure 34.
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Typical Application (continued)
1
Normalized Transmission
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600
700
Wavelength (nm)
800
900
1000
D018
Figure 31. Normalized Transmission Spectral Response of the Chosen Dark Window
After choosing the dark window, measure the attenuating effect of the dark window for later compensation. In
order to measure this attenuation, measure a fluorescent light source with a lux meter, then measure that same
light with the OPT3001-Q1 device under the dark window. To measure accurately, it is important to use a fixture
that can accommodate either the lux meter or the design containing the OPT3001-Q1 device and dark window,
with the center of each of the sensing areas being in exactly the same X, Y, Z location, as shown in Figure 32.
The Z placement of the design (distance from the light source) is the top of the window, and not the OPT3001Q1 device itself.
Light Source
Light Source
OPT3001
and
Window
Lux
Meter
Figure 32. Fixture With One Light Source Accommodating Either a Lux Meter or the Design (Window and
OPT3001-Q1 Device) in the Exact Same X,Y,Z Position
The fluorescent light in this location measures 1000 lux with the lux meter, and 73 lux with the OPT3001-Q1
device under the dark window within the application. Therefore, the window has an effective transmission of
7.3% for the fluorescent light. This 7.3% is the weighted average attenuation across the entire spectrum,
weighted by the spectral response of the lux meter (or photopic response).
For all subsequent OPT3001-Q1 measurements under this dark window, the following formula is applied.
Compensated Measurement = Uncompensated Measurement / (7.3%)
30
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Typical Application (continued)
8.2.3 Application Curves
To validate that the design example now measures correctly, create a sequential number of different light
intensities with the fluorescent light by using neutral density filters to attenuate the light. Different light intensities
can also be created by changing the distance between the light source, and the measurement devices. However,
these two methods for changing the light level have minor accuracy tradeoffs that are beyond the scope of this
discussion. Measure each intensity with both the lux meter and the OPT3001-Q1 device under the window, and
compensate using Equation 5. The results are displayed in Figure 33, and show that the application accurately
reports results very similar to the lux meter.
To validate that the design measures a variety of light sources correctly, despite the large ratio of infrared
transmission to visible light transmission of the window, measure the application with a halogen bulb and an
incandescent bulb. Use the physical location and light attenuation procedures that were used for the fluorescent
light. The results are shown in Figure 34.
The addition of the dark window changes the results as seen by comparing the results of the same measurement
with a window (Figure 34) and without a window (Figure 3). Even after the expected change, the performance is
still good. All data are both within 15% of the correct answer, and within 15% of the other bulb measurements.
Results can vary at different angles of light because the OPT3001-Q1 device does not match the lux meter at all
angles of light.
If the measurement variation between the light sources is not acceptable, choose a different window that has a
closer ratio of visible light transmission to infrared light transmission.
1000
1000
Compensated
Uncompensated
900
800
OPT3001 Output (Lux)
800
OPT3001 Output (Lux)
Fluorescent
Halogen
Incandescent
900
700
600
500
400
300
700
600
500
400
300
200
200
100
100
0
0
0
100
200
300
400 500 600
Lux Meter (Lux)
700
800
900 1000
0
100
D019
D001
Figure 33. Uncompensated and Compensated Output of
the OPT3001-Q1 Device Under a Dark Window Illuminated
by Fluorescent Light Source
200
300
400 500 600
Lux Meter (Lux)
700
800
900 1000
D020
Figure 34. Compensated Output of the OPT3001-Q1 Device
Under a Dark Window Illuminated by Fluorescent,
Halogen, and Incandescent Light Sources
8.3 Do's and Don'ts
As with any optical product, special care must be taken into consideration when handling the OPT3001-Q1
device. Although the OPT3001-Q1 device has low sensitivity to dust and scratches, proper optical device
handling procedures are still recommended.
The optical surface of the device must be kept clean for optimal performance in both prototyping with the device
and mass production manufacturing procedures. Tweezers with plastic or rubber contact surfaces are
recommended to avoid scratches on the optical surface. Avoid manipulation with metal tools when possible. The
optical surface must be kept clean of fingerprints, dust, and other optical-inhibiting contaminants.
If the device optical surface requires cleaning, the use of de-ionized water or isopropyl alcohol is recommended.
A few gentile brushes with a soft swab are appropriate. Avoid potentially abrasive cleaning and manipulating
tools and excessive force that can scratch the optical surface.
If the OPT3001-Q1 device performs less than optimally, inspect the optical surface for dirt, scratches, or other
optical artifacts.
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9 Power-Supply Recommendations
Although the OPT3001-Q1 device has low sensitivity to power-supply issues, good practices are always
recommended. For best performance, the OPT3001-Q1 VDD pin must have a stable, low-noise power supply with
a 100-nF bypass capacitor close to the device and solid grounding. There are many options for powering the
OPT3001-Q1 device, because the device current consumption levels are very low.
10 Layout
10.1 Layout Guidelines
The PCB layout design for the OPT3001-Q1 device requires a couple of considerations. Bypass the power
supply with a capacitor placed close to the OPT3001-Q1 device. Note that optically reflective surfaces of
components also affect the performance of the design. The three-dimensional geometry of all components and
structures around the sensor must be taken into consideration to prevent unexpected results from secondary
optical reflections. Placing capacitors and components at a distance of at least twice the height of the component
is usually sufficient. The most optimal optical layout is to place all close components on the opposite side of the
PCB from the OPT3001-Q1 device. However, this approach may not be practical for the constraints of every
design.
Electrically connecting the thermal pad to ground is recommended. This connection can be created either with a
PCB trace or with vias to ground directly on the thermal pad itself. If the thermal pad contains vias, they are
recommended to be of a small diameter (< 0.2 mm) to prevent them from wicking the solder away from the
appropriate surfaces.
An example PCB layout with the OPT3001-Q1 device is shown in Figure 35.
10.2 Layout Example
Bypass Capacitor
OPT3001
To VDD
Power Supply
To
Processor
Figure 35. Example PCB Layout With the OPT3001-Q1 Device
32
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• OPT3001: Ambient Light Sensor Application Guide (SBEA002)
• OPT3001EVM User's Guide (SBOU134)
• QFN/SON PCB Attachment Application Report (SLUA271)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
12.1 Soldering and Handling Recommendations
The OPT3001-Q1 device has been qualified for three soldering reflow operations per JEDEC JSTD-020.
Note that excessive heat may discolor the device and affect optical performance.
See application report QFN/SON PCB Attachment (SLUA271), for details on soldering thermal profile and other
information. If the OPT3001-Q1 device must be removed from a PCB, discard the device and do not reattach.
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Soldering and Handling Recommendations (continued)
As with most optical devices, handle the OPT3001-Q1 device with special care to ensure optical surfaces stay
clean and free from damage. See the Do's and Don'ts section for more detailed recommendations. For best
optical performance, solder flux and any other possible debris must be cleaned after soldering processes.
12.2 DNP (S-PDSO-N6) Mechanical Drawings
Figure 36. Package Orientation Visual Reference of Pin 1
(Top View)
34
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DNP (S-PDSO-N6) Mechanical Drawings (continued)
Top View
0.49
0.39
0.09
Side View
Figure 37. Mechanical Outline Showing Sensing Area Location
(Top and Side Views)
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35
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPT3001IDNPRQ1
ACTIVE
USON
DNP
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
ED
OPT3001IDNPTQ1
ACTIVE
USON
DNP
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
ED
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2018
OTHER QUALIFIED VERSIONS OF OPT3001-Q1 :
• Catalog: OPT3001
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPT3001IDNPRQ1
USON
DNP
6
3000
330.0
18.4
2.3
2.3
0.9
8.0
12.0
Q1
OPT3001IDNPTQ1
USON
DNP
6
250
180.0
12.4
2.3
2.3
0.9
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPT3001IDNPRQ1
USON
DNP
6
3000
356.0
338.0
48.0
OPT3001IDNPTQ1
USON
DNP
6
250
193.0
193.0
70.0
Pack Materials-Page 2
PACKAGE OUTLINE
USON - 0.65 mm mm max height
DNP0006A
PLASTIC SMALL OUTLINE NO-LEAD
2.1
1.9
B
1
A
6
2.1
1.9
PIN 1
INDEX AREA
4
3
C
0.65
0.55
SEATING PLANE
0.08
0.05
0.00
0.65±0.1
EXPOSED THERMAL
PAD
(0.2) TYP
4
3
2X 1.3
1.35±0.1
4X 0.65
1
6
6X 0.3
0.2
PIN 1 ID
0.1
0.05
6X 0.35
0.25
C A
C
B
4221434/C 01/2018
NOTES:
1.
2.
3.
4.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
Optical package with clear mold compound.
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EXAMPLE BOARD LAYOUT
USON - 0.65 mm mm max height
DNP0006A
PLASTIC SMALL OUTLINE NO-LEAD
SEE DETAILS
(0.65)
6X (0.5)
SYMM
℄
6X (0.25)
6
1
(1.35)
SYMM
℄
(0.8)
4X (0.65)
3
4
(Ø0.2) VIA
TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221434/C 01/2018
NOTES: (continued)
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
EXAMPLE STENCIL DESIGN
USON - 0.65 mm mm max height
DNP0006A
PLASTIC SMALL OUTLINE NO-LEAD
(0.62)
6X (0.5)
SYMM
℄
6X (0.25)
6
1
SYMM
(1.25)
℄
4X (0.65)
3
METAL
TYP
4
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 40X
4221434/C 01/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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