ON NCP6951B Camera pmic with flash led driver Datasheet

NCP6951B
Camera PMIC with Flash
LED Driver
The NCP6951B integrated circuit is part of the ON Semiconductor
mini power management IC family. It is optimized to supply battery
powered portable application sub−systems such as camera function,
microprocessors... etc. This device integrates one high efficiency
600 mA Step−down DCDC converter with DVS (Dynamic Voltage
Scaling), 5 low dropout (LDO) voltage regulators and a 1.5 A Flash
LED driver in WLCSP24 package.
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MARKING
DIAGRAM*
Features
• One Flash LED Driver:
♦
•
•
•
•
•
•
Adaptive boost supply or bypass mode depending on Vin and
Vflash conditions
♦ Programmable flash current from 100 mA to 1.6 A by 100 mA
steps
♦ Programmable safety and inhibit timer to limit the flash duration
and protect the application
One DCDC Converter:
♦ Peak efficiency 96%
♦ Programmable output voltage from 0.8 V to 2.3 V by 50 mV steps
♦ 600 mA output current capability
Five Low Noise − Low Dropout Regulators
♦ Programmable output voltage from 1.7 V to 3.3 V for LDOs 1,2,3
♦ Programmable output voltage from 1.2 V to 2.85 V for LDO 4 & 5
♦ 200 mA output current capability: LDO’s 1, 2, 3 & 4
♦ 300 mA output current capability: LDO 5
♦ 45 mVrms low output noise
Control
♦ 400 kHz / 3.4 MHz I2C control interface
♦ Hardware enable pin
♦ Customizable power up sequencer
Extended Input Voltage Range 2.5 V to 5.5 V
♦ Support of newest battery technologies
Optimized Power Efficiency
♦ 82 mA very low quiescent current at no load
♦ Dynamic voltage scaling on DCDC converter
♦ Regulators can be supplied from DCDC converter output
Small Footprint
♦ Package WLCSP24 2.57 x 1.65 mm2
♦ DCDC converter runs at 3.0 MHz using a 1 mH inductor and
10 mF capacitor or 2.2 mH inductor and 4.7 mF capacitor
Typical Applications
• Cellular Phones
• Digital Cameras
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 0
6951B
AWLYWW
G
WLCSP24
CASE 567JA
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
PIN ASSIGNMENT
PGND2
VOUT3
VOUT2
VIN1
VOUT1
A1
A2
A3
A4
A5
PVIN1
A6
SW2
FLSEL
AGND
SCL
FB1
SW1
B1
B2
B3
B4
B5
B6
SW2
FLEN
AGND
HWEN
SDA
PGND1
C1
C2
C3
C4
C5
C6
VBST
FL
VBG
VOUT4
VIN2
VOUT5
D1
D2
D3
D4
D5
D6
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 34 of
this data sheet.
• Personal Digital Assistant and Portable Media Player
• GPS
1
Publication Order Number:
NCP6951/D
NCP6951B
NCP6951B
VBG
100nF
AGND
DCDC 1
600mA
Core
PVIN1
2.2uF
System Supply
DCDC 1 Out
SW1
FB1
1uH
10uF
PGND1
1.0uF
VIN1
System Supply
System or
DCDC Supply
VOUT1
VIN2
LDO1
200mA
VOUT2
1uF
LDO2
200mA
LDO3
200mA
VOUT3
LDO4
200mA
VOUT4
LDO5
300mA
VOUT 5
HWEN
Enabling
Thermal
Protection
Power Up &
Down
Sequencer
SDA
Processor I @C
System or
DCDC Supply
SCL
I@C
SW2
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
VBST
1uH
4.7uF
PGND 2
Boost
Converter
1 x 22uF 0603 or
2 x 10uF 0402
1.5A LED
Driver
FL
Flash LED Current Select
PA transmit burst, Torch, etc
FLSEL
Flash Enable Signal
FLEN
LED Current
Select
Enabling
Flash LED
Flash
Control
1.5A LED
Driver
Figure 1. Functional Block Diagram
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NCP6951B
Table 1. PIN OUT DESCRIPTION
Pin
Name
Type
Description
VIN1
Power Input
Analog Supply. This pin is the device analog, digital and LDO 1, 2 & 3 supply. A 1.0 mF ceramic
capacitor or larger must bypass this input to ground. This capacitor should be placed as close a
possible to this pin.
Reference Voltage. A 0.1 mF ceramic capacitor must bypass this pin to the ground
POWER
A4
D3
VBG
Analog Input
B3, C3
AGND
Analog Ground
Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
CONTROL AND SERIAL INTERFACE
C4
HWEN
Digital Input
Hardware Enable. Active high will enable the part; there is internal pull down resistor on this pin.
B4
SCL
Digital Input
I2C interface Clock
C5
SDA
Digital
Input/Output
I2C interface Data
DCDC CONVERTER
A6
PVIN1
Power Input
DCDC Power Supply. This pin must be decoupled to ground by a 2.2 mF ceramic capacitor. This
capacitor should be placed as close a possible to this pin .
B6
SW1
Power Output
DCDC Switch Power. This pin connects power transistors to one end of the inductor. Typical application uses 1.0 mH inductor; refer to application section for more information.
B5
FB1
Analog Input
DCDC Feedback Voltage. Must be connected to the output capacitor. This is the input to the error
amplifier.
C6
PGND1
Power Ground
DCDC Power Ground. This pin is the power ground and carries the high switching current. High
quality ground must be provided to prevent noise spikes. To avoid high−density current flow in a
limited PCB track, a local ground plane is recommended.
LDO REGULATORS
A4
VIN1
Power Input
LDO 1, 2 & 3 Power and Core supply (see Power table)
LDO 4 & 5 Power Supply. This pin requires a 1 mF decoupling capacitor.
D5
VIN2
Power Input
A5
VOUT1
Power Output
LDO 1 Output Power. This pin requires a 1 mF decoupling capacitor.
A3
VOUT2
Power Output
LDO 2 Output Power. This pin requires a 1 mF decoupling capacitor.
A2
VOUT3
Power Output
LDO 3 Output Power. This pin requires a 1 mF decoupling capacitor.
D4
VOUT4
Power Output
LDO 4 Output Power. This pin requires a 1 mF decoupling capacitor.
D6
VOUT5
Power Output
LDO 5 Output Power. This pin requires a 1 mF decoupling capacitor.
FLASH LED DRIVER
D1
VBST
Power Output
Flash Led Driver Boost Output. This pin is the output of the boost converter. It requires a 10 mF
decoupling capacitor.
B1, C1
SW2
Power Output
Flash Led Driver Switch Power. This pin connects power transistors to one end of the inductor.
Typical application uses 1.0 mH inductor; refer to application section for more information.
A1
PGND2
Power Ground
Flash Led Driver Power Ground. This pin is the power ground and carries the high switching current. High quality ground must be provided to prevent noise spikes. To avoid high−density current
flow in a limited PCB track, a local ground plane is recommended.
D2
FL
Power Output
Flash Led Driver Output Power. This pin is the output of the current source of the flash LED driver. It needs a flash led to connect.
B2
FLSEL
Logic Input
Flash Led Driver Select Pin. Active high will select the reduced flash level.
C2
FLEN
Logic Input
Flash Led Driver Enable Pin. Active high will enable the flash mode.
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3
NCP6951B
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Analog and power pins: AVIN, PVIN, SW, VIN1, VIN2, VOUT1, VOUT2,
VOUT3, VOUT4, VOUT5, FB, VBG Pins
VA
−0.3 to + 6.0
V
VDG
IDG
−0.3 to VA +0.3 ≤ 6.0
10
V
mA
Storage Temperature Range
TSTG
−65 to + 150
°C
Maximum Junction Temperature
TJMAX
−40 to +150
°C
MSL
Level 1
−
Human Body Model (HBM) ESD Rating (Note 2)
ESDHBM
2000
V
Charged Device Model (CDM) ESD Rating (Note 2)
ESDCDM
1000
V
Digital pins: SCL, SDA, HWEN Pin:
Input Voltage
Input Current
Moisture Sensitivity (Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) per JEDEC standard: JESD22−A114
Charged Device Model (CDM) per JEDEC standard: JESD22−C101.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
VIN1 PVIN
Parameter
Conditions
Min
Typ
Max
Unit
Core Power Supply, DCDC power supply and
LDOs 1, 2 & 3
2.5
5.5
V
LDOs 4 & 5 Input Voltage range
1.7
5.5
V
TA
Ambient Temperature Range
−40
25
+ 85
°C
TJ
Junction Temperature Range (Note 6)
−40
25
+125
°C
RqJA
Thermal Resistance Junction to Case
−
80
−
°C/W
TA = 25°C
−
1250
−
mW
TA = 85°C
−
500
−
mW
2.2
mH
VIN2
PD
L
Power Dissipation Rating (Note 4)
1
Inductor for DCDC converter (Note 4)
10
mF
1
mF
Output Capacitors for VBG
100
nF
Cpvin
Input Capacitor for DCDC Converter (Note 4)
2.2
mF
Cvin1
Input Capacitor for Vin1 (Note 4)
1
mF
Cvin2
Input Capacitor for Vin2 (Note 4)
1
mF
Co
Output Capacitor for DCDC Converter (Note 4)
Output Capacitors for LDO (Note 4)
CBG
VFL
0.65
LED Voltage
Lowest torch setting
IFL = 1 A
IFL = 1 A
2.0
2.8
3.3
V
4.5
4.9
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
4. Refer to the Application Information section of this data sheet for more details.
5. The RqCA is dependent of the PCB heat dissipation. Board used to drive this data was a NCP6951EVB board. It is a multilayer board with
1−ounce internal power and ground planes and 2−ounce copper traces on top and bottom of the board.
6. The maximum power dissipation (PD) is dependent by input voltage, maximum output current and external components selected.
R qJA +
125 * T A
PD
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NCP6951B
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1
= VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are
referenced to TJ = + 25°C and default configuration (Note 9).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DCDC on – no load – no switching
LDOs off
TA = up to +85°C
−
32
−
mA
DCDC on – no load – no switching
LDOs on – no load
TA = up to +85°C
−
80
−
DCDC Off
LDOs on – no load
TA = up to +85°C
−
55
−
−
6.0
−
−
0.7
−
Input Voltage Range
2.5
−
5.5
V
IOUTMAX
Maximum Output Current
0.6
−
−
A
−1
0
SUPPLY CURRENT: Pins VIN1, VIN2, PVIN
IQ
ISLEEP
IOFF
Operating quiescent current
Product sleep mode current
Product off current
mA
HWEN on
All DCDC and LDOs off
VIN = 2.5 V to 5.5 V
TA = up to +85°C
mA
HWEN off
I2C interface disabled
VIN = 2.5 V to 5.5 V
TA = up to +85°C
DCDC CONVERTER
PVIN
DVOUT
Output Voltage DC Error
DCOUT
DCDC Output Voltage
FSW
Switching Frequency
Io=300 mA, PWM mode (Note 9)
Programmable 50 mV steps (Note 9)
0.8
1
%
2.3
V
2.7
3
3.3
MHz
RONHS
P−Channel MOSFET ON Resistance
From PVIN1 to SW1 pins,
Pvin1 = 3.6 V
−
185
−
mW
RONLS
N−Channel MOSFET ON Resistance
From SW1 to PGND1 pins,
Pvin1 = 3.6 V
−
335
−
mW
Peak Inductor Current
Open loop
2.5 V ≤ PVIN ≤ 5.5 V
1.0
1.35
1.7
A
Load Regulation
IOUT from 300 mA to IOUTMAX
−
−0.5
−
%/A
Line Regulation
IOUT = 100 mA
2.5 V ≤ VIN ≤ 5.5 V
−
0
−
%/V
−
100
−
%
−
128
−
7.0
−
W
LDO1, LDO2, LDO3 Input Voltage
Range
2.5
−
5.5
V
IOUTMAX1,2,3
Maximum Output Current
200
−
−
mA
ILIM1,2,3
Output Current Limitation
−
−
500
mA
ISC1,2,3
Short Circuit Protection
−
130
−
mA
Vout1,2,3
Output Voltage
3.3
V
IPK
D
tSTART
RDISDCDC
Maximum Duty Cycle
Soft−Start Time
From HWEN to 90% of Output Voltage (Note 10)
DCDC Active Output Discharge
ms
LDO1, LDO2, LDO3
VIN1
(Note 9)
Programmable, see table. (Note 9)
7. Devices that use non−standard supply voltages which do not conform to the intent
the VDD voltage to which the pull−up resistors RP are connected.
8. Refer to the Application Information section of this data sheet for more details.
9. Guaranteed by design and characterized.
10. Tested in production at VOUT = 2.0 V.
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I2C
1.7
bus system levels must relate their input levels to
NCP6951B
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1
= VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are
referenced to TJ = + 25°C and default configuration (Note 9).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LDO1, LDO2, LDO3
tSTART1
ΔVOUT1,2,3
VDROP
ms
Soft−Start Time
From HWEN to 90% of Output
Voltage (Note 10)
−
128
Output Voltage Accuracy DC
IOUT1,2, 3 = 200 mA
−2
VNOM
+2
%
Load Regulation
IOUT1,2, 3 = 0 mA to 200 mA
−
0.4
−
%
Line Regulation
VIN1 = (Vout + Drop) to 5.5 V
VOUT1,2 = 2.8 V, VOUT3 = 1.8 V
IOUT1,2,3 = 200 mA
−
0.3
−
%
Dropout Voltage
IOUT1,2,3 = 200 mA,
VOUT = 3.3 V − 2%
mV
135
IOUT1,2,3 = 200 mA,
VOUT = 2.8 V − 2%
−
170
270
F = 1 kHz, 100 mV peak to peak
VOUT1,2 = 2.8 V, VOUT3 = 1.8 V
IOUT1,2,3 = 5 mA
−
−70
−
F = 10 kHz, 100 mV peak to peak
VOUT1,2 = 2.8 V, VOUT3 = 1.8 V
IOUT1,2,3 = 5 mA
−
−60
−
10 Hz ³ 100 kHz, 5 mA
VOUT1,2,3 = 2.8 V
−
45
−
mV
−
15
−
W
LDO4 and LDO5 Input Voltage
1.7
−
5.5
V
IOUTMAX4
Maximum Output Current
200
−
−
mA
IOUTMAX5
Maximum Output Current
300
−
−
mA
ILIM4
Output Current Limitation
(Note 9)
−
−
500
mA
ILIM5
Output Current Limitation
(Note 9)
−
−
600
mA
ISC4
Short Circuit Protection
−
130
−
mA
ISC5
Short Circuit Protection
−
180
−
mA
1.2
−
2.85
V
PSRR
Ripple Rejection
Noise
RDISLDO1,2,3
LDO Active Output Discharge
dB
LDO4 and LDO5
VIN2
Vout4,5
LDO 4&5 Output voltage
Programmable, see table. (Note 9)
I2C
ms
tSTART2
Soft−Start Time
Time from
command ACK to
90% of Output Voltage.
−
128
ΔVOUT4
Output Voltage Accuracy
IOUT4 = 200 mA
−2
VNOM
+2
%
ΔVOUT5
Output Voltage Accuracy
IOUT5 = 300 mA
−2
VNOM
+2
%
Load Regulation
IOUT4 = 0 mA to 200 mA
IOUT5 = 0 mA to 300 mA
−
0.4
−
%
Line Regulation
VIN2 = (Vout + Drop) to 5.5 V
VOUT4 = 2.8 V, VOUT5 = 1.8 V
IOUT4 = 200 mA, IOUT5 = 300 mA
−
0.3
−
%
7. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to
the VDD voltage to which the pull−up resistors RP are connected.
8. Refer to the Application Information section of this data sheet for more details.
9. Guaranteed by design and characterized.
10. Tested in production at VOUT = 2.0 V.
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NCP6951B
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1
= VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are
referenced to TJ = + 25°C and default configuration (Note 9).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOUT4 = 200 mA
VOUT4 = 2.8 V − 2%
−
170
270
mV
IOUT5 = 300 mA
VOUT5 = 2.8 V − 2%
−
120
220
LDO4 and LDO5
VDROP
Dropout Voltage
IOUT5 = 300 mA
VOUT5 = 1.8 V − 2%
PSRR
Ripple Rejection
Noise
RDISLDO4,5
250
dB
F = 1 kHz, 100 mV peak to peak
IOUT4= 5 mA, IOUT5= 5 mA
−
−70
−
F = 10 kHz, 100 mV peak to peak
IOUT4,5= 5 mA
−
−60
−
10 Hz ³ 100 kHz, 5 mA
VOUT4,5 = 2.8 V
−
45
−
mV
−
15
−
Ω
LDO 4&5 Active Output Discharge
FLASH LED DRIVER
Input Voltage
Pass through mode
Boost mode
2.8
2.8
5.5
4.5
V
UVLOL
UVLO low threshold
I2C programmable with 150 mV
steps (Note 9)
2.75
3.2
V
UVLOH
UVLO high threshold
I2C programmable with 150 mV
steps (Note 9)
2.9
3.35
V
−50
50
mV
3.0
5.0
V
350
mV
VIN
UVLOacc
VBST
VBST – VFL
UVLO threshold accuracy
Boost output voltage
(Note 9)
Driver headroom
Flash Current
I2C
programmable with 100 mA
steps (Note 9)
100
1600
mA
IFLLOW
Reduced Current
I2C programmable with 100 mA
steps (Note 9)
100
1600
mA
ITORCH
Torch Current
I2C programmable with 33 mA
steps (Note 9)
33
533
mA
IFLACC
Flash Current Accuracy
IFL = 300 mA
8
%
ITORCHACC
Torch Current Accuracy
ITORCH = 100 mA
10
%
Flash Current Slope
Ramp up or down
100/16
mA/ms
Torch Current Slope
Ramp up or down
33/16
mA/ms
PA Burst Blanking Speed
From flash to reduced setting
10
ms
IFL
FSW
Boost Switching Frequency
1.8
2
2.2
MHz
RON_H
High−Side MOSFET ON Resistance
70
mW
RON_L
Low−Side MOSFET ON Resistance
60
mW
I2C programmable with 600 mA
steps (Note 9)
ILIM−BOOST
ICCFL
Short Circuit Detect Threshold
1.8
3.6
1.2
A
V
7. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to
the VDD voltage to which the pull−up resistors RP are connected.
8. Refer to the Application Information section of this data sheet for more details.
9. Guaranteed by design and characterized.
10. Tested in production at VOUT = 2.0 V.
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NCP6951B
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1
= VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are
referenced to TJ = + 25°C and default configuration (Note 9).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.1
−
−
−
V
−
0.4
V
0.1
1
mA
1.7
−
5.0
V
HWEN, FLSEL, FLEN
VIH
High level input Voltage Threshold
VIL
Low level Voltage Threshold
IPD
Logic Pins Pull−down (input bias
current)
I2C
VI2C
Voltage at SCL and SDA line
VI2CIL
SCL, SDA low input voltage
SCL, SDA pin (Note 7)
−
−
0.5
V
VI2CIH
SCL, SDA high input voltage
SCL, SDA pin (Note 7)
0.8xVI2C
−
−
V
VI2COL
SCL, SDA low output voltage
ISINK = 3 mA
−
−
0.4
V
−
−
3.4
MHz
FSCL
I2C
clock frequency
TOTAL DEVICE
VUVLO
Under Voltage Lockout
VIN rising
−
−
2.5
V
VUVLOH
Under Voltage Lockout Hysteresis
VIN falling
60
−
200
mV
Thermal Shut Down Protection
−
150
−
°C
Warning Rising Edge
−
135
−
°C
Thermal Shut Down Hysteresis
−
15
−
°C
TSD
TWARNING
TSDH
7. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to
the VDD voltage to which the pull−up resistors RP are connected.
8. Refer to the Application Information section of this data sheet for more details.
9. Guaranteed by design and characterized.
10. Tested in production at VOUT = 2.0 V.
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NCP6951B
90
90
85
85
80
80
75
EFF (%)
EFF (%)
TYPICAL CHARACTERISTICS
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
Vin = 3.2 V
Vin = 2.9 V
Vin = 2.7 V
Vin = 2.5 V
70
65
60
55
75
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
Vin = 3.2 V
Vin = 2.9 V
Vin = 2.7 V
Vin = 2.5 V
70
65
60
55
50
50
0.1
1
10
100
0.1
1000
1
10
100
1000
IOUT (mA)
IOUT (mA)
Figure 2. DCDC1 Efficiency vs. IOUT (auto
mode) VOUT = 0.8 V
Figure 3. DCDC1 Efficiency vs. IOUT (auto
mode) VOUT = 1.2 V
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NCP6951B
100
100
95
95
90
90
85
85
80
EFF (%)
EFF (%)
TYPICAL CHARACTERISTICS
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
Vin = 3.2 V
Vin = 2.9 V
Vin = 2.7 V
Vin = 2.5 V
75
70
65
60
55
70
60
55
50
0.1
1
10
100
0.1
1000
1
10
100
1000
IOUT (mA)
IOUT (mA)
Figure 4. DCDC1 Efficiency vs. IOUT (auto
mode) VOUT = 1.8 V
Figure 5. DCDC1 Efficiency vs. IOUT (auto
mode) VOUT = 2.3 V
1.0
1.0
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
Vin = 3.3 V
Vin = 3.2 V
Vin = 3.2 V
Vin = 3.0 V
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.9 V
0.5
DCLOAD (%)
0.5
DCLOAD (%)
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.9 V
Vin = 3.6 V
Vin = 3.3 V
Vin = 2.9 V
Vin = 2.7 V
65
50
0
Vin = 3.8 V
Vin = 3.7 V
Vin = 3.6 V
Vin = 3.5 V
0
−0.5
−0.5
−1.0
−1.0
0
50
100
150
200
0
250
50
100
150
200
250
IOUT (mA)
IOUT (mA)
Figure 6. LDO1 Load Regulation (VOUT = 2.8 V)
Figure 7. LDO1 Load Regulation (VOUT = 3.3 V)
1.0
1.0
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
Vin = 2.9 V
Vin = 2.7 V
Vin = 2.5 V
Vin = 2.3 V
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
0.5
DCLOAD (%)
0.5
DCLOAD (%)
80
75
0
Vin = 2.5 V
Vin = 1.9 V
Vin = 1.8 V
Vin = 1.7 V
0
−0.5
−0.5
−1.0
−1.0
0
50
100
150
200
0
250
50
100
150
200
250
IOUT (mA)
IOUT (mA)
Figure 8. LDO1 Load Regulation (VOUT = 1.8 V)
Figure 9. LDO1 Load Regulation (VOUT = 1.2 V)
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10
NCP6951B
TYPICAL CHARACTERISTICS
1.0
250
Vin = 5.5 V
Vin = 5.0 V
Vin = 4.2 V
Vin = 3.6 V
VDROP (mV)
DCLOAD (%)
0.5
LDO1
LDO2
LDO3
Vin = 2.5 V
Vin = 1.9 V
Vin = 1.8 V
Vin = 1.7 V
0
200
150
−0.5
100
−1.0
0
50
100
150
200
250
300
2.5
350
2.6
2.7
2.8
IOUT (mA)
3.0
3.1
3.2
3.3
VOUT SETTING (V)
Figure 10. LDO5 Load Regulation (VOUT = 1.2 V)
Figure 11. Dropout Voltage vs. VOUT, LDO1, 2
& 3 (IOUT = 200 mA)
300
0
LDO1
LDO2
LDO3
LDO4
LDO5
−10
−20
−30
250
PSRR (dB)
VDROP (mV)
2.9
LDO5
LDO4
200
−40
−50
−60
−70
−80
−90
−100
150
1.8 1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
100
2.8
1000
VOUT SETTING (V)
100,000
FREQUENCY (Hz)
Figure 12. Dropout Voltage vs. VOUT, LDO4 & 5
(IOUT = 200 mA for LDO4 and 300 mA for LDO5)
Figure 13. LDOx PSRR (VIN = 3.6 V − VOUT −
1.8 V − IOUT = 5 mA)
100
100
95
90
80
EFFICIENCY (%)
90
EFFICIENCY (%)
10,000
85
80
75
−40°C
25°C
85°C
70
65
70
60
50
40
−40°C
25°C
85°C
30
20
10
0
60
3.2 3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
3.0
3.5
4.0
4.5
5.0
VBAT (V)
VBAT (V)
Figure 14. Flash LED Efficiency vs. Input
Voltage (IFLASH = 700 mA, VIN Falling)
Figure 15. Torch LED Efficiency vs. Input
Voltage (ITORCH = 300 mA, VIN Falling)
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11
5.5
NCP6951B
Detailed Description
capabilities of the device can be exceeded. A thermal
protection circuit is therefore implemented to prevent the
part from damage. This protection circuit is only activated
when the core is in active mode (at least one output channel
is enabled). During thermal shutdown, all outputs of
NCP6951B are off.
When NCP6951B returns from thermal shutdown, it can
re−start in two different configurations depending on
REARM[7:6] bits ($09 register). If REARM[7:6] = 00 then
NCP6951B re−starts with default register values, otherwise
it re−starts with register values set prior to thermal
shutdown.
In addition, a thermal warning is implemented which can
inform the processor through an interrupt that NCP6951B is
close to its thermal shutdown so that preventive action can
be taken by software.
The NCP6951B is optimized to supply the different sub
systems of battery powered portable applications. The IC
can be supplied directly from the latest technology single
cell batteries such as Lithium−Polymer as well as from triple
alkaline cells. Alternatively, the IC can be supplied from a
pre−regulated supply rail in case of multi−cell or mains
powered applications.
The output voltage range, current capabilities and
performance of the switched mode DCDC converter are
well suited to supply the different peripherals in the system
as well as to supply processor cores. To reduce overall power
consumption of the application, Dynamic Voltage Scaling
(DVS) is supported on the DCDC converter. For PWM
operation, the converter runs on a local 3 MHz clock. A low
power PFM mode is provided that ensures that even at low
loads high efficiency can be obtained. All the switching
components are integrated including the compensation
networks and synchronous rectifier. Small sized 1 mH
inductor and 10 mF bypass capacitor are required for typical
applications.
The general purpose low dropout regulators can be used
to supply the lower power rails in the application. To
improve on overall application standby current, the bias
current of these regulators are made very low. The regulators
have two separated input supply pin to be able to connect
them independently to either the system supply voltage or to
the output of the DCDC converter in the application. The
regulators are bypassed with a small size 1.0 mF capacitor.
The IC is controlled through the I2C interface that allows
to program amongst others the output voltages of the
different supply rails as well as to configure its behavior. In
addition to this bus, a digital hardware enable control pin
(HWEN) is provided.
Active Output Discharge
By default, to prevent any disturbances on power−up
sequence, output discharge is activated as soon as the input
voltage is valid (upper than UVLO+ hyst).
After power up sequence and during ON state, output
discharge can be independently enabled / disabled by
appropriate settings in the DIS register (refer to the register
definition section).
If a power down sequence, UVLO or thermal shutdown
events occurs, the output discharge paths are activated until
the next PUS and ON state.
When the IC is turned off when VIN1 drops down below
UVLO threshold, no shut down sequence is expected, all
supplies are disabled and outputs turn to high impedance.
Enabling
The HWEN pin controls the device start up. If HWEN is
raised, this starts the power up sequencer (PUS). If HWEN
is made low, device enters in shutdown mode and all
regulators will be turned off with inverted PUS of power up.
A built−in pull−down resistor disables the device if this
pin is left unconnected.
When HWEN is high, the different power rails can be
independently enabled / disabled by writing the appropriate
bit in the ENABLE register.
Under Voltage Lockout
The core does not operate for voltages below the under
voltage lockout (UVLO) threshold and all internal circuitry,
both analog and digital, is held in reset.
NCP6951B functionality is guaranteed down to VUVLO
when the battery is falling. A hysteresis is implemented to
avoid erratic on / off behavior of the IC. Due to its 200 mV
hysteresis, when the battery is rising, re−start is guaranteed
at 2.5 V.
Power Up Sequence and HWEN
When enabling part with HWEN pin, the part will be set
with the default configuration factory programmed in the
registers, if no I2C programming has been done as described
in the below table.
Thermal Shutdown
Given the output power capabilities of the on chip step
down converters and low drop out regulators the thermal
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12
NCP6951B
Table 5. DEFAULT POWER UP SEQUENCER
Delay (in ms) from Tstart
Sequence
Default Assignment
Default Vprog
Default Mode and ON/OFF
128
To: 000
DCDC
1.20 V
Auto PFM/PWM
OFF
256
T1: 001
LDO1
2.80 V
OFF
384
T2: 010
LDO2
2.80 V
OFF
512
T3: 011
LDO3
1.80 V
OFF
640
T4: 100
LDO4
2.80 V
OFF
768
T5: 101
LDO5
1.80 V
OFF
NOTE:
Additional power sequence are available. Please contact your ON representative for further information.
In order to power up the circuit, the input voltage VIN1
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up including:
• Internal references
• Core circuitry “Wake Up Time”
• DCDC “Bias Time”
These delays are internals and cannot be bypassed.
As the default configuration factory is programmed with
disable state for the DCDC and LDOs, an I2C access must
be done at the end of the bias time to enable the supplies.
In addition a user programmable delay will also take place
between end of Core circuitry turn on (Bias time) and Start
up time: The PowerSupplies_T[2..0] bits of TIME register
will set this user programmable delay with a 128 ms
resolution (note: please contact your ON Semiconductor
representative for additional resolution options). The output
discharge of the DCDC and LDOs are done during this time
slot. NOTE: During the Bias time, the I2C interface is not
active during the first 50 ms. Any I2C request to the IC during
this time period will result in a NACK reply.
However, I2C registers can be read and written while
HWEN pin is still low (except blanking time of 50 ms
typical). By programming the appropriate registers (see
registers description section), the power up sequence default
can be modified and set upon requirements (please contact
your ON Semiconductor representative for additional PUS
options)
Figure 16. IPUS
The initial power up sequence (IPUS) is described in
Figure 16.
VIN1, VIN2
UVLO
POR
HWEN
O
F
F
VOUT DCDC
600 us
typ
(DCDC_T[2:0] + 1) x
128 μs*
M
O
DVS ramp
Time
VOUT LDOx D
E
(LDOx_T[2:0] + 1) x
128 μs*
Bias
Time
128 us
Soft start90%
I@C
Figure 17. IPUS
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13
NCP6951B
DCDC Converter
VIN1, VIN2
The converter can operate in two modes: PWM mode and
PFM mode. In PWM mode the converter operates at a fixed
frequency and adapts its duty cycle to regulate to the desired
output voltage. The advantage of this mode is that the EMI
noise is predictable. However, at lower loadings the
efficiency is degraded. In PFM mode some switching pulses
are skipped to control the output voltage. This allows
maintaining high efficiency even at low loadings. In
addition, no high frequency clock is required which
provides additional current savings. The switchover point
between both modes is chosen depending on the supply
conditions such that highest efficiency is obtained over the
entire load range.
The switch over between PWM/PFM modes can occur
automatically but the switcher can be set in auto switching
mode PFM / PWM by I2C programming.
A soft start is provided to limit inrush currents when
enabling the converters. The soft start consists of ramping
gradually the reference to the switcher.
Additional current limitation is provided by a peak current
limiter that monitors and limits the current through the
inductor.
DCDC converter output voltage can be set by I2C
MODEDCDC bit is used to program switcher mode
control.
UVLO
POR
HWEN
(DCDC_T[2:0] + 1) x
128 μs*
S
L
E
E
P
VOUT DCDC
O
F
F
VOUT LDOx
M
O
D
E
M
O
D
E
DVS ramp
Time
70
us
typ
(LDOx_T[2:0] + 1) x
128 μs*
Soft start90%
600μs Bias
min Time
I@C
128 us
Ì
Figure 18. Sleep Mode PUS (SMPUS)
A third turn on sequence is also available by I2C. Indeed
each power supply can be turn off/on through I2C register.
In this case no biasing time is required except for DCDC bias
time (32 ms typical).
VIN1, VIN2
UVLO
POR
Table 6. MODEDCDC BIT DESCRIPTION
HWEN
MODEDCDC
DCDC Mode Control
0
Mode is auto switching PFM / PWM (default)
1
Mode is PWM only
VOUT DCDC
Bias time
32μs
DVS ramp
Time
VOUT LDOx
Dynamic Voltage Scaling (DVS)
Soft start 90%
Step down converters support dynamic voltage scaling
(DVS). This means the output voltage can be reprogrammed
based upon I2C commands to provide the different voltages
required by the processor. The change between set points is
managed in a smooth manner without disturbing the
operation of the processor.
When programming a higher voltage, the reference of the
switcher and therefore the output is raised in 50 mV/ 2.67 ms
(default) steps such that the dV/dt is controlled. When
programming a lower voltage the output voltage will
decrease based on the output capacitor value and the load.
The DVS system makes sure that the voltage ramp down will
not exceed the steps settings.
128 us
LDOx,
DCDC
OFF/
ON
I@C
Figure 19. ON Mode PUS (OPUS)
Shutdown by HWEN
When HWEN is tied low, all supplies are disabled with
reverted turn on sequence detailed in default Power Up
Sequencer table. If different turn off sequence is required, a
different programming can be done by I2C.
V2
Internal
Reference
Output
Voltage
nV
nt
Figure 20. Dynamic Voltage Scaling Effect Timing
Figure 21. DVS Figure
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14
NCP6951B
Programmability
Individual bits generating interrupts will be set to 1 in the
INT_ACK register (I2C read only register), indicating the
interrupt source. INT_ACK register is reset by an I2C read.
INT_SEN registers (read only registers) are real time
indicators of interrupt sources.
DCDC converter has two different output voltages
programmed by default in the DCDC_V1 and V2 bank. The
DCDC output voltage can be changed from V1 to V2 with
the DCDC_V2/V1 bit in $08 register.
Table 7. DCDC_V2/1 BIT DESCRIPTION
DCDC_V2/1
Force Register Reset
Bit Description
0
Output voltage is set to DCDC_V2
1
Output voltage is set to DCDC_V1(Default)
•
•
•
The two DVS bits in register TIME determine ramp up
time per each voltage step.
Flash LED Driver
Table 8. DVS BIT DESCRIPTION
DVS [0]
NCP6951B includes an adaptive boost converter with an
high side current source allowing the use of a thermally
grounded flash LED.
Flash LED driver has two mains operating modes: flash
mode and torch mode which is controlled thru the I2C
interface and the FLEN and FLSEL pins.
Bit Description
0
2.67 ms per step (default)
1
10.67 ms per step
DCDC Step Down Converter and LDOs End of Turn On
Sequence
Adaptive Boost − Bypass Converter
To indicate the end of the power up sequence, a power
good sense bit is available at the $0A address. (SEN_PG).
Sense bit is set to 0 during power up sequence and 16 x
digital clock (128’s by default). The Power good sense bit is
released to 1 after this sequence and trig ACK_PG interrupt.
The interrupt is reset by a read or HWEN.
NCP6951B includes an adaptive boost−bypass converter
to optimize the efficiency of the flash LED driver. The
boost−bypass converter monitors the flash LED voltage and
the battery voltage.
When VBST < VFL + 250 mV, the adaptive boost−bypass
converter operates in boost mode and regulates VBST = VFL
+ 275 mV.
When VBAT ≥ VFL + 540 mV, the adaptive boost−bypass
converter operates in bypass mode and VBST = VBAT.
Boost Mode
The adaptive boost−bypass converter implements an
architecture allowing the device to operate in Continuous
Conduction Mode (CCM) and Discontinuous Conduction
Mode (DCM).
The adaptive boost−bypass converter operates in DCM in
order to save power and improve efficiency at low loads by
reducing the switching frequency. When current in the
inductor becomes continuous, the controller automatically
turns to CCM mode and goes back in DCM when current in
the inductor is discontinuous.
Bypass Mode
The adaptive boost−bypass converter has been designed
to manage conditions for which VBAT becomes close to VFL
+ 275 mV. In that case the adaptive boost−bypass converter
enters automatically in bypass mode from boost mode. The
VBST voltage is the copy of the input voltage minus a
dropout voltage resulting from the resistance of the internal
P−MOSFET plus the inductor.
Figure 22. Power Good Behavior
Interrupt
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual edge monitoring).
The interrupt sources include:
Table 9. INTERRUPT SOURCES
Register
$0B
UVLO
Under voltage threshold
PUS
End of power up sequence
WNRG
Thermal warning
TSD
Thermal shutdown
The I2C registers are reset when the part is in Off Mode:
Vin<UVLO or
I2C and HWEN not present or
Restart from TSD event (REARM_ TSD[7:6]=00,
register $09)
Timeout Description
NCP6951B includes 2 timers which help to prevent any
damage to the part due to too high flash duration or too close
consecutive flash.
The 3 bits SAFETY_TIMER[2:0] set a maximum flash
duration from 32 ms to 1024 ms.
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15
NCP6951B
Low Battery Voltage Adaptive mode:
2 thresholds can be programmed thru I2C to reduce the
flash current in case the battery voltage is too low.
When Vin goes below UVLO_High, the NCP6951B try to
recover by decreasing the current down to I reduced, and
then increase it up to the IFL FAULT – 1.
The 4 bits INHIBIT_TIMER[3:0] register set a minimum
off time duration after the flash from 0 to 7680 ms.
When FLEN is going high, SAFETY_TIMER is started
and the flash current source is turn off if FLEN pin is not
pulling down before the end of the timer. The timer is reset
when FLEN is going low.
After a flash pulse, the flash current source can remain
disabled for a guaranteed off period and as such will ignore
the state of the FLEN pin.
FLEN
Nfault
Nfault – 1
Nfault – 2
Nfault – 3
I_LED
Timeout
I REDUCED
Safety
Timer
I FLASH or
I TORCH
Inhibit
Timer
VIN
UVLO _H
FL_EN
Valid Flash
Inhibit Timer prevents Flash
Flash duration limited by Safety Timer
t
Figure 23. Battery Voltage Adaptive Mode Behavior
debounce
Figure 25. Battery Voltage Adaptive Mode Behavior
PA Burst Blanking
When Vin goes below UVLO low, flash current is
stopped.
Low Battery Voltage Reduce mode:
2 thresholds can be programmed thru I2C to reduce the
flash current in case the battery voltage is too low.
When Vin goes below UVLO_High, I flash is decreased
down to I reduced.
When Vin goes below UVLO low, flash current is
stopped.
When the flash is enabled and the FLSEL pin being pulled
high, the reduced flash LED current is selected. Normally
the reduced LED current level is programmed much lower
than the flash LED current so that FLSEL high selects the
reduced level. A dedicated bit is available to invert the
polarity of the FLSEL pin.
During PA burst blanking, the transition to the lower
current is instantaneity. The transition to the higher current
follow the ramp time set in the FLASH_SETTING register.
V_IN
V_IN
Undervoltage High
Undervoltage Low
PA Burst
I_LED
Normal Flash Level
Normal Flash Level
Disable
Operation
I_LED
Reduced Flash Level
Reduced Flash Level
Disabled
FL_EN
FL_SEL
Figure 26. Battery Voltage Reduce Mode Behavior
FL_EN
The die temperature is also permanently monitored. And
2 different behaviors can also be set with the
die_temp_mode bit.
Figure 24. Battery Voltage Adaptive Mode Behavior
Low Battery Protection and Die Temperature
Management in Flash Mode
The battery voltage is permanently monitored. 2 different
behaviors can be set with the battery_voltage_mode bit.
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16
NCP6951B
Die Temperature Management Adaptative mode:
(FLEN = 0 || Timeout ) && /TSD high
&& /UVLO _L
0A
UVLO _L || TSD High
FLEN = 1 && /
TSD high && /
UVLO _L
UVLO _H || TSD Low
I FLASH
UVLO _L || TSD
High
I REDUCED
FLEN = 0 ||
Timeout
FLEN
POR
Nfault
FLASH
ready
FLEN = 0 || Timeout
Nfault – 1
Nfault – 2
Bit FLASH _EN
UVLO _L || TSD
High
/UVLO _H
I = I FLASH
Startup
Nfault – 3
IFL= IFL
fault – 1
Ramp I up to
I FLASH
FLEN = 0 || Timeout
I REDUCED
Low battery adaptative
mode and die temperature
management reduce mode
I FLASH
135 °C
125 °C
T°
Figure 30. State Machine Battery Voltage Adaptative
Mode and Die Temperature Reduce Mode
Figure 27. Die Temperature Adaptative Mode
Behavior
(FLEN = 0 || Timeout ) && /TSD high
&& /UVLO _L
0A
UVLO _L || TSD High
Die Temperature Management Reduce mode:
FLEN = 1 && /
TSD high && /
UVLO _L
UVLO _H || TSD Low
I FLASH
UVLO _L || TSD
High
I REDUCED
FLEN = 0 ||
Timeout
High (145°C)
POR
Low (135°C)
FLASH
ready
FLEN = 0 || Timeout
Warning (125°C)
Bit FLASH _EN
FLEN = 0 || Timeout
UVLO _L || TSD
High
/TSD Low
I = I FLASH
Startup
IFL= IFL
fault – 1
Ramp I up to
I FLASH
Low battery reduce mode
and die temperature
management adaptative
mode
Normal
Figure 31. State Machine Battery Voltage Reduce
Mode and Die Temperature Adaptative Mode
Reduced
Disabled
Figure 28. Die Temperature Reduce Mode Behavior
(FLEN = 0 || Timeout ) && /TSD high
&& /UVLO _L
The following state machine describe the behavior of the
part with the combination of the 4 monitoring modes:
0A
UVLO _L || TSD High
FLEN = 1 && /
TSD high && /
UVLO _L
UVLO _H || TSD Low
I FLASH
UVLO _L || TSD
High
I REDUCED
FLEN = 0 ||
Timeout
(FLEN = 0 || Timeout ) && /TSD high
&& /UVLO _L
POR
FLASH
ready
FLEN = 0 || Timeout
0A
UVLO _L || TSD High
FLEN = 1 && /
TSD high && /
UVLO _L
UVLO _L || TSD
High
Bit FLASH _EN
I REDUCED
FLEN = 0 ||
Timeout
POR
Startup
UVLO _H || TSD Low
I FLASH
FLASH
ready
Low battery reduce mode
and die temperature
management reduce mode
FLEN = 0 || Timeout
I = I FLASH
Startup
Bit FLASH _EN
FLEN = 0 || Timeout
/UVLO _H && /
TSD Low
Figure 32. State Machine Battery Voltage Mode and
Die Temperature Reduce Mode
UVLO _L || TSD
High
IFL= IFL
fault – 1
Ramp I up to
I FLASH
Low battery adaptative
mode and die temperature
management adaptative
mode
Figure 29. State Machine Battery Voltage and Die
Temperature Adaptative Mode
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17
NCP6951B
Low Battery Protection in Torch Mode
RED_EYE register. The user has only to send the sequence
with the FLEN pin. A time out can be activated (2 s) in case
a FL_EN pulse is not sent after the first pulse to reset the
function.
In case of torch mode, when UVLO_L threshold is
reached, the torch current is set to 0 mA and the UVLO flag
is set. NCP6951B recovers its torch current when Vin reach
UVLO_H if the TORCH_RETRY bit is set.
Normal Flash Level
Preflash Level
V_IN
Undervoltage High
I_LED
Undervoltage Low
I_LED
Torch Level
Disable Operation
I_LED
Disabled
FL_EN
Torch Level
Retry Operation
Disabled
Set for up to 3 Pre
Flashes, set duration,
set the Preflash Level
Torch
Enable
Figure 34. Anti Red−eye Behavior
I2C Compatible Interface
Figure 33. Battery Voltage Reduce Mode Behavior
NCP6951B can support a subset of I2C protocol, below
are detailed introduction for I2C programming.
Anti Red−eye Function
I2C Communication Description
NCP6951B includes an anti red−eye function. Pre−flash
level and number of pre−flash pulses can be set thru the
ON Semiconductor communication protocol is a subset of
I2C protocol.
Figure 35. General Protocol Description
• In case of read operation, the NCP6951B will output
The first byte transmitted is the Chip address (with LSB
bit sets to 1 for a read operation, or sets to 0 for a Write
operation). Then the following data will be:
• In case of a Write operation, the register address
(@REG) we want to write in followed by the data we
will write in the chip. The writing process is
incremental. So the first data will be written in @REG,
the second one in @REG + 1... The data are optional.
the data out from the last register that has been accessed
by the last write operation. Like writing process,
reading process is an incremental process.
Read Out from Part
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
then start or a Repeated Start will initiate the read transaction
from the register address the initial write transaction has set:
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18
NCP6951B
Figure 36. Read Out from Part
The first WRITE sequence will set the internal pointer on the register we want access to. Then the read transaction will start
at the address the write transaction has initiated.
Transaction with Real Write then Read
1. With Stop Then Start
Figure 37. Write Followed by Read Transaction
Write in Part
Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register
we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2,..., Reg +n.
Write n Registers:
Figure 38. Write in N Registers
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NCP6951B
I2C Address
NCP6951B has fixed I2C but different I2C address (by default $10, 7 bit address, see below table A7~A1), NCP6951B
supports 7−bit address only.
Table 10. NCP6951B I2C ADDRESS
I2C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0 (Default)
W $20 /R $21
0
0
1
0
0
0
0
X
ADDRESS
$10
0
0
1
0
0
0
0
−
Different default address is available upon request
Register Map
Following register map describes I2C registers.
Registers can be:
Reserved
Address is reserved and register is not physically designed
Spare
Address is reserved and register is physically designed
Table 11. REGISTERS SUMMARY
Address
Register Name
Type
Default
Function
$00
GENERAL_SETTINGS
RW
$00
DVS control Settings
$01
LDO1_SETTINGS
RW
$39
LDO1 register settings
$02
LDO2_SETTINGS
RW
$59
LDO2 register settings
$03
LDO3_SETTINGS
RW
$6C
LDO3 register settings
$04
LDO4_SETTINGS
RW
$9E
LDO4 register settings
$05
LDO5_SETTINGS
RW
$B1
LDO5 register settings
$06
DCDC_SETTINGS1
RW
$09
DCDC register settings 1
$07
DCDC_SETTINGS2
RW
$07
DCDC register settings 2
$08
ENABLE
RW
$80
Enable and DVS register settings
$09
PULLDOWN
RW
$3F
Active discharge and rearming register
$0A
STATUS
R
$04
Status or sense register
$0B
INTERRUPT_ACK
RC
$00
Interrupt register
$0C
FLASH_SETTING
RW
$1F
Flash current register
$0D
REDUCED_CURRENT
RW
$00
Reduced current register
$0E
TORCH_CURRENT
RW
$00
Torch current register
$0F
PROTECTION
RW
$20
Boost peak inductor current and UVLO register
$10
FLASH_TIMER
RW
$13
Safety timer register
$11
RED_EYE
RW
$43
Red eye register
$12
FLASH_CONFIGURATION
RW
$08
Flash configuration register
$13
FLASH_ENABLE
RW
$00
Flash enable register
$14
FLASH_STATUS
RC
$00
Flash status register
$15 to $FF
−
−
−
Reserved. Do not access to those registers
Details of the registers are in the following section.
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NCP6951B
Registers Description
Table 12. GENERAL_SETTINGS REGISTER
Name: GENERAL_SETTINGS
Address: $00
Type: RW
Default: $00
D7
D6
D5
D4
D3
D2
D1
D0
spare=0
spare=0
spare=0
DVS
spare=0
spare=0
spare=0
spare=0
D1
D0
Table 13. BIT DESCRIPTION OF GENERAL_SETTINGS REGISTER
Bit
Bit Description
DVS[0]
Ramp up time per voltage step
Table 14. LDO1_SETTINGS REGISTER
Name: LDO1_SETTINGS
Address: $01
Type: RW
D7
Default: $39
D6
D5
LDO1_T [2:0]
D4
D3
D2
LDO1_V[4:0]
Table 15. BIT DESCRIPTION OF LDO1_SETTINGS REGISTER
Bit
Bit Description
LDO1_V[4:0]
LDO1 output voltage setting, refer to Table 17
LDO1_T[2:0]
LDO1 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO1 startup
Delay time = (LDO1_T[2:0] + 1) * 128 ms
NOTE:
64 ms, 128 ms, 1ms, 2 ms OTP options (128 ms default value)
Table 16. LDO2_SETTINGS REGISTER
Name: LDO2_SETTINGS
Address: $02
Type: RW
Default: $59
D7
D6
D5
LDO2_T [2:0]
D4
D3
D2
D1
D0
LDO2_V[4:0]
Table 17. BIT DESCRIPTION OF LDO2_SETTINGS REGISTER
Bit
Bit Description
LDO2_V[4:0]
LDO2 output voltage setting, refer to Table 17
LDO2_T[2:0]
LDO2 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO2 startup
Delay time = (LDO2_T[2:0] + 1) * 128 ms
Table 18. LDO3_SETTINGS REGISTER
Name: LDO3_SETTINGS
Address: $03
Type: RW
D7
LDO3_T [2:0]
Default: $6C
D6
D5
D4
D3
D2
D1
D0
LDO3_V[4:0]
Table 19. BIT DESCRIPTION OF LDO3_SETTINGS REGISTER
Bit
Bit Description
LDO3_V[4:0]
LDO3 output voltage setting, refer to Table 17
LDO3_T[2:0]
LDO3 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO3 startup
Delay time = (LDO3_T[2:0] + 1) * 128 ms
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NCP6951B
Table 20. LDO1_V[4:0], LDO2_V[4:0], LDO3_V[4:0] SETTING TABLE
Register
Vout(V)
Register
Vout(V)
Register
Vout(V)
Register
Vout(V)
00000
1.70
01000
1.70
10000
2.10
11000
2.75
00001
1.70
01001
1.70
10001
2.20
11001
2.80
00010
1.70
01010
1.70
10010
2.30
11010
2.85
00011
1.70
01011
1.75
10011
2.40
11011
2.90
00100
1.70
01100
1.80
10100
2.50
11100
2.95
00101
1.70
01101
1.85
10101
2.60
11101
3.00
00110
1.70
01110
1.90
10110
2.65
11110
3.10
00111
1.70
01111
2.00
10111
2.70
11111
3.30
D2
D1
D0
Table 21. LDO4_SETTINGS REGISTER
Name: LDO4_SETTINGS
Address: $04
Type: RW
Default: $9E
D7
D6
D5
LDO4_T [2:0]
D4
D3
LDO4_V[4:0]
Table 22. BIT DESCRIPTION OF LDO4_SETTINGS REGISTER
Bit
Bit Description
LDO4_V[4:0]
LDO4 output voltage setting, refer to Table 22
LDO4_T[2:0]
LDO4 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO4 startup
Delay time = (LDO4_T[2:0] + 1) * 128 ms
Table 23. LDO5_SETTINGS REGISTER
Name: LDO5_SETTINGS
Address: $05
Type: RW
Default: $B1
D7
D6
D5
LDO5_T [2:0]
D4
D3
D2
D1
D0
LDO5_V[4:0]
Table 24. BIT DESCRIPTION OF LDO5_SETTINGS REGISTER
Bit
Bit Description
LDO5_V[4:0]
LDO5 output voltage setting, refer to Table 22
LDO5_T[2:0]
LDO5 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO5 startup
Delay time = (LDO5_T[2:0] + 1) * 128 ms
Table 25. LDO4_V[4:0], LDO5_V[4:0] SETTING TABLE
Register
Vout(V)
Register
Vout(V)
Register
Vout(V)
Register
Vout(V)
00000
1.20
01000
1.35
10000
1.75
11000
2.40
00001
1.20
01001
1.40
10001
1.80
11001
2.50
00010
1.20
01010
1.45
10010
1.85
11010
2.60
00011
1.20
01011
1.50
10011
1.90
11011
2.65
00100
1.20
01100
1.55
10100
2.00
11100
2.70
00101
1.20
01101
1.60
10101
2.10
11101
2.75
00110
1.25
01110
1.65
10110
2.20
11110
2.80
00111
1.30
01111
1.70
10111
2.30
11111
2.85
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NCP6951B
Table 26. DCDC_SETTINGS1 REGISTER
Name: DCDC_SETTINGS1
Address: $06
Type: RW
Default: $09
D7
D6
D5
DCDC_T[2:0]
D4
D3
D2
D1
D0
DCDC_V1[4:0]
Table 27. BIT DESCRIPTION OF DCDC_SETTINGS1 REGISTER
Bit
Bit Description
DCDC_V1[4:0]
DCDC output voltage setting 1, refer to Table 26
DCDC_T[2:0]
DCDC startup delay time setting (delay time between HWEN transitions from LOW to High and DCDC startup
Delay time = (DCDC_T[2:0] + 1) * 128 ms
Table 28. DCDC_SETTINGS2 REGISTER
Name: DCDC_SETTINGS2
Address: $07
Type: RW
Default: $07
D7
D6
D5
spare=0
spare=0
MODEDCDC
D4
D3
D2
D1
D0
DCDC_V2[4:0]
Table 29. BIT DESCRIPTION OF DCDC_SETTINGS2 REGISTER
Bit
Bit Description
DCDC_V2[4:0]
DCDC output voltage setting 2, refer to Table 26
MODEDCDC
DCDC Operating Mode
0: Auto switching PFM / PWM (default)
1: Forced PWM
Table 30. DCDC_Vx[4:0] SETTING TABLE
DCDC_V1/2
Vout(V)
DCDC_V1/2
Vout(V)
DCDC_V1/2
Vout(V)
DCDC_V1/2
Vout(V)
00000
0.80V
01000
1.15V
10000
1.55V
11000
1.95V
00001
0.80V
01001 (V1)*
1.20V
10001
1.60V
11001
2.00V
00010
0.85V
01010
1.25V
10010
1.65V
11010
2.05V
00011
0.90V
01011
1.30V
10011
1.70V
11011
2.10V
00100
0.95V
01100
1.35V
10100
1.75V
11100
2.15V
00101
1.00V
01101
1.40V
10101
1.80V
11101
2.20V
00110
1.05V
01110
1.45V
10110
1.85V
11110
2.25V
00111
1.10V
01111 (V2)
1.50V
10111
1.90V
11111
2.30V
*Default value: V1
Table 31. ENABLE REGISTER
Name: ENABLE
Address: $08
Type: RW
Default: $80
D7
D6
D5
D4
D3
D2
D1
D0
DCDC_V2/V1
spare=0
DCDC_ EN
LDO5_ EN
LDO4_ EN
LDO3_ EN
LDO2_ EN
LDO1_ EN
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NCP6951B
Table 32. BIT DESCRIPTION OF ENABLE REGISTER
Bit
Bit Description
DCDC_V2/V1
DCDC output voltage setting
0: DCDC converter output voltage is set to DCDC_V2
1: DCDC converter output voltage is set to DCDC_V1
DCDC_ EN
DCDC Enabling
0: Disabled
1: Enabled
LDO5_ EN
LDO5 Enabling
0: Disabled
1: Enabled
LDO4_ EN
LDO4 Enabling
0: Disabled
1: Enabled
LDO3_ EN
LDO3 Enabling
0: Disabled
1: Enabled
LDO2_ EN
LDO2 Enabling
0: Disabled
1: Enabled
LDO1_ EN
LDO1 Enabling
0: Disabled
1: Enabled
Table 33. PULLDOWN REGISTER
Name: PULLDOWN
Address: $09
Type: RW
Default: $3F
D7
D6
D5
D4
D3
D2
D1
D0
REARM_ TSD[7]
REARM_TSD[7]
REARM_
TSD[6]
DCDC_
PULLDOWN
LDO5_
PULLDOWN
LDO4_
PULLDOWN
LDO3_
PULLDOWN
LDO2_
PULLDOWN
LDO1_
PULLDOWN
Table 34. BIT DESCRIPTION OF PULLDOWN REGISTER
Bit
Bit Description
REARM_ TSD[7:6]
Device Rearming after Thermal Shut Down
11: N/A
10: No re−arming after TSD
01: Re−arming active after TSD with no reset of I2C registers: new power−up sequence is initiated with
I2C registers values.
00: Re−arming active after TSD with reset of I2C registers: new power−up sequence is initiated with default I2C registers values (default).
DCDC_ PULLDOWN
DCDC active output discharge
0: Disabled
1: Enabled
LDO5_ PULLDOWN
LDO5 active output discharge
0: Disabled
1: Enabled
LDO4_ PULLDOWN
LDO4 active output discharge
0: Disabled
1: Enabled
LDO3_ PULLDOWN
LDO3 active output discharge
0: Disabled
1: Enabled
LDO2_ PULLDOWN
LDO2 active output discharge
0: Disabled
1: Enabled
LDO1_ PULLDOWN
LDO1 active output discharge
0: Disabled
1: Enabled
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NCP6951B
Table 35. STATUS REGISTER
Name: STATUS
Address: $0A
Type: R
Default: $04
D7
D6
D5
D4
D3
D2
D1
D0
spare=0
spare=0
spare=0
spare=0
SEN_UVLO
SEN_/PUS
SEN_TSD
SEN_WNRG
Table 36. BIT DESCRIPTION OF STATUS REGISTER
Bit
Bit Description
SEN_UVLO
UVLO sense
0: Input voltage is higher than (UVLO + hyst) threshold.
1: Input voltage is lower than (UVLO) threshold.
SEN_PUS
Power up sequence
0: Power up sequence on going
1: Power up sequence finished or HWEN is low
SEN_TSD
Thermal Shut Down sense
0: IC temperature is below TSD threshold
1: IC temperature is over TSD threshold
SEN_WNRG
Thermal warning sense
0: IC temperature is below Thermal Warning threshold
1: IC temperature is over Thermal Warning threshold
Table 37. INTERRUPT_ACK REGISTER
Name: INTERRUPT_ACK
Address: $0B
Type: RC
Default: $00
D7
D6
D5
D4
D3
D2
D1
D0
spare=0
spare=0
spare=0
spare=0
ACK_UVLO
ACK_PUS
ACK_TSD
ACK_WNRG
D1
D0
Table 38. BIT DESCRIPTION OF INTERRUPT_ACK REGISTER
Bit
Bit Description
ACK_UVLO
UVLO sense acknowledge
0: Cleared
1: SEN_UVLO Dual edge triggered interrupt
ACK_PUS
Power up sequence sense acknowledge
0: Cleared
1: SEN_PUS Rising edge triggered interrupt
ACK_TSD
Thermal Shut Down sense acknowledge
0: Cleared
1: SEN_TSD Dual edge triggered interrupt
ACK_WNRG
Thermal warning sense acknowledge
0: Cleared
1: SEN_WNRG Dual edge triggered interrupt
NOTE:
SEN_PUS rising edge appears (16) x 128 ms (default) after HWEN rising edge.
Table 39. FLASH_SETTING REGISTER
Name: FLASH_CURRENT
Address: $0C
Type: RW
Default: $1F
D7
Spare = 0
D6
D5
D4
D3
FLASH_TR[1:0]
D2
FLASH_CURRENT[4:0]
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NCP6951B
Table 40. BIT DESCRIPTION OF FLASH_SETTING
REGISTER
Bit
Bit Description
FLASH_CURRENT[4:0]
Defines the flash current.
FLASH_TR[1:0]
Defines the flash ramp time.
Table 41. BIT DESCRIPTION OF FLASH_CURRENT[4:0]
Register Value
FLASH_CURRENT[4:0] (mA)
Register Value
FLASH_CURRENT[4:0] (mA)
00000
100
10000
800
00001
133
10001
900
00010
166
10010
1000
00011
200
10011
1100
00100
233
10100
1200
00101
266
10101
1300
00110
300
10110
1400
00111
333
10111
1500
01000
366
11000
1600
01001
400
11001
1600
01010
433
11010
1600
01011
466
11011
1600
01100
500
11100
1600
01101
533
11101
1600
01110
600
11110
1600
01111
700
11111
1600
Table 42. BIT DESCRIPTION OF FLASH_TR[1:0]
Register Value
FLASH_TR[1:0] (V)
00
100 mA / 16 ms
01
100 mA / 32 ms
10
100 mA / 64 ms
11
100 mA / 128 ms
Table 43. REDUCED_CURRENT REGISTER
Name: FLASH_CURRENT
Address: $0D
Type: RW
Default: $00
D7
D6
D5
D4
Spare = 0
Spare = 0
Spare = 0
Spare = 0
D3
Bit Description
REDUCED_CURRENT[3:0]
Defines the reduced current.
D1
REDUCED_CURRENT[3:0]
Table 44. BIT DESCRIPTION OF
REDUCED_CURRENT REGISTER
Bit
D2
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D0
NCP6951B
Table 45. BIT DESCRIPTION OF
REDUCED_CURRENT[3:0]
Register Value
REDUCED_CURRENT[3:0] (mA)
0000
100
0001
200
0010
300
0011
400
0100
500
0101
600
0110
700
0111
800
1000
900
1001
1000
1010
1100
1011
1200
1100
1300
1101
1400
1110
1500
1111
1600
Table 46. TORCH_CURRENT REGISTER
Name: TORCH_CURRENT
Address: $0E
Type: RW
Default: $00
D7
D6
Spare = 0
Spare = 0
D5
D4
D3
TORCH_TR[1:0]
D1
D0
TORCH_CURRENT[3:0]
Table 47. BIT DESCRIPTION OF TORCH_CURRENT
REGISTER
Bit
D2
Table 49. BIT DESCRIPTION OF
TORCH_CURRENT[3:0]
Bit Description
Register Value
TORCH_CURRENT[3:0] (mA)
TORCH_CURRENT[3:0]
Defines the torch current.
0000
33
TORCH_TR[1:0]
Defines the torch ramp time.
0001
66
0010
100
0011
133
Table 48. BIT DESCRIPTION OF TORCH_TR[1:0]
Register Value
TORCH_TR[1:0] (V)
0100
166
00
33 mA / 64 ms
0101
200
01
33 mA / 128 ms
0110
233
10
33 mA / 256 ms
0111
266
11
33 mA / 512 ms
1000
300
1001
333
1010
366
1011
400
1100
433
1101
466
1110
500
1111
533
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NCP6951B
Table 50. PROTECTION REGISTER
Name: UVLO
Address: $0F
Type: RW
Default: $20
D7
D6
D5
Spare = 0
Spare = 0
D4
D3
ILIM[1:0]
UVLO_HIGH[1:0]
Table 51. BIT DESCRIPTION OF PROTECTION
REGISTER
Bit
D2
D1
D0
UVLO_LOW[1:0]
Table 53. BIT DESCRIPTION OF UVLO_HIGH[1:0]
Register Value
UVLO_HIGH[1:0] (V)
Bit Description
00
2.9
UVLO_LOW[1:0]
Defines the UVLO low threshold.
01
3.05
UVLO_HIGH[1:0]
Defines the UVLO high threshold.
10
3.2
ILIM_CURRENT[1:0]
Defines the boost peak inductor current.
11
3.35
Table 54. BIT DESCRIPTION OF ILIM_CURRENT[1:0]
Table 52. BIT DESCRIPTION OF UVLO_LOW[1:0]
Register Value
UVLO_LOW[1:0] (V)
00
2.75
01
2.9
10
3.05
11
3.2
Register Value
ILIM[2:0] (A)
00
1.8
01
2.4
10
3.0
11
3.6
Table 55. FLASH_TIMER REGISTER
Name: SAFETY_TIMER
Address: $10
Type: RW
Default: $13
D7
D6
Spare = 0
D5
D4
D3
INHIBIT_TIMER[3:0]
Bit
Bit Description
SAFETY_TIMER[2:0]
Defines the safety timing. (maximum flash duration)
INHIBIT_TIMER[3:0]
Defines the inhibit timing. (off duration after a flash)
Table 57. BIT DESCRIPTION OF SAFETY_TIMER[4:0]
SAFETY_TIMER (ms)
$0
32
$1
64
$2
128
$3
256
$4
512
$5
1024
D1
SAFETY_TIMER[2:0]
Table 56. BIT DESCRIPTION OF FLASH_TIMER REGISTER
Bit[2:0]
D2
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D0
NCP6951B
Table 58. BIT DESCRIPTION OF INHIBIT_TIMER[4:0]
Bit[3:0]
INHIBIT_TIMER(ms)
$00
512
$01
1024
$02
1536
$03
2048
$04
2560
$05
3072
$06
3584
$07
4096
$08
4608
$09
5120
$0A
5632
$0B
6144
$0C
6656
$0D
7168
$0E
7680
$0F
8192
Table 59. RED_EYE REGISTER
Name: RED_EYE
Address: $11
Type: RW
Default: $43
D7
D6
D5
Spare = 0
RED_EYE_TIMEOUT
D4
D3
PRE_FLASH_CURRENT[3:0]
D2
D1
PRE_FLASH_COUNT[1:0]
Table 60. BIT DESCRIPTION OF RED_EYE REGISTER
Bit
Bit Description
PRE_FLASH_COUNT[1:0]
Set the number of preflash pulses.
PRE_FLASH_CURRENT[3:0]
Set the preflash current.
RED_EYE_TIMEOUT
Activate or disactivate the timeout protection (2 s) between each pulses of the red eye
functionality (preflash and flash pulses)
Table 61. BIT DESCRIPTION OF
PRE_FLASH_COUNT[1:0]
Register Value
PRE_FLASH_COUNT
00
0
01
1
10
2
11
3
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D0
NCP6951B
Table 62. BIT DESCRIPTION OF
PRE_FLASH_CURRENT[3:0]
Register Value
PRE_FLASH_CURRENT[3:0] (mA)
0000
100
0001
200
0010
300
0011
400
0100
500
0101
600
0110
700
0111
800
1000
900
1001
1000
1010
1100
1011
1200
1100
1300
1101
1400
1110
1500
1111
1600
Table 63. FLASH_CONFIGURATION REGISTER
Name: FLASH_ENABLE
Address: $12
Type: RW
Default: $08
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Spare = 0
Spare =0
Spare = 0
FLSEL_POL
TORCH_RETRY
BAT_V_SEL
DIE_TEMP_SEL
Table 64. BIT DESCRIPTION OF FLASH_CONFIGURATION REGISTER
Bit
Bit Description
DIE_TEMP_SEL
Select the low battery voltage mode. (0 = reduce mode, 1 = adaptative mode)
BAT_V_SEL
Select the die temperature monitoring mode. (0 = reduce mode, 1 = adaptative mode)
TORCH_RETRY
Enable the retry operation for the torch low battery monitoring function.
FLSEL_POL
Select the polarity of the FLSEL pin (0 = active low, 1 = active high)
Table 65. FLASH_ENABLE REGISTER
Name: FLASH_ENABLE
Address: $13
Type: RW
Default: $00
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Spare = 0
Spare = 0
RED_EYE_EN
INHIBIT_EN
SAFETY_EN
TORCH_EN
FLASH_EN
Table 66. BIT DESCRIPTION OF FLASH_ENABLE REGISTER
Bit
Bit Description
FLASH_EN
Enable the flash mode. (flash is turn on when FLEN pin goes high)
TORCH_EN
Enable the torch mode.
SAFETY_EN
Enable the safety timer functionality.
INHIBIT_EN
Enable the inhibit timer functionality.
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NCP6951B
Table 67. FLASH_STATUS REGISTER
Name: FLASH_STATUS
Address: $14
Type: RC
Default: $00
D7
D6
D5
D4
D3
D2
D1
D0
TORCH_UVLO
FLASH_DIE_TEMP
FLASH_PA_BURST
FLASH_UVLO
FLASH_OVP
FLASH_SC
FLASH_TSD
FLASH_TIMEOUT
Table 68. BIT DESCRIPTION OF FLASH_STATUS REGISTER
Bit
Bit Description
FLASH_TIMEOUT
Indicates a flash timeout event.
FLASH_TSD
Indicates a flash TSD fault.
FLASH_SC
Indicates a short circuit fault.
FLASH_OVP
Indicates an OVP fault.
FLASH_UVLO
Indicates a flash UVLO event.
FLASH_PA_BURST
Indicates a PA burst blanking event.
FLASH_DIE_TEMP
Indicates a Flash TSD warning event.
TORCH_UVLO
Indicates a torch UVLO_L event.
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31
NCP6951B
Application Information
NCP 6951B
2.2 uF
PVIN
VBG
100nF
AGND
DCDC 1
600 mA
Core
System Supply
SW
DCDC1 Out
1uH
FB
10uF
PGND
1uF
VIN1
System Supply
1 .0uF
LDO 1
200 mA
VOUT 1
LDO 2
200 mA
VOUT 2
LDO 3
200 mA
VOUT 3
Power Up /
Down
Sequencer
LDO 4
200 mA
VOUT 4
VOUT 5
I@C
LDO 5
300 mA
VIN2
System Supply
Or
DCDC Out
1 .0uF
1uF
Thermal
Protection
HWEN
Enabling
1 .0uF
1 .0uF
1 .0uF
SDA
Processor I @C
SCL
Battery Supply
VBST
SW2
1 uH
1 x 22 uF 0603 or
2 x 10 uF 0402
4.7 uF
Boost
Converter
1.5A LED
Driver
FL
PGND2
FLSEL
Flash LED Current Select
PA transmit burst , Torch , etc
FLEN
Flash Enable Signal
LED Current
Select
Flash
Control
Enabling
Flash LED
1.5A LED
Driver
Figure 39. Typical Application Schematic
Inductor Selection
NCP6951B DCDC converters typically use 1 mH
inductor. Use of different values can be considered to
optimize operation in specific conditions. The inductor
parameters directly related to device performances are
saturation current, DC resistance and inductance value. The
inductor ripple current (DIL) decreases with higher
inductance.
DI L + V O
V
1* O
VIN
L
With:
• Fsw = Switching Frequency (Typical 3 MHz)
• L = Inductor value
• DIL = Peak−To−Peak inductor ripple current
• ILMAX = Maximum Inductor Current
To achieve better efficiency, ultra low DC resistance
inductor should be selected.
The saturation current of the inductor should be higher
than the ILMAX calculated with the above equations.
(eq. 1)
F SW
I LMAX + I OMAX )
DI L
2
(eq. 2)
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32
NCP6951B
Table 69. INDUCTOR L = 1.0 mH
Supplier
Part #
Size (mm) (L x l x T)
DC Rated Current (A)
DCR Max at 255C (mW)
TOKO
DFE201610R−1R0M
2.0 x 1.6 x 1.0
2.2
66
TOKO
DFE252012R−1R0M
2.5 x 2.0 x 1.2
3.4
38
TOKO
DFE252012P−1R0M
2.5 x 2.0 x 1.2
3.8
35
MURATA
LQH44PN−1R0NP0
4.0 x 3.5 x 1.8
2.5
36
MURATA
LQM2HPN−1R0MG0
2.5 x 2.0 x 1.0
1.6
69
TOKO
FDSD0412−H−1R0M
4.2 x 4.2 x 1.2
4.7
37
Output Capacitor Selection for DC to DC converters
The output ripple voltage in PWM mode can be estimated
by:
Selecting the proper output capacitor is based on the
desired output ripple voltage. NCP6951B DCDC converters
typically use 10 mF output capacitor. Ceramic capacitors
with low ESR values will have the lowest output ripple
voltage and are strongly recommended. The output
capacitor requires either an X7R or X5R dielectric.
DV O + V O
1*
VO
VIN
L
F SW
ǒ
(eq. 3)
2
p
1
CO
f
) ESR
Ǔ
Table 70. RECOMMENDED OUTPUT CAPACITOR FOR DC TO DC CONVERTERS
Manufacturer
Part Number
Case Size
Height Typ. [mm]
C [mF]
MURATA
GRM188R60J106ME47
0603
0.8
10
MURATA
GRM188R60J226MEA0
0603
0.8
22
TDK
C1608X5R0C106K/M
0603
0.8
10
TDK
C1005X5R0J106M050BC
0402
0.5
10
TDK
C1608X5R0J226M080AC
0603
0.8
22
Input Capacitor Selection for DC to DC Converters
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is 1/2 of maximum
output current. A low profile ceramic capacitor of 4.7 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to PVIN1 and PVIN2 pins.
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly.
Table 71. RECOMMENDED INPUT CAPACITOR FOR DC TO DC CONVERTERS
Supplier
Part Number
Case Size
Height Typ. [mm]
C [uF]
MURATA
GRM188R60J475KE
0603
0.8
4.7
MURATA
GRM188R60J106ME
0603
0.8
10
TDK
C1608X5R0C475K/M
0603
0.8
4.7
TDK
C1608X5R0C106K/M
0603
0.8
10
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33
NCP6951B
Output Capacitor for LDOs
PCB Layout Recommendation
For stability reason, a typical 1 mF ceramic output
capacitor is suitable for LDOs. The LDO output capacitor
should be placed as close as possible to the NCP6951B
output pin.
The high speed operation of the NCP6951B demands
careful attention to board layout and component placement.
To prevent electromagnetic interference (EMI) problems
and reduce voltage ripple of the device, any high current
copper trace which see high frequency switching should be
optimized. Therefore, use short and wide traces for power
current paths and for power ground tracks, power plane and
ground plane are recommended if possible.
Both the inductor and input/output capacitor of each DC
to DC converters are in the high frequency switching path
where current flow may be discontinuous. These
components should be placed as close to NCP6951B as
possible to reduce parasitic inductance connection. Also it
is important to minimize the area of the switching nodes and
use the ground plane under them to minimize cross−talk to
sensitive signals and ICs. It’s suggested to keep as complete
of a ground plane under NCP6951B as possible.
PGND and AGND pin connection must be connected to
the ground plane. Care should be taken to avoid noise
interference between PGND and AGND.
It is always good practice to keep the sensitive tracks such
as feedback connection (FB1 / FB2) away from switching
signal connections (SW1 / SW2) by laying the tracks on the
other side or inner layers of PCB.
Input Capacitor for LDOs
NCP6951B LDOs do not require specific input
capacitors. However, a typical 1 mF ceramic capacitor
placed close to LDOs’ input is helpful for load transient.
Power input of LDO can be connected to main power
supply. However, for optimum efficiency and lower
NCP6951B thermal dissipation, the lowest voltage available
in the system is preferred. Input voltage of each LDO should
always be higher than VOUT + VLDODROP (VDROP, LDO
dropout voltage at maximum current).
Capacitor DC Bias Characteristics
Real capacitance of ceramic capacitor changes versus DC
voltage. Special care should be taken to DC bias effect in
order to make sure that the real capacitor value is always
higher than the minimum allowable capacitor value
specified.
0402
0402
0402
0402
VOUT2
VIN1
VOUT1
FLSEL
AGND
SCL
FB1
PVIN1
SW1
SW2
FLEN
AGND
HWEN
SDA
PGND
1
VBST
FL
VBG
VOUT4
VIN2
VOUT5
0603
VOUT3
SW2
DFE201610R
DFE252012P
PGND2
0402
0402
0402
0603
0603
0603
Figure 40. Recommended PCB Components Placement
Thermal Considerations
taken of LDO VDROP, the larger it is, the higher dissipation
it will bring to NCP6951B. Keep a large copper plane under
and close to NCP6951B is helpful for thermal dissipation.
Careful attention must be paid to the power dissipation of
the NCP6951B. The power dissipation is a function of
efficiency and output power. Hence, increasing the output
power requires better components selection. Care should be
Table 72. ORDERING INFORMATIONS
Device
NCP6951BFCCT1G
Marking
Package
Shipping†
6951B
WLCSP24 (Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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34
NCP6951B
PACKAGE DIMENSIONS
WLCSP24, 2.57x1.65
CASE 567JA
ISSUE C
D
PIN A1
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A
B
ÈÈ
DIE COAT
A3
E
DIM
A
A1
A2
A3
b
D
E
e
A2
0.10 C
2X
DETAIL A
0.10 C
2X
TOP VIEW
DETAIL A
MILLIMETERS
MIN
MAX
−−−
0.60
0.17
0.23
0.36 REF
0.02 REF
0.24
0.29
2.57 BSC
1.65 BSC
0.40 BSC
A
0.10 C
A1
0.05 C
NOTE 3
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
A1
PACKAGE
OUTLINE
e/2
24X
b
e
0.05 C A B
0.03 C
0.40
PITCH
e
D
C
24X
0.40
PITCH
B
DIMENSIONS: MILLIMETERS
e/2
A
1
2
3
4
5
0.25
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
6
BOTTOM VIEW
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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35
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCP6951/D