DUAL SLOPEAID CONVERTERS ADC-14I, A'DC-17I, ADCIIOO GENERAL DESCRIPTION Dual slope integrating AID converters perform a conversion by first integrating the input signal for.a fixed period of time, and then measuring the time required to return the integrator to zero when it is integrated in the opposite direction with a fixed reference 'Signal. A major benefit of this technique is that it results in very high rejection of normal mode noise when the signal integration time period is set equal to one cycle of the power line. OBS ADCllOO The ADCll00 is a new dual slope AID converter in a compact 2" x 4" x 0.4" module. It can be triggered externally, or internally at a rate of about 4 conversions/sec, or it can be wired to start a new conversion'when the conversion in progress is completed. It is ideal for driving a display, or feeding data .to a computer, or for doing both jobs simultaneously. Since it requires only +5V power, and has a normal mode noise rejection ratio of 40dB minimum, it is a natural choice for installation at transducer locations. OLE ADC-141 and ADC-171 These two high resolution converters are identical except for output coding. The ADO-141 has 14-bit binary plus sign coding, while the ADC-171 has 4Y2digits plus sign output coding. Both feature a normal mode rejection ratio of 70dB; an aut9matic zero correction cycle, and a gainTC of only :!:10ppm/uC. TE BLOCK DIAGRAM ADCllOO BLOCK DIAGRAM ADC-141 & ADC-171 72 INPUT POLAR ITV 1 2 3 4 ~OAO 0 '"aooo-""4000 ~-- 5 6 7 B 9 10 11 12 - ~ - 13 14 0------- D o 0 0 1B 19 20 21 ,==~II I 20 '-'-10 ,,~ 4 I ClOCK 'REF -- 36 35 DATA OUTPUTS ~DOWN -~ ~G-<) CONTROL -,,-_...._- OUT ON PIN '15V <> "'-"<> LOGIC - ON THE ADC IS OUT I--~ l:2':o 5 141 PINS BITS 3 6 ) AND THROUGH 8 ARf OMITT[ 0 14 AAE ON PINS THE MSB 9 THROUGH IS ON PIN 4 20 32 31 27 AND AESPfCTIVELY 1022 20 23 40 24 80 25 29 28 ~~~;;'~K~ ~V-ERTCM}J- -~1" NOT[ 36 37 REF IN u .~~.:-:-:======-- ~P ~r< B 9 10 11 1 14 215 4 16 6 17 -~ ,- 0 SIATUS 23 24 25 26 HOLD POLARITY READY TRIGGER 40 0---,-'" 0--~---RAMP 22 48 47 1000 0--- BOO 400 o ,c,o <> TOo0-" BO 0-- 15 16 17 67 ANALOG GRD 66 OFFSET 65 OVERLOAD 64 REF IN ~RRANGE BIT 2 43 RAMP DOWN 42 FREO. ADJ 100 31 200 32 400 33 BOO 34 1000 35 40 DIGITAL GRD ---<> 39 ClOCK IN 3B CLOCK OUT I 37 "VDC N( 1. 2. 3. 94 CONVERTERS SPEOFICATION SUMMARY (Typical Model Resolution Linearity Error Analog Input Range Impedance Bias Current Resolution Continuous Overload2 @ +25°C unless otherwise noted) ADC-171 14 binary bits plus sign :to.Ol% 4Yz BCD digits 1 plus sign * 0 DC ".. .. 1.0mV!bit * 1:11 "....a * * 70dB 4Oms max OBS ." .. CD :t12V * * :tl0V 180kQ N/A 0.61mV/bit :tl00V max Normal Mode Rejection @ 60Hz3 Conversion Time :I ADC-14I Digital Control Inputs and Outputs Data Outputs Output Code * 0 0 * Sign plus ma!!nitude BCD OLE TemperatUre Coefficients Gain Offset Power Required Package Style Package Dimensions Price (1-9) (100+) * * :tlOppm/OC :tl011V 1° C +15V @ 30mA -15V @ 30mA +5V @ 200mA C-5 3" x 4" x 0.4" $259. * * * TE * * * 1 Maximum digital output code is 11999, which corresponds to an input of 11.999V. 2 Maximum overload that can be sustained indefinitely, with power on or off, without endangering the unit. 3 Both the ADC-I andADCII00 can be adjusted by the user to optimize the normal mode rejection of 50Hz noise, rather than 60Hz noise, if desired. 4The ADCII00 has provisions for connecting an external phase locked loop that can increase the normal rejection ratio to over 100dB. s In the event of an overload, it can take as long as 70ms to complete a conversion. *S.eecifications mode noise same as for model ADC-141. TIMING DIAGRAM ADC-14I & ADC-17I I--- 25 SAMPLES/SEC 100ns CONVERT COMMAND NOTE 2 NOTE 1 CONVERSION CYCLE Lj b I -jfI ~/~~1 FS COUNT ~~ CLOCK GATED TO COUNTER MAX---oj MIN I TIMING DIAGRAM ADCll 00 OUTPUT COUNT I1111III1I11I11111111 mrus TRIGGER---! RAMPiJp 2ERO 'CORRECT RAMP DOWN INTEGRATOR 1 POLARITY POLARITY OUTPUT :: OVERLOAD IIil'/to,,<,1'/(C. - - toGI'/-1lcIilCto =t: \~"\ . 833ms-l-1661ms . 1661msH :1 10111 t r--r- 2 STATUS 3 VALID \\G~~"\\O~ \GI' I ~.--- VALID (When Romp OVERLOAD; Down Interval Exceeds 16 2I3msIJu. , NOTES: 1. Maximum delay of one clock pulse to synchronize with clock. 2. Delay of "v I1h clock periods to reset counter and strobe comparator for polarity data. 3. 7ms min delay for drift correction phase. 'Reference integration time t" 20~:V loaded input, tm.. " 50ms. x 16.61ms. In the event of an ov", : Polarity data is valid anytime aft., the completion of the signal intO9..tion time po<iOO. .\In the event of an overloaded input, the overload output will go to a log;' "1" approx. 42ms after the conversion commences. However, the status output will not return to zero until the integrator has been integrated back to zero, which can be as long as lams after the conv.,s;on began. CONVERTERS 95