CD74HCT4067-Q1 SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 HIGH-SPEED CMOS LOGIC 16-CHANNEL ANALOG MULTIPLEXER and DEMULTIPLEXER Check for Samples: CD74HCT4067-Q1 1 FEATURES • • 1 • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H1A – Device CDM ESD Classification Level C2 Wide Analog Input Voltage Range Low ON Resistance – 70 Ω Typical (VCC = 4.5 V) Fast Switching and Propagation Speeds Break-Before-Make Switching – 6 ns Typical (VCC = 4.5 V) Fanout (Over Temperature Range) – Standard Outputs: 10 LSTTL Loads – Bus Driver Outputs: 15 LSTTL Loads Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs 4.5-V to 5.5-V Operation Direct LSTTL Input Logic Compatibility: VIL = 0.8 • V Max, VIH = 2 V Min CMOS Input Compatibility: II ≤ 1 µA at VOL, VOH 2 APPLICATIONS • • • Automotive Analog Switch Analog Multiplexer and Demultiplexer M PACKAGE (TOP VIEW) COMMON I/O I7 I6 I5 I4 I3 I2 I1 I0 S0 S1 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC I8 I9 I10 I11 I12 I13 I14 I15 E S2 S3 3 DESCRIPTION The CD74HCT4067-Q1 device is a digitally controlled analog switch that utilizes silicon-gate CMOS technology to achieve operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits. This analog multiplexer and demultiplexer controls analog voltages that may vary across the voltage supply range. It is a bidirectional switch, thus allowing any analog input to be used as an output and vice-versa. The switch has low (on) resistance and low (off) leakages. In addition, the device has an enable control that, when high, disables all switches to their off state. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) (3) PACKAGE (2) DW-SOIC-M Reel of 2000 ORDERABLE PART NUMBER (3) TOP-SIDE MARKING CD74HCT4067QM96Q1 HCT4067I For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. The suffix 96 denotes tape and reel. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HCT4067-Q1 SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 www.ti.com Table 1. FUNCTION TABLE (1) (1) S0 S1 S2 S3 E SELECTED CHANNEL X X X X H None L L L L L 0 H L L L L 1 L H L L L 2 H H L L L 3 L L H L L 4 H L H L L 5 L H H L L 6 H H H L L 7 L L L H L 8 H L L H L 9 L H L H L 10 H H L H L 11 L L H H L 12 H L H H L 13 L H H H L 14 H H H H L 15 H = High level L = Low level X = Don't care Logic Diagram (Positive Logic) I0 9 10 S0 11 S1 S2 14 S3 13 P Binary 1 of 16 Decoder SN = 5 Stages E = 4 Stages N 14 – Output Circuits Same As Above (With Analog Inputs) I1 to I14 1 P 15 E 2 Common Input/Output N 16 I15 Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 CD74HCT4067-Q1 www.ti.com SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS (1) 3.1 over operating free-air temperature range (unless otherwise noted) VALUE MIN MAX UNIT VCC Supply voltage range (2) IIK Input clamp current (VI < −0.5 V or VI > VCC + 0.5 V) ±20 mA IOK Output clamp current (VO < −0.5 V or VO > VCC + 0.5 V) ±20 mA IO Switch current (VO > −0.5 V or VO < VCC + 0.5 V) ±25 mA IO Output source or sink current per output pin (VO > −0.5 V or VO < VCC + 0.5 V) ±25 mA Continuous current through VCC or GND ±50 mA 150 °C 150 °C 400 V 250 V −0.5 TJ Maximum junction temperature Tstg Storage temperature range ESD Rating Human Body Model (HBM) AEC-Q100 classification level H1A −65 Charged Device Model (CDM) AEC-Q100 classification level C2 Latch-up per JESD78D (1) (2) 7 V Class 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are referenced to GND, unless otherwise specified. 3.2 THERMAL INFORMATION CD74HCT4067-Q1 THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance 62.3 θJCtop Junction-to-case (top) thermal resistance 30.5 θJB Junction-to-board thermal resistance 31.8 ψJT Junction-to-top characterization parameter 7.7 ψJB Junction-to-board characterization parameter 31.5 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) 3.3 UNIT DW (24 PINS) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage tt Input transition (rise and fall) time TA Operating free-air temperature (1) MIN MAX 4.5 5.5 UNIT 2 VCC = 4.5 V V V 0.8 V 0 VCC V 0 VCC V 0 500 ns –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 3 CD74HCT4067-Q1 SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 3.4 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VI MIN II Logic input IIZ VIS = VCC or GND, E = VCC VCC or GND ron IO = 1 mA Δron Between any two switches TYP MIN MAX 5.5 V ±0.1 ±1 µA 5.5 V ±0.8 ±8 µA VCC or GND 4.5 V 70 160 200 VIS = VCC to GND VCC to GND 4.5 V 90 180 225 4.5 V 10 ΔICC Per input pin: 1 unit load (1) CI Control inputs UNIT MAX VIS = VCC or GND ICC (1) TA = −40°C to 125°C TA = 25°C VCC VCC or GND 5.5 V VCC − 2.1 V 4.5 V to 5.5 V Ω Ω 100 8 80 µA 360 450 µA 10 10 pF For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. 3.5 HCT INPUT LOADING (1) 3.6 INPUT UNIT LOADS (1) S0 – S3 0.5 E 0.3 Unit load is ΔICC limit specified in the electrical characteristics table, for example, 360 μA max at 25°C. SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) see Figure 5 FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd In Common I/O CL = 15 pF 5V CL = 50 pF 4.5 V ten E Common I/O CL = 15 pF 5V CL = 50 pF 4.5 V ten Sn Common I/O CL = 15 pF 5V CL = 50 pF 4.5 V tdis E Common I/O CL = 15 pF 5V CL = 50 pF 4.5 V tdis Sn Common I/O CL = 15 pF 5V CL = 50 pF 4.5 V PARAMETER TA = −40°C TO 125°C TA = 25°C VCC MIN TYP MAX MIN UNIT MAX 6 15 19 60 75 60 75 55 69 58 73 25 25 23 21 ns ns ns ns ns 3.7 OPERATING CHARACTERISTICS VCC = 5 V, TA = 25°C, input tr, tf = 6 ns PARAMETER Cpd (1) 4 TEST CONDITIONS Power dissipation capacitance (1) MIN TYP 96 MAX UNIT pF Cpd is used to determine the dynamic power consumption (PD), per package. PD = (Cpd × VCC2 × fI) + Σ (CL + CS) × VCC2 × fO fO = output frequency fI = input frequency CL = output load capacitance CS = switch capacitance VCC = supply voltage Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 CD74HCT4067-Q1 www.ti.com SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 3.8 ANALOG CHANNEL CHARACTERISTICS TA = 25°C PARAMETER fmax VCC (1) (2) TYP UNIT MHz Switch frequency response bandwidth at −3 dB See Figure 1 and Figure 7 4.5 V 89 Sine-wave distortion See Figure 2 4.5 V 0.051 % Switch OFF signal feedthrough See Figure 4 and Figure 8 4.5 V −75 dB 5 pF 50 pF CS Switch input capacitance CCOM Common capacitance (1) (2) TEST CONDITIONS Adjust input voltage to obtain 0 dBm at output, f = 1 MHz. VIS is centered at VCC / 2 4 PARAMETER MEASUREMENT INFORMATION VCC VCC VOS SWITCH ON VIS 0.1 F 50 Ω 10 pF dB METER Sine Wave VIS SWITCH ON VOS 10 F 10 kΩ 50 pF DISTORTION METER VCC / 2 VCC / 2 fIS = 1 kHz to 10 kHz Figure 1. Frequency-Response Test Circuit Figure 2. Sine-Wave Distortion Test Circuit VCC fIS ≥ 1-MHz Sine Wave R = 50 Ω C = 10 pF VCC 600 Ω SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6 ns fCONT = 1 MHz 50% DUTY CYCLE V OS 0.1 µF SWITCH V IS 600 Ω dB R R VCC / 2 VCC / 2 Figure 3. Control-to-Switch Feedthrough Noise Test Circuit V OS OFF 10 pf SCOPE VC = VIL C METER VCC / 2 Figure 4. Switch OFF Signal Feedthrough Test Circuit Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 5 CD74HCT4067-Q1 SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd LOAD CIRCUIT 3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% 90% tPHL 90% 1.3 V 1.3 V 0V tPHL 90% tr Out-of-Phase Output 3V Output Control VOH 1.3 V 10% tf VOL 1.3 V 10% tf 1.3 V 10% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 1.3 V Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL ≈VCC Output Waveform 1 (see Note B) tPLH 90% tPLZ tPZL 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. t PLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 CD74HCT4067-Q1 www.ti.com SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 5 TYPICAL CHARACTERISTICS ON Resistance vs Input Signal Voltage ON Resistance − Ω 100 TA = 25ºC GND = 0 V 80 60 VCC = 4.5 V 40 20 0 1 2 Switch Frequency Response 0 Channel-ON Bandwidth − dB 120 3 4 4.5 5 6 Input Signal Voltage − V Figure 6. 7 8 −2 −4 −6 −8 VCC = 4.5 V RL = 50 Ω TA = 25°C −10 104 9 105 106 107 Frequency − Hz 108 Figure 7. Switch-OFF Signal Feedthrough vs Frequency Switch-Off Signal Feedthrough − dB 0 −20 VCC = 4.5 V RL = 50 Ω TA = 25°C −40 −60 −80 −100 104 105 106 107 108 f − Frequency − Hz Figure 8. Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 7 CD74HCT4067-Q1 SCLS601B – DECEMBER 2004 – REVISED AUGUST 2012 www.ti.com 6 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April, 2008) to Revision B Page • Changed H2 to H1A and C3B to C2 throughout document ................................................................................................... 1 • Added AEC-Q100 info to Features......................................................................................................................................... 1 • Removed from Features: Wide Operating Temperature Range: –40°C to 85°C ................................................................... 1 • Added applications ................................................................................................................................................................. 1 • Replaced SOIC-M package info in ordering info table with new row for DW-SOIC-M package............................................ 1 • Added ESD ratings to Abs Max table ..................................................................................................................................... 3 • Added latch-up row in Abs Max table..................................................................................................................................... 3 • Changed max TA value from 85°C to 125°C .......................................................................................................................... 3 • Changed TA = -40°C to 85°C column to TA = -40°C to 125°C ............................................................................................... 4 • Changed TA = -40°C to 85°C column to TA = -40°C to 125°C ............................................................................................... 4 8 Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: CD74HCT4067-Q1 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD74HCT4067QM96Q1 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HCT4067I D24067IM96G4Q1 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT4067I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF CD74HCT4067-Q1 : • Catalog: CD74HCT4067 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HCT4067QM96Q1 Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HCT4067QM96Q1 SOIC DW 24 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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